MINI - UART

SYNTHESIZABLE UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER WITH MICROPROCESSOR BUS

Mini-UART
Jeung Joon Lee 8/28/2001

Recommended digital logic background: entry-level to medium 1.0 Introduction The mini-UART is a fully functional, synthesizable, Universal Asynchronous Receiver Transmitter soft core, ideal for embedded processor applications or system-onprogrammable-chip. The core is based upon the ultra-compact micro-UART core. (also from www.cmosexod.com) A dedicated synchronous microprocessor bus interface module is wrapped around the micro-UART. All internal operations of the mini-UART can be controlled and programmed by the microprocessor bus. The external microprocessor can program the baud rate, the interrupt masks and the transmit/receive buffers. A status register can be polled in real-time to keep progress of the transmitter as well as the receiver. The mini-UARTs microprocessor bus interfaces seamlessly with the PopCorn-V3 microprocessor core, or to any other synchronous microprocessor bus such as most Intel microcontrollers. Figure 1 illustrates the top level functional block diagram.

mp_int.v This is the synchronous microprocessor bus interface. This module contains the register file, all of the required synchronizers (to cross the uart_clk and mp_clk domain) and bus control. u_xmit.v This is the asynchronous transmitter. A state-machine, serializer and support logic comprises the main bulk of the logic. u_rec.v This is the asynchronous receiver. A dual-rank synchronizer, state-machine, deserializer and support logic comprises the bulk of the logic. u_baud.v This is the baud-rate generator. An internal baud-clock which is 16 times the desired baud-rate is generated off of the external clock. uart_inc.h This is the configuration file. The baud-rate, external clock rate and the size of the data-byte are all set from this file. The clock generated from this module feeds the u_rec and u_baud modules. The following table describes the default port list of the micro-UART.
Signal W id th Ty pe Description

register file

baud gen

sys_clk
uart_clk

mp_clk mp_cs_l mp_addx mp_data_to_uart mp_data_from_uart mp_rd_l mp_wr_l mp_int_l

xmit control

uart_XMIT_dataH

sys_rst_l uart_clk mp_clk

1 1 1

I O I

main system clock. This clock is used to generate the baud rate clock, namely uart_clk. main system reset baud-clock. 16 x baud-rate This is the clock source of the synchronous microprocessor bus. This clock is unrelated to any other clock. It can be faster or slower than the sys_clk. Mini-UART chip select. All synchronous accesses to the UART needs to have this signal asserted active low. This 3 bit address specifies the register to access in the miniUART This is the data from the external micro to the mini-UART. This is the data from the miniUART to the external micro. Active low signal which drives data onto the mp_data_from_uart bus to the external micro Active low signal which is used to latch data into the mic-UARTs register file Active low output signal which is used as synchronous interrupt (mp_clk) to the external microprocessor This is an output pin which comes from the UARTs tranmitter unit.

rec synchronize rs

uart_REC_dataH

micro-UART

mp_cs_l

Figure 1 Functional Block diagram of the Mini-UART

mp_addx

2.0 Mini-UART IP Package A total of 6 files comprises the mini-UART core: uart.v mp_int.v u_xmit.v u_rec.v baud.v uart_inc.h All for the exception of mp_int.v are the same modules as that of the micro-UART core. uart.v This is the top-level hierarchy module. All sub-modules are instantiated here. No logic is present in this module.

mp_data_to_uart mp_data_from_uart mp_rd_l

8 8 1

I O I

mp_wr_l

mp_int_l

uart_XMIT_dataH

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MINI - UART

SYNTHESIZABLE UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER WITH MICROPROCESSOR BUS

uart_REC_dataH

During idle cycles, this pin becomes active high This is an input pin to the UARTs receiver unit. During idle cycles,

Baud_reg_lo = baud_rate_divisor % 256 Baud_reg_hi = (baud_rate_divisor baud_reg_lo ) / 256 Where % is the modulus operation (reminder of division). For example, if sys_clk is 53.25MHz, and the desired baud_rate is 2400 baud, then Baud_rate_divisor = 53250000 Hz --------------------------( 16 * 2 * 2400 baud)

3.0 Software Interface The software interface to the mini-UART is fairly simple. All communication setup and status is accomplished through the synchronous microprocessor bus. The microprocessor has read ability to all register within the mini-UART. Table 1 summarizes the registers in the mini-UART. Address 00 00 01 02 03 04 05 Mode W R R/W R/W R R/W R/W Register Name XMIT_DAT_REG REC_DAT_REC BAUD_REG_LO BAUD_REG_HI STAT_REG INT_STAT_REG INT_ENA_REG

= 693 then, baud_rate_lo register is programmed with 181 or 0xB5, and baud_rate_hi is programmed with 2. The uart_clock (16 x baud_rate) is not updated until the baud_reg_hi is written. Thus it is strongly recommend to write to the baud_reg_lo first, then baud_reg_hi.

Table 1 Summary of the Register in mini-UART XMIT_DAT_REG 0x00 Write Only 7 This register holds the data to be sent to the remote UART. Data is sent automatically whenever a value is written to this register. If a new value is written while current value is being transmitted, the new value will be ignored, and not transmitted. 7 6 5 4 3 2 Xmit Data[7:0] 0, wo 1 0 6 5

4 3 2 Baud_reg[15:8] 0, wo

4 3 2 Baud_reg[7:0] 0, wo

STAT_REG

0x03

Read Only

This register holds the real-time status of the UARTs receiver and trasmitter. This register is read only.

7 REC_DAT_REG 0x00 Read Only

1 Rec_data_avail 0,r

0 Xmit_bus y 0, r

This register hold the data received from the remote UART. The data is valid to be read only when the receive data available bit from the STAT_REG is set. At all other times the data in this register is not guaranteed to be valid.

Xmit_busy This bit when high indicates that a value written to XMIT_DAT_REG is being sent over the UART. When this bit is low, it indicates that the UARTs transmitter is free to sent another data. Rec_data_avail This bit when high indicates that a data was received from the other UART, thus the value in REC_DAT_REG is ready to be read by the external processor. When this bit is low, it indicates that a data is currently being received by the UARTs receiver unit.

4 3 2 Rec Data[7:0] 0, ro

BAUD_REG_LO BAUD_REG_HI

0x01 0x02

Read / Write Read / Write

These registers holds the lower and upper bytes of 16 bit baud rate divisor. The registers are read and writable. The UARTs baud rate is compute as follows: Baud_rate_divisor = sys_clk -------------------------------(16 * 2 * baud_rate)

INT_STAT_REG

0x04

read / write

The value to be programmed to the baud_reg_lo is then computed as:

This register holds status bits which are the source of interrupt. When the corresponding enable bit is set in the INT_ENA_REG, and the bit in this register is set, an interrupt is generated to the external processor. All of the status bits in this register must be written to 0 in order to clear the external interrupt.

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SYNTHESIZABLE UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER WITH MICROPROCESSOR BUS

7 6 5 4 3 2 1 Stat_rec_data H 0,rw

0 Stat_xmit_emptyH 0, rw

Figure 3 illustrates the timing diagram for writing data into the mini-UARTs register. Similarly, figure 3 illustrates the timing diagram of reading data from the mini-UARTs internal register. Note that due to the separate unidirectional data bus, the read data bus is gated only by the address, and not by the mp_rd_l.

mp_clk

Stat_xmit_emptyH This bit when set indicates that the UARTs transmitter is not busy (i.e. has finished transmitting the last value). When the corresponding interrupt enable bit is set in the INT_ENA_REG, an active low interrupt is generated to the external micro. This status bit, once set does not get cleared automatically, thus the external micro must clear this bit. Stat_rec_dataH This bit when set indicates that the UARTs receiver has a new data for the micro to read. ). When the corresponding interrupt enable bit is set in the INT_ENA_REG, an active low interrupt is generated to the external micro. This status bit, once set does not get cleared automatically, thus the external micro must clear this bit.

tas

mp_addx

valid address

mp_cs_l
tcs

mp_wr_l mp_data_to_uart
trs tds tdh

valid

tas = address stable delay tcs = chip select stable delay trs = read stable tds = data setup tdh = data hold

Figure 2 Writing data to mini-UART's registers INT_ENA_REG 0x05 read / write

This is the interrupt enable register. When the bits in this register is set and the corresponding status bit in the INT_STAT_REG is set, then an active low interrupt is generated to the external processor.

mp_clk
tas

mp_addx

valid address

7 6 5 4 3 2 1 ena_rec_data H 0,rw

0 ena_xmit_emptyH

mp_cs_l
tcs

mp_rd_l

0, rw

mp_data_from_uart

tad

tdh

Ena_xmit_emptyH When this bit is set, it enable the stat_xmit_emptyH interrupt. Ena_rec_dataH When this bit is set, it enables the stat_rec_dataH interrupt.

valid

tas = address stable delay tcs = chip select stable delay tad = address stable to data tdh = data hold

4.0 Hardware Interface The hardware interface to the mini-UART is also relatively easy. The mini-UART has 2 main interface buses: the UART pins and the synchronous micro bus. The UART pins consists of transmit and receive pins and can be connected to a level-translator for communication to a PC, or can be connected directly to a remote devices UART which does not require level-translators. The synchronous micro bus is an 8 bit parallel bus by which all mini-UARTs operations are commanded and monitored. The data bus features separate unidirectional buses for ease of implementation in System-on-Chip and in FPGAs.

Figure 3 Reading data from mini-UART's internal register

5.0 Microprocessor Interface Clock Domain Crossing The microprocessor interface handles the two clock domain using synchronizers and one-shot logic. The synchronizer is needed to interface the microprocessor bus, which operates at the mp_clk, to the micro-UART core which operates at the uart_clk.

6.0 Programming Examples Using the mini-UART with a microcontroller or microprocessor is relatively simple.

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MINI - UART

SYNTHESIZABLE UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER WITH MICROPROCESSOR BUS

; *********** ; UART SET_UP ; *********** ; Write Baud rate - LOW ldi acc,#01h stp acc,#01h ; Write Baud rate - HI ldi acc,#00h stp acc,#02h ; Clear any pending UART interrtups ldi acc,#00h stp acc,#04h ; Enable UART interrupts (rec and Xmit) ldi acc,#0Fh stp acc,#05h ; verify that the data writtne to ; the UART is correct ldp acc,#01h cmpacci #01h jne ERROR ldp acc,#02h cmpacci #00h jne ERROR ldp acc,#05h cmpacci #0Fh jne ERROR ; ; ; ; ; ; ; ; ******************* SEND DATA TO UART ******************* AX will have the data to be sent to the UART so, initialize it ldi ei ax,#76h ; enable the global interrupt

; send data to UART stp ax,#00h ;write to UART XMIT reg

The above is code fragment in PopCorn-V3 assembler (PopCorn-V3 microprocessor is also available from www.cmosexod.com). This code initializes the mini-UART by setting the UARTs baud rate registers. It then clears all pending interrupt status bits, then writes to the interrupt enable register. Finally, data is written to the transmitter register, which will cause the UARTs transmit unit to transmit the data.

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