Technical Reference Manual

Real-time, Low Power Network, Multimedia Direct Execution Microprocessor For The JME Platform TM M aJ-200T

Trade marks aJ-200 is trademark of aJile Systems, Inc. Sun, Sun Microsystems and Java are all trademarks of Sun Microsystems in the United States and other countries. All other trademarks are the property of their respective owners
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TableofContents
1. INTRODUCTION ........................................................................................................................................................................ 1 1.1. FEATURES ........................................................................................................................................................................... 2 1.2. BLOCK DIAGRAM ................................................................................................................................................................ 5 1.3. SYSTEM DEVELOPMENT SUPPORT ..................................................................................................................................... 5 1.3.1. Java Technology Based Runtime System ...................................................................................................... 6 1.3.2. aJile Real-time Kernel .......................................................................................................................................... 6 1.3.3. Optimizing Linker/Application Builder ............................................................................................................ 6 1.3.4. Application Debugging Tools ............................................................................................................................ 6 1.4. TARGET DEVICES................................................................................................................................................................. 7 2. ARCHITECTURE OVERVIEW .............................................................................................................................................. 12 2.1. AHB BASED DEVICES ...................................................................................................................................................... 12 2.1.1. Java Processor .................................................................................................................................................... 12 2.1.2. AHB Controller (AHBC) ..................................................................................................................................... 12 2.1.3. DMA Controller (DMAC) .................................................................................................................................... 12 2.1.4. Single-chip 10/100 Ethernet Controller ......................................................................................................... 13 2.1.5. Encryption and Decryption Engine ................................................................................................................ 13 2.1.6. Single-chip USB 2.0 OTG Controller (USB OTG) ........................................................................................ 14 2.1.7. LCD Controller (LCDC) ...................................................................................................................................... 15 2.1.8. Video Capture ...................................................................................................................................................... 16 2.1.9. MediaCodec .......................................................................................................................................................... 17 2.1.10. External Bus Interface Unit (EBI) .................................................................................................................... 18 2.1.11. AHB to APB Bridge (APB Bridge) ................................................................................................................... 19 2.2. APB PERIPHERAL DEVICES ............................................................................................................................................. 20 2.2.1. Peripheral Interrupt Controller (PINTC)......................................................................................................... 20 2.2.2. Timers/Counters.................................................................................................................................................. 20 2.2.3. Watch Dog Timer (WDT) .................................................................................................................................... 20 2.2.4. Real Time Controller (RTC) .............................................................................................................................. 21 2.2.5. GPIO Ports ............................................................................................................................................................ 21 2.2.6. Pulse Width Modulators (PWMs) .................................................................................................................... 21 2.2.7. IC ............................................................................................................................................................................ 22 2.2.8. Synchronous Serial Port Controller (SSPC) ................................................................................................ 22 2.2.9. IS / AC97/ SPI Controller (IS / AC97C/ SPI) ................................................................................................ 23 2.2.10. Compact Flash Controller (CFC) ..................................................................................................................... 23 2.2.11. Multimedia Card and Secure Digital Host Controller (MMC / SDC / SDIO)........................................... 24 2.2.12. UARTs ................................................................................................................................................................... 24 2.2.13. IrDA/UART4 .......................................................................................................................................................... 25 2.3. PHASE LOCKED LOOPS (PLLS) ...................................................................................................................................... 25 2.4. SYSTEM CONFIGURATION ................................................................................................................................................. 26 2.5. OPERATING VOLTAGES ..................................................................................................................................................... 26 2.6. OPERATING TEMPERATURE .............................................................................................................................................. 26 2.7. PACKAGE .......................................................................................................................................................................... 26 3. PIN ASSIGNMENT .................................................................................................................................................................. 27 3.1. SIGNAL DESCRIPTIONS ..................................................................................................................................................... 27
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3.2. 4. 5. 4.1.

PACKAGE INFORMATION ................................................................................................................................................... 49 INTERNAL REGISTERS....................................................................................................................................................... 52

MEMORY MAP......................................................................................................................................................................... 51 SYSTEM CONFIGURATION ................................................................................................................................................. 76 5.1. CLOCK SOURCES.............................................................................................................................................................. 76 5.1.1. XIN Oscillator ....................................................................................................................................................... 78 5.1.2. OSCLIN Oscillator ............................................................................................................................................... 78 5.1.3. 12 MHz Crystal ..................................................................................................................................................... 78 5.1.4. 25 MHz Crystal ..................................................................................................................................................... 79 5.1.5. Phase Locked Loop 1 (PLL1) ........................................................................................................................... 80 5.1.6. Peripheral Phase Locked Loop 2 (PLL2) ...................................................................................................... 81 5.1.7. Peripheral Phase Locked Loop 3 (PLL3) ...................................................................................................... 81 5.1.8. DLL ......................................................................................................................................................................... 82 5.2. OPERATION MODES .......................................................................................................................................................... 83 5.2.1. Reset Mode ........................................................................................................................................................... 83 5.2.2. Normal Mode ........................................................................................................................................................ 85 5.2.3. Power Saving Modes ......................................................................................................................................... 85 5.2.4. RTC operation ...................................................................................................................................................... 86 5.3. SYSTEM CONFIGURATION REGISTERS ............................................................................................................................. 87

6.

JAVA PROCESSOR .............................................................................................................................................................. 107 6.1. OVERVIEW ....................................................................................................................................................................... 107 6.2. JEMCORE-II PROCESSOR CORE ................................................................................................................................... 107 6.3. MULTIPLE JVM MANAGER (MJM) ................................................................................................................................. 108 6.4. JEMCORE-II REGISTER DESCRIPTION .......................................................................................................................... 109 6.4.1. MJM Register Descriptions ............................................................................................................................. 110 6.4.1.9. Clock Timer 0 Reload Register ....................................................................................................................... 115 6.4.2. Interrupt Controller ............................................................................................................................................ 118 6.5. CUSTOM INSTRUCTIONS ................................................................................................................................................. 122 6.6. INSTRUCTION AND DATA CACHE (I & D CACHE) ............................................................................................................ 122 6.6.1. Register Description ........................................................................................................................................ 122 6.6.2. Functional Description .................................................................................................................................... 124 6.6.3. Bus Interface ...................................................................................................................................................... 125 6.7. TEST INTERFACE ............................................................................................................................................................. 126 6.7.1. Reset Sequence ................................................................................................................................................ 129 6.7.2. Reset Processing Steps .................................................................................................................................. 130 6.7.3. Data Structure of Initialization Data Blocks (IDBs) .................................................................................. 132

7.

AHB CONTROLLER ............................................................................................................................................................. 134 7.1. GENERAL DESCRIPTION ................................................................................................................................................. 134 7.2. ARBITER .......................................................................................................................................................................... 135 7.3. REGISTER SLAVE ............................................................................................................................................................ 135 7.4. DECODER ........................................................................................................................................................................ 135 7.5. MULTIPLEXER (MUX) ..................................................................................................................................................... 135 7.6. PROGRAMMING MODEL .................................................................................................................................................. 135 7.6.1. Register Descriptions ...................................................................................................................................... 136

8.

DMA CONTROLLER (DMAC) ............................................................................................................................................. 139 8.1. OVERVIEW ....................................................................................................................................................................... 139 8.2. DMA ROUTING TABLE .................................................................................................................................................... 139 8.2.1. AHB Master Interface ....................................................................................................................................... 140 8.2.2. AHB Slave Interface ......................................................................................................................................... 140

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8.2.3. FIFO Buffer ......................................................................................................................................................... 140 8.2.4. DMA Core ............................................................................................................................................................ 140 8.3. PROGRAMMING MODEL .................................................................................................................................................. 140 8.3.1. General Description ......................................................................................................................................... 140 8.3.2. Prioritizing Arbiter ............................................................................................................................................ 140 8.3.3. Chain Transfer ................................................................................................................................................... 141 8.4. DMA HARDWARE HANDSHAKE MODE ........................................................................................................................... 143 8.5. DMA NORMAL MODE ..................................................................................................................................................... 144 8.6. SUMMARY OF THE DMA CONTROLLER REGISTERS ...................................................................................................... 145 8.6.1. Interrupt Status Register (Offset == 0x00) .................................................................................................. 147 8.6.2. Interrupt for Terminal Count Status Register (Offset == 0x04) ............................................................. 148 8.6.3. Interrupt for Terminal Count Clear Register (Offset == 0x08) ............................................................... 148 8.6.4. Error/Abort Interrupt Status Register (Offset == 0x0C)........................................................................... 149 8.6.5. Error/Abort Interrupt Status Clear Register (Offset == 0x10) ................................................................ 150 8.6.6. Terminal Count Status Register (Offset == 0x14) ..................................................................................... 151 8.6.7. Error/Abort Status Register (Offset == 0x18) ............................................................................................. 151 8.6.8. Channel Enable Status Register (Offset == 0x1C) .................................................................................... 153 8.6.9. Channel Enable Status Register (Offset == 0x20) .................................................................................... 153 8.6.10. Main Configuration Status Register (Offset == 0x24) .............................................................................. 154 8.6.11. Synchronization Register (Offset == 0x28) ................................................................................................ 154 8.6.12. DMAC Revision Register (DMAC_REVISION) (Offset = 0x30) ............................................................... 155 8.6.13. DMAC Feature Register (DMAC_FEATURE) (Offset = 0x34) .................................................................. 155 8.6.14. Channel 0 : 7 Control Register (Offset == 0x100, 0x120, 0x140, 0x160, 0x180, 0x1A0,................... 156 0x1C0, 0x1E0 ) ...................................................................................................................................................................... 156 8.6.15. Channel 0:7 Configuration Register (Offset == 0x104, 0x124, 0x144, 0x164, 0x184, 0x1A4, 0x1C4, 0x1E4) 159 8.6.16. Channel 0:7 Source Address Register (Offset == 0x108, 0x128, 0x148, 0x168, 0x188, 0x1A8, 0x1C8, 0x1E8) ....................................................................................................................................................................... 159 8.6.17. Channel 0:7 Destination Address Register (Offset == 0x10C, 0x12C, 0x14C, 0x16C, 0x18C, 0x1AC, 0x1CC, 0x1EC) ...................................................................................................................................................... 159 8.6.18. Channel 0:7 Linked List Descriptor Pointer (Offset == 0x110, 0x130, 0x150, 0x160, 0x180, 0x1A0, 0x1C0, 0x1E0) ....................................................................................................................................................................... 159 8.6.19. Channel 0:7 Transfer Size Register (Offset == 0x114, 0x134, 0x153, 0x174, 0x194, 0x1B4, 0x1D4, 0x1F4) 160 8.7. PROGRAMMING SEQUENCE ............................................................................................................................................ 160 9. EXTERNAL BUS INTERFACE (EBI) ................................................................................................................................. 163 9.1. OVERVIEW ....................................................................................................................................................................... 163 9.2. ARCHITECTURE DESCRIPTION ........................................................................................................................................ 163 9.2.1. AHB Slave Interface ......................................................................................................................................... 164 9.2.2. Tri-state Multiplexer Interface ........................................................................................................................ 164 9.2.3. Registers ............................................................................................................................................................. 164 9.2.4. Arbitrator ............................................................................................................................................................. 164 9.2.5. Summary of EBI Registers ............................................................................................................................. 164 9.2.6. Register Description ........................................................................................................................................ 165 9.3. STATIC MEMORY CONTROLLER (SMC).......................................................................................................................... 166 9.3.1. Overview ............................................................................................................................................................. 166 9.3.2. Interface Types .................................................................................................................................................. 167 9.3.3. Synchronous Devices...................................................................................................................................... 169 9.3.4. ZBTTM Devices.................................................................................................................................................... 170 9.3.5. Memory bus width ............................................................................................................................................ 170 9.3.6. NAND Interface .................................................................................................................................................. 172 9.3.7. Summary of Static Memory Controller Registers ..................................................................................... 178 9.3.8. Shadow Status Register (Offset == 0x40) ................................................................................................... 186

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9.3.9. Programming Sequence ................................................................................................................................. 187 9.4. SDRAM CONTROLLER (SDRAMC).............................................................................................................................. 188 9.4.1. General Description ......................................................................................................................................... 188 9.4.2. AHB Channel ...................................................................................................................................................... 189 9.4.3. Refresh Controller ............................................................................................................................................ 190 9.4.4. Arbiter .................................................................................................................................................................. 190 9.4.5. Control Engine................................................................................................................................................... 191 9.4.6. Programming Model ......................................................................................................................................... 191 9.4.7. Address Mapping .............................................................................................................................................. 199 9.4.8. Programming Sequence ................................................................................................................................. 202 9.4.9. Example ............................................................................................................................................................... 204 10. LCD CONTROLLER (LCDC) .......................................................................................................................................... 206 10.1. OVERVIEW ....................................................................................................................................................................... 206 10.2. APPLICATION ................................................................................................................................................................... 208 10.3. ARCHITECTURE OVERVIEW ............................................................................................................................................ 209 10.3.1. AHB Slave Interface ......................................................................................................................................... 209 10.3.2. FIFO Controllers and FIFOs ........................................................................................................................... 209 10.3.3. Pixel Data Unpack ............................................................................................................................................. 210 10.4. DATA MODE ..................................................................................................................................................................... 212 10.4.1. Raw RGB Mode.................................................................................................................................................. 212 10.4.2. YCbCr422 Mode................................................................................................................................................. 212 10.4.3. YCbCr420 Mode................................................................................................................................................. 212 10.4.4. RGB Palette Mode ............................................................................................................................................. 213 10.5. COLOR MANAGEMENT .................................................................................................................................................... 213 10.5.1. Contrast Control................................................................................................................................................ 213 10.5.2. Brightness Contrast ......................................................................................................................................... 214 10.5.3. Sharpness ........................................................................................................................................................... 214 10.5.4. Hue & Saturation ............................................................................................................................................... 214 10.5.5. Gamma Correction ........................................................................................................................................... 214 10.5.6. Dither Controller................................................................................................................................................ 214 10.6. IMAGE CONTROLLER ...................................................................................................................................................... 214 10.6.1. Picture In Picture (PIP) .................................................................................................................................... 214 10.6.2. Picture Out of Picture (POP) .......................................................................................................................... 215 10.7. ON-SCREEN DISPLAY (OSD) ......................................................................................................................................... 215 10.7.1. Font Based Architecture ................................................................................................................................. 215 10.7.2. Attribut Description .......................................................................................................................................... 216 10.7.3. OSD Window Control ....................................................................................................................................... 216 10.8. SCALAR ........................................................................................................................................................................... 217 10.8.1. Box Filter ............................................................................................................................................................. 217 10.8.2. 1024x24 Line Buffer.......................................................................................................................................... 217 10.8.3. 1024x24 Line Buffer Controller...................................................................................................................... 217 10.8.4. 2048x24 Line Buffer.......................................................................................................................................... 217 10.8.5. 2048x24 Line Buffer Controller...................................................................................................................... 218 10.8.6. Vertical Scalar FIR ............................................................................................................................................ 218 10.8.7. Vertical Scalar Coefficient Generator .......................................................................................................... 218 10.8.8. Scalar Data FIFO ............................................................................................................................................... 218 10.8.9. Horizontal Scalar FIR ....................................................................................................................................... 218 10.8.10. Horizontal Scalar Coefficient Generator ..................................................................................................... 218 10.9. TFT PANEL INTERFACE .................................................................................................................................................. 219 10.10. INTERRUPT CONTROLLER .......................................................................................................................................... 219 10.11. PROGRAMMING MODEL ............................................................................................................................................. 219 10.11.1. Summary of LCD Control Registers ............................................................................................................ 219 10.11.2. Register Description ........................................................................................................................................ 221

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10.11.3. LCD Timing and Polarity Parameter............................................................................................................. 226 10.11.4. LCD Output Format Parameters.................................................................................................................... 228 10.11.5. LCD Image Parameters.................................................................................................................................... 230 10.11.6. LCD Image Color Management...................................................................................................................... 232 10.11.7. LCD Gamma Correction .................................................................................................................................. 233 10.11.8. Scalar Control Registers ................................................................................................................................. 235 10.11.9. OSD Control Registers .................................................................................................................................... 238 10.11.10. LCD Horizontal Timing Control (Offset == 0x00).................................................................................. 240 10.11.11. LCD Vertical Timing Control (Offset == 0x04) ....................................................................................... 241 10.11.12. LCD Clock and Signal Polarity Control (Offset == 0x08) ................................................................... 242 10.11.13. LCD Panel Frame Base Address (Offset == 0x10) ............................................................................... 243 10.11.14. LCD Interrupt Enable Mask (Offset == 0x18) ......................................................................................... 243 10.11.15. LCD Panel Pixel Parameters (Offset == 0x1C) ...................................................................................... 243 10.11.16. LCD Interrupt Status Clear (Offset == 0x20) .......................................................................................... 244 10.11.17. LCD Interrupt Status (Offset == 0x24) ..................................................................................................... 245 10.11.18. OSD Scaling and Dimension Control (Offset == 0x34) ....................................................................... 245 10.11.19. OSD Position Control (Offset == 0x38) ................................................................................................... 246 10.11.20. OSD Foreground Color Control (Offset == 0x3C) ................................................................................ 246 10.11.21. OSD Background Color Control (Offset == 0x40) ................................................................................ 246 10.11.22. GPI/GPO Control (Offset == 0x44)............................................................................................................ 247 10.11.23. LCD Palette RAM Accessing Port (Offset == 0x200 ~ 0x3FC)........................................................... 247 10.11.24. OSD Font Database Write Accessing Port (Offset == 0x8000 ~ 0xBFFC) ...................................... 248 10.11.25. OSD Window Attribute Write Accessing Port (Offset == 0xC000 ~ 0xC7FC) ................................ 249 10.12. APPLICATION .............................................................................................................................................................. 249 11. ETHERNET 10/100 CONTROLLER .............................................................................................................................. 250 11.1. OVERVIEW ....................................................................................................................................................................... 250 11.2. FUNCTIONAL BLOCK DESCRIPTION ................................................................................................................................ 251 11.2.1. AHB_MASTER ................................................................................................................................................... 251 11.2.2. AHB_SLAVE ....................................................................................................................................................... 251 11.2.3. DMA_ARBITER .................................................................................................................................................. 251 11.2.4. TXDMA ................................................................................................................................................................. 251 11.2.5. RXDMA................................................................................................................................................................. 252 11.2.6. TXMAC ................................................................................................................................................................. 252 11.2.7. RXMAC................................................................................................................................................................. 253 11.2.8. REGIST ................................................................................................................................................................ 254 11.2.9. PWR_MANAGE .................................................................................................................................................. 254 11.2.10. 10/100 T-Base Ethernet PHY .......................................................................................................................... 254 11.3. MAC FUNCTION DESCRIPTION ....................................................................................................................................... 257 11.3.1. Half-Duplex (CSMA/CD Access Protocol) ................................................................................................... 257 11.3.2. Full-Duplex Ethernet ........................................................................................................................................ 258 11.3.3. Loop Back ........................................................................................................................................................... 259 11.3.4. Transmit Descriptors and Data Buffers ...................................................................................................... 259 11.3.5. Receive Descriptors and Data Buffers ........................................................................................................ 260 11.3.6. Transmitting Packets ....................................................................................................................................... 263 11.3.7. Receiving Packets ............................................................................................................................................ 263 11.3.8. Zero-Copy ........................................................................................................................................................... 263 11.3.9. Ethernet Address Filtering ............................................................................................................................. 264 11.3.10. DMA Arbitration Scheme................................................................................................................................. 265 11.3.11. Wake-On-LAN .................................................................................................................................................... 266 11.3.11.1. Link Status Change ........................................................................................................................................... 266 11.3.11.2. Magic Packet .................................................................................................................................................... 266 11.3.12. Power Down Mode ............................................................................................................................................ 267 11.4. FLOW CONTROL.............................................................................................................................................................. 267

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11.5. PROGRAMMING MODEL .................................................................................................................................................. 268 11.5.1. Summary of the MAC Controller Registers ................................................................................................ 268 11.5.2. Register Descriptions ...................................................................................................................................... 269 11.5.3. Phy Register Description ................................................................................................................................ 287 11.6. PROGRAMMING GUIDE .................................................................................................................................................... 293 11.6.1. PHY Configuration ............................................................................................................................................ 293 11.6.2. Frame Transmitting Procedure ..................................................................................................................... 293 11.6.3. Frame Receiving Procedure........................................................................................................................... 294 11.6.4. Procedures to enter and exit the power down mode .............................................................................. 295 11.7. APPLICATION ................................................................................................................................................................... 296 12. AES-DES ENGINE (AES-DES) ...................................................................................................................................... 298 12.1. OVERVIEW ....................................................................................................................................................................... 298 12.1.1. AHB Slave and Control Register................................................................................................................... 299 12.1.2. AHB Master......................................................................................................................................................... 299 12.1.3. DMA Engine ........................................................................................................................................................ 299 12.1.4. Data FIFO ............................................................................................................................................................ 299 12.1.5. Security Engine ................................................................................................................................................. 300 12.2. MEMORY MAP / REGISTER DEFINITION .......................................................................................................................... 300 12.3. REGISTER DESCRIPTIONS............................................................................................................................................... 301 12.3.1. Encryption Control Register (offset==0x00 EncryptControl) ................................................................ 301 12.3.2. Reserved Register (offset==0x04 Reserved) ............................................................................................. 302 12.3.3. FIFO Status Register (offset==0x08 FIFOStatus)...................................................................................... 302 12.3.4. Parity Error Register (offset==0x0c PErrStatus) ....................................................................................... 302 12.3.5. Security Key N Register (offset == 0x10 ~ 0x2c)....................................................................................... 302 12.3.6. Initial Vector N Register (offset==0x30 ~ 0x3c) ......................................................................................... 302 12.3.7. Reserved Register (offset==0x40 Reserved) ............................................................................................. 303 12.3.8. Reserved Register (offset==0x44 Reserved) ............................................................................................. 303 12.3.9. DMA Source Address Register (offset==0x48 DMASrc) ......................................................................... 303 12.3.10. DMA Destination Address Register (offset==0x4c DMADes) ................................................................ 303 12.3.11. DMA Transfer Size Register (offset==0x50 DMATrasSize) ..................................................................... 303 12.3.12. DMA Control Register (offset==0x54 DMACtrl) ......................................................................................... 303 12.3.13. FIFO Threshold Register (offset==0x58 FIFOThold) ................................................................................ 304 12.3.14. Interrupt Enable Register (offset==0x5c IntrEnable) ............................................................................... 304 12.3.15. Interrupt Source Register (offset==0x60 IntrSrc) ..................................................................................... 304 12.3.16. Masked Interrupt Status (offset==0x64 MaskedIntrStatus) .................................................................... 305 12.3.17. Interrupt Clear Register (offset==0x68 IntrClr) .......................................................................................... 305 12.3.18. Revision Register (offset==0x70 REVISION).............................................................................................. 305 12.3.19. Feature Register (offset==0x74 FEATURE) ................................................................................................ 305 12.3.20. Last Initial Vector N Register (offset==0x80 ~ 0x8c) ................................................................................ 305 12.3.21. Initialization / Application Information ........................................................................................................ 306 13. USB 2.0 OTG CONTROLLER (USBC) ........................................................................................................................ 310 13.1. OVERVIEW ....................................................................................................................................................................... 310 13.2. ARCHITECTURE OVERVIEW ............................................................................................................................................ 312 13.2.1. DMA Controller .................................................................................................................................................. 312 13.2.2. Host Controller .................................................................................................................................................. 313 13.2.3. Register Files ..................................................................................................................................................... 314 13.2.4. Microprocessor Interface Controller............................................................................................................ 315 13.2.5. FIFO Controller .................................................................................................................................................. 315 13.2.6. Device Endpoint 0 Control Transfer Controller (CXF) ............................................................................. 317 13.2.7. Parallel Interface Engine (PIE) ....................................................................................................................... 318 13.2.8. OTG Bus Monitor .............................................................................................................................................. 319 13.2.9. Register Files (RGF) ......................................................................................................................................... 321
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13.2.10. Power Management and Speed Emulation (PWE).................................................................................... 321 13.2.11. AHB SPLIT-Capable Slave (HBS) .................................................................................................................. 322 13.2.12. AHB Buffer (HBF) .............................................................................................................................................. 322 13.2.13. AHB Buffer Controller (BFC) .......................................................................................................................... 323 13.3. USB RESET AND POWER SAVING MODE ....................................................................................................................... 323 13.3.1. USB Reset ........................................................................................................................................................... 323 13.4. POWER SAVING MODE .................................................................................................................................................... 324 13.5. PROGRAMMING MODEL .................................................................................................................................................. 328 13.5.1. Summary of the USBC Registers.................................................................................................................. 328 13.5.2. General Registers and Function ................................................................................................................... 328 13.5.3. On-The-Go Controller Register (Address = 080h ~ 0BFh) ...................................................................... 336 13.5.4. Global Controller Register (Address = 0C0h ~ 0FFh) .............................................................................. 340 13.5.5. Device Controller Registers (Address = 100h ~ 1FFh) ............................................................................ 341 13.5.6. In Endpoint x MaxPacket Size Register (One per Endpoint, x = 1 ~ 8) ............................................... 353 (Address = 160 + 4(x-1)h) ................................................................................................................................................... 353 13.5.7. OUT Endpoint x MaxPacketSize Register (One per Endpoint, x = 1 ~ 8) ............................................ 354 (Address = 180 + 4(x-1)h) ................................................................................................................................................... 354 13.5.8. Endpoint 1 ~ 4 Map Register (Address = 1A0h) ........................................................................................ 354 13.5.9. Endpoint 5 ~ 8 Map Register (Address = 1A4h) ........................................................................................ 355 13.5.10. FIFO Map Register (Address = 1A8h) .......................................................................................................... 355 13.5.11. FIFO Configuration (Address = 1ACH) ........................................................................................................ 356 13.5.12. FIFO x Instruction and Byte Count Register (One per FIFO, x = 0 ~ 3) ............................................... 358 (Address = 1B0 + 4xh) ........................................................................................................................................................ 358 13.5.13. DMA Target FIFO Number Register (Address = 1C0h) ............................................................................ 359 13.5.14. DMA Controller Parameter Setting 1 Register (Address = 1C8h) ......................................................... 359 13.5.15. DMA Controller Parameter Setting 2 Register (Address = 1CCh) ........................................................ 361 13.5.16. DMA Controller Parameter Setting 3 Register (Address = 1D0h) ......................................................... 361 13.5.17. DMA Controller Status Register (Address = 1D4h) .................................................................................. 361 13.6. USB OTG PHY .............................................................................................................................................................. 362 13.6.1. PLL and Clock Control .................................................................................................................................... 363 13.6.2. Receive Logic .................................................................................................................................................... 363 13.6.3. Transmit Logic ................................................................................................................................................... 366 13.6.4. Modes .................................................................................................................................................................. 368 13.6.5. Speed Selection ................................................................................................................................................ 368 13.6.6. UTMI+ level 2 ...................................................................................................................................................... 368 13.6.7. LS Keep-Alive Generation .............................................................................................................................. 369 13.6.8. UTMI+ level 3 ...................................................................................................................................................... 369 13.6.9. Line State ............................................................................................................................................................ 370 13.6.10. Electrical Specifications ................................................................................................................................. 370 13.7. APPLICATION ................................................................................................................................................................... 374 14. MEDIACODEC .................................................................................................................................................................. 376 14.1. OVERVIEW ....................................................................................................................................................................... 376 14.1.1. AHB Interface ..................................................................................................................................................... 377 14.1.2. DMA ...................................................................................................................................................................... 377 14.1.3. Motion Estimation ............................................................................................................................................. 377 14.1.4. DCT/IDCT............................................................................................................................................................. 378 14.1.5. Quantization/Inverse Quantization ............................................................................................................... 378 14.1.6. AC/DC Prediction .............................................................................................................................................. 378 14.1.7. Zigzag Scan ........................................................................................................................................................ 378 14.1.8. Variable Length Coding/Decoding ............................................................................................................... 378 14.1.9. Motion Compensation ..................................................................................................................................... 378 14.1.10. Local Memory Controller ................................................................................................................................ 378 14.2. MODES OF OPERATION ................................................................................................................................................... 384

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14.3. PROGRAMMING ............................................................................................................................................................... 385 14.3.1. ME Control Register (MECTL, Offset ==0x20000) ..................................................................................... 387 14.3.2. ME Coefficient Register (MECR, Offset == 0x20008) ............................................................................... 387 14.3.3. Minimum SAD Result Register (MIN_SAD, Offset == 0x2000C) ............................................................. 387 14.3.4. ME Command Queue Start Address Register (CMDADDR, Offset == 0x20010) .............................. 388 14.3.5. ME Current and Result Block Start Address Register (MECADDR, Offset == 0x20014)................. 388 14.3.6. Horizontal Offset Register (HOFFSET, Offset == 0x20018) .................................................................... 388 14.3.7. MC Control Register (MCCTL, Offset == 0x2001C) .................................................................................. 388 14.3.8. MC Interpolation Block Start Address Register (MEIADDR, Offset == 0x20024) .............................. 390 14.3.9. Coprocessor Status Register (CPSTS, Offset ==0x20028) ..................................................................... 390 14.3.10. Quantization Coefficient Register 0 (QCR0, Offset == 0x2002C) .......................................................... 392 14.3.11. De-Zigzag Scan Buffer Address/Quantization Block Address Register (DZAR/QAR, Offset == 0x20038) 392 14.3.12. ACDC Predictor Buffer Address Register (ACDCPBAR, Offset == 0x20040) .................................... 392 14.3.13. VLC/VLD Data Address Register (VADR, Offset == 0x20044) ................................................................ 392 14.3.14. ME Current Block Deviation Register (CURDEV, Offset == 0x20048) .................................................. 393 14.3.15. Bit-Stream Access Data Register (BADR, Offset == 0x2004C) .............................................................. 393 14.3.16. Bit-Stream Access Length Register/Auto-buffering Local Memory Pointer (BALR/ABLP, Offset == 0x20050)............................................................................................................................................................................ 393 14.3.17. MC Interpolation and Result Block Start Address Register (MCIADDR, Offset == 0x20058) ..... 394 14.3.18. VLD Control Register (VLDCTL, Offset == 0x2005C) ............................................................................... 394 14.3.19. VOP Parameter 0 Register (VOP0, Offset == 0x20060) ............................................................................ 395 14.3.20. VOP Parameter 1 Register (VOP1, Offset == 0x20064) ............................................................................ 395 14.3.21. Differential Motion Vector 0/Start Code Register (MVD0/SCODE, Offset == 0x20068) .................... 395 14.3.22. Differential Motion Vector 1/Re-sync Marker Register (MVD1/RSMRK, Offset == 0x2006C) ...... 395 14.3.23. VLD Table Output Address (TOADR, Offset == 0x20070) ....................................................................... 396 14.3.24. VLD Status Register (VLDSTS, Offset == 0x20074).................................................................................. 398 14.3.25. Auto-Buffer System Data Address (ABADR, Offset == 0x20078) ......................................................... 399 14.3.26. Inner CPU Control Register (INNER_CPUCTL, Offset == 0x2007C) ..................................................... 399 14.3.27. VOP Size Register (VOP_SIZE, Offset == 0x20080) .................................................................................. 400 14.3.28. Prediction MV Buffer Start Address Register (PMVADDR, Offset == 0x20084)................................. 400 14.3.29. Image Output Format Select Register (DTOFMT, Offset == 0x20088) ................................................. 400 14.3.30. Inner CPU Interrupt Mask Register (INNER_MASK, Offset == 0x20090)............................................. 401 14.3.31. External CPU Interrupt Mask Register (EXT_MASK, Offset == 0x20094) ........................................... 401 14.3.32. Interrupt Flag (after masked) Register (INT_FLAG, Offset == 0x20098) ............................................ 402 14.3.33. Interrupt Status (before masked) Register (INT_STS, Offset == 0x2009C) ........................................ 403 14.3.34. Minimum Coded Unit Block Number Register (MCUBR, Offset == 0x20008) .................................... 403 14.3.35. Minimum Coded Unit Table Index Register (MCUTIR, Offset == 0x2002C) ........................................ 403 14.3.36. JPEG Previous Y DC Value Register (PYDCR, Offset == 0x20030) ...................................................... 404 14.3.37. JPEG Previous UV DC Value Register (PUVDCR, Offset == 0x20034) ................................................ 404 14.3.38. VLD Look Up Table Register (VLDLUTR, Offset == 0x20068) ................................................................ 404 14.3.39. VLC Last Word Register (VLASTWORD, Offset == 0x2006C) ................................................................ 405 14.3.40. JPEG Sequencer Control register (JPGSeqCtl, Offset == 0x200A0) ................................................... 405 14.3.41. JPEG Frame Information Register 1 (JPGFrmInfo1, Offset == 0x200A4) ........................................... 405 14.3.42. JPEG Frame Information Register 2 (JPGFrmInfo2, Offset == 0x200A8) ........................................... 406 14.3.43. JPEG Frame Information Register 3 (JPGFrmInfo3, Offset == 0x200AC) .......................................... 406 14.4. ME COMMAND DEFINITIONS ........................................................................................................................................... 406 14.4.1. ME Buffer Structure .......................................................................................................................................... 406 14.4.2. DMA Control Registers .................................................................................................................................... 413 14.4.3. DMA System Memory Base Address Register (Offset == 0x20400) ..................................................... 414 14.4.4. DMA Local Memory Base Address Register/Block Width Register, Offset == 0x20404) ................ 414 14.4.5. DMA Block Width Register (Offset == 0x20408) ........................................................................................ 415 14.4.6. DMA Control and Length Register (Offset == 0x2040C) ......................................................................... 415 14.4.7. DMA Chain Command Address Register (Offset == 0x20410) .............................................................. 417

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14.4.8. 14.4.9. 14.4.10. 14.4.11. 14.4.12. 14.4.13. 14.4.14. 14.4.15. 14.4.16. 14.4.17. 15.

DMA Status Register (Offset == 0x20414)................................................................................................... 417 DMA Group Control Register (Offset == 0x2041C) .................................................................................. 417 DMA Group Sync Register (Offset == 0x20420) ........................................................................................ 417 DMA Auto-buffer Control Register (Offset == 0x20424) .......................................................................... 418 DMA Threshold Value Register (Offset== 0x20428) ................................................................................. 418 DMA Auto Interrupt Register (Offset: 0x2042c) ......................................................................................... 418 System Bitstream Buffer Size (Offset ==0x20430) ................................................................................... 419 JPEG Frame Information Register 4 (JPGFrmInfo4, Offset == 0x20434) ............................................ 419 JPEG Frame Information Register 5 (JPGFrmInfo5, Offset == 0x20438) ............................................ 419 JPEG Frame Information Register 6 (JPGFrmInfo6, Offset == 0x2043C) ........................................... 420

VIDEO CAPTURE ............................................................................................................................................................. 421

15.1. GENERAL DESCRIPTION ................................................................................................................................................. 421 15.2. VIDEO PORT .................................................................................................................................................................... 422 15.2.1. ITU-R BT. 656...................................................................................................................................................... 422 15.2.2. ITU-R BT. 656 like .............................................................................................................................................. 423 15.2.3. 8-/16-bit H/V Reference Control Interface ................................................................................................... 423 15.2.4. 8-/16-bit H/V Sync Control Interface ............................................................................................................. 424 15.3. DE-INTERLACER .............................................................................................................................................................. 425 15.4. DE-NOISE ........................................................................................................................................................................ 425 15.5. SIZE-DOWN ...................................................................................................................................................................... 425 15.6. OSD ................................................................................................................................................................................ 426 15.7. COLOR SPACE CONVERSION .......................................................................................................................................... 426 15.8. WINDOW CLIP ................................................................................................................................................................. 426 15.9. VBI EXTRACTION ............................................................................................................................................................ 426 15.10. DMA ........................................................................................................................................................................... 426 15.11. VIDEO DATA OUTPUT FORMAT .................................................................................................................................. 426 15.11.1. RGB888................................................................................................................................................................ 426 15.11.2. RGB565................................................................................................................................................................ 426 15.11.3. YCbCr 4:4:4 ........................................................................................................................................................ 426 15.11.4. YCbCr 4:2:2 ........................................................................................................................................................ 426 15.11.5. Macro Block Order Sequence ........................................................................................................................ 427 15.11.6. Macro Block 16 x 16 ......................................................................................................................................... 427 15.11.7. Macro Block 8 x 8.............................................................................................................................................. 428 15.11.8. Macro Block 4 x 4.............................................................................................................................................. 428 15.11.9. Two-split Memory Block.................................................................................................................................. 429 15.12. PROGRAMMING MODEL ............................................................................................................................................. 429 15.12.1. Summary of Video Capture Block Registers ............................................................................................. 429 15.12.2. Capture Control Register (Offset= 0x0000) ................................................................................................ 432 15.12.3. VCAPUPD Register (Offset = 0x0004) .......................................................................................................... 433 15.12.4. CAPCLK Register (Offset = 0x0008)............................................................................................................. 434 15.12.5. PVSIZE0 Register (Offset = 0x0010) ............................................................................................................. 434 15.12.6. PVSIZE1 (Offset = 0x0014) .............................................................................................................................. 435 15.12.7. PVSIZE2 Register (Offset = 0x0018) ............................................................................................................. 435 15.12.8. RCSIZE0 Register (Offset = 0x0020) ............................................................................................................ 435 15.12.9. RCSIZE1 Register (Offset = 0x024)............................................................................................................... 435 15.12.10. RCSIZE2 Register (Offset = 0x0028) ........................................................................................................ 436 15.12.11. BORDER_SIZE Register (Offset = 0x0030) ............................................................................................ 436 15.12.12. BORDER_COLOR Register (Offset = 0x0034) ....................................................................................... 437 15.12.13. DESTFORMAT Register (Offset = 0x0038) ............................................................................................. 437 15.12.14. FMRATE Register (Offset = 0x0040) ........................................................................................................ 439 15.12.15. SRCIF Register (Offset = 0x0044)............................................................................................................. 440 15.12.16. SRCSIZE0 Register (Offset = 0x0050) ..................................................................................................... 442 15.12.17. PVSIZE3 Register (Offset = 0x0054) ........................................................................................................ 442

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15.12.18. 15.12.19. 15.12.20. 15.12.21. 15.12.22. 15.12.23. 15.12.24. 15.12.25. 15.12.26. 15.12.27. 15.12.28. 15.12.29. 15.12.30. 15.12.31. 15.12.32. 15.12.33. 15.12.34. 15.12.35. 15.12.36. 15.12.37. 15.12.38. 15.12.39. 15.12.40. 15.12.41. 15.12.42. 15.12.43. 15.12.44. 15.12.45. 15.12.46. 15.12.47. 15.12.48. 15.12.49. 15.12.50. 15.12.51. 15.12.52. 15.12.53. 15.12.54. 15.12.55. 15.12.56. 15.12.57. 15.12.58. 15.12.59. 15.12.60. 15.12.61. 15.12.62. 15.12.63. 15.12.64. 15.12.65. 15.12.66. 15.12.67. 15.12.68. 15.12.69. 15.12.70. 15.12.71.

PVSIZE4 Register (Offset = 0x0058) ........................................................................................................ 442 SRCSIZE1 Register (Offset = 0x0060) ..................................................................................................... 442 RCSIZE3 Register (Offset = 0x0064) ........................................................................................................ 443 RCSIZE4 Register (Offset = 0x0068) ........................................................................................................ 443 DICTRL0 Register (Offset = 0x01D0) ....................................................................................................... 443 DICTRL1 Register (Offset = 0x01D4) ....................................................................................................... 444 DNCTRL0 Register (Offset = 0x01E0) ..................................................................................................... 444 DNCTRL1 Register (Offset = 0x01E4) ..................................................................................................... 444 DNCTRL2 Register (Offset = 0x01EC) ..................................................................................................... 444 PDMA0 Register (Offset = 0x0200)........................................................................................................... 445 RDMA0 Register (Offset = 0x0204) .......................................................................................................... 446 MEMSRC0 Register (Offset == 0x0208) .................................................................................................. 447 MEMSRC1 Register (Offset = 0x020C) .................................................................................................... 447 MEMSRC2 Register (Offset = 0x0210)..................................................................................................... 447 PDMA1 Register (Offset = 0x0218)........................................................................................................... 447 RDMA1 Register (Offset = 0x021C) .......................................................................................................... 448 PMDEST0 Register (Offset = 0x0220) ...................................................................................................... 448 PMDEST1 Register (Offset = 0x0224) ...................................................................................................... 448 PMDEST2 Register (Offset = 0x0230) ...................................................................................................... 448 PMDEST3 Register (Offset = 0x0234) ...................................................................................................... 448 PMDEST4 Register (Offset = 0x0240) ...................................................................................................... 449 PMDEST5 Register (Offset = 0x0244) ...................................................................................................... 449 RMDEST0 Register (Offset = 0x0250) ..................................................................................................... 449 RMDEST1 Register (Offset = 0x0254) ..................................................................................................... 449 RMDEST2 Register (Offset = 0x0260) ..................................................................................................... 450 RMDEST3 Register (Offset = 0x264)........................................................................................................ 450 RMDEST4 Register (Offset = 0x0270) ..................................................................................................... 450 RMDEST5 Register (Offset = 0x0274) ..................................................................................................... 450 VBICTRL0 Register (Offset = 0x0290) ..................................................................................................... 450 VBICTRL1 Register (Offset = 0x0294) ..................................................................................................... 450 VBICTRL2 Register (Offset = 0x02A0) .................................................................................................... 450 VBICTRL3 Register (Offset = 0x02B0) .................................................................................................... 451 OSDFONT Register (Offset = 0x0300) .................................................................................................... 451 OSDDISP Register (Offset = 0x0304) ....................................................................................................... 451 OSDREAD Register (Offset = 0x0308)..................................................................................................... 452 OSDEN Register (Offset = 0x030C) .......................................................................................................... 452 OSDPAT0 Register (Offset = 0x0310) ...................................................................................................... 452 OSDPAT1 Register (Offset = 0x0314) ...................................................................................................... 453 OSDPAT2 Register (Offset = 0x0318) ...................................................................................................... 453 OSDPAT3 Register (Offset = 0x031C)...................................................................................................... 453 OSDPAT4 Register (Offset = 0x0320) ...................................................................................................... 453 OSDPAT5 Register (Offset = 0x0324) ...................................................................................................... 454 OSDPAT6 Register (Offset = 0x0328) ...................................................................................................... 454 OSDCOR0 Register (Offset = 0x0330) ..................................................................................................... 454 OSDWSZ0 Register (Offset = 0x0334) ..................................................................................................... 455 OSDSSZ0 Register (Offset = 0x0338) ...................................................................................................... 455 OSDFSZ0 Register (Offset = 0x033C) ..................................................................................................... 455 OSDCOR1 Register (Offset = 0x0340) ..................................................................................................... 455 OSDWSZ1 Register (Offset = 0x0344) ..................................................................................................... 456 OSDSSZ1 Register (Offset = 0x0348) ...................................................................................................... 456 OSDFSZ1 Register (Offset = 0x034C) ..................................................................................................... 456 OSDCOR2 Register (Offset = 0x0350) ..................................................................................................... 456 OSDWSZ2 Register (Offset = 0x0354) ..................................................................................................... 457 OSDSSZ2 Register (Offset = 0x0358) ...................................................................................................... 457

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OSDFSZ2 Register (Offset = 0x035C) ..................................................................................................... 458 OSDCOR3 Register (Offset = 0x0360) ..................................................................................................... 458 OSDWSZ3 Register (Offset = 0x0364) ..................................................................................................... 458 OSDSSZ3 Register (Offset = 0x0368) ...................................................................................................... 459 OSDFSZ3 Register (Offset = 0x036C) ..................................................................................................... 459 INTSTS Register (Offset = 0x03E0) .......................................................................................................... 459 INTMASK Register (Offset = 0x03E4) ...................................................................................................... 459 TEST_MODE0 Register (Offset = 0x03F0) .............................................................................................. 460

AHB TO APB BRIDGE (APB BRIDGE) ........................................................................................................................ 463

16.1. GENERAL DESCRIPTION ................................................................................................................................................. 463 16.2. CONTROL REGISTER ....................................................................................................................................................... 463 16.3. PROGRAMMING MODEL .................................................................................................................................................. 464 16.3.1. Summary of the APB Bridge Registers ....................................................................................................... 464 16.3.2. Register Descriptions ...................................................................................................................................... 464 17. PERIPHERAL INTERRUPT CONTROLLER (PINTC) ................................................................................................ 466 17.1. GENERAL DESCRIPTION ................................................................................................................................................. 466 17.2. APB ................................................................................................................................................................................ 466 17.3. CONFIGURATION REGISTER BLOCK ............................................................................................................................... 467 17.4. INTERRUPT DETECT BLOCK ........................................................................................................................................... 467 17.5. INTERRUPT ROUTING TABLE .......................................................................................................................................... 467 17.6. PROGRAMMING MODEL .................................................................................................................................................. 471 17.6.1. Summary of Interrupt Controller Registers ............................................................................................... 471 17.6.2. Register Descriptions ...................................................................................................................................... 471 17.6.3. Programming Sequence ................................................................................................................................. 474 18. GENERAL PURPOSE INPUT / OUTPUT (GPIO) ....................................................................................................... 475 18.1. GENERAL DESCRIPTION ................................................................................................................................................. 475 18.2. PROGRAMMING MODEL .................................................................................................................................................. 476 18.2.1. Summary of General Purpose I/O Registers .............................................................................................. 476 18.2.2. Register Descriptions ...................................................................................................................................... 480 18.3. TIMING ............................................................................................................................................................................. 484 18.3.1. Write to GpioDataOut Register ...................................................................................................................... 484 18.3.2. Positive Edge Trigger ...................................................................................................................................... 484 18.3.3. Level High Trigger ............................................................................................................................................ 484 18.4. PROGRAMMING SEQUENCE ............................................................................................................................................ 484 19. PULSE WIDTH MODULATORS (PWMS) ..................................................................................................................... 486 19.1. OVERVIEW ....................................................................................................................................................................... 486 19.1.1. APB Slave ........................................................................................................................................................... 486 19.1.2. PWM Channels .................................................................................................................................................. 487 19.1.3. Counters and Comparators ............................................................................................................................ 487 19.1.4. Control Registers .............................................................................................................................................. 487 19.2. PROGRAMMING MODEL .................................................................................................................................................. 488 19.2.1. Summary of PWM Registers .......................................................................................................................... 488 19.2.2. Register Descriptions ...................................................................................................................................... 488 19.3. PULSE WIDTH MODULATOR OUTPUT SIGNAL EXAMPLES ............................................................................................ 493 20. I2C BUS INTERFACE CONTROLLER ......................................................................................................................... 495 GENERAL DESCRIPTIONS ............................................................................................................................................... 495 REGISTER FILES ............................................................................................................................................................. 496 CONTROL LOGIC ............................................................................................................................................................. 496 SCLOUT GENERATOR .................................................................................................................................................... 496
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20.5. DE-BOUNCE CIRCUIT...................................................................................................................................................... 496 20.6. PROGRAMMING MODEL .................................................................................................................................................. 496 20.6.1. Summary of I2C Controller Registers .......................................................................................................... 496 20.6.2. Register Descriptions ...................................................................................................................................... 496 20.7. PROGRAMMING SEQUENCE ............................................................................................................................................ 501 20.7.1. Slave Mode Data Write Programming Sequence ...................................................................................... 501 20.7.2. Slave Mode Data Read Programming Sequence ...................................................................................... 501 20.7.3. Master Mode Data Write Programming Sequence ................................................................................... 501 20.7.4. Master Mode Data Read Programming Guide ........................................................................................... 502 21. WATCH DOG TIMER (WDT) ........................................................................................................................................... 504 21.1. GENERAL DESCRIPTIONS ............................................................................................................................................... 504 21.2. PROGRAMMING MODEL .................................................................................................................................................. 505 21.2.1. Summary of WDT Registers ........................................................................................................................... 505 21.2.2. Register Descriptions ...................................................................................................................................... 505 21.3. TIMING ............................................................................................................................................................................. 507 21.3.1. Write to WdLoad Register............................................................................................................................... 507 21.4. WRITE TO WDLOAD REGISTER ...................................................................................................................................... 507 21.5. PROGRAMMING SEQUENCE ............................................................................................................................................ 508 22. TIMER/COUNTERS.......................................................................................................................................................... 509 22.1. OVERVIEW ....................................................................................................................................................................... 509 22.2. TIMER INPUT/OUTPUT BLOCK ........................................................................................................................................ 510 22.3. GENERAL PURPOSE TIMER/COUNTER REGISTER SUMMARY ....................................................................................... 512 22.3.1. Global Mode Register ...................................................................................................................................... 513 22.3.2. Timer/Counter Input/Output Mode Register ............................................................................................... 515 22.3.3. Timer/Counter Input/Output Polarity Selection Register........................................................................ 516 22.3.4. Global Trigger Register ................................................................................................................................... 517 22.3.5. Interrupt Status Register................................................................................................................................. 518 22.3.6. Prescaler ............................................................................................................................................................. 519 22.4. TIMER/COUNTER BLOCK ................................................................................................................................................ 520 22.4.1. Timer/Counter Registers ................................................................................................................................. 521 22.4.2. Reload Register ................................................................................................................................................. 524 22.4.3. Current Time Register ..................................................................................................................................... 524 22.4.4. Sample Time Register ...................................................................................................................................... 525 22.4.5. Status and Interrupt Clear Register ............................................................................................................. 525 22.5. TIMER/COUNTER OPERATION ......................................................................................................................................... 527 22.5.1. Basic Cyclic Timing.......................................................................................................................................... 527 22.5.2. External Triggering ........................................................................................................................................... 530 22.6. WATCHDOG OPERATION ................................................................................................................................................. 533 22.6.1. Single Cycle Operation.................................................................................................................................... 535 22.6.2. Chaining Multiple Timers ................................................................................................................................ 537 22.6.3. PWM Mode .......................................................................................................................................................... 540 23. REAL TIME CLOCK (RTC) ............................................................................................................................................. 546 GENERAL DESCRIPTIONS ............................................................................................................................................... 546 APB INTERFACE ............................................................................................................................................................. 547 RTC ALARM REGISTERS ................................................................................................................................................ 547 RTC CONTROL REGISTERS............................................................................................................................................ 547 RTC RECORD REGISTER................................................................................................................................................ 547 SYNC BLOCK .................................................................................................................................................................. 547 RTC COUNTER ............................................................................................................................................................... 548 RTC AUTO ALARM LOGIC .............................................................................................................................................. 548 RTC COMPARE LOGIC.................................................................................................................................................... 548
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23.10. FREQUENCY DIVIDER ................................................................................................................................................. 548 23.11. PROGRAMMING MODEL ............................................................................................................................................. 548 23.11.1. Summary Of Real Time Clock Registers..................................................................................................... 548 23.11.2. Register Descriptions ...................................................................................................................................... 549 23.12. TIMING ........................................................................................................................................................................ 554 23.12.1. Write to RtcSecond Register.......................................................................................................................... 554 23.12.2. Second Alarm..................................................................................................................................................... 554 23.12.3. Auto Second Alarm .......................................................................................................................................... 554 23.13. PROGRAMMING SEQUENCE ....................................................................................................................................... 554 24. SD MEMORY CARD HOST CONTROLLER (SDC) .................................................................................................... 555 24.1. GENERAL DESCRIPTIONS ............................................................................................................................................... 555 24.2. APB SLAVE .................................................................................................................................................................... 556 24.3. INTERRUPT LOGIC ........................................................................................................................................................... 556 24.4. DMA LOGIC .................................................................................................................................................................... 556 24.5. CLOCK DIVIDER .............................................................................................................................................................. 556 24.6. CRC CHECKER AND GENERATOR .................................................................................................................................. 557 24.7. CONTROLLER REGISTERS .............................................................................................................................................. 557 24.8. SD COMMAND / DATA UNIT ............................................................................................................................................ 557 24.9. FIFO................................................................................................................................................................................ 557 24.10. PROGRAMMING MODEL ............................................................................................................................................. 557 24.10.1. Summary of SD Host Controller Registers ................................................................................................ 557 24.10.2. Register Descriptions ...................................................................................................................................... 558 24.11. PROGRAMMING SEQUENCE ....................................................................................................................................... 565 25. COMPACT FLASH HOST INTERFACE CONTROLLER (CFC) ............................................................................... 567 25.1. GENERAL DESCRIPTIONS ............................................................................................................................................... 567 25.2. APB SLAVE .................................................................................................................................................................... 568 25.3. HOST CONTROLLER ........................................................................................................................................................ 568 25.4. ACTIVE BUFFER CONTROL ............................................................................................................................................. 568 25.5. PROGRAMMING MODEL .................................................................................................................................................. 569 25.5.1. Summary of CF Host Interface Controller Registers ............................................................................... 569 25.5.2. Register Descriptions ...................................................................................................................................... 569 25.6. DMA HANDSHAKING PROTOCOL ................................................................................................................................... 575 25.7. PROGRAMMING SEQUENCE ............................................................................................................................................ 576 25.7.1. Work flow of Active Buffer Controller .......................................................................................................... 576 26. UART AND IRDA CONTROLLER ................................................................................................................................. 578 26.1. GENERAL DESCRIPTIONS ............................................................................................................................................... 578 26.2. APB INTERFACE ............................................................................................................................................................. 580 26.3. PRESCALER .................................................................................................................................................................... 580 26.4. BAUD RATE GENERATOR ............................................................................................................................................... 580 26.5. TX FIFO AND RX FIFO ................................................................................................................................................... 580 26.6. STATUS FIFO .................................................................................................................................................................. 580 26.7. CONFIGURATION AND STATUS REGISTERS .................................................................................................................... 580 26.8. MODEM CONTROL AND FLAGS ....................................................................................................................................... 580 26.9. SIR LOGIC....................................................................................................................................................................... 581 26.10. FIR LOGIC .................................................................................................................................................................. 581 26.11. SIP GENERATOR ........................................................................................................................................................ 581 26.12. MODES OF OPERATION .............................................................................................................................................. 581 26.13. UART MODE .............................................................................................................................................................. 581 26.14. IRDA 1.3 SIR MODE .................................................................................................................................................. 583 26.15. IRDA 1.3 FIR MODE .................................................................................................................................................. 583 26.15.1. FIR Transmission Closing Method ............................................................................................................... 583
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26.15.2. FIR Data-Receive Method in PIO mode ....................................................................................................... 584 26.16. TX FIFO UNDERRUN IN FIR MODE ........................................................................................................................... 585 26.17. RX FIFO OVERRUN IN FIR MODE ............................................................................................................................. 585 26.18. ST FIFO OVERRUN IN FIR MODE.............................................................................................................................. 586 26.19. DMA OPERATION IN FIR MODE ................................................................................................................................ 586 26.20. DMA DATA-TRANSMIT MODE .................................................................................................................................... 586 26.21. DMA DATA-RECEIVE MODE ...................................................................................................................................... 586 26.22. PROGRAMMING MODEL ............................................................................................................................................. 587 26.22.1. Summary of UART and IrDA Communications Controller Registers .................................................. 587 26.22.2. Registers Descriptions .................................................................................................................................... 588 26.23. PROGRAMMING SEQUENCE ....................................................................................................................................... 606 26.23.1. SIR Mode ............................................................................................................................................................. 606 26.23.2. SIR Data Transmission Mode ........................................................................................................................ 607 26.23.3. FIR Mode ............................................................................................................................................................. 608 26.24. RS-232 INTERFACE ................................................................................................................................................... 610 26.25. INFRARED INTERFACE ................................................................................................................................................ 610 27. SYNCHRONOUS SERIAL PORT CONTROLLER (SSP/I2S/AC97) ........................................................................ 612 27.1. GENERAL DESCRIPTION ................................................................................................................................................. 612 27.2. APB INTERFACE ............................................................................................................................................................. 613 27.3. REGISTER BLOCK ........................................................................................................................................................... 613 27.4. INTERRUPT GENERATION CONTROL............................................................................................................................... 613 27.5. SERIAL CLOCK GENERATOR .......................................................................................................................................... 614 27.6. TRANSMIT / RECEIVE CONTROL ..................................................................................................................................... 614 27.7. SSP OPERATION............................................................................................................................................................. 614 27.7.1. SSP Reset ........................................................................................................................................................... 614 27.7.2. SSP Serial Clock Ratio and Bit Rate ............................................................................................................ 614 27.7.3. SSP Frame Format ............................................................................................................................................ 615 27.7.4. Texas Instrument SSP Frame Format .......................................................................................................... 615 27.7.5. Motorola SPI Frame Format ........................................................................................................................... 616 27.7.6. National Semiconductor Microwire Frame Format .................................................................................. 618 27.7.7. Philips I2S Frame Format ................................................................................................................................ 620 27.7.8. Intel AC-Link Frame Format ........................................................................................................................... 621 27.7.9. Transmit / Receive FIFO Read / Write .......................................................................................................... 624 27.8. DMA INTERFACE............................................................................................................................................................. 625 27.9. LOOP BACK MODE TESTING .......................................................................................................................................... 625 27.10. PROGRAMMING MODEL ............................................................................................................................................. 625 27.10.1. Summary of SSP Control Registers ............................................................................................................. 625 27.10.2. Register Descriptions ...................................................................................................................................... 626 27.11. PROGRAMMING GUIDELINE ........................................................................................................................................ 631 27.11.1. Master Mode Initialization ............................................................................................................................... 632 27.11.2. Slave Mode Initialization ................................................................................................................................. 632 28. DC CHARACTERISTICS................................................................................................................................................. 634 ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................... 634 RECOMMENDED OPERATING CONDITIONS ..................................................................................................................... 634 I/O PAD CAPACITANCE ................................................................................................................................................... 634 DC CHARACTERISTICS FOR XIN CRYSTAL ................................................................................................................... 634 DC CHARACTERISTICS FOR OSLIN CRYSTAL .............................................................................................................. 634 CHARACTERISTICS FOR 25 MHZ (ETHERNET PHY)...................................................................................................... 635 CHARACTERISTICS FOR 12 MHZ (USB OTG PHY) ..................................................................................................... 635 DC CHARACTERISTICS FOR 3.3V I/O PINS ................................................................................................................... 635 DC CHARACTERISTICS FOR 2.5 V I/O PINS................................................................................................................... 635 DC CHARACTERISTICS FOR 1.8 V I/O PINS .............................................................................................................. 636
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28.11. POWER CONSUMPTION .............................................................................................................................................. 637 28.12. DC CHARACTERISTICS FOR PLLS ........................................................................................................................... 637 28.13. DC CHARACTERISTICS FOR DLL .............................................................................................................................. 638 28.14. USB OTG PHY ......................................................................................................................................................... 640 28.14.1. Electrical characteristics ................................................................................................................................ 640 28.14.2. Static Characteristics: Analog I/O Pins (DP/DM) ...................................................................................... 640 28.14.3. Dynamic Characteristics: Analog I/O Pins (DP/DM)................................................................................ 641 28.15. POWER CONSUMPTION .............................................................................................................................................. 642 28.16. ESD AND LATCHUP .................................................................................................................................................... 643 29. AC CHARACTERISTICS................................................................................................................................................. 644 29.1. AC TIMING FOR SDRAM INTERFACE ............................................................................................................................ 644 29.2. AC TIMING FOR SMC INTERFACE .................................................................................................................................. 644 29.2.1. Write Cycle ......................................................................................................................................................... 644 29.2.2. Read Cycle .......................................................................................................................................................... 645 29.3. AC TIMING FOR I2C INTERFACE ..................................................................................................................................... 645 29.4. AC TIMING FOR SD CARD INTERFACE .......................................................................................................................... 646 29.5. AC TIMING FOR CCIT-656 INPUT .................................................................................................................................. 646 29.6. AC TIMING FOR CCIT-656 OUTPUT .............................................................................................................................. 647 29.7. AC TIMING FOR SONY 16-BIT YUV INPUT ..................................................................................................................... 647 29.8. AC TIMING FOR AC97 INTERFACE ................................................................................................................................. 647 29.8.1. Cold Reset .......................................................................................................................................................... 647 29.8.2. Warm Reset ........................................................................................................................................................ 647 29.8.3. AC Link Clock .................................................................................................................................................... 648 29.8.4. Data Input and Output ..................................................................................................................................... 648 29.8.5. Signal Rise and Fall Time ............................................................................................................................... 649 29.9. AC TIMING FOR I2S INTERFACE ..................................................................................................................................... 649 29.10. AC TIMING FOR ETHERNET PHY .............................................................................................................................. 650 30. ESD AND LATCHUP ........................................................................................................................................................ 651

FIGURE 1-1. FIGURE 1-2 FIGURE 1-3. FIGURE 1-4. FIGURE 1-5. FIGURE 1-6. FIGURE 1-7. FIGURE 1-8. FIGURE 1-9. FIGURE 1-10. FIGURE 4-1. FIGURE 5-1. FIGURE 5-2. FIGURE 5-3. FIGURE 5-4. FIGURE 5-5. FIGURE 5-6. FIGURE 5-7. FIGURE 5-8. FIGURE 5-9.
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BLOCK DIAGRAM OF AJ-200 ........................................................................................................................................... 5 AJILE JAVA RUNTIME FOR AJ-200 .................................................................................................................................... 7 M2M NETWORK EDGE DEVICES ..................................................................................................................................... 8 M2M CELLULAR TERMINALS.......................................................................................................................................... 8 IP CAMERA/ SURVEILLANCE SYSTEMS ............................................................................................................................ 9 WIRELESS SMART RFID READERS .................................................................................................................................. 9 WIRELESS GAMING DEVICES ........................................................................................................................................ 10 IPTVS............................................................................................................................................................................ 10 PERSONAL NAVIGATION DEVICES (PNDS) ................................................................................................................... 11 THIN CLIENTS ........................................................................................................................................................... 11 ADDRESS MEMORY MAP ............................................................................................................................................... 51 JEMBUILDER SYSTEM CONFIGURATION SCREEN .......................................................................................................... 76 CLOCK GENERATION AND DISTRIBUTION ............................................................................................................... 77 HIGH FREQUENCY CRYSTAL .......................................................................................................................................... 78 LOW FREQUENCY CRYSTAL ........................................................................................................................................... 78 EXTERNAL CLOCK SOURCE FOR 12 MHZ ...................................................................................................................... 79 EXTERNAL CLOCK SOURCE FOR 12 MHZ ...................................................................................................................... 79 25 MHZ CRYSTAL ......................................................................................................................................................... 79 EXTERNAL CLOCK SOURCE FOR 25 MHZ ...................................................................................................................... 80 BLOCK DIAGRAM OF ALL CLOCKS ASSOCIATED WITH SDRC ......................................................................................... 82
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FIGURE 5-10. FIGURE 5-11. FIGURE 5-12. FIGURE 5-13. FIGURE 5-14. FIGURE 6-1. FIGURE 6-2. FIGURE 6-3. FIGURE 6-4. FIGURE 6-5. FIGURE 6-6. FIGURE 6-7. FIGURE 6-8. FIGURE 7-1. FIGURE 8-1. FIGURE 8-2. FIGURE 8-3. FIGURE 8-4. FIGURE 8-5. FIGURE 8-6. FIGURE 8-7. FIGURE 9-1. FIGURE 9-2. FIGURE 9-3. FIGURE 9-4. FIGURE 9-5. FIGURE 9-6. FIGURE 9-7. FIGURE 9-8. FIGURE 9-9. FIGURE 9-10. FIGURE 9-11. FIGURE 9-12. FIGURE 9-13. FIGURE 9-14. FIGURE 9-15. FIGURE 9-16. FIGURE 9-17. FIGURE 9-18. FIGURE 9-19. FIGURE 9-20. FIGURE 9-21. FIGURE 9-22. FIGURE 9-23. FIGURE 9-24. FIGURE 9-25. FIGURE 9-26. FIGURE 9-27. FIGURE 9-28. FIGURE 9-29. FIGURE 9-30. FIGURE 9-31. FIGURE 9-32. FIGURE 9-33.

RESET LOGIC ............................................................................................................................................................ 83 POWER-ON RESET (POR) ......................................................................................................................................... 84 POR TIMING WAVEFORM ......................................................................................................................................... 85 COLD RESET TIMING WAVEFORM ............................................................................................................................. 85 BATTERY BACKUP FOR RTC ..................................................................................................................................... 87 JAVA PROCESSOR FUNCTIONAL BLOCK........................................................................................................................ 107 BLOCK DIAGRAM OF JEMCORE-II .............................................................................................................................. 108 MULTIPLE JVM MANAGEMENT (MJM)....................................................................................................................... 109 CACHE ORGANIZATION ............................................................................................................................................... 125 TEST CONTROL UNIT ................................................................................................................................................... 126 JEMCORE-II 1149.1 INTERFACE.................................................................................................................................. 127 DATA STRUCTURE FOR RESET SEQUENCE ..................................................................................................................... 129 DATA BLOCKS ............................................................................................................................................................. 132 BLOCK DIAGRAM OF AHB CONTROLLER .................................................................................................................... 134 DMA CONTROLLER FUNCTIONAL BLOCK DIAGRAM .................................................................................................. 139 ARBITRATION SCHEME ................................................................................................................................................ 141 CHAIN TRANSFER OPERATION ..................................................................................................................................... 142 LINKED LIST DESCRIPTOR ........................................................................................................................................... 142 EXAMPLE FOR THE HARDWARE HANDSHAKE MODE TRANSFER .................................................................................. 144 DMA HARDWARE HANDSHAKE PROTOCOL ................................................................................................................ 144 EXAMPLE FOR THE DMA NORMAL MODE TRANSFER ................................................................................................. 145 BLOCK DIAGRAM OF EBI ............................................................................................................................................ 163 BLOCK DIAGRAM OF STATIC MEMORY CONTROLLER .................................................................................................. 167 8-BIT ASYNCHRONOUS INTERFACE .............................................................................................................................. 167 16-BIT ASYNCHRONOUS INTERFACE ............................................................................................................................ 168 32-BIT ASYNCHRONOUS INTERFACE ............................................................................................................................ 168 NOR FLASH INTERFACE ............................................................................................................................................... 169 INTERFACE WITH A SYNCHRONOUS DEVICE.................................................................................................................. 169 CONNECTION SCHEME OF ZBT DEVICES ................................................................................................................. 170 32-BIT MEMORY CONNECTION .................................................................................................................................... 170 16-BIT MEMORY CONNECTION ............................................................................................................................... 171 8-BIT MEMORY CONNECTION ................................................................................................................................. 171 SIMPLIFIED BLOCK DIAGRAM OF THE NAND INTERFACE ...................................................................................... 173 COMMAND LATCH CYCLE ...................................................................................................................................... 174 ADDRESS LATCH CYCLE ......................................................................................................................................... 174 STATUS READ CYCLE.............................................................................................................................................. 175 INPUT DATA LATCH CYCLE ..................................................................................................................................... 175 SEQUENTIAL READ CYCLE ..................................................................................................................................... 176 READ 1 OPERATION CYCLE .................................................................................................................................... 176 READ 1 OPERATION CYCLE .................................................................................................................................... 177 ERASE CYCLE ......................................................................................................................................................... 177 INTERFACE BETWEEN AJ-200 AND NAND MEMORY............................................................................................... 178 TIMING DIAGRAM OF SMC WRITE TO ASYNCHRONOUS DEVICES............................................................................. 181 TIMING DIAGRAM OF SMC READ FROM ASYNCHRONOUS DEVICES ......................................................................... 182 TIMING DIAGRAM OF SMC WRITE TO SYNCHRONOUS EARLY WRITE DEVICES ......................................................... 184 TIMING DIAGRAM OF SMC WRITE TO SYNCHRONOUS EARLY WRITE DEVICES ......................................................... 184 TIMING DIAGRAM OF SMC WRITE TO SYNCHRONOUS LATE WRITE DEVICES ........................................................... 185 TIMING DIAGRAM OF SMC WRITE TO SYNCHRONOUS LATE WRITE DEVICES ........................................................... 185 TIMING DIAGRAM OF SMC WRITE TO SYNCHRONOUS LATE-LATE WRITE DEVICES .................................................. 185 TIMING DIAGRAM OF SMC WRITE TO SYNCHRONOUS LATE-LATE WRITE DEVICES .................................................. 185 TIMING DIAGRAM OF BURST ROMS ....................................................................................................................... 186 BLOCK DIAGRAM OF SDRAM CONTROLLER ......................................................................................................... 189 BASIC SDRAM ACCESS TIMING ............................................................................................................................ 192 32-BIT SDRAM MEMORY SYSTEM......................................................................................................................... 204

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FIGURE 9-34. FIGURE 10-1. FIGURE 10-2 FIGURE 10-3. FIGURE 10-4. FIGURE 10-5. FIGURE 10-6. FIGURE 10-7. FIGURE 10-8. FIGURE 10-9. FIGURE 10-10. FIGURE 11-1. FIGURE 11-2. FIGURE 11-3. FIGURE 11-4. FIGURE 11-5. FIGURE 11-6. FIGURE 11-7. FIGURE 11-8. FIGURE 12-1. FIGURE 13-1. FIGURE 13-2. FIGURE 13-3. FIGURE 13-4. FIGURE 13-5. FIGURE 13-6. FIGURE 13-7. FIGURE 13-8. FIGURE 13-9. FIGURE 13-10. FIGURE 13-11. FIGURE 13-12. FIGURE 13-13. FIGURE 13-14. FIGURE 13-15. FIGURE 13-16. FIGURE 13-17. FIGURE 13-18. FIGURE 13-19. FIGURE 13-20. FIGURE 13-21. FIGURE 13-22. FIGURE 13-23. FIGURE 13-24. FIGURE 13-25. FIGURE 13-26. FIGURE 13-27. FIGURE 13-28. FIGURE 13-29. FIGURE 13-30. FIGURE 13-31. FIGURE 13-32. FIGURE 14-1. FIGURE 14-2.

SINGLE READ-WRITE-CYCLE ................................................................................................................................. 205 BLOCK DIAGRAM OF LCD CONTROLLER ............................................................................................................... 208 EXAMPLE APPLICATION FOR LCD CONTROLLER .................................................................................................... 209 PALETTE REMAPPING OPERATION........................................................................................................................... 213 SHARPNESS ............................................................................................................................................................. 214 PIP.......................................................................................................................................................................... 215 POP ........................................................................................................................................................................ 215 FONT STRUCTURE (12X16 DOTS PER FONT) ........................................................................................................... 216 OSD BASIC OPERATION DESCRIPTION ................................................................................................................... 217 BLOCK DIAGRAM OF SCALER ................................................................................................................................. 217 BASIC TFT INTERFACE TIMING DIAGRAM .............................................................................................................. 219 ETHERNET CONTROLLER BLOCK DIAGRAM ........................................................................................................... 250 TRANSMIT FRAME CONTROL FLOW OF TXMAC .................................................................................................... 253 RECEIVE FRAME CONTROL FLOW OF RXMAC ...................................................................................................... 254 BLOCK DIAGRAM OF 10/100BASE PHY ................................................................................................................. 256 TRANSMIT RING DESCRIPTOR STRUCTURE ............................................................................................................. 259 RECEIVE RING DESCRIPTOR STRUCTURE................................................................................................................ 261 EXAMPLE OF INCOMING PACKET PLACEMENT ......................................................................................................... 264 10/10 ETHERNET PORT SCHEMATICS ...................................................................................................................... 296 AES ENGINE .......................................................................................................................................................... 299 USB OTG BLOCK DIAGRAM .................................................................................................................................. 311 DMA CONTROLLER BLOCK DIAGRAM ................................................................................................................... 313 HOST CONTROL BLOCK DIAGRAM ......................................................................................................................... 314 FIFOCTL BLOCK DIAGRAM .................................................................................................................................. 316 CXF BLOCK DIAGRAM ........................................................................................................................................... 317 PIE BLOCK DIAGRAM ............................................................................................................................................ 318 OTG BUS MONITOR BLOCK DIAGRAM................................................................................................................... 319 RGF BLOCK DIAGRAM ........................................................................................................................................... 321 PWE BLOCK DIAGRAM .......................................................................................................................................... 322 USB RESET AND HIGH-SPEED DETECTION HANDSHAKE TIMING CHART ............................................................... 323 USB OTG ASSERTS U_SUSP_N TO TURN OFF THE PLL IN PHY ............................................................................. 324 USBC WAKENED UP BY HOST RESUME / RESET..................................................................................................... 326 USBC WAKENED UP BY AP.................................................................................................................................... 328 BLOCK DIAGRAM OF USB OTG PHY .................................................................................................................... 363 HS RECEIVE TIMING DIAGRAM FOR 8-BIT DATA .................................................................................................... 364 HS RECEIVE WITH DATA UNDER-RUNS .................................................................................................................. 364 HS RXERROR TIMING DIAGRAM DC CHARACTERISTICS ....................................................................................... 365 HS RECEIVE TIMING DIAGRAM FOR 16-BIT DATA, ODD BYTE COUNT ................................................................... 365 HS RECEIVE TIMING DIAGRAM FOR 16-BIT DATA, EVEN BYTE COUNT ................................................................. 365 FS/LS RECEIVER OPERATION ................................................................................................................................. 366 HS TRANSMIT TIMING DIAGRAM FOR 8-BIT DATA ................................................................................................. 366 HS TRANSMIT WITH DATA UNDER-RUNS DUE ........................................................................................................ 367 HS TRANSMIT TIMING DIAGRAM FOR 16-BIT DATA, ODD BYTE COUNT ................................................................ 367 HS TRANSMIT TIMING DIAGRAM FOR 16-BIT DATA, EVEN BYTE COUNT............................................................... 367 FS/LS TRANSMITTER OPERATION DIAGRAM .......................................................................................................... 368 LS KEEP-ALIVE GENERATION DIAGRAM ................................................................................................................ 369 HS INTER-PACKET DELAY FOR A TRANSMIT FOLLOWED BY A RECEIVE .......................................................................... 371 FS/LS INTER-PACKET DELAY FOR A RECEIVE FOLLOWED BY A TRANSMIT ............................................................. 372 FS/LS INTER-PACKET DELAY FOR A TRANSMIT FOLLOWED BY A RECEIVE ............................................................. 373 TIMING CONSTRAINT DIAGRAM ............................................................................................................................. 373 FULL SPEED TIMING DIAGRAM ............................................................................................................................... 374 USB- OTG INTERFACE ........................................................................................................................................... 375 BLOCK DIAGRAM OF MEDIACODEC ........................................................................................................................ 377 NON-CIRCULAR ADDRESS GENERATION FOR AN 8X8 BLOCK ................................................................................. 379

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FIGURE 14-3. FIGURE 14-4. FIGURE 14-5. FIGURE 14-6. FIGURE 14-7. FIGURE 14-8. FIGURE 14-9. FIGURE 14-10. FIGURE 14-11. FIGURE 14-12. FIGURE 15-1. FIGURE 15-2. FIGURE 15-3. FIGURE 15-4. FIGURE 15-5. FIGURE 15-6. FIGURE 15-7. FIGURE 15-8. FIGURE 15-9. FIGURE 15-10. FIGURE 15-11. FIGURE 15-12. FIGURE 15-13. FIGURE 15-14. FIGURE 15-15. FIGURE 15-16. FIGURE 15-17. FIGURE 15-18. FIGURE 15-19. FIGURE 15-20. FIGURE 16-1. FIGURE 17-1. FIGURE 18-1. FIGURE 18-2. FIGURE 18-3. FIGURE 18-4. FIGURE 19-1. FIGURE 19-2. FIGURE 19-3. FIGURE 19-4. FIGURE 20-1. FIGURE 20-2. FIGURE 21-1. FIGURE 21-2. FIGURE 21-3. FIGURE 22-1. FIGURE 22-2. FIGURE 22-3. FIGURE 22-4. FIGURE 22-5. FIGURE 22-6. FIGURE 22-7. FIGURE 22-8. FIGURE 22-9.

SEARCH WINDOW INSIDE FRAME BUFFER ON SYSTEM MEMORY ........................................................................... 380 SEARCH WINDOW INSIDE LOCAL MEMORY ............................................................................................................ 381 SEQUENTIAL-TO-SEQUENTIAL TRANSFER............................................................................................................... 382 2D-TO-SEQUENTIAL TRANSFER .............................................................................................................................. 382 2D-TO-2D TRANSFER ............................................................................................................................................. 382 XD-TO-3D TRANSFER ............................................................................................................................................. 383 XD-TO-4D TRANSFER ............................................................................................................................................. 383 CHAIN TRANSFER FUNCTION .................................................................................................................................. 384 ME BUFFER IN ENCODING MODE ............................................................................................................................ 407 ME BUFFER IN DECODING MODE ........................................................................................................................... 407 VIDEO CAPTURE BLOCK ......................................................................................................................................... 422 VERTICAL INTERVAL OF ITU-BT.656 ...................................................................................................................... 423 TIMING OF ITU-R BT. 656 LIKE.............................................................................................................................. 423 VERTICAL TIMING OF 8-BIT H/V REFERENCE CONTROL.......................................................................................... 424 HORIZONTAL TIMING OF 8-BIT H/V REFERENCE CONTROL .................................................................................... 424 VERTICAL TIMING OF 16-BIT H/V SYNC. CONTROL ................................................................................................ 424 HORIZONTAL TIMING OF 16-BIT H/V SYNC. CONTROL ........................................................................................... 425 INDEPENDENT PREVIEW AND RECORD PATH SIZE-DOWN ........................................................................................ 425 MACRO BLOCK ORDER IN ONE IMAGE ................................................................................................................... 427 PIXEL OUTPUT ORDER IN ONE 16 X 16 MACRO BLOCK .......................................................................................... 427 PIXEL OUTPUT ORDER IN ONE 8 X 8 MACRO BLOCK .............................................................................................. 428 PIXEL OUTPUT ORDER IN ONE 4 X 4 MACRO BLOCK .............................................................................................. 428 YCBCR 4:2:0 MACRO BLOCK ORDER IN TWO-SPLIT MEMORY BLOCK .................................................................. 429 RELATIONSHIP BETWEEN SOURCE IMAGE AND TARGET IMAGE ............................................................................... 435 RELATIONSHIP BETWEEN BORDER WIDTH/HEIGHT AND CROP WINDOW ................................................................ 437 VPSRC_X AND VP_SRC_Y .................................................................................................................................. 443 SOURCE ACTIVE WINDOW ...................................................................................................................................... 443 PITCH OF SUB-WINDOW OF PREVIEW AND RECORD PATH....................................................................................... 448 START ADDRESS OF DESTINATION FRAME BUFFER ................................................................................................. 449 OSD FONT RAM AND DISPLAY RAM .................................................................................................................... 452 BLOCK DIAGRAM OF AHB TO APB BRIDGE ........................................................................................................... 463 INTC BLOCK DIAGRAM ......................................................................................................................................... 466 GPIO BLOCK DIAGRAM ......................................................................................................................................... 475 WRITE TO GPIODATAOUT REGISTER ...................................................................................................................... 484 POSITIVE EDGE TRIGGER ........................................................................................................................................ 484 LEVEL HIGH TRIGGER ............................................................................................................................................ 484 BLOCK DIAGRAM OF PWMS ................................................................................................................................. 486 BLOCK DIAGRAM OF PWMS ................................................................................................................................. 487 BASIC PULSE WIDTH WAVEFORM ........................................................................................................................... 493 BASIC CHOP PULSE WIDTH WAVEFORM ................................................................................................................. 494 BLOCK DIAGRAM OF I2C CONTROLLER .................................................................................................................. 495 RELATIONSHIP AMONG TSR SCL, AND SDA .......................................................................................................... 500 BLOCK DIAGRAM OF WATCH DOG TIMER ............................................................................................................... 504 WRITE TO WDLOAD REGISTER ............................................................................................................................... 507 WATCH DOG TIMER INTERRUPT.............................................................................................................................. 508 TOP LEVEL BLOCK DIAGRAM OF TIMER/COUNTERS ............................................................................................... 510 GENERAL PURPOSE TIMER/COUNTER BLOCK DIAGRAM ........................................................................................ 512 GENERAL PURPOSE TIMER/COUNTER PRESCALER .................................................................................................. 520 TIMER/COUNTER BLOCK DIAGRAM ....................................................................................................................... 521 BASIC TIMER/COUNTER WAVEFORM ...................................................................................................................... 521 CYCLIC TIMER WITH EXTERNAL SAMPLE AND PULSE OUTPUT ............................................................................... 527 WAVEFORM OF CYCLIC TIMER WITH EXTERNAL SAMPLE AND OUTPUT ................................................................... 530 EXTERNAL TIMER TRIGGER CONTROL.................................................................................................................... 530 WAVEFORM ILLUSTRATING EXTERNAL TIMER TRIGGERS ....................................................................................... 532

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FIGURE 22-10. FIGURE 22-11. FIGURE 22-12. FIGURE 22-13. FIGURE 22-14. FIGURE 22-15. FIGURE 22-16. FIGURE 22-17. FIGURE 22-18. FIGURE 22-19. FIGURE 23-1. FIGURE 23-2. FIGURE 23-3. FIGURE 23-4. FIGURE 24-1. FIGURE 24-2. FIGURE 25-1. FIGURE 25-2. FIGURE 25-3. FIGURE 25-4. FIGURE 25-5. FIGURE 25-6. FIGURE 25-7. FIGURE 25-8. FIGURE 26-1. FIGURE 26-2. FIGURE 26-3. FIGURE 26-4. FIGURE 26-5. FIGURE 26-6. FIGURE 26-7. FIGURE 26-8. FIGURE 27-1. FIGURE 27-2. FIGURE 27-3. FIGURE 27-4. FIGURE 27-5. FIGURE 27-6. FIGURE 27-7. FIGURE 27-8. FIGURE 27-9. FIGURE 27-10. FIGURE 27-11. FIGURE 27-12. FIGURE 27-13. FIGURE 27-14. FIGURE 27-15. FIGURE 27-16. FIGURE 27-17. FIGURE 27-18. FIGURE 27-19. TABLE 4-1. TABLE 5-1.

EXTERNAL WATCHDOG TIMER OPERATION ............................................................................................................. 533 EXTERNAL WATCHDOG TIMER WAVEFORM ............................................................................................................ 535 SINGLE CYCLE WAVEFORM .................................................................................................................................... 536 SINGLE CYCLE COUNTER PERFORMING A WATCHDOG FUNCTION .......................................................................... 537 TIMER CHAINING CONFIGURATION (72 BITS).......................................................................................................... 539 TIMER CHAINING (48 BITS) WAVEFORM ................................................................................................................. 540 PULSE WIDTH MODULATION MODE ........................................................................................................................ 540 PWM WAVEFORM .................................................................................................................................................. 541 SAMPLE MODE ....................................................................................................................................................... 542 SAMPLED WAVEFORM ............................................................................................................................................. 542 BLOCK DIAGRAM OF RTC ...................................................................................................................................... 546 WRITE RTCSECOND REGISTER ............................................................................................................................... 554 SECOND ALARM ..................................................................................................................................................... 554 AUTO SECOND ALARM ........................................................................................................................................... 554 BLOCK DIAGRAM OF SD HOST CONTROLLER......................................................................................................... 556 FLOW CHART OF SENDING 512-BYTE DATA TO SD MEMORY CARD ....................................................................... 566 BLOCK DIAGRAM OF CF HOST INTERFACE CONTROLLER....................................................................................... 568 ATTRIBUTE MEMORY READ TIMING SPECIFICATION ............................................................................................... 571 CONFIGURATION REGISTER WRITE TIMING SPECIFICATION .................................................................................... 572 COMMON MEMORY WRITE TIMING SPECIFICATION ................................................................................................ 572 COMMON MEMORY READ TIMING SPECIFICATION ................................................................................................. 572 I/O READ TIMING SPECIFICATION ........................................................................................................................... 573 I/O WRITE TIMING SPECIFICATION ......................................................................................................................... 573 DMA HANDSHAKING PROTOCOL ........................................................................................................................... 575 BLOCK DIAGRAM OF UART AND IRDA COMMUNICATIONS CONTROLLER ............................................................. 579 UART DATA REPRESENTATION AND SAMPLING ...................................................................................................... 582 SIR ENCODING ....................................................................................................................................................... 583 SERIAL INFRARED INTERACTION PULSE ................................................................................................................. 585 INTERCONNECTION BETWEEN MCR AND MSR IN LOOP BACK MODE .................................................................... 596 RS-232 INTERFACE ................................................................................................................................................. 610 INTERFACE WITH VISHAY TRANSCEIVER................................................................................................................. 611 INTERFACE WITH HSDL-1100 ................................................................................................................................ 611 BLOCK DIAGRAM OF SSP/I2S/AC97/SPI CONTROLLER ......................................................................................... 613 RELATION AMONG SSPCLK, SCLK_IN AND SAMPLE POINT ................................................................................... 615 TIS SSP FRAME FORMAT FOR SINGLE TRANSFER .................................................................................................. 615 TIS SSP FRAME FORMAT FOR CONTINUOUS TRANSFER ........................................................................................ 616 RELATION BETWEEN FRAME / SYNC SCLK OF SPI ................................................................................................. 617 MOTOROLAS SPI FRAME FORMAT FOR SINGLE TRANSFER .................................................................................... 618 MOTOROLAS SPI FRAME FORMAT FOR CONTINUOUS TRANSFER........................................................................... 618 NATIONAL SEMICONDUCTOR MICROWIRE FRAME FORMAT FOR SINGLE TRANSFER ............................................... 619 NATIONAL SEMICONDUCTOR MICROWIRE FRAME FORMAT FOR CONTINUOUS TRANSFER ..................................... 620 PHILIPS I2S BASIC FRAME FORMAT ....................................................................................................................... 620 POSSIBLE VARIATION OF I2S FRAME FORMAT (I) .................................................................................................... 621 POSSIBLE VARIATION OF I2S FRAME FORMAT (II) .................................................................................................. 621 INTELS AC-LINK FRAME FORMAT ......................................................................................................................... 622 START OF AC-LINK FRAME..................................................................................................................................... 622 RELATIONSHIP BETWEEN TX / RX FIFO AND SLOT VALID....................................................................................... 623 AC-LINK COLD RESET ............................................................................................................................................ 623 AC-LINK WARM RESET .......................................................................................................................................... 624 SETUP / HOLD TIME OF SSP .................................................................................................................................... 625 DMA INTERFACE TIMING ....................................................................................................................................... 625

INTERNAL REGISTERS.................................................................................................................................................... 52 PLL1-BASED CLOCK ASSIGNMENT ............................................................................................................................... 80

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TABLE 5-2. TABLE 5-3. TABLE 5-4. TABLE 5-5. TABLE 5-6. TABLE 5-7. TABLE 5-8. TABLE 5-9. TABLE 5-10. TABLE 5-11. TABLE 5-12. TABLE 5-13. TABLE 5-14. TABLE 5-15. TABLE 5-16. TABLE 5-17. TABLE 5-18. TABLE 6-1. TABLE 6-2. TABLE 6-3. TABLE 6-4. TABLE 6-5. TABLE 6-6. TABLE 6-7. TABLE 6-8. TABLE 6-9. TABLE 6-10. TABLE 6-11. TABLE 6-12. TABLE 6-13. TABLE 6-14. TABLE 6-15. TABLE 6-16. TABLE 6-17. TABLE 6-18. TABLE 6-19. TABLE 6-20. TABLE 6-21. TABLE 6-22. TABLE 6-23. TABLE 6-24. TABLE 6-25. TABLE 6-26. TABLE 6-27. TABLE 6-28. TABLE 6-29. TABLE 7-1. TABLE 7-2. TABLE 7-3. TABLE 7-4. TABLE 7-5. TABLE 7-6. TABLE 8-1. TABLE 8-2.

PLL2 CLOCK ASSIGNMENT ........................................................................................................................................... 81 PLL3 CLOCK ASSIGNMENT ........................................................................................................................................... 82 EFFECT OF EACH TYPE OF RESET ON INTERNAL REGISTER STATE ................................................................................. 83 SUMMARY OF SYSTEM CONFIGURATION REGISTERS ..................................................................................................... 87 PLL1 CONTROL REGISTER 0 (PLL1CR0) ..................................................................................................................... 87 LOCK TIMES FOR PLL1 .................................................................................................................................................. 88 PLL2 CONTROL REGISTER 1 (PLL2CR1) ..................................................................................................................... 89 PLL2 CONTROL REGISTER 3 (PLL2CR2) ..................................................................................................................... 89 DLL CONTROL REGISTER (DLLCR) ........................................................................................................................ 90 AHB MODULE CLOCK OFF CONTROL REGISTER (AHBMCLKOFF) ....................................................................... 91 APB MODULE CLOCK OFF CONTROL REGISTER (APBMCLKOFF) ........................................................................ 92 CLOCK CONTROL REGISTER (CCR) .......................................................................................................................... 94 MULTIFUNCTION PORT SETTING REGISTER 0 (MFPSR0) ......................................................................................... 96 MULTI-FUNCTION PORT SETTING REGISTER (MFPSR1)........................................................................................... 98 DRIVING CAPABILITY AND SLEW RATE CONTROL REGISTER 0 (DCSRCR0) .......................................................... 100 DRIVING CAPABILITY AND SLEW RATE CONTROL REGISTER 1 (DCSRCR1) .......................................................... 102 DRIVING CAPABILITY AND SLEW RATE CONTROL REGISTER 2 (DCSRCR2) .......................................................... 103 SUMMARY OF JEMCORE-II REGISTERS ....................................................................................................................... 109 SUMMARY OF MJM REGISTERS ................................................................................................................................... 110 MJM JVM REGISTER ................................................................................................................................................... 111 ABORT TIMER REGISTER ............................................................................................................................................. 112 ABORT TIMER RELOAD REGISTER ............................................................................................................................... 112 PRESCALAR RELOAD REGISTER .................................................................................................................................. 113 JSI ALARM REGISTER.................................................................................................................................................. 113 TIMER MODE REGISTER .............................................................................................................................................. 113 JSI TIMER REGISTER ................................................................................................................................................... 114 PIANO TIMER 0 RELOAD REGISTER ........................................................................................................................ 114 CLOCK TIMER 0 RELOAD REGISTER ....................................................................................................................... 115 JVM 0 TIMER ENABLE REGISTER ........................................................................................................................... 115 PIANO ROLL TIMER 0 REGISTER ............................................................................................................................. 116 CLOCK TIMER 0 REGISTER ..................................................................................................................................... 116 PIANO ROLL TIMER 1 RELOAD REGISTER ............................................................................................................... 116 CLOCK TIMER 1 RELOAD REGISTER ....................................................................................................................... 117 JVM1 TIMER ENABLE REGISTER ............................................................................................................................ 117 PIANO ROLL TIMER 1 REGISTER ............................................................................................................................. 117 CLOCK TIMER 1 REGISTER ..................................................................................................................................... 118 AJ-200 INTERRUPT ASSIGNMENTS .......................................................................................................................... 118 JEMBUILDER INTERRUPT LEVEL ASSIGNMENT ...................................................................................................... 120 INTERRUPT TRANSLATION REGISTERS .................................................................................................................... 120 INTERRUPT CONTROLLER REGISTER SUMMARY ..................................................................................................... 121 PENDING INTERRUPT REGISTER .............................................................................................................................. 121 REGISTER SUMMARY .............................................................................................................................................. 122 CACHE CONFIGURATION REGISTER 0 (CCR0) ......................................................................................................... 122 CACHE CONTROL REGISTER ................................................................................................................................... 123 BOUNDARY SCAN INSTRUCTION CODES ................................................................................................................. 128 BOUNDARY SCAN INSTRUCTION CODES ................................................................................................................. 128 SUMMARY OF THE AHB CONTROLLER REGISTERS ...................................................................................................... 135 AHB SLAVE 0 BASE/SIZE REGISTER ........................................................................................................................... 136 PRIORITY CONTROL REGISTER .................................................................................................................................... 137 AHB MASTER REQUEST ROUTING TABLE ................................................................................................................... 137 TRANSFER CONTROL REGISTER .................................................................................................................................. 137 INTERRUPT CONTROL REGISTER ................................................................................................................................. 137 DMA ROUTING TABLE ............................................................................................................................................... 139 ADDRESS MAP FOR LINKED LIST DESCRIPTOR (BASE: CN_LLP [31:2])...................................................................... 142

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TABLE 8-3. TABLE 8-4. TABLE 8-5. TABLE 8-6. TABLE 8-7. TABLE 8-8. TABLE 8-9. TABLE 8-10. TABLE 8-11. TABLE 8-12. TABLE 8-13. TABLE 8-14. TABLE 8-15. TABLE 8-16. TABLE 8-17. TABLE 8-18. TABLE 8-19. TABLE 8-20. TABLE 8-21. TABLE 8-22. TABLE 8-23. TABLE 8-24. TABLE 8-25. TABLE 8-26. TABLE 8-27. TABLE 9-1. TABLE 9-2. TABLE 9-3. TABLE 9-4. TABLE 9-5. TABLE 9-6. TABLE 9-7. TABLE 9-8. TABLE 9-9. TABLE 9-10. TABLE 9-11. TABLE 9-12. TABLE 9-13. TABLE 9-14. TABLE 9-15. TABLE 9-16. TABLE 9-17. TABLE 9-18. TABLE 9-19. TABLE 9-20. TABLE 9-21. TABLE 9-22. TABLE 9-23. TABLE 9-24. TABLE 9-25. TABLE 9-26. TABLE 9-27. TABLE 9-28. TABLE 9-29.

CONTROL FIELD DEFINITION IN THE LINKED LIST DESCRIPTOR. ................................................................................. 142 TOTAL TRANSFER SIZE DEFINITION IN THE LINKED LIST DESCRIPTOR ........................................................................ 143 ADDRESS MAP FOR LINKED LIST DESCRIPTOR (BASE: CN_LLP [31:2])...................................................................... 143 CONTROL FIELD DEFINITION IN THE LINKED LIST DESCRIPTOR .................................................................................. 143 TOTAL TRANSFER SIZE DEFINITION IN THE LINKED LIST DESCRIPTOR ........................................................................ 143 SUMMARY OF THE DMA CONTROLLER REGISTERS ..................................................................................................... 145 INT REGISTER ............................................................................................................................................................. 147 INT_TC REGISTER ................................................................................................................................................. 148 INT_TC_CLR REGISTER ....................................................................................................................................... 148 INT_ERR REGISTER .............................................................................................................................................. 149 INT_ERR_CLR REGISTER..................................................................................................................................... 150 TC REGISTER ......................................................................................................................................................... 151 ERR REGISTER ....................................................................................................................................................... 152 CH_EN REGISTER .................................................................................................................................................. 153 CH_BUSY REGISTER ............................................................................................................................................. 153 CSR REGISTER ....................................................................................................................................................... 154 SYNC REGISTER .................................................................................................................................................... 155 DMA REVISION REGISTER ..................................................................................................................................... 155 DMA FEATURE REGISTER ...................................................................................................................................... 155 CN_CSR REGISTER ................................................................................................................................................ 156 CN_CFG REGISTER ................................................................................................................................................ 159 CN_SRCADDR REGISTER ........................................................................................................................................ 159 CN_DSTADDR REGISTER ........................................................................................................................................ 159 CN_LLP REGISTER ................................................................................................................................................. 160 CN_SIZE REGISTER ............................................................................................................................................... 160 SUMMARY OF EBI REGISTERS ..................................................................................................................................... 164 EBI CONTROL REGISTER ............................................................................................................................................. 165 GRANT WINDOW UNIT REGISTER ................................................................................................................................. 165 MIN GRANT WINDOW SIZE OF MATERS (3~0) REGISTER ............................................................................................... 165 MIN GRANT WINDOW SIZE OF MATERS (7~4) REGISTER ............................................................................................... 166 ADDRESS TO MBEN TRANSLATION (BUS WIDTH= 16 & LITTLE ENDIANESS) ................................................................ 170 ADDRESS TO MBEN TRANSLATION (BUS WIDTH= 16 & LITTLE ENDIANESS) ................................................................ 171 ADDRESS TO MBEN TRANSLATION (BUS WIDTH= 16 & LITTLE ENDIANESS) ................................................................ 172 STATIC MEMORY CONTROLLER REGISTER SUMMARY ................................................................................................. 178 MEMORY BANK CONFIGURATION REGISTERS ......................................................................................................... 178 MEMORY BANK TIMING PARAMETER REGISTERS ................................................................................................... 180 ADDRESS SETUP TIME ............................................................................................................................................ 181 CHIP-SELECT WRITE-ENABLE DELAY....................................................................................................................... 181 WRITE ENABLE WIDTH .......................................................................................................................................... 182 WRITE ENABLE TO CHIP SELECT DELAY ................................................................................................................ 182 ADDRESS HOLD TIME ............................................................................................................................................. 182 TURN AROUND TIME ............................................................................................................................................... 182 ADDRESS SETUP TIME (AST) ................................................................................................................................. 183 CHIP-SELECT TO WRITE-ENABLE DELAY (CTW) ..................................................................................................... 183 OUTPUT ENABLE WIDTH ........................................................................................................................................ 183 OUTPUT ENABLE TO CHIP SELECT DELAY .............................................................................................................. 183 ADDRESS HOLD TIME .............................................................................................................................................. 183 TURN AROUND TIME ............................................................................................................................................... 183 TRNA REGISTER .................................................................................................................................................... 186 AT1 REGISTER SETTING MAPPING FOR BURST ROM ............................................................................................... 186 AT2 REGISTER SETTING MAPPING FOR BURST ROM ............................................................................................... 186 SHADOW STATUS REGISTER .................................................................................................................................... 187 BANK TYPE SETTING .............................................................................................................................................. 188 SDRAM CONTROLLER REGISTER SUMMARY ......................................................................................................... 192

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TABLE 9-30. TABLE 9-31. TABLE 9-32. TABLE 9-33. TABLE 9-34. TABLE 9-35. TABLE 9-36. TABLE 9-37. TABLE 9-38. TABLE 9-39. TABLE 9-40. TABLE 9-41. TABLE 9-42. TABLE 9-43. TABLE 9-44. TABLE 9-45. TABLE 9-46. TABLE 10-1. TABLE 10-2. TABLE 10-3. TABLE 10-4. TABLE 10-5. TABLE 10-6. TABLE 10-7. TABLE 10-8. TABLE 10-9. TABLE 10-10. TABLE 10-11. TABLE 10-12. TABLE 10-13. TABLE 10-14. TABLE 10-15. TABLE 10-16. TABLE 10-17. TABLE 10-18. TABLE 10-19. TABLE 10-20. TABLE 10-21. TABLE 10-22. TABLE 10-23. TABLE 10-24. TABLE 10-25. TABLE 10-26. TABLE 10-27. TABLE 10-28. TABLE 10-29. TABLE 10-30. TABLE 10-31. TABLE 10-32. TABLE 10-33. TABLE 10-34. TABLE 10-35. TABLE 10-36. TABLE 10-37.

SDRAM TIMING PARAMETER 1 REGISTER ............................................................................................................. 192 SDRAM TIMING PARAMETER 2 REGISTER ............................................................................................................. 193 SDRAM CONFIGURATION REGISTER ..................................................................................................................... 193 SDRAM CONFIGURATION REGISTER 2................................................................................................................... 194 EXTERNAL BANK CONFIGURATION REGISTER ........................................................................................................ 196 ARBITER CONTROL REGISTER ................................................................................................................................ 197 ARBITER CONTROL REGISTER ................................................................................................................................ 197 MOBILE SDRAM SUPPORT REGISTER .................................................................................................................... 198 CONTROLLER REVISION REGISTER ......................................................................................................................... 198 CONTROLLER FEATURE REGISTER (OFFSET = 0X104) ............................................................................................ 198 ADDRESS DECODING WITH MEMORY BUS WIDTH BEING 32 (AMTSEL = 0) ......................................................... 199 ADDRESS DECODING WITH MEMORY BUS WIDTH BEING 16 (AMTSEL=0) ........................................................... 200 ADDRESS DECODING WITH MEMORY BUS WIDTH BEING 8 (AMTSEL=0) ............................................................. 200 ADDRESS DECODING WITH MEMORY BUS WIDTH BEING 32 (AMTSEL = 1) ......................................................... 201 ADDRESS DECODING WITH MEMORY BUS WIDTH BEING 16 (AMTSEL=1) ........................................................... 201 ADDRESS DECODING WITH MEMORY BUS WIDTH BEING 8 (AMTSEL=1) ............................................................. 202 TYPICAL VALUE OF TIMING PARAMETER 0 ............................................................................................................. 202 LITTLE ENDIAN BYTE, LITTLE ENDIAN PIXEL ........................................................................................................ 210 BIG ENDIAN BYTE, BIG ENDIAN PIXEL................................................................................................................... 210 LITTLE ENDIAN BYTE, BIG ENDIAN PIXEL ............................................................................................................. 211 MAPPING FOR RAW RGB MODE ............................................................................................................................. 212 PIXEL SEQUENCE FOR YCBCR422 MODE ............................................................................................................... 212 COMPONENT LOCATION/SEQUENCE FOR YCBCR420 MODE ................................................................................... 212 PALETTE RAM DATA STRUCTURE (FOR ENTRY 0) .................................................................................................. 213 FONT ATTRIBUTE STRUCTURE ................................................................................................................................ 216 LCD 18-BIT AND 24-BIT INTERFACE ...................................................................................................................... 219 CONTROL REGISTER SUMMARY .............................................................................................................................. 219 LCD FUNCTION ENABLE ........................................................................................................................................ 221 LCD PANEL PIXEL PARAMETERS ............................................................................................................................ 222 LCD INTERRUPT ENABLE MASK ............................................................................................................................ 223 LCD INTERRUPT STATUS CLEAR ............................................................................................................................ 224 LCD INTERRUPT STATUS ........................................................................................................................................ 224 FRAME BUFFER PARAMETER .................................................................................................................................. 224 LCD PANEL IMAGE0 FRAME0 BASE ADDRESS......................................................................................................... 225 LCD PANEL IMAGE 1 FRAME0 BASE ADDRESS ........................................................................................................ 225 PANEL IMAGE2 FRAME0 BASE ADDRESS ................................................................................................................. 225 LCD PANEL IMAGE3 FRAME0 BASE ADDRESS......................................................................................................... 225 PATGEN PATTERN BAR DISTANCE ........................................................................................................................... 225 FIFO THRESHOLD CONTROL .................................................................................................................................. 226 GPI/GPO CONTROL I ............................................................................................................................................. 226 LCD HORIZONTAL TIMING CONTROL ..................................................................................................................... 226 LCD VERTICAL TIMING CONTROL ......................................................................................................................... 227 LCD VERTICAL TIMING CONTROL ......................................................................................................................... 228 LCD POLARITY CONTROL ...................................................................................................................................... 228 LCD SERIAL PANEL PIXEL PARAMETERS ................................................................................................................ 229 LCD CCIR656 PARAMETERS ................................................................................................................................. 230 LCD PIP PARAMETERS ........................................................................................................................................... 231 PIP SUBPICTURE1 POSITION ................................................................................................................................... 231 PIP SUBPICTURE DIMINATION ................................................................................................................................ 231 PIP SUB-PICTURE2 POSITION ................................................................................................................................. 231 PIP SUB-PICTURE2 DIMINATION ............................................................................................................................. 232 LCD COLOR MANAGEMENT PARAMENT0 .............................................................................................................. 232 LCD COLOR MANAGEMENT PARAMENT1 .............................................................................................................. 232 LCD COLOR MANAGEMENT PARAMENT2 .............................................................................................................. 233

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TABLE 10-38. TABLE 10-39. TABLE 10-40. TABLE 10-41. TABLE 10-42. TABLE 10-43. TABLE 10-44. TABLE 10-45. TABLE 10-46. TABLE 10-47. TABLE 10-48. TABLE 10-49. TABLE 10-50. TABLE 10-51. TABLE 10-52. TABLE 10-53. TABLE 10-54. TABLE 10-55. TABLE 10-56. TABLE 10-57. TABLE 10-58. TABLE 10-59. TABLE 10-60. TABLE 10-61. TABLE 10-62. TABLE 10-63. TABLE 10-64. TABLE 10-65. TABLE 10-66. TABLE 10-67. TABLE 10-68. TABLE 10-69. TABLE 10-70. TABLE 10-71. TABLE 10-72. TABLE 10-73. TABLE 10-74. TABLE 11-1. TABLE 11-2. TABLE 11-3. TABLE 11-4. TABLE 11-5. TABLE 11-6. TABLE 11-7. TABLE 11-8. TABLE 11-9. TABLE 11-10. TABLE 11-11. TABLE 11-12. TABLE 11-13. TABLE 11-14. TABLE 11-15. TABLE 11-16. TABLE 11-17.

LCD COLOR MANAGEMENT PARAMENT3 .............................................................................................................. 233 LCD GAMMA RED LOOKUP TABLE......................................................................................................................... 233 LCD GAMMA GREEN LOOKUP TABLE .................................................................................................................... 234 LCD GAMMA BLUE LOOKUP TABLE....................................................................................................................... 234 LCD PALETTE RAM WRITE ACCESSING PORT ....................................................................................................... 235 HORIZONTAL RESOLUTION REGISTER OF SCALAR INPUT ........................................................................................ 235 VERTICAL RESOLUTION REGISTER OF SCALAR INPUT .............................................................................................. 235 HORIZONTAL RESOLUTION REGISTER OF SCALAR OUTPUT ...................................................................................... 235 VERTICAL RESOLUTION REGISTER OF SCALAR OUTPUT ........................................................................................... 236 MISCELLANEOUS CONTROL REGISTER .................................................................................................................... 236 HORIZONTAL HIGH THRESHOLD REGISTER .............................................................................................................. 236 HORIZONTAL LOW THRESHOLD REGISTER ............................................................................................................... 237 VERTICAL HIGH THRESHOLD REGISTER ................................................................................................................... 237 VERTICAL LOW THRESHOLD REGISTER.................................................................................................................... 237 SCALAR RESOLUTION PARAMETERS ........................................................................................................................ 237 OSD SCALING AND DIMENSION CONTROL ............................................................................................................... 238 OSD POSITION CONTROL ........................................................................................................................................ 238 OSD FOREGROUND COLOR CONTROL ..................................................................................................................... 238 OSD BACKGROUND COLOR CONTROL .................................................................................................................... 239 OSD FONT DATABASE WRITE ACCESSING PORT .................................................................................................... 239 OSD WINDOW ATTRIBUTE WRITE ACCESSING PORT .............................................................................................. 240 LCD HORIZONTAL TIMING CONTROL ..................................................................................................................... 240 LCD VERTICAL TIMING CONTROL ......................................................................................................................... 241 LCD CLOCK AND SIGNAL POLARITY CONTROL ...................................................................................................... 242 LCD PANEL FRAME BASE ADDRESS ....................................................................................................................... 243 LCD INTERRUPT ENABLE MASK ............................................................................................................................ 243 LCD PANEL PIXEL PARAMETERS ............................................................................................................................ 243 LCD INTERRUPT STATUS CLEAR ............................................................................................................................ 244 LCD INTERRUPT STATUS ........................................................................................................................................ 245 OSD SCALING AND DIMENSION CONTROL ............................................................................................................. 245 OSD POSITION CONTROL ....................................................................................................................................... 246 OSD FOREGROUND COLOR CONTROL .................................................................................................................... 246 OSD BACKGROUND COLOR CONTROL ................................................................................................................... 246 GPI/GPO CONTROL ............................................................................................................................................... 247 LCD PALETTE RAM ACCESSING PORT ................................................................................................................... 247 OSD FONT DATABASE WRITE ACCESSING PORT .................................................................................................... 248 OSD WINDOW ATTRIBUTE WRITE ACCESSING PORT .............................................................................................. 249 TRANSMIT DESCRIPTOR .......................................................................................................................................... 260 TXDES0 ................................................................................................................................................................ 260 TXDES1 ................................................................................................................................................................ 260 RECEIVE DESCRIPTOR ............................................................................................................................................ 261 RXDES0 ................................................................................................................................................................ 261 RXDES1 ................................................................................................................................................................ 262 RXDES2 ................................................................................................................................................................ 263 ETHERNET ADDRESS FILTERING ............................................................................................................................. 264 WAKE-UP FRAME FORMAT....................................................................................................................................... 267 MAC CONTROLLER REGISTER SUMMARY .............................................................................................................. 268 INTERRUPT STATUS REGISTER ................................................................................................................................ 269 INTERRUPT MASK REGISTER .................................................................................................................................. 270 MAC MOST SIGNIFICANT ADDRESS REGISTER ...................................................................................................... 270 MAC LEAST SIGNIFICANT ADDRESS REGISTER ...................................................................................................... 270 MULTICAST ADDRESS HASH TABLE 0 REGISTER .................................................................................................... 270 MULTICAST ADDRESS HASH TABLE 1 REGISTER .................................................................................................... 270 TRANSMIT POLL DEMAND REGISTER...................................................................................................................... 271

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TABLE 11-18. TABLE 11-19. TABLE 11-20. TABLE 11-21. TABLE 11-22. TABLE 11-23. TABLE 11-24. TABLE 11-25. TABLE 11-26. TABLE 11-27. TABLE 11-28. TABLE 11-29. TABLE 11-30. TABLE 11-31. TABLE 11-32. TABLE 11-33. TABLE 11-34. TABLE 11-35. TABLE 11-36. TABLE 11-37. TABLE 11-38. TABLE 11-39. TABLE 11-40. TABLE 11-41. TABLE 11-42. TABLE 11-43. TABLE 11-44. TABLE 11-45. TABLE 11-46. TABLE 11-47. TABLE 11-48. TABLE 11-49. TABLE 11-50. TABLE 11-51. TABLE 11-52. TABLE 11-53. TABLE 11-54 TABLE 11-55 TABLE 11-56 TABLE 11-57 TABLE 11-58 TABLE 11-59. TABLE 11-60 TABLE 12-1. TABLE 12-2. TABLE 12-3. TABLE 12-4. TABLE 12-5. TABLE 12-6. TABLE 12-7. TABLE 12-8. TABLE 12-9. TABLE 12-10. TABLE 12-11.

RECEIVE POLL DEMAND REGISTER ........................................................................................................................ 271 TRANSMIT RING BASE ADDRESS REGISTER ............................................................................................................ 271 RECEIVE RING BASE ADDRESS REGISTER .............................................................................................................. 271 INTERRUPT TIMER CONTROL REGISTER .................................................................................................................. 271 TRANSMIT INTERRUPT ............................................................................................................................................ 273 RECEIVE INTERRUPT............................................................................................................................................... 273 AUTOMATIC POLLING TIMER CONTROL REGISTER ................................................................................................. 274 DMA BURST LENGTH AND ARBITRATION CONTROL REGISTER .............................................................................. 275 REVISION REGISTER ............................................................................................................................................... 278 FEATURE REGISTER ................................................................................................................................................ 278 MAC CONTROL REGISTER ..................................................................................................................................... 278 MAC STATUS REGISTER ......................................................................................................................................... 279 PHY CONTROL REGISTER....................................................................................................................................... 279 PHY WRITE DATA REGISTER .................................................................................................................................. 280 FLOW CONTROL REGISTER ..................................................................................................................................... 280 BACK PRESSURE REGISTER .................................................................................................................................... 280 WAKE-ON-LAN REGISTER ..................................................................................................................................... 281 WAKE-ON-LAN STATUS REGISTER ........................................................................................................................ 282 WAKE-UP FRAME CRC REGISTER .......................................................................................................................... 282 WAKE-UP FRAME BYTE MASK 1ST DOUBLE WORD REGISTER ............................................................................... 282 WAKE-UP FRAME BYTE MASK 1ST DOUBLE WORD REGISTER ............................................................................... 283 WAKE-UP FRAME BYTE MASK 1ST DOUBLE WORD REGISTER ............................................................................... 283 WAKE-UP FRAME BYTE MASK 4ST DOUBLE WORD REGISTER ............................................................................... 284 TEST SEED REGISTER ............................................................................................................................................. 285 DMA/FIFO STATE REGISTER ................................................................................................................................. 285 TEST MODE REGISTER ............................................................................................................................................ 285 TX_MCOL AND TX_SCOL COUNTER REGISTER .................................................................................................. 285 RPF AND AEP COUNTER REGISTER ........................................................................................................................ 286 XM AND PG COUNTER REGISTER........................................................................................................................... 286 RUNT_CNT AND TLCC COUNTER REGISTER ....................................................................................................... 286 CRCER_CNT AND FTL_CNT COUNTER REGISTER .............................................................................................. 286 RLC AND RCC COUNTER REGISTER ...................................................................................................................... 286 BROC COUNTER REGISTER. .................................................................................................................................. 286 MULCA COUNTER REGISTER ................................................................................................................................ 287 RP COUNTER REGISTER.......................................................................................................................................... 287 XP COUNTER REGISTER ......................................................................................................................................... 287 BASIC MODE CONTROL REGISTER (BMCR) ........................................................................................................... 288 BASIC MODE STATUS REGISTER (BMSR) ............................................................................................................... 288 PHY IDENTIFIER REGISTER 1 ................................................................................................................................. 289 PHY IDENTIFIER REGISTER 2 ................................................................................................................................. 290 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) .................................................................................... 290 DEFINITIONS FOR AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) ......................................... 291 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ............................................................................................. 292 BLOCK SIZE OF EACH MODE ................................................................................................................................... 300 CIPHER OPERATION CYCLE..................................................................................................................................... 300 MEMORY MAP/REGISTER DEFINITION ...................................................................................................................... 300 ENCRYPTION CONTROL REGISTER ........................................................................................................................... 301 RESERVED REGISTER .............................................................................................................................................. 302 FIFO STATUS REGISTER .......................................................................................................................................... 302 PARITY ERROR REGISTER ........................................................................................................................................ 302 SECURITY KEY N REGISTER .................................................................................................................................... 302 INITIAL VECTOR N REGISTER .................................................................................................................................. 303 DMA SOURCE ADDRESS REGISTER .......................................................................................................................... 303 DMA DESTINATION REGISTER ................................................................................................................................ 303

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TABLE 12-12. TABLE 12-13. TABLE 12-14. TABLE 12-15. TABLE 12-16. TABLE 12-17. TABLE 12-18. TABLE 12-19. TABLE 12-20. TABLE 12-21. TABLE 12-22. TABLE 12-23. TABLE 12-24. TABLE 12-25. TABLE 12-26. TABLE 12-27. TABLE 13-1. TABLE 13-2. TABLE 13-3. TABLE 13-4. TABLE 13-5. TABLE 13-6. TABLE 13-7. TABLE 13-8. TABLE 13-9. TABLE 13-10. TABLE 13-11. TABLE 13-12. TABLE 13-13. TABLE 13-14. TABLE 13-15. TABLE 13-16. TABLE 13-17. TABLE 13-18. TABLE 13-19. TABLE 13-20. TABLE 13-21. TABLE 13-22. TABLE 13-23. TABLE 13-24. TABLE 13-25. TABLE 13-26. TABLE 13-27. TABLE 13-28. TABLE 13-29. TABLE 13-30. TABLE 13-31. TABLE 13-32. TABLE 13-33. TABLE 13-34. TABLE 13-35. TABLE 13-36. TABLE 13-37. TABLE 13-38.

DMA TRANSFER SIZE REGISTER.............................................................................................................................. 303 DMA CONTROL REGISTER ...................................................................................................................................... 304 FIFO THRESHOLD REGISTER ................................................................................................................................... 304 INTERRUPT ENABLE REGISTER ................................................................................................................................ 304 INTERRUPT SOURCE REGISTER ................................................................................................................................ 305 MASKED INTERRUPT STATUS................................................................................................................................... 305 INTERRUPT CLEAR REGISTER .................................................................................................................................. 305 REVISION REGISTER ................................................................................................................................................ 305 FEATURE REGISTER ................................................................................................................................................. 305 LAST INITIAL VECTOR N REGISTER ......................................................................................................................... 306 BYTE SEQUENCE OF INITIAL VECTOR ..................................................................................................................... 306 AES-128 KEY STREAM OF BYTE SEQUENCE .......................................................................................................... 306 AES-192 KEY STREAM OF BYTE SEQUENCE .......................................................................................................... 307 AES-256 KEY STREAM OF BYTE SEQUENCE. ......................................................................................................... 307 DES KEY STREAM OF BYTE SEQUENCE. ................................................................................................................ 307 TRIPLE-DES KEY STREAM OF BYTE SEQUENCE ..................................................................................................... 308 SUMMARY OF THE USBC REGISTERS ..................................................................................................................... 328 HC CAPABILITY REGISTER ..................................................................................................................................... 329 HC STRUCTURE PARAMETERS ................................................................................................................................ 329 HC CAPABILITY PARAMETERS ................................................................................................................................ 329 HC USB COMMAND REGISTER .............................................................................................................................. 330 HC USB STATUS REGISTER .................................................................................................................................... 331 HC USB INTERRUPT ENABLE REGISTER ................................................................................................................ 332 HC FRAME INDEX REGISTER .................................................................................................................................. 333 HC PERIODIC FRAME LIST BASE ADDRESS REGISTER............................................................................................. 333 HC CURRENT ASYNCHRONOUS LIST ADDRESS REGISTER ...................................................................................... 333 HC PORT STATUS AND CONTROL REGISTER ............................................................................................................ 333 MISCELLANEOUS REGISTER ................................................................................................................................... 335 OTG CONTROL/STATUS REGISTER (ADDRESS = 080H)........................................................................................... 336 OTG INTERRUPT STATUS REGISTER ....................................................................................................................... 338 OTG INTERRUPT ENABLE REGISTER ...................................................................................................................... 340 HC/OTG/DEV INTERRUPT STATUS REGISTER........................................................................................................ 340 MASK OF HC/OTG/DEV INTERRUPT ..................................................................................................................... 340 MAIN CONTROL REGISTER ..................................................................................................................................... 341 DEVICE ADDRESS REGISTER .................................................................................................................................... 342 TEST REGISTER....................................................................................................................................................... 342 SOF FRAME NUMBER REGISTER ............................................................................................................................ 343 SOF MASK TIME REGISTER .................................................................................................................................... 343 PHY TEST MODE REGISTER ..................................................................................................................................... 343 VENDOR-SPECIFIC I/O CONTROL REGISTER ............................................................................................................. 344 CX CONFIGURATION AND STATUS REGISTER ........................................................................................................... 344 CONFIGURATION AND FIFO STATUS REGISTER ....................................................................................................... 345 IDLE COUNTER REGISTER ........................................................................................................................................ 345 MASK OF INTERRUPT GROUP REGISTER ................................................................................................................... 346 MASK OF INTERRUPT SOURCE GROUP 0 REGISTER ................................................................................................... 346 MASK OF INTERRUPT SOURCE GROUP 1 REGISTER ................................................................................................... 347 MASK OF INTERRUPT SOURCE GROUP 2 REGISTER ................................................................................................... 347 INTERRUPT GROUP REGISTER .................................................................................................................................. 348 INTERRUPT SOURCE GROUP 0 REGISTER .................................................................................................................. 348 INTERRUPT SOURCE GROUP 1 REGISTER .................................................................................................................. 349 INTERRUPT SOURCE GROUP 2 REGISTER .................................................................................................................. 349 RECEIVE ZERO-LENGTH DATA PACKET REGISTER .................................................................................................... 351 TRANSFER ZERO-LENGTH DATA PACKET REGISTER .................................................................................................. 352 ISOCHRONOUS SEQUENTIAL ERROR/ABORT REGISTER ............................................................................................. 352

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TABLE 13-39. TABLE 13-40. TABLE 13-41. TABLE 13-42. TABLE 13-43. TABLE 13-44. TABLE 13-45. TABLE 13-46. TABLE 13-47. TABLE 13-48. TABLE 13-49. TABLE 13-50. TABLE 13-51. TABLE 13-52. TABLE 13-53. TABLE 14-1. TABLE 14-2. TABLE 14-3. TABLE 14-4. TABLE 14-5. TABLE 14-6. TABLE 14-7. TABLE 14-8. TABLE 14-9. TABLE 14-10. TABLE 14-11. TABLE 14-12. TABLE 14-13. TABLE 14-14. TABLE 14-15. TABLE 14-16. TABLE 14-17. TABLE 14-18. TABLE 14-19. TABLE 14-20. TABLE 14-21. TABLE 14-22. TABLE 14-23. TABLE 14-24. TABLE 14-25. TABLE 14-26. TABLE 14-27. TABLE 14-28. TABLE 14-29. TABLE 14-30. TABLE 14-31. TABLE 14-32. TABLE 14-33. TABLE 14-34. TABLE 14-35. TABLE 14-36. TABLE 14-37. TABLE 14-38. TABLE 14-39.

IN ENDPOINT X MAXPACKET SIZE REGISTER ............................................................................................................ 353 OUT ENDPOINT X MAXPACKETSIZE REGISTER ......................................................................................................... 354 ENDPOINT 1~4 MAP REGISTER ................................................................................................................................ 354 ENDPOINT 5~8 MAP REGISTER ................................................................................................................................ 355 FIFO MAP REGISTER ............................................................................................................................................... 356 FIFO CONFIGURATION ............................................................................................................................................ 356 FIFO X INSTRUCTION AND BYTE COUNT REGISTER ................................................................................................. 358 DMA TARGET FIFO NUMBER REGISTER ................................................................................................................. 359 DMA CONTROLLER PARAMETER SETTING 1 REGISTER ............................................................................................ 359 DMA CONTROLLER PARAMETER SETTING 2 REGISTER ............................................................................................ 361 DMA CONTROLLER PARAMETER SETTING 3 REGISTER ............................................................................................ 361 DMA CONTROLLER STATUS REGISTER .................................................................................................................... 362 XCVRSELECT AND TERMSELECT ............................................................................................................................ 369 LINE STATE AND TRANSFER MODE SELECTION (3) ................................................................................................. 370 HS INTER-PACKET DELAY FOR A RECEIVE FOLLOWED BY A TRANSMIT .......................................................................... 370 MPEG4 ENCODER/DECODER LOCAL MEMORY MAPPING ...................................................................................... 385 MPEG-4 ENCODER/DECODER CONTROL REGISTERS AND LOCAL MEMORY........................................................... 385 JPEG ENCODER/DECODER REGISTERS ................................................................................................................... 386 ME CONTROL REGISTER OFFSET............................................................................................................................ 387 MECR .................................................................................................................................................................... 387 MINIMUM SAD RESULT REGISTER ......................................................................................................................... 387 ME COMMAND QUEUE START ADDRESS REGISTER ................................................................................................ 388 MECADDR ........................................................................................................................................................... 388 HOFFSET .............................................................................................................................................................. 388 MCCTL ................................................................................................................................................................. 388 MEIADDR............................................................................................................................................................. 390 CPSTS ................................................................................................................................................................... 390 QCR0 ..................................................................................................................................................................... 392 DZAR/QAR ........................................................................................................................................................... 392 ACDCPBAR .......................................................................................................................................................... 392 VADR .................................................................................................................................................................... 392 CURDEV ............................................................................................................................................................... 393 BADR .................................................................................................................................................................... 393 BALR .................................................................................................................................................................... 393 MCIADDR ............................................................................................................................................................ 394 VLDCTL ............................................................................................................................................................... 394 VOPO .................................................................................................................................................................... 395 VOP1 ..................................................................................................................................................................... 395 MVD0/SCODE ...................................................................................................................................................... 395 MVD1/RSMRK ..................................................................................................................................................... 396 TOADR ................................................................................................................................................................. 396 VLDSTS ................................................................................................................................................................ 398 ABADR ................................................................................................................................................................. 399 INNER_CPUCTL .................................................................................................................................................... 399 VOP_SIZE ............................................................................................................................................................. 400 PMVADDR ............................................................................................................................................................ 400 DTOFMT ............................................................................................................................................................... 401 INNER_MASK ..................................................................................................................................................... 401 EXT_MASK .......................................................................................................................................................... 401 INT_FLAG ............................................................................................................................................................ 402 INT_STS................................................................................................................................................................ 403 MCUBR ................................................................................................................................................................. 403 MCUTIR................................................................................................................................................................ 404 PYDCR .................................................................................................................................................................. 404

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TABLE 14-40. TABLE 14-41. TABLE 14-42. TABLE 14-43. TABLE 14-44. TABLE 14-45. TABLE 14-46. TABLE 14-47. TABLE 14-48. TABLE 14-49. TABLE 14-50. TABLE 14-51. TABLE 14-52. TABLE 14-53. TABLE 14-54. TABLE 14-55. TABLE 14-56. TABLE 14-57. TABLE 14-58. TABLE 14-59. TABLE 14-60. TABLE 14-61. TABLE 14-62. TABLE 14-63. TABLE 14-64. TABLE 14-65. TABLE 15-1. TABLE 15-2. TABLE 15-3. TABLE 15-4. TABLE 15-5. TABLE 15-6. TABLE 15-7. TABLE 15-8. TABLE 15-9. TABLE 15-10. TABLE 15-11. TABLE 15-12. TABLE 15-13. TABLE 15-14. TABLE 15-15. TABLE 15-16. TABLE 15-17. TABLE 15-18. TABLE 15-19. TABLE 15-20. TABLE 15-21. TABLE 15-22. TABLE 15-23. TABLE 15-24. TABLE 15-25. TABLE 15-26. TABLE 15-27. TABLE 15-28.

PUVDCR ............................................................................................................................................................... 404 VLDLUTR............................................................................................................................................................. 404 VLASTWORD ...................................................................................................................................................... 405 JPGSEQCLT ............................................................................................................................................................ 405 JPGFRMINFO1 ........................................................................................................................................................ 405 JPGFRMINFO2 ........................................................................................................................................................ 406 JPGFRMINFO3 ........................................................................................................................................................ 406 ME COMMANDS ..................................................................................................................................................... 408 ME COMMAND SEQUENCE EXAMPLE IN ENCODING MODE .................................................................................... 412 ME COMMAND SEQUENCE EXAMPLE IN DECODING MODE .................................................................................... 412 DMA CONTROL REGISTERS.................................................................................................................................... 413 DMA SYSTEM MEMORY BASE ADDRESS REGISTER ............................................................................................... 414 DMA LOCAL MEMORY BASE ADDRESS /BLOCK WIDTH REGISTER ........................................................................ 414 DMA BLOCK WIDTH REGISTER ............................................................................................................................. 415 DMA CONTROL AND LENGTH REGISTER ................................................................................................................ 415 DMA CHAIN COMMAND ADDRESS REGISTER ........................................................................................................ 417 DMA STATUS REGISTER ......................................................................................................................................... 417 DMA GROUP CONTROL REGISTER ......................................................................................................................... 417 DMA GROUP SYNC REGISTER ................................................................................................................................ 417 DMA AUTO-BUFFER CONTROL REGISTER .............................................................................................................. 418 DMA THRESHOLD VALUE REGISTER ...................................................................................................................... 418 DMA AUTO INTERRUPT REGISTER ......................................................................................................................... 418 SYSTEM BITSTREAM BUFFER SIZE.......................................................................................................................... 419 JPEG FRAME INFORMATION REGISTER 4 ................................................................................................................ 419 JPEG FRAME INFORMATION REGISTER 5 ................................................................................................................ 419 JPEG FRAME INFORMATION REGISTER 6 ................................................................................................................ 420 U-R BT. 656 EAV AND SAV SEQUENCE ................................................................................................................. 422 VIDEO CAPTURE CONTROL REGISTERS .................................................................................................................. 429 CAPTURE CONTROL REGISTER ............................................................................................................................... 432 VAPUPD REGISTER ............................................................................................................................................... 433 TIMING DIAGRAM OF SYNC_REG_UPDATE .............................................................................................................. 434 CLOCK CONTROL REGISTER ................................................................................................................................... 434 PVSIZE0 REGISTER ............................................................................................................................................... 434 PVSIZE1 REGISTER ............................................................................................................................................... 435 PVSIZE2 REGISTER ............................................................................................................................................... 435 RCSIZE0 REGISTER ............................................................................................................................................... 435 RCSIZE1 REGISTER ............................................................................................................................................... 435 RCSIZE2 REGISTER ............................................................................................................................................... 436 BORDER_SIZE REGISTER .................................................................................................................................... 436 BORDER_COLOR REGISTER ............................................................................................................................... 437 DESTFORMAT REGISTER ..................................................................................................................................... 437 FMRATE REGISTER ............................................................................................................................................... 439 SRCIF REGISTER.................................................................................................................................................... 440 SRCSIZE0 REGISTER ............................................................................................................................................. 442 PVSIZE3 REGISTER ............................................................................................................................................... 442 PVSIZE4 REGISTER ............................................................................................................................................... 442 SRCSIZE1 REGISTER ............................................................................................................................................. 442 RCSIZE3 REGISTER ............................................................................................................................................... 443 RCSIZE4 REGISTER ............................................................................................................................................... 443 DICTRL0 REGISTER ............................................................................................................................................. 444 DICTRL1 REGISTER .............................................................................................................................................. 444 DNCTRL0 REGISTER ............................................................................................................................................. 444 DNCTRL1 REGISTER ............................................................................................................................................. 444 DNCTRL2 REGISTER ............................................................................................................................................. 444

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TABLE 15-29. TABLE 15-30. TABLE 15-31. TABLE 15-32. TABLE 15-33. TABLE 15-34. TABLE 15-35. TABLE 15-36. TABLE 15-37. TABLE 15-38. TABLE 15-39. TABLE 15-40. TABLE 15-41. TABLE 15-42. TABLE 15-43. TABLE 15-44. TABLE 15-45. TABLE 15-46. TABLE 15-47. TABLE 15-48. TABLE 15-49. TABLE 15-50. TABLE 15-51. TABLE 15-52. TABLE 15-53. TABLE 15-54. TABLE 15-55. TABLE 15-56. TABLE 15-57. TABLE 15-58. TABLE 15-59. TABLE 15-60. TABLE 15-61. TABLE 15-62. TABLE 15-63. TABLE 15-64. TABLE 15-65. TABLE 15-66. TABLE 15-67. TABLE 15-68. TABLE 15-69. TABLE 15-70. TABLE 15-71. TABLE 15-72. TABLE 15-73. TABLE 15-74. TABLE 15-75. TABLE 15-76. TABLE 15-77. TABLE 15-78. TABLE 15-79. TABLE 15-80. TABLE 15-81. TABLE 15-82.

PDMA0 REGISTER ................................................................................................................................................. 445 RDMA0 REGISTER ................................................................................................................................................. 446 MEMSRC0 REGISTER ............................................................................................................................................ 447 MEMSRC1 REGISTER ............................................................................................................................................ 447 MEMSRC2 REGISTER ............................................................................................................................................ 447 PDMA1 REGISTER ................................................................................................................................................. 448 RDMA1 REGISTER ................................................................................................................................................. 448 PMDEST0 REGISTER ............................................................................................................................................. 448 PMDEST1 REGISTER ............................................................................................................................................. 448 PMDEST2 REGISTER ............................................................................................................................................. 448 PMDEST3 REGISTER ............................................................................................................................................. 449 PMDEST4 REGISTER ............................................................................................................................................. 449 PMDEST5 REGISTER ............................................................................................................................................. 449 RMDEST0 REGISTER ............................................................................................................................................ 449 RMDEST1 REGISTER ............................................................................................................................................ 449 RMDEST2 REGISTER ............................................................................................................................................ 450 RMDEST3 REGISTER ............................................................................................................................................ 450 RMDEST4 REGISTER ............................................................................................................................................ 450 RMDEST5 REGISTER ............................................................................................................................................ 450 VBICTRL0 REGISTER ............................................................................................................................................ 450 VBICTRL1 REGISTER ............................................................................................................................................ 450 VBICTRL2 REGISTER ............................................................................................................................................ 450 VBICTRL3 REGISTER ............................................................................................................................................ 451 OSDFONT REGISTER ............................................................................................................................................ 451 OSDDISP REGISTER .............................................................................................................................................. 451 OSDREAD REGISTER ............................................................................................................................................ 452 OSDEN REGISTER ................................................................................................................................................. 452 OSDPAT0 REGISTER .............................................................................................................................................. 453 OSDPAT1 REGISTER .............................................................................................................................................. 453 OSDPAT2 REGISTER .............................................................................................................................................. 453 OSDPAT3 REGISTER .............................................................................................................................................. 453 OSDPAT4 REGISTER .............................................................................................................................................. 453 OSDPAT5 REGISTER .............................................................................................................................................. 454 OSDPAT6 REGISTER .............................................................................................................................................. 454 OSDCOR0 REGISTER ............................................................................................................................................ 454 OSDWSZ0 REGISTER ............................................................................................................................................ 455 OSDSSZ0 REGISTER .............................................................................................................................................. 455 OSDFSZ0 REGISTER .............................................................................................................................................. 455 OSDCOR1 REGISTER ............................................................................................................................................ 455 OSDWSZ1 REGISTER ............................................................................................................................................ 456 OSDSSZ1 REGISTER .............................................................................................................................................. 456 OSDFSZ1 REGISTER .............................................................................................................................................. 456 OSDCOR2 REGISTER ............................................................................................................................................ 457 OSDWSZ2 REGISTER ............................................................................................................................................ 457 OSDSSZ2 REGISTER .............................................................................................................................................. 457 OSDFSZ2 REGISTER .............................................................................................................................................. 458 OSDCOR3 REGISTER ............................................................................................................................................. 458 OSDWSZ3 REGISTER ............................................................................................................................................ 458 OSDSSZ3 REGISTER .............................................................................................................................................. 459 OSDFSZ3 REGISTER .............................................................................................................................................. 459 INTSTS REGISTER ................................................................................................................................................. 459 INTMASK REGISTER ............................................................................................................................................ 459 TEST_PAT0 REGISTER .......................................................................................................................................... 460 TEST_PAT1 REGISTER .......................................................................................................................................... 461

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TABLE 16-1. TABLE 16-2. TABLE 17-1. TABLE 17-2. TABLE 17-3. TABLE 17-4. TABLE 17-5. TABLE 17-6. TABLE 17-7. TABLE 17-8. TABLE 17-9. TABLE 17-10. TABLE 17-11. TABLE 17-12. TABLE 17-13. TABLE 17-14. TABLE 17-15. TABLE 17-16. TABLE 17-17. TABLE 17-18. TABLE 17-19. TABLE 18-1. TABLE 18-2. TABLE 18-3. TABLE 18-4. TABLE 18-5. TABLE 18-6. TABLE 18-7. TABLE 18-8. TABLE 18-9. TABLE 18-10. TABLE 18-11. TABLE 18-12. TABLE 18-13. TABLE 18-14. TABLE 18-15. TABLE 18-16. TABLE 18-17. TABLE 18-18. TABLE 18-19. TABLE 19-1. TABLE 19-2. TABLE 19-3. TABLE 19-4. TABLE 19-5. TABLE 19-6. TABLE 19-7. TABLE 19-8. TABLE 19-9. TABLE 19-10. TABLE 19-11. TABLE 19-12. TABLE 19-13. TABLE 19-14.

SUMMARY OF APB BRIDGE REGISTERS .................................................................................................................. 464 APB SLAVE N BASE/SIZE REGISTER ....................................................................................................................... 464 INTERRUPT ROUTING TABLE FOR IRQS ................................................................................................................. 467 INTERRUPT ROUTING TABLE FOR FRQS ................................................................................................................. 469 SUMMARY OF INTERRUPT CONTROLLER REGISTERS ............................................................................................... 471 THE IRQ SOURCE REGISTER................................................................................................................................... 471 THE IRQ MASK REGISTER ...................................................................................................................................... 471 THE IRQ INTERRUPT CLEAR REGISTER .................................................................................................................. 472 THE IRQ TRIG MODE REGISTER ............................................................................................................................. 472 THE IRQ TRIG LEVEL REGISTER ............................................................................................................................ 472 THE IRQ STATUS REGISTER .................................................................................................................................... 472 THE FIQ SOURCE REGISTER ................................................................................................................................... 472 THE FIQ MASK REGISTER ...................................................................................................................................... 473 THE FIQ INTERRUPT CLEAR REGISTER................................................................................................................... 473 THE FIQ TRIG MODE REGISTER ............................................................................................................................. 473 THE FIQ TRIG LEVEL REGISTER ............................................................................................................................. 473 THE FIQ STATUS REGISTER .................................................................................................................................... 473 REVISION REGISTER ............................................................................................................................................... 473 FEATURE REGISTER FOR INPUT NUMBER ................................................................................................................ 474 FEATURE REGISTER FOR IRQ DE-BOUNCE LOCATION ............................................................................................ 474 FEATURE REGISTER FOR FIQ DE-BOUNCE LOCATION ............................................................................................. 474 SUMMARY OF GENERAL PURPOSE I/O REGISTERS .................................................................................................. 476 GPIO DATAOUT REGISTER ..................................................................................................................................... 480 GPIO DATAIN REGISTER ........................................................................................................................................ 480 PIN DIRECTION REGISTER....................................................................................................................................... 480 GPIO DATA BIT SET REGISTER ............................................................................................................................... 481 GPIO DATA BIT CLEAR REGISTER .......................................................................................................................... 481 PIN PULL ENABLE REGISTER .................................................................................................................................. 481 PIN PULL TYPE REGISTER ....................................................................................................................................... 481 PULL TRUTH TABLE ................................................................................................................................................ 481 INTERRUPT ENABLE REGISTER ............................................................................................................................... 482 INTERRUPT RAW STATE REGISTER .......................................................................................................................... 482 INTERRUPT MASKED STATE REGISTER ................................................................................................................... 482 INTERRUPT MASK REGISTER .................................................................................................................................. 482 INTERRUPT CLEAR .................................................................................................................................................. 482 INTERRUPT TRIGGER METHOD REGISTER ............................................................................................................... 483 INTERRUPT BOTH EDGE TRIGGER REGISTER .......................................................................................................... 483 INTERRUPT RISE OR NEG EDGE TRIGGER REGISTER ............................................................................................... 483 BOUNCE ENABLE REGISTER ................................................................................................................................... 483 BOUNCE CLOCK PRE-SCALE REGISTER .................................................................................................................. 484 SUMMARY OF PWM CONTROL REGISTER ............................................................................................................... 488 MASTER ENABLE AND CLEAR CONTROL REGISTER (OFFSET==0X00).................................................................... 489 MASTER OUTPUT MODE REGISTER (OFFSET==0X04) ............................................................................................ 489 PWM0 WAVEFORM CONTROL REGISTER (OFFSET==0X10) ................................................................................... 490 PWM0 EDGE COUNT REGISTER A (OFFSET==0X14) .............................................................................................. 490 PWM0 EDGE COUNT REGISTER B (OFFSET==0X18).............................................................................................. 491 PWM0 CURRENT COUNT REGISTER (OFFSET==0X1C) .......................................................................................... 491 PWM1 WAVEFORM CONTROL REGISTER (OFFSET==0X20).................................................................................... 491 PWM1 EDGE COUNT REGISTER A (OFFSET==0X24) .............................................................................................. 491 PWM1 EDGE COUNT REGISTER B (OFFSET==0X28).............................................................................................. 492 PWM1 CURRENT COUNT REGISTER (OFFSET==0X2C) .......................................................................................... 492 PWM2 WAVEFORM CONTROL REGISTER (OFFSET==0X30).................................................................................... 492 PM2 EDGE COUNT REGISTER A (OFFSET==0X34) ................................................................................................. 492 PWM2 EDGE COUNT REGISTER B (OFFSET==0X38).............................................................................................. 493

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TABLE 19-15. TABLE 20-1. TABLE 20-2. TABLE 20-3. TABLE 20-4. TABLE 20-5. TABLE 20-6. TABLE 20-7. TABLE 20-8. TABLE 21-1. TABLE 21-2. TABLE 21-3. TABLE 21-4. TABLE 21-5. TABLE 21-6. TABLE 21-7. TABLE 21-8. TABLE 22-1. TABLE 22-2. TABLE 22-3. TABLE 22-4. TABLE 22-5. TABLE 22-6. TABLE 22-7. TABLE 22-8. TABLE 22-9. TABLE 22-10. TABLE 22-11. TABLE 22-12. TABLE 22-13. TABLE 22-14. TABLE 22-15. TABLE 22-16. TABLE 22-17. TABLE 22-18. TABLE 22-19. TABLE 22-20. TABLE 22-21. TABLE 22-22. TABLE 22-23. TABLE 22-24. TABLE 22-25. TABLE 22-26. TABLE 22-27. TABLE 22-28. TABLE 22-29. TABLE 22-30. TABLE 22-31. TABLE 22-32. TABLE 22-33. TABLE 22-34. TABLE 22-35. TABLE 22-36. TABLE 23-1.

PWM2 CURRENT COUNT REGISTER (OFFSET==0X3C) .......................................................................................... 493 SUMMARY OF I2C CONTROLLER REGISTER ............................................................................................................. 496 I2C CONTROL REGISTER ........................................................................................................................................ 496 I2C STATUS REGISTER ............................................................................................................................................. 498 I2C CLOCK DIVIDER REGISTER .............................................................................................................................. 499 I2C DATA REGISTER ................................................................................................................................................ 499 I2C SLAVE ADDRESS REGISTER............................................................................................................................... 500 I2C SET / HOLD TIME & GLITCH SUPPRESSION SETTING REGISTER. ...................................................................... 500 I2C BUS MONITOR REGISTER.................................................................................................................................. 501 SUMMARY OF WDT REGISTERS .............................................................................................................................. 505 WDCOUNTER REGISTER ......................................................................................................................................... 506 WDLOAD REGISTER ............................................................................................................................................... 506 WDRESTART REGISTER .......................................................................................................................................... 506 WDCR REGISTER ................................................................................................................................................... 506 WDSTATUS REGISTER ............................................................................................................................................. 507 WDCLEAR REGISTER.............................................................................................................................................. 507 WDINTRCTER REGISTER ........................................................................................................................................ 507 TIMER/COUNTER REGISTER SUMMARY .................................................................................................................. 513 GLOBAL MODE REGISTER ...................................................................................................................................... 514 TIMER/COUNTER INPUT/OUTPUT MODE REGISTER ................................................................................................ 515 GPTC INPUT/OUTPUT POLARITY REGISTER ............................................................................................................ 516 GPTC GLOBAL TRIGGER REGISTER ....................................................................................................................... 517 GPTC INTERRUPT STATUS REGISTER ..................................................................................................................... 518 TIMER/COUNTER (X=0,1,2) MODE REGISTER ......................................................................................................... 522 RELOAD REGISTER ................................................................................................................................................. 524 CURRENT TIMER REGISTER .................................................................................................................................... 525 TIMER/COUNTER (X=0,1,2) RELOAD REGISTER (GPTCX_SVR) ............................................................................ 525 TIMER/COUNTER (X=0,1,2) RELOAD REGISTER (GPTCX_STICR) STATUS (READ) ................................................ 525 TIMER/COUNTER (X=0,1,2) RELOAD REGISTER (GPTCX_STICR) INTERRUPT CLEAR (WRITE) ............................ 526 GPTC GLOBAL MODE REGISTER ............................................................................................................................. 528 TIMER/COUNTER I/O MODE REGISTER .................................................................................................................... 528 TIMER/COUNTER I/O POLARITY REGISTER .............................................................................................................. 528 TIMER/COUNTER 0 MODE REGISTER ........................................................................................................................ 528 T/C CONFIGURATION FOR EXTERNAL TRIGGERING ................................................................................................. 531 TIMER/COUNTER I/O MODE REGISTER .................................................................................................................... 531 TIMER/COUNTER I/O POLARITY REGISTER .............................................................................................................. 531 TIMER/COUNTER 0 MODE REGISTER ........................................................................................................................ 531 CONFIGURATION FOR WATCHDOG MONITOR OF EXTERNAL LOGIC ........................................................................ 533 TIMER/COUNTER I/O MODE REGISTER .................................................................................................................... 534 TIMER/COUNTER I/O POLARITY REGISTER .............................................................................................................. 534 TIMER/COUNTER 0 MODE REGISTER ........................................................................................................................ 534 CONFIGURATION SINGLE CYCLE OPERATION.......................................................................................................... 535 TIMER/COUNTER 0 MODE REGISTER ........................................................................................................................ 536 CONFIGURATION FOR TIMER CHAINING (48-BIT) .................................................................................................... 537 TIMER/COUNTER I/O MODE REGISTER .................................................................................................................... 537 TIMER/COUNTER 0 MODE REGISTER ........................................................................................................................ 538 TIMER/COUNTER 1 MODE REGISTER ........................................................................................................................ 538 TIMER/COUNTER 2 MODE REGISTER ........................................................................................................................ 538 WAVEFORM MODULE.............................................................................................................................................. 542 WAVEFORM MODULE (X=1 OR 2) MODE REGISTER (WFX_MR) ............................................................................ 543 WAVEFORM MODULE (X=1 OR 2) MODE REGISTER (WFX_RDP) ........................................................................... 544 WAVEFORM MODULE (X=1 OR 2) MODE REGISTER (WFX_WRP) .......................................................................... 545 WAVEFORM MODULE (X=1 OR 2) MODE REGISTER (WFX_CP) .............................................................................. 545 CROSSING CLOCK DOMAIN SIGNALS ...................................................................................................................... 547

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TABLE 23-2. TABLE 23-3. TABLE 23-4. TABLE 23-5. TABLE 23-6. TABLE 23-7. TABLE 23-8. TABLE 23-9. TABLE 23-10. TABLE 23-11. TABLE 23-12 TABLE 23-13 TABLE 23-14 TABLE 23-15 TABLE 23-16 TABLE 23-17. TABLE 23-18. TABLE 24-1. TABLE 24-2. TABLE 24-3. TABLE 24-4. TABLE 24-5. TABLE 24-6. TABLE 24-7. TABLE 24-8. TABLE 24-9. TABLE 24-10. TABLE 24-11. TABLE 24-12. TABLE 24-13. TABLE 24-14. TABLE 24-15. TABLE 24-16. TABLE 24-17. TABLE 24-18 TABLE 24-19. TABLE 24-20. TABLE 24-21. TABLE 24-22. TABLE 24-23. TABLE 24-24. TABLE 25-1. TABLE 25-2. TABLE 25-3. TABLE 25-4. TABLE 25-5. TABLE 25-6. TABLE 25-7. TABLE 25-8. TABLE 25-9. TABLE 25-10. TABLE 25-11. TABLE 25-12. TABLE 26-1.

SUMMARY OF RTC REGISTERS ............................................................................................................................... 548 RTCSECOND REGISTER ........................................................................................................................................... 549 RTCMINUTE REGISTER ........................................................................................................................................... 549 RTCHOUR REGISTER............................................................................................................................................... 550 RTCDAY REGISTER ................................................................................................................................................ 550 ALARMSECOND REGISTER ..................................................................................................................................... 550 ALARMMINUTE REGISTER ..................................................................................................................................... 550 ALARMHOUR REGISTER ......................................................................................................................................... 550 RTCRECORD REGISTER ........................................................................................................................................... 551 RTC CONTROL REGISTER ....................................................................................................................................... 551 WRTCSECOND REGISTER ....................................................................................................................................... 552 WRTCMINUTE REGISTER ....................................................................................................................................... 552 WRTCHOUR REGISTER ........................................................................................................................................... 552 WRTCDAY REGISTER ............................................................................................................................................. 553 INTRSTATE REGISTER ............................................................................................................................................. 553 RTCDIVIDE REGISTER............................................................................................................................................. 553 RTCREVISION REGISTER ......................................................................................................................................... 553 SUMMARY OF SD HOST CONTROLLER REGISTERS .................................................................................................. 557 COMMAND REGISTER ............................................................................................................................................. 558 ARGUMENT REGISTER (OFFSET: 0X04) ................................................................................................................... 558 RESPONSE0-3 REGISTER ......................................................................................................................................... 559 SHORT RESPONSE AND LONG RESPONSE. ............................................................................................................... 559 RESPONDED COMMAND REGISTER. ........................................................................................................................ 559 DATA CONTROL REGISTER. ..................................................................................................................................... 559 DATA BLOCK LENGTH............................................................................................................................................ 559 DATA TIMER REGISTER ........................................................................................................................................... 560 DATA LENGTH REGISTER. ....................................................................................................................................... 560 STATUS REGISTER ................................................................................................................................................... 561 CLEAR REGISTER. ................................................................................................................................................... 561 INTERRUPT MASK REGISTER. ................................................................................................................................. 562 POWER CONTROL REGISTER ................................................................................................................................... 562 CLOCK CONTROL REGISTER ................................................................................................................................... 562 BUS WIDTH REGISTER ............................................................................................................................................ 563 DATA WINDOW REGISTER ....................................................................................................................................... 563 MMC INTERRUPT RESPONSE TIME ......................................................................................................................... 563 GENERAL PURPOSE OUTPUT ................................................................................................................................... 563 SDIO CONTROL REGISTER (OFFSET: 0X6C)............................................................................................................ 564 SDIO CONTROL REGISTER ..................................................................................................................................... 564 SDIO STATUS REGISTER ......................................................................................................................................... 564 FEATURE REGISTER ................................................................................................................................................ 565 REVISION REGISTER ............................................................................................................................................... 565 SUMMARY OF CF HOST INTERFACE CONTROLLER REGISTERS................................................................................ 569 CF HOST STATUS REGISTER ................................................................................................................................... 569 CF HOST CONTROL REGISTER. ............................................................................................................................... 570 ACCESS TIMING CONFIGURATION REGISTER .......................................................................................................... 571 ATTRIBUTE MEMORY ACCESS TIMING TABLE ......................................................................................................... 572 COMMON MEMORY ACCESS TIMING TABLE ........................................................................................................... 572 I/O ACCESS TIMING TABLE. .................................................................................................................................... 573 ACTIVE BUFFER CONTROL REGISTER ..................................................................................................................... 573 ACTIVE BUFFER DATA REGISTER. ........................................................................................................................... 574 MULTI SECTOR REGISTER ....................................................................................................................................... 575 TRANSFER SIZE MODE2 ENABLE REGISTER ........................................................................................................... 575 TRANSFER SIZE MODE2 COUNTER REGISTER ......................................................................................................... 575 SUMMARY OF UART/SIR MODE REGISTERS .......................................................................................................... 587

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TABLE 26-2. TABLE 26-3. TABLE 26-4. TABLE 26-5. TABLE 26-6. TABLE 26-7. TABLE 26-8. TABLE 26-9. TABLE 26-10. TABLE 26-11. TABLE 26-12. TABLE 26-13. TABLE 26-14. TABLE 26-15. TABLE 26-16. TABLE 26-17. TABLE 26-18. TABLE 26-19. TABLE 26-20. TABLE 26-21. TABLE 26-22. TABLE 26-23. TABLE 26-24 TABLE 26-25. TABLE 26-26. TABLE 26-27. TABLE 26-28. TABLE 26-29. TABLE 26-30. TABLE 26-31. TABLE 26-32. TABLE 26-33. TABLE 26-34. TABLE 26-35. TABLE 26-36. TABLE 26-37. TABLE 26-38. TABLE 26-39. TABLE 26-40. TABLE 26-41. TABLE 27-1. TABLE 27-2. TABLE 27-3. TABLE 27-4. TABLE 27-5. TABLE 27-6. TABLE 27-7. TABLE 27-8.

RECEIVER BUFFER REGISTER ................................................................................................................................. 589 TRANSMITTER HOLDING REGISTER ........................................................................................................................ 589 INTERRUPT ENABLE REGISTER ............................................................................................................................... 589 INTERRUPT IDENTIFICATION REGISTER ................................................................................................................... 590 INTERRUPT CONTROL TABLE .................................................................................................................................. 590 FIFO CONTROL REGISTER ...................................................................................................................................... 592 RECEIVERS FIFO TRIGGER LEVEL ........................................................................................................................ 593 TRANSMITTERS FIFO TRIGGER LEVEL.................................................................................................................. 593 LINE CONTROL REGISTER ....................................................................................................................................... 593 PARITY SETTING TABLE ........................................................................................................................................... 594 WORD LENGTH AND STOP BITS SETTING TABLE..................................................................................................... 594 MODEM CONTROL REGISTER.................................................................................................................................. 595 LINE STATUS REGISTER .......................................................................................................................................... 596 MODEM STATUS REGISTER ..................................................................................................................................... 598 SCRATCH PAD REGISTER ......................................................................................................................................... 598 BAUDRATE DIVISOR LATCH LSB ............................................................................................................................ 598 BAUD RATE DIVISOR LATCH MSB. ........................................................................................................................ 599 PRESCALER REGISTER ............................................................................................................................................ 599 MODE DEFINITION REGISTER ................................................................................................................................. 599 AUXILIARY CONTROL REGISTER ............................................................................................................................ 600 STATUS FIFO TRIGGER LEVEL................................................................................................................................ 600 TRANSMIT FRAME LENGTH REGISTER LOW ........................................................................................................... 601 TRANSMIT FRAME LENGTH REGISTER HIGH .......................................................................................................... 601 MAXIMUM RECEIVER FRAME-LENGTH LOW .......................................................................................................... 601 MAXIMUM RECEIVER FRAME-LENGTH HIGH ......................................................................................................... 601 PREAMBLE LENGTH REGISTER ............................................................................................................................... 601 NUMBER OF FIR PREAMBLES ................................................................................................................................. 602 FIR MODE INTERRUPT IDENTIFICATION REGISTER ................................................................................................. 602 FIR MODE INTERRUPT IDENTIFICATION REGISTER ................................................................................................. 602 FIR MODE INTERRUPT ENABLE REGISTER ............................................................................................................. 603 IRDA MODE INTERRUPT ENABLE REGISTER........................................................................................................... 603 STATUS FIFO LINE STATUS REGISTER .................................................................................................................... 604 STATUS FIFO RECEIVED FRAME LENGTH REGISTER LOW ................................................................................... 604 STATUS FIFO RECEIVED FRAME LENGTH REGISTER HIGH .................................................................................. 604 FIR MODE LINK STATUS REGISTER ........................................................................................................................ 605 FIR MODE LINK STATUS INTERRUPT ENABLE REGISTER ........................................................................................ 605 RX FIFO COUNT REGISTER .................................................................................................................................... 606 LAST FRAME LENGTH REGISTER LOW.................................................................................................................... 606 LAST FRAME LENGTH REGISTER HIGH ................................................................................................................... 606 FRAME NUMBER DECODING TABLE ........................................................................................................................ 606 SUMMARY OF SSP CONTROL REGISTERS ................................................................................................................ 625 SSP CONTROL REGISTER 0 ..................................................................................................................................... 626 SSP CONTROL REGISTER 1 ..................................................................................................................................... 627 SSP CONTROL REGISTER 2 ..................................................................................................................................... 628 SSP STATUS REGISTER ........................................................................................................................................... 629 INTERRUPT CONTROL REGISTER ............................................................................................................................. 629 INTERRUPT STATUS REGISTER ................................................................................................................................ 630 AC97 MASK CONTROL REGISTER .......................................................................................................................... 631

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1. Introduction
The aJile Systems aJ-200 is the low-power, real-time, networked, direct execution microprocessor for the JME platform. The aJ-200 is designed to power the next wave of the Internet, secured, and smart appliances that require high-performance Java execution, real-time response, DSP, multimedia, network access capabilities in a secured manner. The aJ-200 directly executes Java Virtual MachineTM (JVM) bytecode instructions, real-time Java threading primitives, and a number of extended bytecode instructions for custom application accelerations. The native JVM bytecode implementation eliminates the typical interpreter or JIT software layers and provides the most optimal Java performance in both memory requirements and execution time. The microcoded RTOS and Java threading primitives also ensure fast, atomic executive operations like context switching object synchronization, scheduling and interrupt processing and eliminate traditional external RTOS layer. The aJ-200 features of a direct-execution Java processor core (JEMCore-IITM) with an enhanced DSP capability, on-chip 32 KB unified instruction and data cache (I&D), a single-chip 10/100 Ethernet controller, encryption/decryption engine, a single-chip USB OTG controller, three video capture ports, a MPEG4/JPEG encoder, an advanced LCD controller, and all I/O peripherals required for many networked real-time embedded devices. The aJ-200 microprocessor, bundled with Suns JME/CLDC or CDC/FP/PBP runtime system, optimizing application builder, debugging tools and evaluation systems provides a complete solution for implementing real-time, networked embedded devices, entirely in pure Java technology. The powerful combination of direct JVM bytecode execution, direct multithreading support, and fully protected multiple JVM environments is ideal for efficient, safe, and robust Java execution and dynamic delivery of the Java based applications / services on-demand over Internet. The aJ-200 is ideally suited to power the next generation of the Internet appliances: M2M cellular terminals iP cameras, video surveillance systems Personal navigation devices Mobile POS terminals Mobile gaming devices Wireless handhelds and webpads Internet VoIP screenphones iPTVs

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Technical Reference Manual 1.1. Features 32-bit Direct Execution Java Processor Core Native JVM bytecode instructions Byte, half-word and word operation Extended bytecode instructions for I/O, threading primitives, graphics, and multimedia operations like audio and DSP algorithms IEEE-754 floating-point arithmetic Fixed-point Multiplier Accumulator (MAC) Native Java threading support Hard real-time, multi-threading kernel in hardware o Thread-to-thread yield in less than 1sec @ 180 MHz o Eliminates traditional RTOS layer Support two independent JVMs in hardware 32 KB writeable control store (WCS) o o Real-time kernel Customs instructions o o Up to 320 Mbytes 360 MBytes/sec memory bandwidth

Peripheral Interrupt Controller Three 24-bit Timer/counters Six Pulse Width Modulations (PWMs) Watchdog Timer Real Time Clock (RTC) Backup battery 1 x Full functional UART 1 x Blue tooth UART 1 x Standard UART 1 x UART/IrDA Configurable shared I/Os Four 16550 Compatible UARTs

General Purpose I/O Ports DMA Controller Synchronous Serial Port (SSP) I2S/AC97/SPI I2C Interface SD/ SDIO/ MMC Memory Card Interface SD memory card protocol version 2.0 SDIO bus protocol version 1.10 Multi Media Card (MMC) version 4.1 CF specification version 1.4 TFC LCD panel interface o o Up to 24-bit bus Resolution programmable up to 1280 x1280 o o Pixel clock rate up to 120 MHz Programmable polarity/duration for output
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Integrated Cache 32 KB Unified Cache for I & D Seamless interface with FLASH (NOR & NAND), ROM, SRAM, and external peripheral devices 8-,16-, 32-bit interface Eight chip selects (banks) Up to 256 Mbytes Seamless interface with SDRAM and mobile SDRAM o 8-, 16-, 32-bit interface
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CF Memory Card Interface LCD Controller

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enable, vertical sync, horizontal sync, pixel clock o o Data/Synchronization on/off control Swap function for red and blue channel RGB 12, 16, 15, 24 bpp Palette (1,2,4,8 bit pixel) YcbCr422 (16 bit per pixel) YcbCr420 Little-endian, and big-endian

calculation nearly bilinear interpolation, threshold nearly bilinear interpolation, most neighborhood interpolation Video Output Port o ITU-R BT. 656 8-bit output

Input mode o o o o

Image Capture Ports Three 8-bit video input ports Maximum resolution up 1920 x 1080 Video input format o o o ITU-R BT. 656 8-/16-bit ITU-R BT.1120 16-/20-bit YCrCb 4:2:2 8-/16-bit H/V reference control signals Output image formats o o o o o RGB 888 RGB 565 YCbCr 4:4:4 YCbCr 4:2:2 YCbCr 4:2:0

Data format o 256 entries 16-bit RGB color palette RAM Color management o o o o Programmable contrast, brightness, sharpness, saturation and hue control Three channel Gamma correction Dithering Maximum two PIP windows to display Resolution is up to the main window size 4-bit blending level 4 in 1 windows PoP display RGB parallel (18/24 bits) Swap of parallel RGB and BGR ITU-R BT. 656 output

Picture in Picture (PiP) o o o

Edge-base line in average de-interlace Noise reduction Individual image size down at preview and the record paths Individual frame skip function at preview and the record paths Output image crop Add Border at Output Image Up to 2048 x 2048 resolution can be implemented by combining the preview and record paths

Picture out of Picture (PoP) o Output Format o o o

Video Scalar Up and down scaling o o o Down scaling ration is from 1/256 to 1x1 Up scaling between 1x1 and 2x2 Three interpolation modes for up scaling

Loop-back path to read the image data through AHB from memory

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MediaCodec Compliant with MPEG-4 (ISO/IEC 14496-2) simple profile L0 ~ L3 standards, including resolutions of Sub QCIF, QCIF, CIF, VGA, 4CIF, and D1 @ 30 fps with a step of 16 Compliant with JPEG (ISO/IEC 10918-1) baseline standard Motion estimation search range: -16 ~ +15.5 (optionally -32 ~ +31.5) with half-pixel accuracy Supports 4MV and unrestricted MV Rate control Constant bit rate and variable bit rate control Full-duplex operation (e.g. video phone and video conference) by software switching encoding and task decoding on the same hardware USB OTG Controller V. 2.0 Integrated USB OTG PHY Transfer rates o o o 1.5 Mbps (low speed) 12 Mbps (full speed) 480 Mbps (high speed) IEEE 1149.1 (JTAG) Interface Boundary scan Low-level debugger interface JPDA Java Debugger Interface 32.768 KHz and 3.6864 MHz oscillators 12 MHz crystal for USB OTG 25 MHz crystal for Ethernet controller Programmable frequency PLLs Power consumption o o o Active mode: 1149 mW Standby mode: 1050 mW Sleep mode: 7mW Core at 1.8V I/Os at 1.8, 2.5 or 3.3V

Clock and PLLs

Designed for low-power operation

Fully static operation up to 180 MHz o o

Implemented in 0.18m CMOS process Operating temperature Commercial range from 0O C to 70O C o Up to 180 MHz Up to 144 MHz Extended temperature range -30O C to 85O C o

10/100 T-Base Ethernet Controller Integrated Ethernet 10/100 PHY DES/Triple-DES/AES encryption/decryption complaint with NIST standard AES 128/192/256-bit keys Encryption/decryption Engine

Package 324-pin TFBGA Body size of 13 mm x 13 mm x 1.2 mm (0.65 mm ball pitch) RoHS compliant (lead-free)

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1.2.

Block Diagram
Java Processor Reset PLLs JTAG Interface Execution Unit Microcode ROM 32KB MJM Fixed-Point MAC WCS 32KB Unified I&D Cache 32 KB AHB Unified Cache 16KB Ethernet PHY USB PHY Video Input1 Video Input 2 Video Input3 Video Output LCD Panel Interface

Power Management Unit

AHB Controller

10/100 Ethernet Controller

USB OTG Controller

Media Codec

Video Capture

LCD Controller

External Bus Interface (EBI)

Encyption Engine

AHB to APB Bridge

DMA Controller

APB

Interrupt Controller

6xPWMs

WDT

RTC

3 x 24-bit Timer/ Counters

GPIO

Quad UARTs

I2C

SSP

I2S/AC97/ SPI

SD/SDIO/MMC Card Interface

CF Card Interface

Figure 1-1. 1.3. System Development Support

Block Diagram of aJ-200

The aJ-200 processor, bundled with Suns JME/CLDC or CDC/FP/PBP runtime system, optimizing application builder, debugging tools and evaluation board provides a complete solution for implementing real-time networked embedded Java technology enabled applications. The aJile Java runtime together with the microcoded real-time kernel supports the Java threading model without the need for a separate RTOS. This aJile unique technology significantly reduces memory requirements and lowers system costs. aJiles Multiple JVM (MJM) technology enables multiple applications to execute concurrently and independently in a deterministic, time-sliced schedule. Each JVM employs its own threading and memory management policies to enable real-time applications to execute concurrently with networked applications without the threat of GC pauses and other interruptions. The MJM capability takes the Java sandbox security model the next level, providing a mechanism to easily isolate applications and allocated resources. aJiles solution enables real-time applications to run independently and safely co-exist with networked applications. Using commercial IDEs for Java technology, application developers can create standalone real-time Java enabled applications totally in the Java language with the performance and memory efficiency of systems

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Technical Reference Manual programmed in C and assembly. Utilizing aJiles development systems, application developers can readily explore the features of the aJ-200 and assess the efficiency and performance of a real-time embedded Java platform. The primary components of the development and runtime environments are summarized as follows: 1.3.1. Java Technology Based Runtime System Run-time environment based on a JME/CLDC or CDC/FP/PBP Includes networking classes, storage classes, and Java communications API Device drivers for integrated peripherals and generic physical device interfacing

1.3.2. aJile Real-time Kernel Microcoded kernel directly supports Java threading Deterministic threading available for real-time monitoring and control Self contained multiple JVM with deterministic switching

1.3.3. Optimizing Linker/Application Builder GUI based application build configuration and control tool - JEM Builder Utilizes standard JVM class files generated by commercial IDEs for Java technology Statically resolves class files and eliminates unused methods and fields Performs bytecode optimizations Performs method substitutions (method invokes replaced by extended bytecode instructions) Builds boot tables, class initialization code, and assigns interrupt and trap handlers Configures JVMs and memory layout in Java language

1.3.4. Application Debugging Tools Host-target communications via an IEEE 1149 (JTAG) interface Host-based full featured bytecode-level debugger Host-based JPDA provided to interface to commercial JPDA compliant source-level debuggers

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Figure 1-2 1.4. Target devices

aJile Java Runtime for aJ-200

The aJ-200 is ideally suited to power a wide range of internet mobile appliances M2M Internet edge controllers M2M cellular terminals Wireless POS terminals iP cameras, video surveillance systems Wireless smart RFID readers Personal navigation systems Mobile gaming devices Thin clients Internet screen VoIP phones iPTVs

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Date&Time

SPI
Bluetooth

UART EBI UART UART

Flash Memory 16MB SDRAM 32 MB

aJ-200
10/100 Ethernet
R-45 Jack

WLAN

SDIO USB OTG

Figure 1-3.

M2M Network Edge Devices

Flash Memory 16MB EBI SDRAM 16 MB

Bluetooth

UART

UMTS/WCDMA ChipSet

UART UART

aJ-200
10/100 Ethernet
R-45 Jack

SPI SDIO

USB OTG

Figure 1-4.

M2M Cellular Terminals

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NAND Flash 16 MB SDRAM 32MB

aJ-200

USB OTG Memory Card

Figure 1-5. IP Camera/ Surveillance Systems

RFID Module

8:16MB Flash GPIO EBI 8:16 MB SDRAM

UART UART UART

aJ-200
R-45 Jack

USB Port

SD

LCD Panel

Figure 1-6.

Wireless Smart RFID Readers

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Bluetooth

16MB SDRAM 16 MBFlash

UART

UART

aJ-102
I2C/I2S

Audio D/A

Figure 1-7.

Wireless Gaming Devices

TV Receiver

Video Encoder

NAND Flash 16 MB SDRAM 32MB

ADSL Modem or LAN

aJ-200

iRDA

I2S

Audio Encoder

Video Encoder

Figure 1-8.
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Bluetooth

32MB SDRAM 32 MBFlash

aJ-200
UART

UART

GPS

I2C/I2S

Audio

Figure 1-9.

Personal Navigation Devices (PNDs)

Date&Time

NAND Flash 32 MB

aJ-200

SDRAM 32MB

Figure 1-10. Thin Clients

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2. Architecture Overview
The system-on-chip aJ-200 is based on dual internal AHB and APB buses. The AHB is dedicated to those devices that require a high memory bandwidth including Java processor, DMA controller, Ethernet controller, AES engine, LCD controller, USB OTG, Mediacodec, and Video Capture Ports. The APB provides the access to other I/O devices that require a low memory bandwidth like Interrupt controller, UARTs, SSP, I2C, SDC, CF, GPIO, Timer/counters, RTC, and PWMs. 2.1. AHB Based Devices 2.1.1. Java Processor The aJiles Java processor is the aJiles third generation of low-power, direct execution processor for Java platform, Java processor. It has been enhanced with a 32-bit fixed point MAC, a 32 KB of unified I & D cache, AHB master interface, and slave APB interface. JEMCore-II directly executes Java Virtual MachineTM (JVM) bytecode instructions, real-time Java threading primitives and a number of extended bytecode instructions for multimedia and networked embedded applications. The JEMCore-II improves Java execution efficiency by eliminating the Java interpreter layer and the RTOS kernel layer. Since JVM bytecode instructions are executed as native instructions, the JEMCore-IIs Java performance is similar to RISC processors executing compiled C. In addition, Java threading primitives (wait, yield, notify, monitor enter/exit) are implemented as extended bytecode instructions, eliminating the need for a traditional RTOS. The result is extremely low executive overhead with thread to thread context switch times of less than 1sec. For Java based multimedia-rich applications, JEMCore-II has also enhanced with a single-cycle fixed-point multiplier accumulator (MAC) to accelerate a wide range of DSP, multimedia and security algorithms. 2.1.2. AHB Controller (AHBC) The main purpose of an AHB Controller is to provide a mechanism that grants the user rights for the Advanced High-performance Bus (AHB). It consists of the following three components: arbiter, decoder and multiplexer. It supports the following features: AMBA 2.0 compliant Multi-level arbitration Round-robin arbitration

2.1.3. DMA Controller (DMAC) The DMA controller provides the enhancement of system performance. The system efficiency is improved by employing the high-speed data transfers between the system and the device. The DMA controller

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Technical Reference Manual provides up to eight configurable channels intended for on-chip I/O devices. It provides memory-tomemory, memory-to-peripheral, peripheral-to-peripheral, and peripheral-to-memory transfers with a shared buffer. It supports the following features: Memory-to-memory, memory-to-peripheral, peripheral-to-peripheral, and peripheral-to-memory transfers Chain transfer Group round-robin arbitration scheme with 4 priority levels 8/16/32-bit data width transfer

2.1.4. Single-chip 10/100 Ethernet Controller The aJ-200 features a single-chip 10/100 Ethernet controller with an integrated 10/100 Ethernet PHY. It consists of an AHB wrapper, DMA engine, on-chip memory (TX FIFO and RX FIFO), MAC, and integrated 10/100 T-base Ethernet PHY. It provides AHB master capability and full compliance with IEEE 802.3 100 Mbps and 10 Mbps specification. The Ethernet DMA controller handles all data transfers between system memory and on-chip memory. With the DMA engine, it can reduce CPU loading, maximize performance and minimize FIFO size. It has on-chip memory for buffering, so external local buffer memory is not needed. It also provides Wake-On-LAN function. It supports three wake-up events link status change, magic packet and wake-up frame. The function allows systems to be waked up by remote side. It supports the following features: DMA engine for transmitting and receiving packets Transmit and receive interrupt mitigation mechanism Two independent TX/RX FIFO (2Kbytes each) Half and full duplex modes Flow control for full duplex and backpressure for half duplex Wake-On-LAN function and three wakeup Event slink status change Magic packet Wake-up frame Four Wake-On-LAN signals (active high, active low, positive pulse, and negative pulse) On-chip 10/100 Ethernet PHY LED status outputs

2.1.5. Encryption and Decryption Engine The AES-DES Cipher engine provides an efficient hardware implementation of DES/Triple-DES and AES
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Technical Reference Manual algorithms for high performance encryption and decryption, which can be applied to various applications. In DES/Triple-DES configuration, it supports four block cipher modes, including ECB, CBC, CFB and OFB. In AES configuration, it supports five block cipher modes, including ECB, CBC, CTR, CFB and OFB. The AES-DES Cipher engine provides DMA function which can reduce the overhead on processor for data transfer and improve system performance. It supports the following basic features: DES/Triple-DES encryption/decryption compliant with NIST standard AES 128/192/256-bit encryption/decryption compliant with NIST standard Block cipher mode DES/Triple-DES o o o o ECB mode CBC mode CFB mode OFB mode ECB mode CBC mode CFB mode OFB mode CTR mode

AES o o o o o

DMA capability

2.1.6. Single-chip USB 2.0 OTG Controller (USB OTG) The aJ-200 includes a single-chip USB 2.0 OTG controller embedded with a USB OTG PHY. It can play a dual-role, a host or peripheral device. When USB OTG acts as a host, it contains the USB host controller that supports all speed transactions. Without the software intervention, the host controller can deal with a transaction-based data structure to offload the CPU and automatically transmit and receive data on the USB bus. When it acts as a peripheral device, each endpoint, except endpoint 0, accepts the programmable HS/FS transfer type to provide a flexibility that is suitable for all kinds of applications. In addition, complying with the OTG standards means both the Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) are supported. It supports the following features Compliant with USB specification revision 2.0 Compliant with On-The-Go supplement to USB 2.0 specification revision 1.0 Transfer rates

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Technical Reference Manual o o o 1.5 Mbps (low speed) 12 Mbps (full speed) 480 Mbps (high speed)

Compatible with EHCI 1.0 OTG SRP and HNP Point-to-point communications with one HS/FS/LS device Hardware configurable endpoints as HS/FS device Both host and device support isochronous/interrupt/control/bulk transfers Compatible with EHCI data structures Embedded the DMA access to FIFO Suspend mode, remote wake-up, and resume 4KB FIFO Integrated USB OTG PHY

2.1.7. LCD Controller (LCDC) The LCD controller provides all control signals necessary for a variety of TFT LCD panels. It supports the following features: LCD panel interface o o o o TFT color displays with up to 24-bit bus interface 1/2/4/8/24- bus width Programmable resolution up to 1280 x 1280 Pixel clock rate up to 120 MHz Data/Synchronization on/off control Swap function for red and blue channel RGB 12(4:4:4), 16(5:6:5), 15(5:5:5), 24(8:8:8) bpp Palette (1/2/4/8 bpp) YcbCr422 (16 bpp) YcbCr420 (separate memory location) Little-endian

Programmable polarity/duration for output enable, vertical sync, horizontal sync, pixel clock o o

Input mode o o o o

Data format o Palette

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Technical Reference Manual o 256 entries 16 bit RGB color palette RAM Programmable contrast, brightness, sharpness, saturation and hue control Three channel Gamma correction Dithering Maximum two PIP windows to display Resolution of PIP window is up to the main window size 4-bit blending level 4 in 1 windows PoP display RGB parallel (18/24 bits) Swap of parallel RGB and BGR ITU-R BT. 656 output Up and down scaling Down scaling ration is from 1/256 to 1x1 Up scaling between 1x1 and 2x2 Three interpolation modes for up scaling calculation Nearly bilinear interpolation Threshold nearly bilinear interpolation Most neighborhood interpolation Master bus error Frame status FIFO under-run Memory base update CIR-656 8-bit output

Color management o o o

Picture in Picture (PiP) o o o

Picture out of Picture (PoP) o Output format o o o

Video Scalar o o o o o o o

Interrupt control o o o o

Video Output o

2.1.8. Video Capture The video capture is in charge of capturing the video data from the ITU-R BT. 656 interface. It provides the de-interlace function to reduce the video artifact for the interlace video. Noise reduction can remove
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Technical Reference Manual the unwanted noise and preserve the fine details and edges. With the size down ability, the user can size down the image to the resolution needed individually for the preview and the record path. The color OSD function at the record path can help the user to paste any characters at the captured video. It supports the following features: Three 8/10-bit video input ports o Maximum input capture resolution up to 1920 x 1080 ITU-R BT 656 8-bit/16-bit input interface ITU-R BT.1120 16-/20bit input interface YCbCr 4:2:2 8-/16-bit with H/V reference control signal interface RGB 888 RGB 565 YCbCr 4:4:4 YCbCr 4:2:2 YCbCr 4:2:0 Video input format o o o

Output image format o o o o o

Edge-base line in average de-interlace Noise reduction Individual image size down at preview and the record paths Individual frame skip function at preview and the record paths Output image crop Add border at output image Up to 2048 x 2048 resolution can be implemented by combining the preview and record paths Loop-back path to read the image data through AHB from memory

2.1.9. MediaCodec The MediaCodec is capable of accelerating multimedia image and video related applications such as MPEG4 and JPEG. This codec includes the hardware engines to accelerate the computation intensive tasks for motion estimation, DCT/IDCT, quantization/inverse quantization, and motion compensation. It supports the following features: Compliant with MPEG-4 (ISO/IEC 14496-2) simple profile L0 ~ L3 standards. Sub QCIF, QCIF, CIF, VGA, 4CIF, and D1 @ 30 fps with a step of 16 Compliant with JPEG (ISO/IEC 10918-1) base-line standard
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Technical Reference Manual Hardware engines for motion estimation/motion compensation, DCT/IDCT, quantization/inverse quantization, AC/DC prediction, and variable length coding/decoding Local memory controller controls local memory shared by DMA master and other mediacodecs blocks DMA controller controls data transfers between system memory and local memory Automatic power down mechanism Motion estimation search range o -16 ~ +15.5 (optionally -32 ~ +31.5) with half-pixel accuracy 4MV and unrestricted MV Rate control o Constant bit rate and variable bit rate control Error resilient tools Encoder supports resynchronization marker and header extension code Decoder supports resynchronization marker, header extension code, data partition and RVLC Short video header (H.263 baseline) H.263/MPEG/JPEG quantization methods JPEG o o o 4 user-defined Huffman tables (2AC and 2DC) 4 programmable quantization tables Interleave and non-interleave scans

YUV 4:4:4, 4:2:2 and 4:2:0 formats Image size up to 64K 64K Full-duplex operation (e.g. video phone and video conference) by software switching encoding and task decoding on the same hardware De-blocking post-filter to enhance decoded output quality (optional) DMA Chain transfer function 2D addressing mode for both source address and destination address 2KB FIFO Embedded RISC to minimize the host CPU loading Performance o MPEG4 simple profile encoding up to D1 @ 30 fps with codec clock speed under 72 MHz

2.1.10. External Bus Interface Unit (EBI)

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Technical Reference Manual The EBI unit provides the seamless interface with Flash, ROM, SRAM, SDRAM and external peripheral devices. It consists of two basic memory controllers: SRAM controller SDRAM controller Static Memory Controller (SMC)

2.1.10.1.

The SMC supports ROM, Flash, SRAM, and external peripheral devices. Each chip select can be individually programmed to an 8-, 16- or 32-bit wide data bus without any additional logic (byte, half-word, and word single transaction). The SMC shares the address and data bus with the SDRAM controller. It supports the following features ROM, FLASH (NAND and NOR), burst-ROM, asynchronous and synchronous SRAM Zero-wait-state write 8-word data FIFO Wide address range up to 256 Mbytes Eight banks and each bank is up to 32Mbytes SDRAM Controller (SDRAMC)

2.1.10.2.

The SDRAM memory controller supports four 8-, 16-, 32-bit wide banks. The SDRAM controller performs auto-refreshing (CBR) during normal operation, and supports SDRAM self-refreshing during Sleep mode. It shares the address and data bus with Static Memory Controller (SMC). The SDRAMC supports the following features: Wide address range up to 512 Mbytes Rich types of SDRAM, and mobile SDRAM Programmable refresh controller Six AHB channels 8-word deep FIFO Automatically enters the power mode

2.1.11. AHB to APB Bridge (APB Bridge) The APB bridge is mainly used to convert the transaction between the APB bus and the AHB bus. The APB bridge is the only bus master on the APB bus and it also serves as a slave on the AHB bus. It provides latching of all address, data and control signals, as well as a second level of decoding to generate slave select signals for the APB peripherals. It supports the following features Speed up to 45 MHz for low-speed APB bus Compliant with AHB 2.0 Specification
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Technical Reference Manual 2.2. APB Peripheral Devices

2.2.1. Peripheral Interrupt Controller (PINTC) The Peripheral Interrupt Controller provides both FIQ and IRQ modes to the JEMCore. It also determines whether the interrupt cause an IRQ or an FIQ to occur and masks the interrupt. It supports the following features: Up to thirty-two fast interrupt (FIQ) inputs Up to thirty-two standard interrupt (IRQ) inputs Interrupts can be routed to either IRQ or FIQ Edge and level triggered interrupt source with positive and negative directions De-bounce circuit for interrupt input sources Independently enable or disable any interrupt source

2.2.2. Timers/Counters The aJ-200 includes three 24-bit timer/counters that can perform a wide range of timing functions. The Timer/Counter functions include frequency measurement, event counting, interval measurement, delay timing, and pulse width modulation. They support the following features: Three independent 24-bit timers 16-bit prescaler Internal chaining of timers External clock, trigger and gate control Two pulse width modulation and waveform modules Flexible interrupt generation

2.2.3. Watch Dog Timer (WDT) The WDT is used to prevent system from infinite looping if the software becomes trapped in deadlock. In normal operation, the user restarts the WDT at regular intervals before the counter counts down to zero. The WDT generates one or a combination of the following signals: reset or interrupt. It supports the following features: Upon timeout, output one or a combination of System Reset / System Interrupt 32-bit down counter PCLK or XIN/16 source selection Variable time-out period of reset Access protection via password and executive mode

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Technical Reference Manual 2.2.4. Real Time Controller (RTC) The RTC is a flexible and low power real time clock. Its powered by an external Lithium battery backup, when the power system is shut down. It accepts two clock sources: APB bus clock (PCLK) and EXTCLK (any frequency clock). When the system enters the sleep mode, the PCLK clock can be gated by the system while the RTC keeps on counting. This mechanism promises the lowest power consumption when the system is asleep. Furthermore, the RTC provides the separate second, minute, hour, and day counters. When the system is in sleep mode, PCLK can be gated to save power consumption Separated second, minute, hour and day counters to reduce power consumption and software complexity Programmable auto second, minute, or hour alarm

2.2.5. GPIO Ports The aJ-200 includes three 32-bit GPIO ports, which provide a large number of shared GPIO pins. Each GPIO can be programmed to as an input or output, or as an interrupt input. It supports rising edge, falling edge, both-edge and high level or low level interrupt sense types. It supports the following features: Three 32-bit GPIO ports Each port can separately trigger a GPIO interrupt Each port interrupt generation can be triggered by rising or falling edge, both edges or high or low level Each port can be pulled high or pulled low Programmable sampling rate for all I/O ports Output data bit can be set or cleared separately All ports are set to input mode at hardware reset

2.2.6. Pulse Width Modulators (PWMs) The aJ-200 contains three enhanced pulse width modulator channels. Each channel provides two PWM outputs, and is controlled by its own set of registers. This allows up to eight PWM outputs using potentially four different PWM frequencies. All four PWM channels use the PCLK signal as the primary timing source. It supports the following features: Three independent PWM channels o Two PWM outputs per channel 45 MHZ input frequency (PCLK) 10-bit prescaler 16-bit counter
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Technical Reference Manual Enhanced period control through 10-bit clock prescaler and 16-bit period counter Dead-band generation with independent rising and falling time control A trip condition can be forced either low or high

2.2.7. IC The I2C is a two-wire bidirectional serial bus that provides a simple and efficient method of data exchange while minimizing the interconnection between devices. The I2C bus interface controller allows the host processor to serve as a master or slave residing on the I2C bus. Data are transmitted to and received from the I2C bus via a buffered interface. It supports the following features: Standard and fast modes through programming the clock divided register 7, 10-bit and general call addressing modes Glitch suppression throughout the de-bounce circuits Programmable slave address Master-transmit, Master-receive, Slave-transmit and Slave-receive modes Slave mode general call address detection Multi-master mode

2.2.8. Synchronous Serial Port Controller (SSPC) The SSPC is a full-duplex synchronous serial interface and can connect to a variety of external analog-todigital (A/D) converters, audio and telecom Codecs, touch panel control chips, and other devices that use serial protocols for data transfer. The SSPC supports Texas Instrument SSP, Motorola SPI, and National Semiconductor Microwire. It supports serial data rate up to 22.5 MHz in master mode. The serial data formats may range from four (4) to thirty-two (32) bits in length. It supports the following features: Motorola SPI, TI SSP, National Semiconductor Microwire Independent SSP clock to ease bit clock generation Master or slave mode Internally or externally controlled serial bit clock Internally or externally controlled frame / sync Programmable frame / sync polarity Programmable serial bit clock polarity, phase and frequency Programmable serial bit data sequence (MSB or LSB first) Programmable threshold interrupt of transmit / receive FIFO Independently programmable interrupt enable / disable 16-word transmit FIFO and 16-word receive FIFO
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Technical Reference Manual DMA REQ/ACK for large data transfers

2.2.9. IS / AC97/ SPI Controller (IS / AC97C/ SPI) The I2S / AC97/ SPI controller provides Philips I2S, Intel AC-link, and the second SPI channel. In AC97 mode, for recording, the AC97 Codec sends digitized audio samples and the controller stores them in memory. For playback or synthesized audio production, the processor retrieves stored audio samples and sends them to the Codec through the AC-link. The external digital-to-analog converter (DAC) in the Codec then converts the audio sample to an analog audio waveform. In IS mode, the controller transfers digitized audio sample between the system memory and an external IS Codec. It can be configured as SPI channel, which supports a serial data rate up to 15 MHz in master mode. It supports the following features Motorola SPI, TI SSP, National Semiconductor Microwire Philips I2S and Intel AC-link Internally or externally controlled serial bit clock Internally or externally controlled frame / sync Programmable frame/sync polarity Programmable serial bit clock polarity, phase and frequency Programmable serial bit data sequence (MSB or LSB first) Programmable I2S format (including zero bits padding and right or left justification) Programmable threshold interrupt of transmit/receive FIFO Independently programmable interrupt enable/disable 16-word transmit FIFO and 16-word receive FIFO DMA REQ/ACK for large data transfers

2.2.10. Compact Flash Controller (CFC) The CFC provides a control interface to connect the CompactFlash cards. It supports common memory, I/O, and attribute memory function with 8/16-bit mode for accessing the resource on the CompactFlash card. The CFC supports card insert / remove detection. It supports the following features: Attribute memory access, common memory access and I/O access DMA and PIO mode Buffer and reset control function Programmable access cycle time for each access type Programmable 8/16-bit mode Active read / write buffer control function
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Technical Reference Manual 64-byte buffer DMA REQ/ACK for large data transfers

2.2.11. Multimedia Card and Secure Digital Host Controller (MMC / SDC / SDIO) The MMC/SD supports MMC and SD/ SDIO interface protocols. It supports hot insertion and removal detection. For SD, it also supports write-protect and 1- or 4-bit bus width for large data transfer without CPU intervention. It supports the following features: SD memory card protocol version. 2.0 o No SPI mode included Multi-function and combo card 1/4-bit SD data transfer mode in the SDIO Multiple block transfer interrupt Read wait operation in the SDIO No SPI mode included Three data bus width mode: 1/4/8 bit Interrupt mode SDIO bus protocol version 1.10 o o o o

MMC bus protocol version. 4.1 o o o

DMA for large data transfers 16-word data FIFO Built-in generation and checks for the 7/16-bit CRC data Variable clock rate o o 0 MHz ~ 50 MHz of the SD card 0 MHz ~ 52 MHz of the MMC card

Hot insertion/removal Write-protect for the SD card

2.2.12. UARTs The aJ-200 provides three UARTs, which use the same programming model. The UART1 supports full modem control capability. The UART2 provides a partial set of modem control pins, including CTSn and RTSn. The UART3 doesnt provide any modem control pins. The three UARTs support baud rates up to 1152 Kbps. It supports the following features High-speed NS 16C550A-compatible UART Programmable baud rates up to 1,152 Kbps
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Technical Reference Manual Ability to add or delete standard asynchronous communications bits (start, stop, and parity) in serial data Programmable baud rate generator that allows the internal clock to be divided by 1 to (216-1) to generate an internal 16 x clock Fully programmable serial interface o o o 5-, 6-, 7-, or 8-bit characters Even, odd, and no parity detection 1-, 1.5-, or 2-stop bit generation

Complete status reporting capability Ability to generate and detect line breaks Fully prioritized interrupt system controls Separate DMA requests for data transmission and reception services Break, parity, overrun, framing error simulation for UART mode UART1 provides 16-byte transmit FIFO and 16-byte receive FIFO UART2 provides 32-byte transmit FIFO and 32-byte receive FIFO UART3 provides 16-byte transmit FIFO and 16-byte receive FIFO

2.2.13. IrDA/UART4 The IrDA/UART4 controller operates at half duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers. It can also be programmed as a simple UART function using the I/O configuration register. It supports the following features: IrDA 1.3 SIR with data rates up to 115.2 Kbps SIR pulse width is programmable as 1.6s or 3/16 of the baud-rate pulse width IrDA 1.3 FIR support Multi-frame transmission and reception in FIR mode Back-to-back infrared frame transmission and reception in FIR mode 32-bit IEEE 802 CRC32 hardware CRC generators and checkers for FIR communications 128-byte transmit FIFO and 64-byte receive FIFO DMA REQ/ACK for large data transfers High-speed NS 16C550A-compatible UART with data rate up to 1,152 Kbps

2.3. Phase Locked Loops (PLLs) The aJ-200 includes three internal PLLs, which are used to generate all clock sources required for Java CPU and integrated peripherals. These PLLs are driven by an external reference clock source that is

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Technical Reference Manual supplied from an external crystal in the range of 1~12 MHz. A typical crystal of 3.6864 MHz is used as the reference clock for the core PLL and the peripheral PLLs. A typical crystal of 32.768 KHz is used to provide an optional slow clock source for the RTC. In addition, there are two dedicated PLLs for the 10/100 Ethernet PHY an USB OTG PHY respectively. 2.4. System Configuration The aJ-200 can be configured to adapt to a wide variety of embedded applications and consumer devices. Clock sources Phase Locked Loops (PLLs) Shared I/O pins Operation modes

These features are controlled with internal memory mapped registers that are initialized as the part of the JEMCore s initialization sequence or dynamically by software. The application builder tool (JEM Builder) provides an intuitive configuration window that allows users to configure the desired features for static operation. However these functions can also be switched dynamically during the execution of applications. 2.5. Operating Voltages

The aJ-200 operating voltages are as follows: Internal voltage of 1.8V I/O voltage of 1.8V or 2.5V or 3.3V Operating Temperature

2.6.

The aJ-200 operates at the following temperature range Industrial range -30O C to 85O C o Frequency up to 144 MHz Commercial range from 0O C to 70O C o Frequency up to 180 MHz 2.7. Package The aJ-200 is housed in a 324-pin TFBGA package in the size of 13mm x 13mm x 1.20mm with a ball pitch of 0.65mm.

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3. Pin Assignment
This chapter describes the aJ-200 signals that are assigned to the pins. 3.1. Signal Descriptions I/O O Pin # Pin Name Description SDRAM/SRAM Address and Data Bus B7 MADDR[24] SDRAM/SRAM memory address bus as C7 MADDR[23] follows: B8 MADDR[22] MADDR [24:15] pins are dedicated for SRAM address lines [24:15]. C8 MADDR[21] MADDR [14:0] pins are used as D9 MADDR[20] SRAM address line [14:0] or SDRAM B9 MADDR[19] address lines MADDR [14:0]. The E9 MADDR[18] MADRRR[14:0] for SDRAM are used C9 MADDR[17] as follows: B10 MADDR[16] MADDR[12:0] address lines are used D10 MADDR[15] to output the column and row address A10 MADDR[14] respectively. F9 MADDR[13] MADDR[14:13] address lines are used C10 MADDR[12] to output the bank select address BA[1:0] respectively. E10 MADDR[11] MADDR23/CLE Command Latch B11 MADDR[10] Enable G9 MADDR[9] The CLE output controls the activating A11 MADDR[8] path for commands sent to the NAND F10 MADDR[7] command register. When active high, D11 MADDR[6] commands are latched into the C11 MADDR[5] command register through the I/O B12 MADDR[4] ports on the rising edge of the WE E11 MADDR[3] signal. Configuration of the pin operation is specified by the bit 18 of C12 MADDR[2] the MFPSR0. This pin operates as G10 MADDR[1] CLE following a reset. A12 MADDR[0] MADDR24/ALE Address Latch Enable The ALE output controls the activating path for address to the internal NAND address registers. Addresses are latched on the rising edge of WE with ALE high. Configuration of the pin operation is specified by the bit 18 of the MFPSR0. This pin operates as ALE following a reset. D12 MDATA[31] SDRAM/SRAM memory data bus B13 MDATA[30]

The aJ-200 signals are listed in the table below as follows: Signal Names MADDR [24:0]

MDATA [31:0]

IO

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Technical Reference Manual C13 A13 E12 A14 F11 C14 G11 B14 F12 A15 D13 E13 G12 D14 B15 F13 C15 E14 A16 B16 D15 C16 G13 E15 F14 A17 B17 A18 B18 C17 E16 D17 D16 C18 H12 D18 G14 F15 A9 E17 SRAM Interface SMC_CS0n O G15 Static memory chip select CS0n. Active MDATA[29] MDATA[28] MDATA[27] MDATA[26] MDATA[25] MDATA[24] MDATA[23] MDATA[22] MDATA[21] MDATA[20] MDATA[19] MDATA[18] MDATA[17] MDATA[16] MDATA[15] MDATA[14] MDATA[13] MDATA[12] MDATA[11] MDATA[10] MDATA[9] MDATA[8] MDATA[7] MDATA[6] MDATA[5] MDATA[4] MDATA[3] MDATA[2] MDATA[1] MDATA[0] MBEn[3] MBEn[2] MBEn[1] MBEn[0] SDRAM Interface SDR_RASn SDR_CASn SDR_CSn SDR_CLK SDR_CLKE O O O O O SDRAM row address strobe. Active low SDRAM column address strobe. Active low SDRAM chip select. Active low SDRAM clock ouput signal. SDRAM clock enable output signal.

MBEn [3:0]

Memory byte enables. Active low SDRAM DQM[3:0] or SRAM byte enables

MWEn

Memory write enable. Active low

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Technical Reference Manual low Static memory chip select CS1n. Active low. NAND chip select signal. Configuration of the pin operation is specified by the bit 18 of the MFPSR0 register. This pin operates as NAND_CSn following a reset. Static memory chip select CS2n. Active low. NAND write enable signal. Configuration of the pin operation is specified by the bit 18 of the MFPSR0 register. This pin operates as NAND_WRn following a reset. Static memory chip select CS3n. Active low. NAND read enable signal. Configuration of the pin operation is specified by the bit 18 of the MFPSR0 register. This pin operates as NAND_REn following a reset. Static memory chip select 4. Active low. General Purpose I/OC18. Configuration of the pin operation is specified by the bit 19 of the MFPSR0. This pin operates as GPIOC18 following a reset. Static memory chip select 5. Active low. General Purpose I/OC19. Configuration of the pin operation is specified by the bit 20 of the MFPSR0 register. This pin operates as GPIOC19 following a reset. Static memory chip select 6. Active low. Full duplex LED output. Active low indicates the full duplex mode the of Ethernet controller. Ethernet link status output. It indicates link status as follows: 0 The link is down 1 The link is up General Purpose I/OC20. Configuration of the pin operation is specified by the bits [5:4] of the MFPSR1 register. This pin operates as GPIOC20 following a reset. Static memory chip select 7. Active low. Link speed LED output. Active low indicated the Ethernet link speed is 100Mbps.

SMC_CS1n NAND_CSn

F17

SMC_CS2n NAND_WRn

F16

SMC_CS3n NAND_REn

H14

SMC_CS4n GPIOC18

O I/O

G16

SMC_CS5n GPIOC19

O I/O

H15

SMC_CS6n FDXLED LINKLED

O O O

J13

GPIOC20

I/O

SMC_CS7n SPELED

O O

G17

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Technical Reference Manual LINKLED O Ethernet link status output. It indicates the link status as follows: 0 The link is down 1 The link is up General Purpose I/OC21. Configuration of the pin operation is specified by the bits [7:6] of the MFPSR1 register. This pin operates as GPIOC21 following a reset. Static memory output enable. Active low LCD Interface LCDHS GPIOC23 O I/O T8 Panel Horizontal synchronization pulse (TFT). General Purpose I/OC23. This pin is operated as GPIOC23 on power reset. Configuration of the pin operation is specified by the bit 8 of the MFPSR1 register. This pin operates as GPIOC23 following a reset. Panel vertical synchronization pulse (TFT). General Purpose I/OC24. Configuration of the pin operation is specified by the bit 8 of the MFPSR1 register. This pin is operated as GPIOC24 on power reset. Panel data enable (TFT). General Purpose I/OC25. Configuration of the pin operation is specified by the bit 8 of the MFPSR1 register. This pin is operated as GPIOC25 on power reset. LCD panel clock. General Purpose I/OB12. Configuration of the pin operation is specified by the bit 8 of the MFPSR1 register. This pin operates as GPIOB12 on power reset. LCD panel data [23:18]. General Purpose I/OA [31:26]. Configuration of the pin operation is specified by the bit 11 of the MFPSR1 register. These pins operate as GPIOA[31:26] on power reset. LCD panel data [17:16]. General Purpose I/OA [25:24]. Configuration of the pin operation is specified by the bit 10 of the MFPSR1 register. These pins operate as GPIOA[25:24] on power reset. LCD panel data [15:8].

GPIOC21

I/O

SMC_OEn

H13

LCDVS GPIOC24

O I/O

U8

LCDE/LCAC GPIOC25

O I/O

N8

LCDPCLK GPIOB12

O I/O

V9

LCDD [23:18] GPIOA [31:26]

O I/O

LCDD [17:16] GPIOA [25:24]

O I/O

P8 R8 U9 N9 T9 R9 P9 V10

LCDD23] LCDD22] LCDD[21] LCDD[20] LCDD[19] LCDD[18] LCDD[17] LCDD[16]

LCDD [15:8]

U10

LCDD[15]

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Technical Reference Manual GPIOA [23:16] I/O N10 T10 R10 V11 U11 T11 P10 R11 V12 U12 T12 P11 V13 R12 U13 LCDD[14] General Purpose I/OA [23:16]. Configuration of the pin operation is LCDD[13] specified by the bit 9 of the MFPSR1 LCDD[12] register. These pins operate as LCDD[11] GPIOA[23:16] on power reset. LCDD[10] LCDD[9] LCDD[8] LCDD[7] LCD panel data [7:0]. General Purpose I/OA [15:8]. LCDD[6] Configuration of the pin operation is LCDD[5] specified by the bit 8 of the MFPSR1 LCDD[4] register. These pins operate as LCDD[3] GPIOA[15:8] on power reset. LCDD[2] LCDD[1] LCDD[0] USB OTG 2.0 Interface A3 USB 2.0 OTG data in data positive pin terminal A4 USB 2.0 OTG data in data negative pin terminal C5 Connects external reference resistor (12 K 1%) to analog GND A7 ID detection A1 Output for P-MOSFET (Vout output switch) A2 Output voltage feedback pin B2 Output for N-MOSFET B1 Input detected voltage from 0V to 5.5V A6 A crystal input. An external 12 MHz crystall input is connected to this pin (USB OTG). This provides the reference clock for USB OTGs PHY. An external 12 MHz clock source with the 3.3 V level can be applied instead of the crystal. A5 Crystal output of 12 MHz (USB OTG) B6 Analog supply voltage (3.3V) B5 Analog ground B4 Analog supply voltage (3.3V) B3 Analog ground C4 Digital supply voltage (3.3V) for PWM D5 Digital ground for PWM C2 Analog supply voltage for VDT C3 Analog ground for VDT Ethernet Controller Interface
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LCDD [7:0] GPIOA [15:8]

O I/O

DP DM RREF IDDIG OTG_PDMOS OTG_VOUT OTG_EXT OTG_VBUS XSCI

I/OAnalog I/OAnalog IAnalog I O I O A IAnalog

XSCO VCCHSRT GNDHSRT VCCA_OTG GNDA_OTG VCC3D_PWM GNDD_PWM VCCA_VDT GNDA_VDT

OAnalog SUP SUP I I I I I I

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Technical Reference Manual TXOP TXON RXIP RXIN RSET_BG RXLED TXLED XTLN O O I I O O O I V4 V5 V2 V3 T2 V7 V8 T1 Twisted pair transmit output. Positive Twisted pair transmit output. Negative Twisted pair transmit input. Positive Twisted pair transmit input. Negative Off-chip resistor. Connect a resistor of 12.3 k 1% to the ground Receive activity Active low indicates the presence of receive activity. Transmit activity Active low indicates the presence of transmit activity. An external 25 Mhz crystal is connected to this pin. This provides the reference clock for PLL of Ethernet PHY. A resistor of 1M between XTLN and XTLP is required. An external 25 MHz clock source with the 1.8 V level can be applied instead of the crystal. 25 MHz crystal input/output 1.8 V digital power supply for the Ethernet PHY Digtal ground for Ethernet PHY 1.8 V analog power supply for Ethernet PHY Analog ground(1.8V) for Ethernet PHY 3.3 V analog power supply for Ethernet PHY Analog ground (3.3 V) for Ethernet PHY JTAG Interface TCK TDI I I V14 U14 Test Clock. The test clock is the clock for 1149 test access port (TAP) controller, instruction register and all data registers. Test Data Input. This pin is used to shift data into the 1194 data and instruction registers. TDI is acaptured on the rising edge of the TCK input. Test Data Output. This pin is used to shift dat aout of the 1149 data and instruction registers. TDO changes on the falling edge of the TCK input NC Test Mode Select. The TSM inputs control sequencing through the 1149 test access port (TAP) state machine Test Reset. Aserting the TRSTn input low, causes the test logic to be reset.
Version 2.1

XTLP VCCKEDP GNDKEDP VCCAEDP GND18AEDP VCC3AEDP GND3AEDP

I/O I I I I I I

U1 R1 V1 U4 U5 U2 U3

TDO

T13

NC TMS TRSTn

I I I

R13 V15 U15

NC(BTDO)

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Technical Reference Manual TRSTn does not reset any system logic in the aJ-102. TRSTn resets the TAP controller and initialize the isntruction register and some data registers to a known state CF Card Interface CFC_NCD1 I P4 CFC card detect 1. It is connected to ground on the CompactFlash Storage Card or CF+ Card. It s used by the host to determine whether the CompactFlash Storage Card or CF+ Card is fully inserted into its socket. The video input bit 6 of the video port 2. General Purpose I/OB11. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB11 on power reset. CFC card detect 2. It is connected to ground on the CompactFlash Storage Card or CF+ Card. It s used by the host to determine whether the CompactFlash Storage Card or CF+ Card is fully inserted into its socket. The video input bit 7 of the capture video port 2. General Purpose I/OB10. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB10 on power reset. CFC ready. The video input bit 5 of the capture video port 2. General Purpose I/OB9. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB9 following a reset. CFC wait. It is driven low by the CompactFlash Storage Card or CF+ Card to signal the host to delay completion of a memory or I/O cycle that is in progress. Capture input clock for video port 2 General Purpose I/OC26. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOC26 following a reset.

VCAP2_VD6 GPIOB11 CFC_NCD2

I I/O I R5

VCAP2_VD7 GPIOB10

I I/O

CFC_RDY VCAP2_VD5 GPIOB9

I I I/O

T5

CFC_RDY

CFC_WAITn

J4

VCAP2_ICLK GPIOC26

I I/O

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Technical Reference Manual CFC_IOIS16n VCAP1_ICLK GPIOC11 I I I/O G5 CFC IO select 16. Capture input clock for video port 1. General Purpose I/OC11. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOC11 following a reset. CFC address bit 10. Capture input clock for video port 0. General purpose I/OB15. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB15 following a reset. CFC address bit 9. The capture video input 9 of the port 0. General purpose I/OB1. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB1 following a reset. CFC address bit 8. The capture video input 8 of the port 0. General purpose I/OB0. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB0 following a reset. CFC address bits [7:0]. The capture video input [7:0] of the port 0. General Purpose I/OB[14:13] are shared with CFC_ADDR[7:6] and I/OB[8:3] are shared with CFC_ADDR[5:0] respectively. Configuration of these pins are specified by the bits [15:14] of the MFPSR1 register. These pins operate as GPIOB[14:13], and GPIOB[8:3] following a reset. CFC register select. The video input bit 1 of the capture video port 2. General purpose I/OB16. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB16 following a reset. CFC card enable 0. It is used with CFC_CEN1 to select the card and to indicate to the card whether a byte or a

CFC_ADDR10 VCAP0_ICLK GPIOB15

O I I/O

F3

CFC_ADDR9 VCAP0_VD9 GPIOB1 CFC_ADDR8 VCAP0_VD8 GPIOB0 CFC_ADDR[7:0] VCAP0_VD[7:0] GPIOB[14:13]& GPIOB[8:3]

O I I/O O I I/O O I I/O

E5

E4

E1 E2 E3 D1 D4 D3 D2 C1

CFC_ADDR7 CFC_ADDR6 CFC_ADDR5 CFC_ADDR4 CFC_ADDR3 CFC_ADDR2 CFC_ADDR1 CFC_ADDR0

CFC_REGn VCAP2_VD1 GPIOB16

O I I/O

J1

CFC_CEN0

R4

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Technical Reference Manual word operation is being performed. The CFC_CEN0 accesses the even byte or the odd byte of the word depending on CFC_ADDRA0 and CFC_CEN1. Vertical synchronous signal input for Sony 16-bit YUV mode. General purpose I/OB17. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB17 following a reset. CFC card enable 1. It is used with CFC_CEN0 to select the card and to indicate to the card whether a byte or a word operation is being performed. The CFC_CEN1 always accesses the odd byte of the word. Horizontal synchronous signal input for Sony 16-bit YUV mode. General purpose I/OB18. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB18 following a reset. CFC output enable. It is used to read data from the CompactFlash Storage Card or CF+ Card and configuration registers. The video input bit 0 of the capture video port 2. General purpose I/OB19. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB19 following a reset. CFC write enable. The video input bit 4 of the capture video port2. General purpose I/OB20. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB20 following a reset. CFC I/O read. The video input bit 3 of the capture video port2. General purpose I/OB21. Configuration of this pin is specified in the I/O configuration register. This pin operates
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VCAP_VSYNC GPIOB17

I I/O

CFC_CEN1

T4

VCAP_HSYNC GPIOB18

I I/O

CFC_OEn

J2

VCAP2_VD0 GPIOB19

I I/O

CFC_WEn VCAP2_VD4 GPIOB20

O I I/O

P5

CFC_IORn VCAP2_VD3 GPIOB21

O I I/O

H5

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Technical Reference Manual as GPIOB21 following a reset. CFC I/O write. The video input bit 2 of the capture video port2. General purpose I/OB22. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB22 following a reset. T6 CFC reset. The video field reference signal. General Purpose IOB2. Configuration of the pin operation is specified by the bits [15:14] of the MFPSR1 register. This pin operates as GPIOB2 following a reset. F2 CFC_DATA[15] CFC data bits [15:4]. The video input bits[9:8] of the capture F1 CFC_DATA[14] video port 2. The two bits are shared with F4 CFC_DATA[13] CFC_DATA[15:14]. F5 CFC_DATA[12] The video input bits [9:0] of the capture G3 CFC_DATA[11] video port 1. These signals are shared G2 CFC_DATA[10] with CFC_DATA[13:0]. G1 CFC_DATA[9] General purpose G4 CFC_DATA[8] GPIOB[31:27],GPIOC31,GPIOC[1:0],GPI H2 CFC_DATA[7] OB[26:23]. Configuration of the pins are specified by the bits [15:14] of the H1 CFC_DATA[6] MFPSR1 register. These pins operate as H3 CFC_DATA[5] GPIOB[31:27],GPIOC31,GPIOC[1:0],GPI H4 CFC_DATA[4] OB[26:23] following a reset. The CFC_DATA [15:4] pins are shared as follows: CFC_DATA15 is shared with GPIOB31 ~ CFC_DATA4 is shared with GPIOB23 J5 CFC_DATA[3] CFC data bits [3:0] and SD data bus [3:0]. K5 CFC_DATA[2] Configuration of the pins operation is K2 CFC_DATA[1] specified by the bit 1 of the MFPSR1 K3 CFC_DATA[0] register. These pins operate as SDIO [3:0] following a reset MMC/SD/SDIO Card Interface K4 SD card detect signal from connector. General Purpose I/OB3. Configuration of the pin operation is specified by the bit 0 of the MFPSR1 register. This pin operates as GPIOB3 following a reset. L3 SD card write protect signal.. General Purpose I/OB4. Configuration J3

CFC_IOWRn VCAP2_VD2 GPIOB22

O I I/O

CFC_RESET VCAP_FIELD GPIOB2

O I I/O

CFC_DATA [15:4] VCAP2_VD[9:8] VCAP1_VD[9:0] GPIOB[31:27]& GPIOC31& GPIOC[1:0]& GPIOB[26:23]

I/0 I I I/O

CFC_DATA[3:0] VCAP1_VD[9:0] SDIO [3:0]

I/O I

SD_CD GPIOB3

I I/O

SD_WP GPIOB4

I I/O

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Technical Reference Manual of the pin operation is specified by the bit 0 of the MFPSR1 register. This pin operates as GPIOB4 following a reset. SD card clock signal. General Purpose I/OB5. Configuration of the pin operation is specified by the bit 0 of the MFPSR1 register. This pin operates as GPIOB5 following a reset. SD command/response signal. General Purpose I/OB6. Configuration of the pin operation is specified by the bit 0 of the MFPSR1 register. This pin operates as GPIOB6 following a reset. I2C SCL GPIOB7 I/O IC clock. General Purpose I/OB7. Configuration of the pin operation is specified by the bit 30 of the MFPSR0 register. This pin operates as GPIOB7 following a reset. P13 IC data. General Purpose I/O8. Configuration of the pin operation is specified by the bit 30 of the MFPSR0 register. This pin operates as GPIOB8 following a reset. Pulse Width Modulators T14 Pulse width modulation PWM0A. General Purpose I/OB13. Configuration of the pin operation is specified by the bit 24 of the MFPSR0 register. This pin operates as GPIOB13 following a reset. V16 Pulse width modulation PWM0B. General Purpose I/OB14. Configuration of the pin operation is specified by the bit 25 of the MFPSR0 register. This pin operates as GPIOB14 following a reset. U16 Pulse width modulation PWM1A. General Purpose I/OB15. Configuration of the pin operation is specified by the bit 26 of the MFPSR0 register. This pin operates as GPIOB15 following a reset. V17 Pulse width modulation PWM1B. General Purpose I/OB16. Configuration of the pin operation is specified by the bit 27 of the MFPSR0 register. This pin operates as GPIOB16 following a reset. V18 Pulse width modulation PWM2A. General Purpose I/OB17. Configuration of the pin operation is specified by the bit
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SD_CLK GPIOB5

O I/O

K1

SD_CMD_RSP GPIOB6

I/O

L2

P12

SDA GPIOB8

I/O

PWM0A GPIOB13

O I/O

PWM0B GPIOB14

O I/O

PWM1A GPIOB15

O I/O

PWM1B GPIOB16

O I/O

PWM2A GPIOB17

O I/O

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Technical Reference Manual 28 of the MFPSR0 register. This pin operates as GPIOB17 following a reset. Pulse width modulation PWM2B. General Purpose I/OB18. Configuration of the pin operation is specified by the bit 29 of the MFPSR0 register. This pin operates as GPIOB18 following a reset. SSP SSPRxD GPIOB19 I I/O U17 Synchronous serial port receive. General Purpose I/OB19. Configuration of the pin operation is specified by the bit 0 of the MFPSR0 register. This pin operates as GPIOB19 following a reset. Synchronous serial port transmit. General Purpose I/OB20. Configuration of the pin operation is specified by the bit 0 of the MFPSR0 register. This pin operates as GPIOB20 following a reset. Synchronous serial port clock. General Purpose I/OB21. Configuration of the pin operation is specified by the bit 0 of the MFPSR0 register. This pin operates as GPIOB21 following a reset. Synchronous serial port frame. General Purpose I/OB22. Configuration of the pin operation is specified by the bit 0 of the MFPSR0 register. This pin operates as GPIOB22 following a reset. I2S/AC97/SSP I2SRxD/SSPRxD GPIOB23 I I/O T17 IS data in / AC97 audio port data in or synchronous serial port receive. General Purpose I/OB23. Configuration of the pin operation is specified by the bit 1 of the MFPSR0 register. This pin operates as GPIOB23 following a reset. IS data out / AC97 audio port data out or synchronous serial port transmit. General Purpose I/OB24. Configuration of the pin operation is specified by the bit 1 of the MFPSR0 register. This pin operates as GPIOB24 following a reset. IS bit clock / AC97 audio port bit clock. Synchronous serial port clock. General Purpose I/OB25. Configuration of the pin operation is specified by the bit 1 of the MFPSR0 register. This pin operates as GPIOB25 following a reset. IS sync / AC97 audio port sync or
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PWM2B GPIOB18

O I/O

T15

SSPTxD GPIOB20

O I/O

U18

SSPCLK GPIOB21

I/O

R16

SSPFS GPIOB22

I/O

R14

I2STxD/SSPTxD GPIOB24

O I/O

T18

I2SCLK/SSPCLK GPIOB25

I/O

R17

I2SFS/SSPFS
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I/O

P14

Technical Reference Manual synchronous serial port frame. General Purpose I/OB26. Configuration of the pin operation is specified by the bit 1 of the MFPSR0 register. This pin operates as GPIOB26 following a reset. IS system clock / AC97 audio port reset signal. General Purpose I/OB27. Configuration of the pin operation is specified by the bit 1 of the MFPSR0 register. This pin operates as GPIOB27 following a reset. AC97 24.576 MHz clock out. General Purpose I/OB28. Configuration of the pin operation is specified by the bit 1 of the MFPSR0 register. This pin operates as GPIOB28 following a reset. UART1 CTS1n I N13 UART1 clear to send. When low, this signal indicates that the modem or data set is ready to exchange data. The CTS1n signal is a modem status input whose conditions can be tested by the CPU reading bit 4 of the Modem Status Register. Bit 4 is the complement of the CTS1n signal. Bit 0 of the Modem Status Register indicates whether the CTS1n input has changed state since the previous reading of the Modem Status Register. CTS1n has no effect on the transmitter. General Purpose I/OB29. Configuration of the pin operation is specified by the bit 2 of the MFPSR0 register. This pin operates as GPIOB29 following a reset. UART1 data carrier detect. When low, this signal indicates that the data carrier has been detected by the modem or data set. The DCD1n signal is a modem status input whose condition can be tested by the CPU reading bit 7 of the Modem Status Register. Bit 7 is the complement of the DCD1n signal. Bit 3 of the Modem Status Register indicates whether the DCD1n input has changed state since the previous reading of the Modem Status Register. DCD1n has no effect on the receiver. General Purpose I/OB30. Configuration of the pin operation is specified by the bit
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GPIOB26

I2S_AC97_RSTn GPIOB27

O I/O

P15

I2S_AC97CLK GPIOB28

O I/O

R18

GPIOB29

I/O

DCD1n

P16

GPIOB30

I/O

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Technical Reference Manual 2 of the MFPSR0 register. This pin operates as GPIOB30 following a reset. UART1 data set ready. When low, this signal indicates that the modem or data set is ready to establish the communications link with the UART1. The DSR1n signal is a modem status input whose condition can be tested by the CPU reading bit 5 of the Modem Status Register. Bit 5 is the complement of the DSR1n signal. Bit 1 of the Modem Status Register indicates whether the DSR1n input has changed state since the previous reading of the Modem Status Register. General Purpose I/OB31. Configuration of the pin operation is specified by the bit 2 of the MFPSR0 register. This pin operates as GPIOB31 following a reset. UART1 ring indicator. When low, this signal indicates that a telephone ringing signal has been received by the modem or data set. The RI1n signal is a modem status input whose condition can be tested by the CPU reading bit 6 of the Modem Status Register. Bit 6 is the complement of the RI1n signal. Bit 2 of the Modem Status Register indicates whether the RI1n input signal has changed from a low to a high state since the previous reading of the Modem Status Register. General Purpose I/OC0. Configuration of the pin operation is specified by the bit 2 of the MFPSR0 register. This pin operates as GPIOC0 following a reset. UART1 data terminal ready. When low, this signal informs the modem or data set that the UART1 is ready to establish a communications link. The DTR1n output signal can be set to an active low by programming bit 0 of the Modem Control Register to a high level. A system reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. General Purpose I/OC1. Configuration of the pin operation is specified by the bit 2
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DSR1n

P17

GPIOB31

I/O

RI1n

N15

GPIOC0

I/O

DTR1n

N14

GPIOC1

I/O

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Technical Reference Manual of the MFPSR0 register. This pin operates as GPIOC1 following a reset. UART1 request to send. When low, this signal informs the modem or data set that the UART1 is ready to exchange data. The RTS1n output signal can be set to an active low by programming bit 1 of the Modem Control Register. A system reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. General Purpose I/OC2. Configuration of the pin operation is specified by the bit 2 of the MFPSR0 register. This pin operates as GPIOC2 following a reset. UART1 receive. General Purpose I/OC3. Configuration of the pin operation is specified by the bit 3 of the MFPSR0 register. This pin operates as GPIOC3 following a reset. UART1 transmit. General Purpose I/OC4. Configuration of the pin operation is specified by the bit 3 of the MFPSR0 register. This pin operates as GPIOC4 following a reset. UART2 RxD2 GPIOC5 I I/O M15 UART2 receive. General Purpose I/OC5. Configuration of the pin operation is specified by the bit 5 of the MFPSR0 register. This pin operates as GPIOC5 following a reset. UART2 transmit. General Purpose I/OC6. Configuration of the pin operation is specified by the bit 5 of the MFPSR0 register. This pin operates as GPIOC6 following a reset. UART2 clear to send. General Purpose I/OC7. Configuration of the pin operation is specified by the bit 4 of the MFPSR0 register. This pin operates as GPIOC7 following a reset. UART2 request to send. General Purpose I/OC8. Configuration of the pin operation is specified by the bit 4 of the MFPSR0 register. This pin operates as GPIOC8 following a reset. UART3
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RTS1n

P18

GPIOC2

I/O

RxD1 GPIOC3

I I/O

N16

TxD1 GPIOC4

O I/O

N17

TxD2 GPIOC6

O I/O

M16

CTS2n GPIOC7

I I/O

N12

RTS2n GPIOC8

O I/O

N18

Technical Reference Manual RxD3 GPIOC9 I I/O M18 UART3 receive. General Purpose I/OC9. Configuration of the pin operation is specified by the bit 6 of the MFPSR0 register. This pin operates as GPIOC9 following a reset. UART3 transmit. General Purpose I/OC10. Configuration of the pin operation is specified by the bit 6 of the MFPSR0 register. This pin operates as GPIOC10 following a reset. UART4 IrDA_RxL I Infrared receive. Primary input to receive serial data from the infrared transceiver module. If the infrared transceiver provides two receive data outputs, the low-speed output should be connected to this pin. UART4 receive. Configuration of the pin operation is specified by the bit 7 of the MFPSR0 register. This pin operates as IrDA_RxL following a reset. M13 Infrared receive. Primary input to receive serial data from the infrared transceiver module. If the infrared transceiver provides two receive data outputs, the high-speed output should be connected to this pin. GPIOC27. Configuration of the pin operation is specified by the bit 7 of the MFPSR0 register. This pin operates as IrDA_RxH following a reset. L13 IrDA transmit signal. UART4 transmit. Configuration of the pin operation is specified by the bit 7 of the MFPSR0 register. This pin operates as TxDA following a reset. Timer/Counter Interface L17 TCK0 input clock. General Purpose I/OC12. Configuration of the pin operation is specified by the bit 9 of the MFPSR0 register. This pin operates as GPIOC12 following a reset. L18 Input Control/Output A0. As input TIOA0 may be configured for a variety of control functions for Timer/Counter 0. TIOA0 may be configured as a timer/counter output. General Purpose I/OC13. Configuration M14

TxD3 GPIOC10

O I/O

M17

RxD4

IrDA_RxH

GPIOC27

I/O

IrDA_TxD TxD4

TCK0 GPIOC12

I I/O

TIOA0

I/O

GPIOC13

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Technical Reference Manual of the pin operation is specified by the bit 10 of the MFPSR0 register. This pin operates as GPIOC13 following a reset. Input Control/Output B0. As input TIOB0 may be configured for a variety of control functions for Timer/Counter0. TIOB0 may be configured as a timer/counter output. General Purpose I/OC28. Configuration of the pin operation is specified by the bit 11 of the MFPSR0 register. This pin operates as GPIOC28 following a reset. TCK1 input clock. General Purpose I/OC14. Configuration of the pin operation is specified by the bit 12 of the MFPSR0 register. This pin operates as GPIOC14 following a reset. Input Control/Output A1. As input TIOA1 may be configured for a variety of control functions for Timer/Counter 1. TIOA1 may be configured as a timer/counter output. General Purpose I/OC15. Configuration of the pin operation is specified by the bit 13 of the MFPSR0 register. This pin operates as GPIOC15 following a reset. Input Control/Output B1. As input TIOB1 may be configured for a variety of control functions for Timer/Counter1. TIOB1 may be configured as a timer/counter output. General Purpose I/OC29. Configuration of the pin operation is specified by the bit 14 of the MFPSR0 register. This pin operates as GPIOC29 following a reset. TCK2 input clock. TV encoder clock output. It outputs 27 MHz TV clock. General Purpose I/OC16. Configuration of the pin operation is specified by the bit 15 of the MFPSR0 register. This pin operates as GPIOC16 following a reset. Input Control/Output A2. As input TIOA2 may be configured for a variety of control functions for Timer/Counter 2. TIOA2 may be configured as a timer/counter output. General Purpose I/OC17. Configuration

TIOB0

I/O

L16

GPIOC28

TCK1 GPIOC14

I I/O

L15

TIOA1

I/O

L14

GPIOC15

TIOB1

I/O

K13

GPIOC29

TCK2 TVCLK GPIOC16

I O I/O

K15

TIOA2

I/O

K14

GPIOC17

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Technical Reference Manual of the pin operation is specified by the bit 16 of the MFPSR0 register. This pin operates as GPIOC17 following a reset. K16 Input Control/Output B2. As input TIOB2 may be configured for a variety of control functions for Timer/Counter2. TIOB2 may be configured as a timer/counter output. General Purpose I/OC30. Configuration of the pin operation is specified by the bit 17 of the MFPSR0 register. This pin operates as GPIOC30 following a reset. General Purpose I/O Port R6 GPIOA[7] General Purpose I/OA [7:0]. Link speed LED output. Active low U6 GPIOA [6] indicates the Ethernet link speed is 100 V6 GPIOA [5] Mbps. P7 GPIOA [4] Full duplex LED output. Active low P6 GPIOA [3] indicates the full duplex mode the of U7 GPIOA [2] Ethernet controller. It can be selected as T7 GPIOA [1] Ethernet link status output as follows: R7 GPIOA [0] 0 Down 1 Up Configuration of the pins is specified by the bits [22:21] of the MFPSR0 register. These pins operate as GPIOA [7:0] following a reset. VLIO ready input. Active high. It can be used to insert a wait state to extend memory cycles. The GPIOA7 input is internally connected with internal VLIO_RDY of the SDRAM controller. The bit 22 of the MFPSR0 register is used to control the VLIO_RDY as follows: 0 Disable, default 1 Enable VLIO_RDY Pixel data output [7:0]. It outputs 8-bit video data in the CCIR-656 format (YVU). These pins are` connected with the external TV encoder. R15 General Purpose I/OC26. Configuration of the pin operation is specified by bit 12 of the MFPSR1 register. This pin operates as GPIOC26 following a reset. T16 General Purpose I/OC11. Configuration of the pin operation is specified by bit 13 of the MFPSR1 register. This pin operates as GPIOC11 following a reset.
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I/O

GPIOC30

GPIOA [7:0] GPIOA1/SPELED GPIOA0/FDXLED/ LINKLED

I/O O O

GPIOA7/ VLIO_RDY

PIX_DO[7:0]

GPIOC26

I/O

GPIOC11

I/O

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Technical Reference Manual Clock, Reset and Test Mode H17 Test mode input (pull down resistor). This pin is reserved for the production mode. For normal operation, it must be tied to ground H16 Cold Reset. The cold reset signal performs a poweron reset on aJ-102 externally. The CRTSn signal must be treated as an open collector signal. The minimum active reset time after the initial power-on reset is 8T (of XIN). The aJ-102 has the capability to activate the CRSTn signal based on command issues via the test interface. The test interface allows software engineer to perform a system reset from the development environment. J16 Reset output. The reset output is an inverted version of CRSTn to provide a reset signal for external system devices requiring an active high reset. J15 Clock output. This output clock is devrived from the intrenal HCLK clock. The CLKO frequency can be configured as 1/2, 1/4, 1/8, 1/16 of the HCLK clock. The output can be disabled to reduce power consumption and electromagentic emission. General Purpose I/OC22. Configuration of the pin operation is specified by bit 3 of the MFPSR1 register. This pin is operated as GPIOC22 on power reset. J14 Wakeup. The wakeup input allows external logic to exit the Java processors standby mode. The Java processors idle mode is exited when an interrupt condition is present. NANDRDY Its used to sample the NAND Flash ready signal when accessing NAND flash devices. G18 This pin is used to provide the reference clock for the internal PLL1, PLL2, and PLL3. The range of the crystal input is 1MHz~12 MHz. The PLL1 multiplies the reference clock and generate the

TESTMODE

CRSTn

Open collector I/O

RSTOUT

CLKO

GPIOC22

I/0

WAKn

NANDRDY

XIN

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Technical Reference Manual required clocks for CPU, AHB devices, and APB devices. The PPLs may be bypassed to apply an external slow clock at XIN. When bypassing the PLL1, XIN is used to drive the internal clocks. A 3.6864 MHz crystal is normally used as the reference clock. An external clock source with the 1.8 V level can be applied instead of the crystal. F18 Reference crystal feedback. XOUT is used to excite the reference oscillator circuit. H18 Digital 1.8 V supply for the high frequency crystal E18 Ground for the high frequency crystal N1 This pin is used to provide the optional clock source for the WDT and RTC. The range of the crystal input is 32KHz~1 MHz. A 32.768 KHz crystal is normally used as the reference clock. An external clock source with the 1.8 V level can be applied instead of the crystal. M1 32.768 KHz crystal output. L1 Digital 1.8 V supply for the low frequency crystal P1 Ground for the low frequency crystal A8 DDL input clock. It is used to feedback the external SDR_CLK as the reference clock for the internal DLL. Voltage Regulator (RTC) R2 5V input supply for the internal voltage regulator. A system power of 5V or an external lithium battery in the range of 3.6 to 4.2V is applied to this pin. P2 Analog ground for the internal voltage regulator. It s always tied to ground even when the internal voltage regulator is not used. T3 3.3 V voltage regulator output. An external 3.3 pF capacitance is connected to the ground, in order to stabilize the internal output voltage. N3 1.8V voltage regulator output. An external 3.3 pF capacitance is connected to the ground, in order to stabilize the internal output voltage.

XIO VCCKXIN GNDXIN OSCLIN

O I I I/O

OSCLIO VCCKOSCL GNDOSCL HCLK

I/O I I I

VCC5A

GNDK_EX

VCC3A

VCCK_EX

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Technical Reference Manual VCCOK POREN I I Indicates the external system power supply (1.8V) is valid. M2 Power on reset enable input for RTC associated with power cut. It s active low. This pin is reserved for the production mode. For normal operation, it must be tied to the ground N2 NC(POROUT) NC Power and Ground Pins Core power (1.8V) H10 VCCK[7] Digital 1.8 V supply for internal logic. They must be connected to the 1.8 V on H7 VCCK[6] the PCB H8 VCCK[5] H9 VCCK[4] J11 VCCK[3] K11 VCCK[2] L11 VCCK[1] M11 VCCK[0] Power for I/O pins G6 VCC3IO[16] Digital 3.3 V supply for all I/O pins. They must be connected to the common G7 VCC3IO[15] 3.3V on the PCB. G8 VCC3IO[14] H11 VCC3IO[13] H6 VCC3IO[12] J12 VCC3IO[11] J6 VCC3IO[10] K12 VCC3IO[9] L12 VCC3IO[8] M10 VCC3IO[7] M12 VCC3IO[6] M7 VCC3IO[5] M8 VCC3IO[4] M9 VCC3IO[3] N11 VCC3IO[2] N6 VCC3IO[1] N7 VCC3IO[0] Grounds C6 GND[28] Ground supply for all I/O pins and internal logic. D6 GND[27] They must be connected to the common D7 GND[26] ground plane on the PCB. D8 GND[25] E6 GND[24] F6 GND[23] F7 GND[22] F8 GND[21]
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NC

VCCK [7:0]

VCC3IO [16:0]

GND [28:0]

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Technical Reference Manual J10 GND[20] J7 GND[19] J8 GND[18] J9 GND[17] K10 GND[16] K6 GND[15] K7 GND[14] K8 GND[13] K9 GND[12] L10 GND[11] L4 GND[10] L5 GND[9] L6 GND[8] L7 GND[7] L8 GND[6] L9 GND[5] M6 GND[4] N4 GND[3] N5 GND[2] P3 GND[1] R3 GND[0] Power Grounds for PLLs E8 1.8 V supply input for DLL. It must be connected to the 1.8V supply on the PCB. E7 Ground supply for the DLL. It must be connected to the common ground plane of the PCB. M5 1.8 V supply input for the PLL1. It must be connected to the 1.8V supply on the PCB. M4 Ground supply for the PLL1. It must be connected to the common ground plane of the PCB. K17 1.8 V supply input for the PLL2. It must be connected to the 1.8V supply on the PCB. K18 Ground supply for the PLL2. It must be connected to the common ground plane of the PCB. J17 1.8 V supply input for the PLL3. It must be connected to the 1.8V supply on the PCB. J18 Ground supply for the PLL3. It must be connected to the common ground plane of the PCB.
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VCC18DLL GNDDLL VCC18PLL1 GNDPLL1 VCC18PLL2 GNDPLL2 VCC18PLL3 GNDPLL3

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Technical Reference Manual

3.2.

Package information

The aJ-200 is housed in a 324-pin TFBGA package in the size of 13 mm x 13 mm x 1.20 mm, with a ball pitch of 0.65 mm

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4. Memory Map
This chapter describes the memory maps and the chip configuration registers of the aJ-200. The base address referred to in each peripheral register address is derived from this table. The following figure shows the detailed memory address map of the aJ-200.
0xB7FF FFFF

Reserved
0xA000 0000 0x9FFF FFFF 0x9FFF FFFF

APB
0x9800 0000 0x97FF FFFF

128 MB

Reserved
0x90D0 0000 0x90CF FFFF 0x90C0 0000 0x90BF FFFF 0x90B0 0000 0x90AF FFFF 0x90A0 0000 0x909F FFFF 0x9090 0000 0x908F FFFF 0x9080 0000 0x907F FFFF 0x9070 0000 0x906F FFFF 0x9060 0000 0x905F FFFF 0x9050 0000 0x904F FFFF 0x9040 0000 0x903F FFFF 0x9030 0000 0x902F FFFF 0x9020 0000 0x901F FFFF 0x9010 0000 0x900F FFFF 0x9000 0000 0x5FFF FFFF 0x5000 0000 0x47FF FFFF 0x1000 0000 0x00FF FFFF

Reserved

Video Capture Port Registers EBI Registers AES Registers Ethernet Registers USBOTG Registers MediaCodec LCDC Registers AHB--APB Registers DMAC Registers SDRAMC Registers SMC Registers AHB Registers Reserved Reserved SDRAM External EBI Device (CS7n) External EBI Device (CS6n) External EBI Device (CS5n) External EBI Device (CS4n) External EBI Device (CS3n) External EBI Device (CS2n) SRAM/ROM/FLASH (CS1n) SRAM/ROM/FLASH (CS0n)

1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 GB 512 MB
0x9930 0000 0x992F FFFF 0x9920 0000 0x991F FFFF 0x9910 0000 0x990F FFFF 0x9900 0000 0x98FF FFFF 0x98F0 0000 0x98EF FFFF 0x98E0 0000 0x98DF FFFF 0x98D0 0000 0x98CF FFFF 0x98C0 0000 0x98BF FFFF 0x98B0 0000 0x98AF FFFF 0x98A0 0000 0x989F FFFF 0x9890 0000 0x988F FFFF 0x9880 0000 0x987F FFFF 0x9870 0000 0x986F FFFF 0x9860 0000 0x985F FFFF 0x9850 0000 0x984F FFFF 0x9840 0000 0x983F FFFF

I2S/AC97 PWM GPIOC GPIOB SDC CFC Reserved SSP I2C IrDA/UART4 INT GPIOA RTC WDT TIMER UART2 UART1 UART3 JEMCore-II

256 MB

0x9830 0000 0x982F FFFF 0x9820 0000 0x981F FFFF 0x9810 0000 0x980F FFFF 0x9800 0000

0x0000 0000

Figure 4-1.

Address Memory Map

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Technical Reference Manual 4.1. Internal Registers

The internal registers in the aJ-200 are listed in Table 4-1 Table 4-1. Device Name AHBC AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller AHB Controller SMC SMC SMC SMC SMC SMC SMC SMC SMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC Address 0x90100000 + 0x00 0x90100000 + 0x04 0x90100000 + 0x08 0x90100000 + 0x0C 0x90100000 + 0x10 0x90100000 + 0x14 0x90100000 + 0x18 0x90100000 + 0x1C 0x90100000 + 0x24 0x90100000 + 0x30 0x90100000 + 0x34 0x90100000 + 0x38 0x90100000 + 0x3C 0x90100000 + 0x44 0x90100000 + 0x48 0x90100000 + 0x4C 0x90100000 + 0x54 0x90100000 + 0x58 0x90100000 + 0x80 0x90100000 + 0x84 0x90100000 + 0x88 0x90200000 + 0x00 0x90200000 + 0x04 0x90200000 + 0x08 0x90200000 + 0x0C 0x90200000 + 0x10 0x90200000 + 0x14 0x90200000 + 0x18 0x90200000 + 0x1C 0x90200000 + 0x40 0x90300000 + 0x00 0x90300000 + 0x04 0x90300000 + 0x08 0x90300000 + 0x0C 0x90300000 + 0x10 0x90300000 + 0x14 Internal Registers Description AHB slave 0 Base/Size Register AHB slave 1 Base/Size Register AHB slave 2 Base/Size Register AHB slave 3 Base/Size Register AHB slave 4 Base/Size Register AHB slave 5 Base/Size Register AHB slave 6 Base/Size Register AHB slave 7 Base/Size Register AHB slave 9 Base/Size Register AHB slave 12 Base/Size Register AHB slave 13 Base/Size Register AHB slave 14 Base/Size Register AHB slave 15 Base/Size Register AHB slave 17 Base/Size Register AHB slave 18 Base/Size Register AHB slave 19 Base/Size Register AHB slave 21 Base/Size Register AHB slave 22 Base/Size Register Priority Control Register Transfer Control Register Interrupt Control Register Memory Bank 0 Configuration Register Memory Bank 0 Timing Parameter Register Memory Bank 1 Configuration Register Memory Bank 1 Timing Parameter Register Memory Bank 2 Configuration Register Memory Bank 2 Timing Parameter Register Memory Bank 3 Configuration Register Memory Bank 3 Timing Parameter Register Shadow Status Register SDRAM Timing Parameter 0 SDRAM Timing Parameter 1 SDRAM Configuration Register External Bank0 Base / Size Register External Bank1 Base / Size Register External Bank2 Base / Size Register

Name Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register PLevel TransCtl IntrSts MB0CR MB0TPR MB1CR MB1TPR MB2CR MB2TPR MB3CR MB3TPR SSR STP0 STP1 SCR EB0BSR EB1BSR EB2BSR

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Technical Reference Manual Device Name SDRAMC SDRAMC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC
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Address 0x90300000 + 0x18 0x90300000 + 0x34 0x90400000 + 0x00 0x90400000 + 0x04 0x90400000 + 0x08 0x90400000 + 0x0C 0x90400000 + 0x10 0x90400000 + 0x14 0x90400000 + 0x18 0x90400000 + 0x1C 0x90400000 + 0x20 0x90400000 + 0x24 0x90400000 + 0x28 0x90400000 + 0x100 0x90400000 + 0x104 0x90400000 + 0x108 0x90400000 + 0x10C 0x90400000 + 0x110 0x90400000 + 0x114 0x90400000 + 0x120 0x90400000 + 0x124 0x90400000 + 0x128 0x90400000 + 0x12C 0x90400000 + 0x130 0x90400000 + 0x134 0x90400000 + 0x140 0x90400000 + 0x144 0x90400000 + 0x148 0x90400000 + 0x14C 0x90400000 + 0x150 0x90400000 + 0x154 0x90400000 + 0x160 0x90400000 + 0x164 0x90400000 + 0x168 0x90400000 + 0x16C 0x90400000 + 0x170 0x90400000 + 0x174 0x90400000 + 0x180 0x90400000 + 0x184 0x90400000 + 0x188 0x90400000 + 0x18C 0x90400000 + 0x190

Name EB3BSR ATOC INT INT_TC INT_TC_CLR INT_ERR/ABT INT_ERR/ABT_CLRR TC ERR/ABT CH_EN CH_BUSY CSR SYNC C0_CSR C0_CFG C0_SrcAddr C0_DstAddr C0_LLP C0_SIZE C1_CSR C1_CFG C1_SrcAddr C1_DstAddr C1_LLP C1_SIZE C2_CSR C2_CFG C2_SrcAddr C2_DstAddr C2_LLP C2_SIZE C3_CSR C3_CFG C3_SrcAddr C3_DstAddr C3_LLP C3_SIZE C4_CSR C4_CFG C4_SrcAddr C4_DstAddr C4_LLP
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Description External Bank3 Base / Size Register Arbiter Time Out Cycles Interrupt Status Register Interrupt for Terminal Count Status Register Interrupt for Terminal Count Clear Register Interrupt for Error/Abort Status Register Interrupt for Error/Abort Clear Register Terminal Count Status Register Error/Abort Status Register Channel Enable Status Register Channel Busy Register Status Register Main Configuration Status Register Sync Register Channel 0 Control Register Channel 0 Configuration Register Channel 0 Source Register Channel 0 Destination Register Channel 0 Linked List Pointer Register Channel 0 Transfer Size Register Channel 1 Control Register Channel 1 Configuration Register Channel 1 Source Register Channel 1 Destination Register Channel 1 Linked List Pointer Register Channel 1 Transfer Size Register Channel 2 Control Register Channel 2 Configuration Register Channel 2 Source Register Channel 2 Destination Register Channel 2 Linked List Pointer Register Channel 2 Transfer Size Register Channel 3 Control Register Channel 3 Configuration Register Channel 3 Source Register Channel 3 Destination Register Channel 3 Linked List Pointer Register Channel 3 Transfer Size Register Channel 4 Control Register Channel 4 Configuration Register Channel 4 Source Register Channel 4 Destination Register Channel 4 Linked List Pointer Register
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Address 0x90400000 + 0x194 0x90400000 + 0x1a0 0x90400000 + 0x1a4 0x90400000 + 0x1a8 0x90400000 + 0x1aC 0x90400000 + 0x1b0 0x90400000 + 0x1b4 0x90400000 + 0x1c0 0x90400000 + 0x1c4 0x90400000 + 0x1c8 0x90400000 + 0x1cC 0x90400000 + 0x1d0 0x90400000 + 0x1d4 0x90400000 + 0x1e0 0x90400000 + 0x1e4 0x90400000 + 0x1e8 0x90400000 + 0x1eC 0x90400000 + 0x1f0 0x90400000 + 0x1f4 0x90500000 + 0x04 0x90500000 + 0x08 0x90500000 + 0x0C 0x90500000 + 0x10 0x90500000 + 0x14 0x90500000 + 0x18 0x90500000 + 0x20 0x90500000 + 0x2C 0x90500000 + 0x40 0x90500000 + 0x44 0x90500000 + 0x48 0x90500000 + 0x4C 0x90500000 + 0x50 0x90500000 + 0x54 0x90500000 + 0x58 0x90500000 + 0x5C 0x90500000 + 0x80 0x90500000 + 0x84 0x90500000 + 0x88 0x90500000 + 0x8C 0x90500000 + 0x90 0x90500000 + 0x94 0x90500000 + 0x98 0x90500000 + 0x9C

Name C4_SIZE C4_CSR C4_CFG C4_SrcAddr C4_DstAddr C4_LLP C4_SIZE C4_CSR C4_CFG C4_SrcAddr C4_DstAddr C4_LLP C4_SIZE C4_CSR C4_CFG C4_SrcAddr C4_DstAddr C4_LLP C4_SIZE Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register Base/Size register ASrcAddr ADstAddr ACyc ACmdR BSrcAddr BDstAddr BCyc BCmdR
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Description Channel 4 Transfer Size Register Channel 5 Control Register Channel 5 Configuration Register Channel 5 Source Register Channel 5 Destination Register Channel 5 Linked List Pointer Register Channel 5 Transfer Size Register Channel 6 Control Register Channel 6 Configuration Register Channel 6 Source Register Channel 6 Destination Register Channel 6 Linked List Pointer Register Channel 6 Transfer Size Register Channel 7 Control Register Channel 7 Configuration Register Channel 7 Source Register Channel 7 Destination Register Channel 7 Linked List Pointer Register Channel 7 Transfer Size Register APB Slave 1 Base/Size Register APB Slave 2 Base/Size Register APB Slave 3 Base/Size Register APB Slave 4 Base/Size Register APB Slave 5 Base/Size Register APB Slave 6 Base/Size Register APB Slave 8 Base/Size Register APB Slave 11 Base/Size Register APB Slave 16 Base/Size Register APB Slave 17 Base/Size Register APB Slave 18 Base/Size Register APB Slave 19 Base/Size Register APB Slave 20 Base/Size Register APB Slave 21 Base/Size Register APB Slave 22 Base/Size Register APB Slave 23 Base/Size Register Source address for DMA channel A Destination address for DMA channel A Cycles for DMA channel A Command register for DMA channel A Source address for DMA channel B Destination address for DMA channel B Cycles for DMA channel B Command register for DMA channel B
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Technical Reference Manual Device Name APB Bridge APB Bridge APB Bridge APB Bridge APB Bridge APB Bridge APB Bridge APB Bridge LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC
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Address 0x90500000 + 0xA0 0x90500000 + 0xA4 0x90500000 + 0xA8 0x90500000 + 0xAC 0x90500000 + 0xB0 0x90500000 + 0xB4 0x90500000 + 0xB8 0x90500000 + 0xBC 0x90600000 + 0x00 0x90600000 + 0x04 0x90600000 + 0x08 0x90600000 + 0x0C 0x90600000 + 0x10 0x90600000 + 0x14 0x90600000 + 0x18 0x90600000 + 0x24 0x90600000 + 0x30 0x90600000 + 0x3C 0x90600000 + 0x48 0x90600000 + 0x4C 0x90600000 + 0x50 0x90600000 + 100 0x90600000 + 104 0x90600000 + 108 0x90600000 + 10C 0x90600000 + 200 0x90600000 + 204 0x90600000 + 300 0x90600000 + 304 0x90600000 + 308 0x90600000 +30C 0x90600000 +310 0x90600000 +400 0x90600000 +404 0x90600000 +408 0x90600000 +40C 0x90600000 +600~6FC 0x90600000

Name CSrcAddr CDstAddr CCyc CCmdR DSrcAddr DDstAddr DCyc DCmdR LCD_function_en LCD_panle_pixel LCD_intr_mask LCD_intr_clr LCD_intr_status LCD_frame_buffer LCD_im0frm0base LCD_im1frm0base LCD_im2frm0base LCD_im3frm0base LCD_patbarcolor LCD_fifoth GPIOControl LCD_hortiming LCD_vertimg0 LCD_vertimg1 LCD_polarity LCD_serialpanel LCD_ccir656 LCD_pipblend LCD_pip1pos LCD_pip1dim LCD_pip2pos LCD_pip2dim LCD_colorman0 LCD_colorman1 LCD_colorman2 LCD_colorman3 LCD_GaRdLUT LCD_GaGnLUT
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Description Source address for DMA channel C Destination address for DMA channel C Cycles for DMA channel C Command register for DMA channel C Source address for DMA channel D Destination address for DMA channel D Cycles for DMA channel D Command register for DMA channel D LCD function enable LCD panle pixel parameter LCD interupt enable mask LCD interrupt status clear LCD interrupt status LCD frame buffer parameter LCD panel image0 frame0 base address LCD panel image1 frame0 base address LCD panel image2 frame0 base address LCD panel image3 frame0 base address LCD pattern generator LCD fifo threshold GPIO control LCD horizontal timing control LCD vertical timing control 0 LCD vertical timing control 1 LCD polarity control LCD serial panel pixel parameters LCD CCIR656 parameters LCD pip parameters PIP sub-picture 1 position PIP sub-picture 1 dimension PIP sub-picture 2 position PIP sub-picture 2 dimension LCD color management parameter 0 LCD color management parameter 1 LCD color management parameter 2 LCD color management parameter 3 LCD Gamma Red Lookup table LCD Gamma Green Lookup table
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Technical Reference Manual Device Name LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec Address +700~7FC 0x90600000 +800~8FC 0x90600000 +A00~BFC 0x90600000 +1100 0x90600000 +1104 0x90600000 +1108 0x90600000 +110C 0x90600000 +1110 0x90600000 +1114 0x90600000 +1118 0x90600000 +111C 0x90600000 +1120 0x90600000 +112C 0x90600000 +2000 0x90600000 +2004 0x90600000 +2008 0x90600000 +200C 0x90600000 +8000~BFFC 0x90700000 0x90708000 0x90710000 0x90714000 0x90718000 0x90717C00 0x9071A000 0x90720000 0x90720008 0x9072000C 0x90720010 0x90720014 0x90720018 0x9072001C 0x90720020 0x90720024 0x90720028 0x9072002C Name LCD_GaBuLUT PaletteWritePort Scal_hor_no_in Scal_ver_no_in Scal_hor_no_out Scal_ver_no_out Scal_misc Scal_hor_high_th Scal_hor_low_th Scal_ver_high_th Scal_hor_low_th Scal_hor_ver_num Osd_ctrl0 Osd_ctrl1 Osd_forecolor Osd_backcolor OSDFont accessing port Program Data Bank0 Bank1 Bank2/3 Bank4 Bank5 MECTL MECR MIN_SAD CMDADDR MECADDR HOFFSET MCCTL MCCADDR MEIADDR CPSTS QCR0 Description LCD Gamma Blue Lookup table LCD palette RAM write accessing port Scalar horizontal resolution input Scalar vertical resolution input Scalar horizontal resolution output Scalar vertical resolution output Scalarmiscellanuos control register Horizontal upscaling high threshold Horizontal upscaling low threshold Vertical upscaling high threshold Vertical upscaling low threshold Scaler resolution parameter OSD control register 0 OSD control register 1 OSD fore color register OSD back color register OSD font RAM accessing port Used by the internal RISC Used by the internal RISC Calculation buffer Current block buffer/Interpolation buffer Reference block buffer Quantization table buffer Deblocking buffer ME control register ME coefficient register Minimum SAD register ME command queue start address register ME current block start address register Horizontal offset to reference block address MC control register MC current block start address register ME interpolation block start address register Coprocessor status register Quantization coefficient register 0

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Technical Reference Manual Device Name MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec
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Address 0x90720038 0x9072003C 0x90720040 0x90720044 0x90720048 0x9072004C 0x90720050 0x90720054 0x90720058 0x9072005C 0x90720060 0x90720064 0x90720068 0x9072006C 0x90720070 0x90720074 0x90720078 0x9072007C 0x90720080 0x90720084 0x90720088 0x90720090 0x90720094 0x90720098 0x9072009C 0x90720008 0x9072001C 0x90720020 0x90720028 0x9072002C 0x90720030 0x90720034 0x90720038

Name DZAR/QAR CKR ACDCPAR VADR CURDEV BITDATA BITLEN MBIDX MCIADDR VLDCTL VOP0 VOP1 MVD0/SCODE MVD1/RSMRK TOADR VLDSTS ASADR INNER_CPUCTL VOP_SIZE PMVADDR DTOFMT INNER_MASK EXT_MASK INT_FLAG INT_STS MCUBR MCCTL MCCADDR CPSTS MCUTIR PYDCR PUVDCR DZAR/QAR
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Description De-zigzag scan buffer address register. Quantization block address register Coprocessor clock control register AC/DC predictor buffer address register VLC/VLD local data address register ME current block deviation register Bit-stream access data port Bit-stream access length/auto-buffer local memory pointer MB index for data partition decoding MC interpolation and result block start address register VLD control register VOP parameter 0 VOP parameter 1 Differential motion vector register 0/Start code Differential motion vector register 1/Re-sync marker VLD table output address VLD status register Auto-buffering system data address Inner CPU control register VOP size register Prediction motion vector buffer start address register Image output format select register Enable bit for the inner CPU interrupt Enable bit for the external CPU interrupt Interrupt flag, read for flag (after mask), write 1 clear Interrupt status, read for status (before mask), read only Minimum coded unit block number register MC control register MC current block start address register Coprocessor status register Minimum coded unit table index register JPEG previous Y dc value register JPEG previous UV dc value register De-zigzag scan buffer address
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Technical Reference Manual Device Name Address Name Description register. Quantization block address register Reserved VLC data output address register Bit-stream access data register Bit-stream access length register MC interpolation and result block start address register VLD control register VLD look up table register VLC output last word VLD status register Auto-buffer system data address JPEG sequence control register JPEG MCU row/column number JPEG restart interval JPEG-encoded bitstream length (unit: byte) System memory base address (word aligned) Local memory base address (word aligned) Block width information Control register and transfer length register (word) Chain command address (four-word aligned) Status register Group execution control Group sync control Auto-buffer control DMA threshold value Auto send interrupt even last cmd is skip/disable The bitstream buffer size in the system memory in units of 64 bytes The start address offset between two MCU Y component of each neighboring MCU row The start address offset between two MCU U component of each neighboring MCU row The start address offset between two MCU V component of each neighboring MCU row Control register
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MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec
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0x9072003C 0x90720044 0x9072004C 0x90720050 0x90720058 0x9072005C 0x90720068 0x9072006C 0x90720074 0x90720078 0x907200A0 0x907200A4 0x907200A8 0x907200AC 0x90720400 0x90720404 0x90720408 0x9072040C 0x90720410 0x90720414 0x90720418 0x9072041C 0x90720420 0x90720424 0x90720428 0x9072042C 0x90720430 0x90720434 0x90720438 0x9072043C 0x90C00000

Reserved VADR BADR BALR MCIADDR VLDCTL VLDLUTR VLASTWORD VLDSTS ABADR JPGSeqCtl JPGFrmInfo1 JPGFrmInfo2 JPGFrmInfo3 SMaddr LMaddr BlkWidth Control CCA Status Reserved GRPC GRPS ABF_ctrl THRESHOLD AUTOINT Sys_buf_size MCUYrow_offset MCUUrow_offset MCUVrow_offset Control
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Technical Reference Manual Device Name MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec MediaCodec Address 0x90C00004 0x90C00008 0x90C00010 0x90C00014 0x90C00018 0x90C00020 0x90C00030 0x90C00040 0x90C00044 0x90C00048 0x90C00050 Name Format Status YBA Hsize Tcnt UBA VBA Ybas_stride Ubas_stride Vbas_stride Frame_Count Description Video format register Interrupt status register Base address of the Y buffer in system memory (word aligned) Image horizontal size register Transfer counter register Base address of the U buffer in system memory (word aligned) Base address of the V buffer in system memory (word aligned) Base address stride for Y buffer Base address stride for U buffer Base address stride for V buffer Record the number of outstanding frames, maximum concurrent frame number and interrupt threshold frame number Writing 0x01 to this port decreases the number of buffered frames by one Host control capability register Host control structure parameters Host control capacity parameters Host control USB command register Host control USB status register Host control USB interrupt enable register Host control frame index register Host control periodic frame list base address register Host control current list address register Host control port status and control register Host control miscellanous register OTG control status register OTG interrupt status register OTG interrupt enable register Global interrupt status register Global mask of OTG interrupt register Device main control register Device address register Device test register Device SOF frame number register Device SOF mask timer register PHY test mode selector register
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MediaCodec

0x90C00060

Frame_Dec

USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG
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0x90800000 + 0x00 0x90800000 + 0x04 0x90800000 + 0x08 0x908A0000 + 0x10 0x90800000 + 0x14 0x90800000 + 0x18 0x90800000 + 0x1C 0x90800000 + 0x24 0x90800000 + 0x28 0x90800000 + 0x30 0x90800000 + 0x40 0x90800000 + 0x80 0x90800000 + 0x84 0x90800000 + 0x88 0x90800000 + 0xC0 0x90800000 + 0xC4 0x90800000 + 0x100 0x90800000 + 0x104 0x90800000 + 0x108 0x90800000 + 0x10C 0x90800000 + 0x110 0x90800000 + 0x114

HCCR HCSPARAMS HCCPARAMS USBCMD USBSTS USBINTR FRINDEX PERIODICLB ASYNCLISTADDR PORTSC HCMIS OTGCS OTGINTS OTGINTEN GBINTS GBMINT DEVMC DEVADDR DEVTEST DEVSOFFN DECSOFMT PHYTMS
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Technical Reference Manual Device Name USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG Address 0x90800000 + 0x118 Name DEVVIOC Description Device vendor specific IO control register Device CX configuration status register Device CX confifuration and FIFO empty status register Device idle counter register Device mask of interrupt group register Device mask of interrupt source group 0 register Device mask of interrupt source group 1 register Device mask of interrupt source group 2 register Device interrupt group register Device interrupt source group 0 register Device interrupt source group 1 register Device interrupt source group 2 register Device receive zero-length data packet register Device transfer zero-length data packet register Device isochronous sequential error/abort register Device in endpoint x maxpacketsize registers. Note: one register per point x= 1~7 Device out endpoint x maxpacketsize registers. Note: one register per point x= 1~7 Device end-point map 14 register Device end-point map 58 register Device FIFO map register Device FIFO configuration register Device FIFO x instruction byte count registers Note: one regsiter per FIFO x=0~3 Device DMA target FIFO number register. Device DMA controller parameter setting 1 register

0x90800000 + 0x11C DEVCXCS 0x90800000 + 0x120 0x90800000 + 0x124 0x90800000 + 0x130 0x90800000 + 0x134 0x90800000 + 0x138 DEVCXCFEMPTY DEVIC DEVMINTG DEVMSG0 DEVMSG1

0x90800000 + 0x13C DEVMSG2 0x90800000 + 0x140 0x90800000 + 0x144 0x90800000 + 0x148 DEVINTG DEVINTG0 DEVINTG1

0x90800000 + 0x14C DEVINTG2 0x90800000 + 0x150 0x90800000 + 0x154 0x90800000 + 0x158 0x90800000 + 0x160+4(X-1) X=(1~7) 0x90800000 + 0x180+4(X-1) X=(1~7) 0x90800000 + 0x1A0 0x90800000 + 0x1A4 0x90800000 + 0x1A8 0x90800000 + 0x1AC DEVRZLDP DEVSZLDP DEVISEA DEVIEPXM

USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG USB 2.0 OTG

DEVOEPXM DEVEPMAP14 DEVEPMAP58 DEVFIFOM DEVFIFOC

0x90800000 + 0x1B0 +4X DEVFIFOXIBC X=0~3 0x90800000 + 0x1C0 DEVDMATFIFON 0x90800000 + 0x1C8 DEVDMACPS1

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Technical Reference Manual Device Name USB 2.0 OTG USB 2.0 OTG Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Address Name Description Device DMA controller parameter setting 2 register Device DMA controller parameter setting 3 register Interrupt Status Register Interrupt Mask Register MAC Most Significant Address Register MAC Least Significant Address Register Multicast Address Hash Table 0 Register Multicast Address Hash Table 1 Register Transmit Poll Demand Register Receive Poll Demand Register Transmit Ring Base Address Register Receive Ring Base Address Register Interrupt Timer Control Register Automatic Polling Timer Control Register DMA Burst Length and Arbitration Control Register Revision Register Feature Register MAC Control Register MAC Status Register PHY Control Register PHY Write Data Register Flow Control Register Back Pressure Register Test Seed Register DMA/FIFO State Register Test Mode Register TX_MCOL and TX_SCOL Counter Register RPF and AEP Counter Register XM and PG Counter Register RUNT_CNT and TLCC Counter Register CRCER_CNT and FTL_CNT Counter Register RLC and RCC Counter Register BROC Counter Register MULCA Counter Register RP Counter Register

0x90800000 + 0x1CC DEVDMACPS2 0x90800000 + 0x1D0 DEVDMACPS3 0x90900000 + 0x00 0x90900000 + 0x04 0x90900000 + 0x08 0x90900000 + 0x0C 0x90900000 + 0x10 0x90900000 + 0x14 0x90900000 + 0x18 0x90900000 + 0x1C 0x90900000 + 0x20 0x90900000 + 0x24 0x90900000 + 0x28 0x90900000 + 0x2C 0x90900000 + 0x30 0x90900000 + 0x34 0x90900000 + 0x38 0x90900000 + 0x88 0x90900000 + 0x8C 0x90900000 + 0x90 0x90900000 + 0x94 0x90900000 + 0x98 0x90900000 + 0x9C 0x90900000 + 0xC4 0x90900000 + 0xC8 0x90900000 +0xCC 0x90900000 + 0xD4 0x90900000 + 0xD8 0x90900000 + 0xDC 0x90900000 + 0xE0 0x90900000 + 0xE4 0x90900000 + 0xE8 0x90900000 + 0xEC 0x90900000 + 0xF0 0x90900000 + 0xF4 ISR IMR MAC_MADR MAC_LADR MAHT0 MAHT1 TXPD RXPD TXR_BADR RXR_BADR ITC APTC DBLAC REVR FEAR MACCR MACSR PHYCR PHYWDATA FCR BPR TS DMAFIFOS TM TX_MCOL/X_SCOL RPF / AEP XM / PG RUNT_CNT/ TLCC CRCER_CNT/FTL_CN T RLC / RCC BROC MULCA RP

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Technical Reference Manual Device Name Ethernet AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES AES EBI EBI EBI EBI EBI Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture
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Address 0x90900000 + 0xF8 0x90A00000 +0x00 0x90A00000 + 0x08 0x90A00000 + 0x0C 0x90A00000 + 0x10 0x90A00000 + 0x14 0x90A00000 + 0x18 0x90A00000 + 0x1C 0x90A00000+ 0x20 0x90A00000+ 0x24 0x90A00000 + 0x28 0x90A00000 + 0x2C 0x90A00000 + 0x30 0x90A00000 + 0x34 0x90A00000 + 0x38 0x90A00000 + 0x3C 0x90A00000 + 0x48 0x90A00000 + 0x4C 0x90A00000 + 0x50 0x90A00000 + 0x54 0x90A00000 + 0x58 0x90A00000 + 0x5C 0x90A00000 + 0x60 0x90A00000 + 0x64 0x90A00000 + 0x68 0x90A00000 + 0x70 0x90A00000 + 0x74 0x90A00000 + 0x80 0x90A00000 + 0x84 0x90A00000 + 0x88 0x90A00000 + 0x8C 0x90B00000 + 0x00 0x90B00000 + 0x30 0x90B00000 + 0x40 0x90B00000 + 0x44 0x90B00000 + 0x48 0x90C00000 + 0x000 0x90C00000 + 0x004 0x90C00000 + 0x008 0x90C00000 + 0x010 0x90C00000 + 0x014 0x90C00000 + 0x018 0x90C00000 + 0x020

Name XP EncrytControl FIFOStatus PErrStatus Key0 Key1 Key2 Key3 Key4 Key5 Key6 Key7 IV0 IV1 IV2 IV3 DMASrc DMADes DMATrasSize DMACtrl FIFOThold IntrEnable IntrSrc MaskedIntrStatus IntrClr REVSION FEATURE LAST_IV0 LAST_IV1 LAST_IV2 LAST_IV3

CR Capture control register UR CCR PV_TARGET_SIZE PV_CROP_OFFSET PV_CROP_SIZE RC_TARGET_SIZE

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Description XP Counter Register Encryption/decryption control register IN/OUT FIFO status information Parity error information The 0th 32 bits of key stream The 1st 32 bits of key stream The 2nd 32 bits of key stream The 3rd 32 bits of key stream The 4th 32 bits of key stream The 5th 32 bits of key stream The 6th 32 bits of key stream The 7th 32 bits of key stream The 0th 32 bits of Initial Vector stream The 1st 32 bits of Initial Vector stream The 2nd 32 bits of Initial Vector stream The 3rd 32 bits of Initial Vector stream DMA source address DMA destination address DMA total transfer size DMA control register FIFO threshold Interrupt enable bit Interrupt source information before mask Interrupt status after mask Interrupt clear register Version register Feature register Last block IV output for next block Last block IV output for next block Last block IV output for next block Last block IV output for next block Version register Control register Grant Window Unit Min. Master Window Size (3~0) Min. Master Window Size (5~4) Capture control register Update register Clock control register PV_TARGET_SIZE register PV_CROP_OFFSET register PV_CROP_SIZE register RC_TARGET_SIZE register
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Technical Reference Manual Device Name Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Address 0x90C00000 + 0x024 0x90C00000 + 0x028 0x90C00000 + 0x030 0x90C00000 + 0x034 0x90C00000 + 0x038 0x90C00000 + 0x040 0x90C00000 + 0x044 0x90C00000 + 0x050 0x90C00000 + 0x054 0x90C00000 + 0x058 0x90C00000 + 0x060 0x90C00000 + 0x064 0x90C00000 + 0x068 0x90C00000 + 0x1d0 0x90C00000 + 0x1d4 0x90C00000 + 0x1e0 0x90C00000 + 0x1e4 0x90C00000 + 0x1ec 0x90C00000 + 0x200 0x90C00000 + 0x204 0x90C00000 + 0x208 0x90C00000 + 0x20c 0x90C00000 + 0x210 0x90C00000 + 0x218 0x90C00000 + 0x21c 0x90C00000 + 0x220 0x90C00000 + 0x224 0x90C00000 + 0x230 0x90C00000 + 0x234 0x90C00000 + 0x240 0x90C00000 + 0x244 0x90C00000 + 0x250 0x90C00000 + 0x254 0x90C00000 + 0x260 0x90C00000 + 0x008 0x90C00000 + 0x010 0x90C00000 + 0x014 0x90C00000 + 0x018 0x90C00000 + 0x020 0x90C00000 + 0x024 0x90C00000 + 0x028 0x90C00000 + 0x030 0x90C00000 + 0x034 0x90C00000 + 0x038 0x90C00000 + 0x040 0x90C00000 + 0x044 Name RC_CROP_OFFSET RC_CROP_SIZE BORDER_SIZE BORDER_COLOR DEST_FORMAT FM_RATE IF_FORMAT SRC_SIZE PV_SWC_OFFSET PV_SWC_SIZE SRC_OFFSET RC_SWC_OFFSET RC_SWC SIZE DI_ELA_TH DI_H_BLANK DN_MODE DN_TH DN_H_BLANK PDMA_MODE RDMA_MODE MEM_SRC_FORMAT MEM_SRC_ST MEM_SRC_SIZE PV_SUB_WIN_PIT RC_SUB_WIN_PIT PMEM_YST0 PMEM_YST1 PMEM_CBST0 PMEM_CBST1 PMEM_CRST0 PMEM_CRST1 RMEM_YST0 RMEM_YST1 RMEM_CBST0 CCR PV_TARGET_SIZE PV_CROP_OFFSET PV_CROP_SIZE RC_TARGET_SIZE RC_CROP_OFFSET RC_CROP_SIZE BORDER_SIZE BORDER_COLOR DEST_FORMAT FM_RATE IF_FORMAT Description RC_CROP_OFFSET register RC_CROP_SIZE register BORDER_SIZE register BORDER_COLOR register DEST_FORMAT register FM_RATE register IF_FORMAT register SRC_SIZE register PV_SWC_OFFSET register PV_SWC_SIZE register SRC_OFFSET register RC_SWC_OFFSET register RC_SWC SIZE register DI_ELA_TH register DI_H_BLANK register DN_MODE register DN_TH register DN_H_BLANK register PDMA_MODE register RDMA_MODE register MEM_SRC_FORMAT register MEM_SRC_ST register MEM_SRC_SIZE register PV_SUB_WIN_PIT register RC_SUB_WIN_PIT register PMEM_YST0 register PMEM_YST1 register PMEM_CBST0 register PMEM_CBST1 register PMEM_CRST0 register PMEM_CRST1 register RMEM_YST0 register RMEM_YST1 register RMEM_CBST0 register Clock control register PV_TARGET_SIZE register PV_CROP_OFFSET register PV_CROP_SIZE register RC_TARGET_SIZE register RC_CROP_OFFSET register RC_CROP_SIZE register BORDER_SIZE register BORDER_COLOR register DEST_FORMAT register FM_RATE register IF_FORMAT register

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Technical Reference Manual Device Name Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Address 0x90C00000 + 0x050 0x90C00000 + 0x054 0x90C00000 + 0x058 0x90C00000 + 0x060 0x90C00000 + 0x064 0x90C00000 + 0x068 0x90C00000 + 0x1d0 0x90C00000 + 0x1d4 0x90C00000 + 0x1e0 0x90C00000 + 0x1e4 0x90C00000 + 0x1ec 0x90C00000 + 0x200 0x90C00000 + 0x204 0x90C00000 + 0x208 0x90C00000 + 0x20c 0x90C00000 + 0x210 0x90C00000 + 0x218 0x90C00000 + 0x21c 0x90C00000 + 0x220 0x90C00000 + 0x224 0x90C00000 + 0x230 0x90C00000 + 0x234 0x90C00000 + 0x240 0x90C00000 + 0x244 0x90C00000 + 0x250 0x90C00000 + 0x254 0x90C00000 + 0x260 0x90C00000 + 0x030 0x90C00000 + 0x034 0x90C00000 + 0x038 0x90C00000 + 0x040 0x90C00000 + 0x044 0x90C00000 + 0x050 0x90C00000 + 0x054 0x90C00000 + 0x058 0x90C00000 + 0x060 0x90C00000 + 0x064 0x90C00000 + 0x068 0x90C00000 + 0x1d0 0x90C00000 + 0x1d4 0x90C00000 + 0x1e0 0x90C00000 + 0x1e4 0x90C00000 + 0x1ec 0x90C00000 + 0x200 0x90C00000 + 0x204 0x90C00000 + 0x208 Name SRC_SIZE PV_SWC_OFFSET PV_SWC_SIZE SRC_OFFSET RC_SWC_OFFSET RC_SWC SIZE DI_ELA_TH DI_H_BLANK DN_MODE DN_TH DN_H_BLANK PDMA_MODE RDMA_MODE MEM_SRC_FORMAT MEM_SRC_ST MEM_SRC_SIZE PV_SUB_WIN_PIT RC_SUB_WIN_PIT PMEM_YST0 PMEM_YST1 PMEM_CBST0 PMEM_CBST1 PMEM_CRST0 PMEM_CRST1 RMEM_YST0 RMEM_YST1 RMEM_CBST0 BORDER_SIZE BORDER_COLOR DEST_FORMAT FM_RATE IF_FORMAT SRC_SIZE PV_SWC_OFFSET PV_SWC_SIZE SRC_OFFSET RC_SWC_OFFSET RC_SWC SIZE DI_ELA_TH DI_H_BLANK DN_MODE DN_TH DN_H_BLANK PDMA_MODE RDMA_MODE MEM_SRC_FORMAT Description SRC_SIZE register PV_SWC_OFFSET register PV_SWC_SIZE register SRC_OFFSET register RC_SWC_OFFSET register RC_SWC SIZE register DI_ELA_TH register DI_H_BLANK register DN_MODE register DN_TH register DN_H_BLANK register PDMA_MODE register RDMA_MODE register MEM_SRC_FORMAT register MEM_SRC_ST register MEM_SRC_SIZE register PV_SUB_WIN_PIT register RC_SUB_WIN_PIT register PMEM_YST0 register PMEM_YST1 register PMEM_CBST0 register PMEM_CBST1 register PMEM_CRST0 register PMEM_CRST1 register RMEM_YST0 register RMEM_YST1 register RMEM_CBST0 register BORDER_SIZE register BORDER_COLOR register DEST_FORMAT register FM_RATE register IF_FORMAT register SRC_SIZE register PV_SWC_OFFSET register PV_SWC_SIZE register SRC_OFFSET register RC_SWC_OFFSET register RC_SWC SIZE register DI_ELA_TH register DI_H_BLANK register DN_MODE register DN_TH register DN_H_BLANK register PDMA_MODE register RDMA_MODE register MEM_SRC_FORMAT register

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Technical Reference Manual Device Name Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture
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Address 0x90C00000 + 0x20c 0x90C00000 + 0x210 0x90C00000 + 0x218 0x90C00000 + 0x21c 0x90C00000 + 0x220 0x90C00000 + 0x224 0x90C00000 + 0x230 0x90C00000 + 0x234 0x90C00000 + 0x240 0x90C00000 + 0x244 0x90C00000 + 0x250 0x90C00000 + 0x254 0x90C00000 + 0x260 0x90C00000 + 0x264 0x90C00000 + 0x270 0x90C00000 + 0x274 0x90C00000 + 0x290 0x90C00000 + 0x294 0x90C00000 + 0x2a0 0x90C00000 + 0x2b0 0x90C00000 + 0x300 0x90C00000 + 0x304 0x90C00000 + 0x308 0x90C00000 + 0x30c 0x90C00000 + 0x310 0x90C00000 + 0x314 0x90C00000 + 0x318 0x90C00000 + 0x31c 0x90C00000 + 0x320 0x90C00000 + 0x324 0x90C00000 + 0x328 0x90C00000 + 0x330 0x90C00000 + 0x334 0x90C00000 + 0x338 0x90C00000 + 0x33c 0x90C00000 + 0x340 0x90C00000 + 0x344 0x90C00000 + 0x348 0x90C00000 + 0x34c 0x90C00000 + 0x350 0x90C00000 + 0x354 0x90C00000 + 0x358

Name MEM_SRC_ST MEM_SRC_SIZE PV_SUB_WIN_PIT RC_SUB_WIN_PIT PMEM_YST0 PMEM_YST1 PMEM_CBST0 PMEM_CBST1 PMEM_CRST0 PMEM_CRST1 RMEM_YST0 RMEM_YST1 RMEM_CBST0 RMEM_CBST1 RMEM_CRST0 RMEM_CRST1 RMEM_VBI_ST0 RMEM_VBI_ST1 VBI_OFFSET VBI_SIZE FONT_RAM_DOOR DISP_RAM_DOOR FONT_RAM_STATUS FONT_WIN_EN OSD_PALT_COLOR0 OSD_PALT_COLOR1 SD_PALT_COLOR2 OSD_PALT_COLOR3 OSD_PALT_COLOR4 OSD_PALT_COLOR5 OSD_PALT_COLOR6 OSD_WIN0_COLOR OSD_WIN0_SIZE

Description MEM_SRC_ST register MEM_SRC_SIZE register PV_SUB_WIN_PIT register RC_SUB_WIN_PIT register PMEM_YST0 register PMEM_YST1 register PMEM_CBST0 register PMEM_CBST1 register PMEM_CRST0 register PMEM_CRST1 register RMEM_YST0 register RMEM_YST1 register RMEM_CBST0 register RMEM_CBST1 register RMEM_CRST0 register RMEM_CRST1 register RMEM_VBI_ST0 register RMEM_VBI_ST1 register VBI_OFFSET register VBI_SIZE register FONT_RAM_DOOR register DISP_RAM_DOOR register FONT_RAM_STATUS register FONT_WIN_EN register OSD palette color 0 register OSD palette color 1 register OSD palette color 2 register OSD palette color 3 register OSD palette color 4 register OSD palette color 5 register OSD palette color 6 register OSD window 0 color setting register OSD window 0 width/height setting register OSD_WIN0_OFFSET OSD window 0 offset register OSD_WIN0_FONT_SPE OSD window 0 font setting register C OSD_WIN1_COLOR OSD window 1 color setting register OSD_WIN1_SIZE OSD window 1 width/height setting register OSD_WIN1_OFFSET OSD window 1 offset register OSD_WIN1_FONT_SPE OSD window 1 font setting register C OSD_WIN2_COLOR OSD window 2 color setting register OSD_WIN2_SIZE OSD window 2 width/height setting register OSD_WIN2_OFFSET OSD window 2 offset register
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Technical Reference Manual Device Name Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture Video Capture JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II
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Address Name 0x90C00000 + 0x35c OSD_WIN2_FONT_SPE C 0x90C00000 + 0x360 0x90C00000 + 0x364 OSD_WIN3_SIZE 0x90C00000 + 0x368 0x90C00000 + 0x36c 0x90C00000 + 0x3e0 0x90C00000 + 0x3e4 0x90C00000 + 0x3f0 0x90C00000 + 0x3f4 0x98000000 + 0x0020 0x98000000 + 0x0024 0x98000000 + 0x0028 0x98000000 + 0x002C 0x98000000 + 0x0030 0x98C00000 + 0x0034 0x9070000 + 0x0038 0x98C00000 + 0x003C 0x9800000 + 0x0040 0x9800000 + 0x0044 0x980000000 + 0x0080 0x980000000 + 0x0084 0x980000000 + 0x0088 0x980000000 + 0x008C 0x980000000 + 0x0090 0x980000000 + 0x0094 0x980000000 + 0x0098 0x980000000 +

Description OSD window 2 font setting register

OSD window 3 color setting register OSD window 3 width/height setting register OSD_WIN3_OFFSET OSD window 3 offset register OSD_WIN3_FONT_SPE OSD window 3 font setting register C CAP_STATUS Video capture status register INT_MASK Interrupt mask register TEST_MODE0 Video capture test mode 0 register TEST_MODE1 Video capture test mode 1 register PRT_RL0 Piano roll timer 0 reload CT_RL0 TMR_EN0 PRT0 CT0 PRT-RL1 CT_RL1 TMR_EN1 PRT1 CT1 PDLLCR0 PDLLCR1 PDLLCR2 DLLCR AHBMCLKOFF APBMCLKOFF CCR MFPSR0
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Clock timer 0 reload JVM 0 piano roll and clock timer enable Piano roll timer 0 Clock timer 0 Piano roll timer 1 reload Clock timer 1 reload JVM 1 piano roll and clock timer enable Piano roll timer 1 Clock timer 1 PLL1 Control Register 0 PLL2 Control Register 1 PLL3 Control Register 1 DLL Control Register AHB Module Clock Off Control Register APB Module Clock Off Control Register Clock control register Multi-Function Port Setting Register
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Technical Reference Manual Device Name JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II Address 0x009C 0x980000000 + 0x00A0 0x980000000 + 0x00A4 0x980000000 + 0x00A8 0x980000000 + 0x00AC 0x98000000 + 0x0100 0x98000000 + 0x0104 0x98000000 + 0x0108 0x98000000 + 0x010C 0x98000000 + 0x0110 0x98000000 + 0x0114 0x98000000 + 0x0118 0x98000000 + 0x011C 0x980000000 + 0x0200 0x980000000 + 0x0204 0x980000000 + 0x0208 0x980000000 + 0x020C 0x980000000 + 0x0210 0x980000000 + 0x0214 0x980000000 + 0x0218 0x980000000 + 0x021C 0x980000000 + 0x0220 0x980000000 + 0x0224 0x980000000 + 0x0228 Name MFPSR1 DCSRCR0 DCSRCR1 DCSRCR2 JVM ABO ABO_RLR PSCL_RLR JSI_ALARM TMODE JSI GPIOT_ILTR UART_ILTR SSP_ILTR I2S_ILTR I2C_ILTR CFC_ILTR SDC_ILTR RTC_ILTR TIMER_ILTR WDT_ILTR LCD_ILTR Description Multi-Function Port Setting Register Driving Capability and Slew Rate Control Register0 Driving Capability and Slew Rate Control Register1 Driving Capability and Slew Rate Control Register2 JVM register Reserved Abort timer Abort timer reload Prescaler reload JSI alarm timer reload Timer mode JSI Timer GPIO Interrupt level translation UART Interrupt level translation SSP Interrupt level translation I2S Interrupt level translation I2C Interrupt level translation CFC Interrupt level translation SDC Interrupt level translation RTC Interrupt level translation TIMER Interrupt level translation WDT Interrupt level translation LCD Interrupt level translation

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Technical Reference Manual Device Name JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II JEMCore-II Address 0x980000000 + 0x022C 0x980000000 + 0x0230 0x980000000 + 0x0234 0x980000000 + 0x0238 0x980000000 + 0x023C 0x980000000 + 0x0240 0x980000000 + 0x0244 0x980000000 + 0x0248 0x980000000 + 0x024C 0x98100000 + 0x00 Name DMA_ILTR ETH_ILTR USB_ILTR MEDIA_ILTR VIDEO_ILTR ISR PIR GPIOT_ILTR UART_ILTR RBR THR DLL IER DLM IIR FCR PSR LCR MCR LSR TST MSR SPR RBR THR DLL IER DLM IIR FCR PSR Description DMA Interrupt level translation ETH Interrupt level translation USB Interrupt level translation MEDIA Interrupt level translation VIDEO Interrupt level translation Interrupt Slip register Pending Interrupt register GPIO Interrupt level translation UART Interrupt level translation Receiver Buffer Register (read) Transmitter Holding Register (Write) Baud Rate Divisor Latch Least Significant Byte (DLAB =1) Interrupt Enable Register Baud Rate Divisor Latch Most Significant Byte (DLAB = 1) Interrupt Identification Register FIFO Control Register Pre-scale Register (DLAB = 1) Line Control Register Modem Control Register Line Status Register Testing Register Modem Status Register Scratch Pad Register Receiver Buffer Register (read) Transmitter Holding Register (Write) Baud Rate Divisor Latch Least Significant Byte (DLAB =1) Interrupt Enable Register Baud Rate Divisor Latch Most Significant Byte (DLAB = 1) Interrupt Identification Register FIFO Control Register Pre-scale Register (DLAB = 1)

UART3

UART3 UART3

0x98100000 + 0x04 0x98100000 + 0x08

UART3 UART3 UART3 UART3 UART3 UART1

0x98100000 + 0x0C 0x98100000 + 0x10 0x98100000 + 0x14 0x98100000 + 0x18 0x98100000 + 0x1C 0x98200000 + 0x00

UART1 UART1

0x98200000 + 0x04 0x98200000 + 0x08

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Technical Reference Manual Device Name UART1 UART1 UART1 UART1 UART1 UART1 Address 0x98200000 + 0x0C 0x98200000 + 0x10 0x98200000 + 0x14 0x98200000 + 0x18 0x98200000 + 0x1C 0x98200000 + 0x0C Name LCR MCR LSR TST MSR SPR RBR THR DLL RBR THR DLL IER DLM IIR FCR PSR LCR MCR LSR TST MSR SPR Tm1Counter Tm1Load Tm1Match1 Tm1Match2 Tm2Counter Tm2Load Tm2Match1 Tm2Match2 Tm3Counter Tm3Load Tm3Match1 Tm3Match2 TmCR IntrState IntrMask WdCounter WdLoad WdRestart Description Line Control Register Modem Control Register Line Status Register Testing Register Modem Status Register Scratch Pad Register Receiver Buffer Register (read) Transmitter Holding Register (Write) Baud Rate Divisor Latch Least Significant Byte (DLAB =1) Receiver Buffer Register (read) Transmitter Holding Register (Write) Baud Rate Divisor Latch Least Significant Byte (DLAB =1) Interrupt Enable Register Baud Rate Divisor Latch Most Significant Byte (DLAB = 1) Interrupt Identification Register FIFO Control Register Pre-scale Register (DLAB = 1) Line Control Register Modem Control Register Line Status Register Testing Register Modem Status Register Scratch Pad Register Timer1 Counter Timer1 Auto Reload Value Timer1 Match Value Timer1 Match Value Timer2 Counter Timer2 Auto Reload Value Timer2 Match Value Timer2 Match Value Timer3 Counter Timer3 Auto Reload Value Timer3 Match Value Timer3 Match Value Timer1, Timer2, Timger3 Control Register Interrupt State of TMR Interrupt Mask of TMR Watch Dog Timer Counter Register Watch Dog Timer Counter Auto Reload Register Watch Dog Timer Counter Restart Register
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UART2 UART2

0x98300000 + 0x00

0x98300000 + 0x04 UART2 0x98300000 + 0x08 UART2 UART2 UART2 UART2 UART2 TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER TIMER WDT WDT WDT 0x98300000 + 0x0C 0x98300000 + 0x10 0x98300000 + 0x14 0x98300000 + 0x18 0x98300000 + 0x1C 0x98400000 + 0x00 0x98400000 + 0x04 0x98400000 + 0x08 0x98400000 + 0x0C 0x98400000 + 0x10 0x98400000 + 0x14 0x98400000 + 0x18 0x98400000 + 0x1C 0x98400000 + 0x20 0x98400000 + 0x24 0x98400000 + 0x28 0x98400000 + 0x2C 0x98400000 + 0x30 0x98400000 + 0x34 0x98400000 + 0x38 0x98500000 + 0x00 0x98500000 + 0x04 0x98500000 + 0x08

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Technical Reference Manual Device Name WDT WDT WDT WDT RTC RTC RTC RTC RTC RTC RTC RTC RTC GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA 0x98700000 + 0x40 GPIOA INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC
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Address 0x98500000 + 0x0C 0x98500000 + 0x10 0x98500000 + 0x14 0x98500000 + 0x18 0x98600000 + 0x00 0x98600000 + 0x04 0x98600000 + 0x08 0x98600000 + 0x0C 0x98600000 + 0x10 0x98600000 + 0x14 0x98600000 + 0x18 0x98600000 + 0x1C 0x98600000 + 0x20 0x98700000 + 0x00 0x98700000 + 0x04 0x98700000 + 0x08 0x98700000 + 0x10 0x98700000 + 0x14 0x98700000 + 0x18 0x98700000 + 0x1C 0x98700000 + 0x20 0x98700000 + 0x24 0x98700000 + 0x28 0x98700000 + 0x2C 0x98700000 + 0x30 0x98700000 + 0x34 0x98700000 + 0x38 0x98700000 + 0x3C

Name WdCR WdStatus WdClear WdIntrCter RtcSecond RtcMinute RtcHour RtcDays AlarmSecond AlarmMinute AlarmHour RtcRecord RtcCR GpioDataOut GpioDataIn PinDir GpioDataSet GpioDataClear PinPullEnable PinPullType IntrEnable IntrRawState IntrMaskedState IntrMask IntrClear IntrTrigger IntrBoth IntrRiseNeg BounceEnable BouncePreScale IRQMR IRQICR IRQTMR IRQTLR IRQSR FIQSR FIQMR FIQICR FIQTMR FIQTLR
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0x98700000 + 0x44 0x98800000 + 0x04 0x98800000 + 0x08 0x98800000 + 0x0C 0x98800000 + 0x10 0x98800000 + 0x14 0x98800000 + 0x20 0x98800000 + 0x24 0x98800000 + 0x28 0x98800000 + 0x2C 0x98800000 + 0x30

Description Watch Dog Timer Control Register Watch Dog Timer Status Watch Dog Timer Clear Watch Dog Timer Interrupt Length RTC Second Register RTC Minute Register RTC Hour Register RTC Day Count Register RTC Second Alarm Register RTC Minute Alarm Register RTC Hour Alarm Register RTC Record Register RTC Control Register GPIOA Data Output Register GPIOA Data Input Register GPIOA Direction Register GPIOA Data Bit Set Register GPIOA Data Bit Clear Register GPIOA Pull Up Register GPIOA Pull High Pull Low Register GPIOA Interrupt Enable Register GPIOA Interrupt Raw Status Register GPIOA Interrupt Masked Status Register GPIOA Interrupt Mask Register GPIOA Interrupt Clear GPIOA Interrupt Trigger Method Register GPIOA Interrupt Edge Trigger By Both GPIOA Interrupt Trigger by Rising or Falling Edge GPIOA Pre-scale Clock Enable. When enabled, PCLK will be divided by BouncePreScale clock. GPIOA Pre-scale, which is used to adjust different PCLK frequencies. IRQ Mask Register IRQ Interrupt Clear Register IRQ Trigger Mode Register IRQ Trigger Level Register IRQ Status Register FIQ Source Register FIQ Mask Register FIQ Interrupt Clear Register FIQ Trigger Mode Register FIQ Trigger Level Register
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Technical Reference Manual Device Name INTC INTC INTC INTC INTC Address 0x98800000 + 0x34 0x98800000 + 0x50 0x98800000 + 0x54 0x98800000 + 0x58 0x98800000 + 0x5C Name FIQSR RRVISION FRIN FRIDL FRFDL RBR THR DLL IER DLM IIR FCR PSR LCR MCR LSR TST MSR SPR MDR ACR TXLENL TXLENH MRXLENL MRXLENH PLR FMIIR_PIO/ FMIIR_DMA FMIIER_PIO/ FMIIER_DMA STFF _STS STFF_RXLENL STFF_RXLENH FMLSR FMLSIER Description FIQ Status Register Revision Register Feature Register for Input Number Feature Register for IRQ De-bounce Location Feature Register for FIQ De-bounce Location Receiver Buffer Register (read) Transmitter Holding Register (Write) Baud Rate Divisor Latch Least Significant Byte (DLAB =1) Interrupt Enable Register Baud Rate Divisor Latch Most Significant Byte (DLAB = 1) Interrupt Identification Register FIFO Control Register Pre-scale Register (DLAB = 1) Line Control Register Modem Control Register Line Status Register Testing Register Modem Status Register Scratch Pad Register Mode Definition Register Auxiliary Control Register Transmitter Frame Length Low Transmitter Frame Length High Maximum Receiver Frame Length Low Maximum Receiver Frame Length High FIR Preamble Length Register FIR Mode Interrupt Identification Register in PIO Mode / FIR Mode Interrupt Identification Register in DMA Mode FIR Mode Interrupt Enable Register for PIO Mode / FIR Mode Interrupt Enable Register for DMA Mode Status FIFO Line Status Register Status FIFO Received Frame Length Register Low Status FIFO Received Frame Length Register Low FIR Mode Link Status Register FIR Mode Link Status Interrupt Enable Register
Version 2.1

IrDA/UART4 IrDA/UART4

0x98900000 + 0x00

0x98900000 + 0x04 IrDA/UART4 0x98900000 + 0x08 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 0x98900000 + 0x0C 0x98900000 + 0x10 0x98900000 + 0x14 0x98900000 + 0x18 0x98900000 + 0x1C 0x98900000 + 0x20 0x98900000 + 0x24 0x98900000 + 0x28 0x98900000 + 0x2C 0x98900000 + 0x30 0x98900000 + 0x34 0x98900000 + 0x38 0x98900000 + 0x3C IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 0x98900000 + 0x40 0x98900000 + 0x44 0x98900000 + 0x48 0x98900000 + 0x4C 0x98900000 + 0x50 0x98900000 + 0x54

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Technical Reference Manual Device Name IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 Address 0x98900000 + 0x58 0x98900000 + 0x5C 0x98900000 + 0x60 0x98900000 + 0x64 0x98900000 + 0x00 0x98900000 + 0x00 0x98900000 + 0x00 0x98900000 + 0x04 0x98900000 + 0x04 0x98900000 + 0x08 0x98900000 + 0x08 0x98900000 + 0x08 0x98900000 + 0x0C 0x98900000 + 0x14 0x98900000 + 0x1C 0x98900000 + 0x20 0x98900000 + 0x24 0x98900000 + 0x28 0x98900000 + 0x2C 0x98900000 + 0x30 0x98900000 + 0x34 0x98900000 + 0x38 0x98900000 + 0x3C IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 IrDA/UART4 I2C I2C I2C
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Name RSR RXFF_CNTR LSTFMLENL LSTFMLENH RBR THR DLL IER DLM IIR PSR FCR LCR LSR SPR MDR ACR TXLENL TXLENH MRXLENL MRXLENH PLR FMIIR_PIO/ FMIIR_DMA FMIIER_PIO/ FMIIER_DMA STFF _STS STFF_RXLENL STFF_RXLENH FMLSR FMLSIER RSR RXFF_CNTR LSTFMLENL LSTFMLENH CR SR CDR
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0x98900000 + 0x40 0x98900000 + 0x44 0x98900000 + 0x48 0x98900000 + 0x4C 0x98900000 + 0x50 0x98900000 + 0x54 0x98900000 + 0x58 0x98900000 + 0x5C 0x98900000 + 0x60 0x98900000 + 0x64 0x98A00000 + 0x00 0x98A00000 + 0x04 0x98A00000 + 0x08

Description Resume Register Rx FIFO Count Register Last Frame Length Register Low Last Frame Length Register High Receiver Buffer Register Transmitter Holding Register Baud Rate Divisor Latch Least Significant Byte (DLAB =1) Interrupt Enable Register Baud Rate Divisor Latch Most Significant Byte (DLAB=1) Interrupt Identification Register Prescaler Register (DLAB = 1) FIFO Control Register Line Control Register Line Status Register Scratch Pad Register Mode Definition Register Auxiliary Control Register Transmitter Frame Length Low Transmitter Frame Length High Maximum Receiver Frame Length Low Maximum Receiver Frame Length High FIR Preamble Length Register FIR Mode Interrupt Identification Register in PIO Mode / FIR Mode Interrupt Identification Register in DMA Mode FIR Mode Interrupt Enable Register for PIO Mode / FIR Mode Interrupt Enable Register for DMA Mode Status FIFO Line Status Register Status FIFO Received Frame Length Register Low Status FIFO Received Frame Length Register Low FIR Mode Link Status Register FIR Mode Link Status Interrupt Enable Register Resume Register Rx FIFO Count Register Last Frame Length Register Low Last Frame Length Register High I2C Control Register I2C Status Register I2C Clock Divided Register
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Technical Reference Manual Device Name I2C I2C I2C I2C SSP SSP SSP SSP SSP SSP SSP SSP Reserved CFC CFC CFC CFC CFC CFC CFC CFC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC SDC
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Address 0x98A00000 + 0x0C 0x98A00000 + 0x10 0x98A00000 + 0x14 0x98A00000 + 0x18 0x98B00000 + 0x00 0x98B00000 + 0x04 0x98B00000 + 0x08 0x98B00000 + 0x0C 0x98B00000 + 0x10 0x98B00000 + 0x14 0x98B00000 + 0x18 0x98B00000 + 0x20 0x98C00000 0x98D00000 + 0x04 0x98D00000 + 0x04 0x98D00000 + 0x08 0x98D00000 + 0x0C 0x98D00000 + 0x10 0x98D00000 + 0x14 0x98D00000 + 0x18 0x98D00000 + 0x1C 0x98E00000 + 0x00 0x98E00000 + 0x04 0x98E00000 + 0x08 0x98E00000 + 0x0C 0x98E00000 + 0x10 0x98E00000 + 0x14 0x98E00000 + 0x18 0x98E00000 + 0x1C 0x98E00000 + 0x20 0x98E00000 + 0x24 0x98E00000 + 0x28 0x98E00000 + 0x2C 0x98E00000 + 0x30 0x98E00000 + 0x34 0x98E00000 + 0x38 0x98E00000 + 0x3C 0x98E00000 + 0x40 0x98E00000 + 0x44 0x98E00000 + 0x48 0x98E00000 + 0x6C 0x98E00000 + 0x70 0x98E00000 + 0x74 0x98E00000 + 0x9C 0x98E00000 + 0xA0

Name DR SAR TGSR BMR SSPCR0 SSPCR1 SSPCR2 SSPSR SSPICR SSPISR SSPDR SSPVR CFSR CFCR CFATCR CFABCR CFABDR CFMSR TSMER TSMCR SDCR SDAR SDRR0 SDRR1 SDRR2 SDRR3 SDRCR SDDCR SDDTR SDDLR SDSR SDCLR SDIMR SDPCR SDCCR SDBWR SDDWR MMCIRT GPO SDIOCR1 SDIOCR2 SDIOSR SDCF SDCR
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Description I2C Data Register I2C Slave Address Register I2C Setup / Hold Time & Glitch Suppression Setting Register I2C Bus Monitor Register SSP Control Register 0 SSP Control Register 1 SSP Control Register 2 SSP Status Register SSP Interrupt Control Register SSP Interrupt Status Register SSP Data Register AC-link Slot Valid Register CF Host Status Register CF Host Control Register Access Timing Configuration Register Active Buffer Controller Register Active Buffer Data Register Multi Sector Register Transfer Size Mode2 Enable Register Transfer Size Mode2 Counter Register Command Register Argument Register Response Register0 Response Register1 Response Register2 Response Register3 Responded Command Register Data Control Register Data Timer Register Data Length Register Status Register Clear Register Interrupt Mask Register Power Control Register Clock Control Register Bus Width Register Data Window Register MMC interrupt repsone time General Purpose Output SDIO Control Register 1 SDIO Control Register 2 SDIO Status Register SDIO Feature Register SDC Revision Register
Version 2.1

Technical Reference Manual Device Name GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB 0x98F00000 + 0x40 GPIOB GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC 0x98F00000 + 0x44 0x99000000 + 0x00 0x99000000 + 0x04 0x99000000 + 0x08 0x99000000 + 0x10 0x99000000 + 0x14 0x99000000 + 0x18 0x99000000 + 0x1C 0x99000000 + 0x20 0x99000000 + 0x24 0x99000000 + 0x28 0x99000000 + 0x2C 0x99000000 + 0x30 0x99000000 + 0x34 0x99000000 + 0x38 0x99000000 + 0x3C 0x99000000 + 0x40 0x99000000 + 0x44 Address 0x98F00000 + 0x00 0x98F00000 + 0x04 0x98F00000 + 0x08 0x98F00000 + 0x10 0x98F00000 + 0x14 0x98F00000 + 0x18 0x98F00000 + 0x1C 0x98F00000 + 0x20 0x98F00000 + 0x24 0x98F00000 + 0x28 0x98F00000 + 0x2C 0x98F00000 + 0x30 0x98F00000 + 0x34 0x98F00000 + 0x38 0x98F00000 + 0x3C Description GPIOB Data Output Register GPIOB Data Input Register GPIOB Direction Register GPIOB Data Bit Set Register GPIOB Data Bit Clear Register GPIOB Pull Up Register GPIOB Pull High Pull Low Register GPIOB Interrupt Enable Register GPIOB Interrupt Raw Status Register GPIOB Interrupt Masked Status IntrMaskedState Register IntrMask GPIOB Interrupt Mask Register IntrClear GPIO Interrupt Clear GPIOB Interrupt Trigger Method IntrTrigger Register IntrBoth GPIOB Interrupt Edge Trigger By Both GPIOB Interrupt Trigger by Rising or IntrRiseNeg Falling Edge GPIOB Pre-scale Clock Enable. When BounceEnable enabled, PCLK will be divided by BouncePreScale clock. GPIOB Pre-scale, which is used to BouncePreScale adjust different PCLK frequencies. GpioDataOut GPIOC Data Output Register GpioDataIn GPIOC Data Input Register PinDir GPIOC Direction Register GpioDataSet GPIOC Data Bit Set Register GpioDataClear GPIOC Data Bit Clear Register PinPullEnable GPIOC Pull Up Register PinPullType GPIOC Pull High Pull Low Register IntrEnable GPIOC Interrupt Enable Register IntrRawState GPIOC Interrupt Raw Status Register GPIOC Interrupt Masked Status IntrMaskedState Register IntrMask GPIOC Interrupt Mask Register IntrClear GPIOC Interrupt Clear GPIOC Interrupt Trigger Method IntrTrigger Register IntrBoth GPIOC Interrupt Edge Trigger By Both GPIOC Interrupt Trigger by Rising or IntrRiseNeg Falling Edge GPIOC Pre-scale Clock Enable. When Master enable and clear enabled, PCLK will be divided by register BouncePreScale clock. GPIOC Pre-scale, which is used to BouncePreScale adjust different PCLK frequencies. Name GpioDataOut GpioDataIn PinDir GpioDataSet GpioDataClear PinPullEnable PinPullType IntrEnable IntrRawState

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Technical Reference Manual Device Name PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM PWM I2S/AC97/SSP I2S/AC97/SSP I2S/AC97/SSP I2S/AC97/SSP I2S/AC97/SSP I2S/AC97/SSP I2S/AC97/SSP I2S/AC97/SSP Address 0x99100000 + 0x00 0x99100000 + 0x04 0x99100000 + 0x08 0x99100000 + 0x0C 0x99100000 + 0x10 0x99100000 + 0x20 0x99100000 + 0x24 0x99100000 + 0x28 0x99100000 + 0x2C 0x99100000 + 0x30 0x99100000 + 0x34 0x99100000 + 0x38 0x99100000 + 0x3C 0x99100000 + 0x40 0x99100000 + 0x44 0x99100000 + 0x48 0x99100000 + 0x4C 0x99400000 + 0x00 0x99400000 + 0x04 0x99400000 + 0x08 0x99400000 + 0x0C 0x99400000 + 0x10 0x99400000 + 0x14 0x99400000 + 0x18 0x99400000 + 0x20 Name MOM PWM0WC PWM0ECA PWM0ECB PWM0CC PWM1WC PWM1ECA PWM1ECB PWM1CC PWM2WC PWM2ECA PWM2ECB PWM2CC PWM3WC PWM3ECA PWM3ECB PWM3CC SSPCR0 SSPCR1 SSPCR2 SSPSR SSPICR SSPISR SSPDR SSPVR Description Master ouput mode register (MOM) PWM0 waveform control register PWM0 edge count register A PWM0 edge count register B PWM0 current counter register PWM1 waveform control register PWM1 edge count register A PWM1 edge count register B PWM1 current counter register PWM2 waveform control register PWM2 edge count register A PWM2 edge count register B PWM2 current counter register PWM3 waveform control register PWM3 edge count register A PWM3 edge count register B PWM3 current counter register SSP Control Register 0 SSP Control Register 1 SSP Control Register 2 SSP Status Register SSP Interrupt Control Register SSP Interrupt Status Register SSP Data Register AC-link Slot Valid Register

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5. System Configuration
The aJ-200 can be configured to adapt to a wide variety of embedded applications and consumer devices. Clock sources Phase Locked Loops (PLLs) Shared I/O pins Operation modes

These features are controlled with internal memory mapped registers that are initialized as the part of the JEMCore s initialization sequence. The application builder tool (JEM Builder) provides an intuitive configuration window to allow users to configure the desired features. A screen shot of the configuration window is shown in the below figure

Figure 5-1. 5.1. Clock Sources

JEMBuilder System Configuration Screen

The aJ-200s clocking system consists of five major clock sources: XIN crystal OSCLIN crystal Programmable Frequency Core PLL (PLL1) up to 160 MHz Programmable Frequency Core PLL (PLL2) up to 160 MHz Programmable Frequency Core PLL (PLL3) up to 160 MHz

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Technical Reference Manual Dedicated PLL for 10/100 Ethernet PHY Dedicated PLL for USB OTG PHY
XIN Crystal Oscillator I/O Cells XIN Crystal XOUT

PLL1

CPUCLK Gated Clock

Java CPU JEMCore-II AHB-based Devices

SDR_CLK

PLL1CRO REG LOCK TIMER

/2

Gated Clock

DLLIN_OUT

DLL
CLKO Divider

Gated Clock

HCLK

LOCK TIMER
/4 IrDASEL /6
0 1 Gated Clock

HCLK

Gated Clock

CLKO
PCLK

PLL1CR1 REG

APB-based Devices
IrDA Clock (47.923 MHz)

PLL2

Gated Clock

UARTSEL
Gated Clock

PLL3

/8 SSPCLKSEL /96
Gated Clock

UART Clock (18.432 Mhz)

PLL1CR2 REG

/6 /4

SSPCLK_SPI

LOCK TIMER
/2 I2SCLKSEL
Gated Clock

SSPCLK_I2SAC97 SPI

/3 1/12 OSCLIN Crystal OSCLIN Crystal Oscillator I/O Cells OSCLOUT 12 MHz XSCI Crystal Oscillator I/O Cells XSCO 25 MHz XTLN Crystal Osciallator I/O Cells XTLP /16

Gated Clock

I2S_AC97CLK

I2S_AC97CLKSEL

WDT Clock RTC Clock

PLL USB PHY

USB OTG PHY

PLL 10/100 Ethenet PHY

10/100 Ethernet PHY

Figure 5-2.

Clock Generation and Distribution

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Technical Reference Manual 5.1.1. XIN Oscillator The aJ-200 provides crystal oscillator I/O pins, which are used to connect with an external high frequency crystal in the range of 1Mhz ~12 MHz. A 3.6864 MHz crystal is normally used as reference clock. The onchip PLLs use the 3.6864 MHz oscillator as a reference clock. The figure below illustrates the typical connection with an external crystal of 32.768 KHz and all required passive components. The values of the external passive components are suggested as follows: Rfb = 1M C1, C2 = 12pF ~ 27pF
C1
XIN

3.6864 MHz Crystal

Rfb
XOUT

Crystal Oscillator I/O Cells

C2

Figure 5-3. 5.1.2. OSCLIN Oscillator

High Frequency Crystal

The aJ-200 provides crystal oscillator I/O pins, which are used to connect with an external low crystal in the range of 32 KHz~ 1MHz. A 32.768 KHZ is used to provide the clock for RTC. The figure below illustrates the typical connection with an external crystal of 32.768 KHz and all required passive components. The values of the external passive components are suggested as follows: Rfb = 10 M C1, C2 = 12pF ~ 27pF
C1
OSCLIN

32.768 KHz Crystal

Rfb
OSCLOUT

Crystal Oscillator I/O Cells

C2

Figure 5-4. 5.1.3. 12 MHz Crystal

Low Frequency Crystal

The 12 MHz oscillator provides the reference clock source for the USB OTG PHY. An external clock source of 12 MHz at the level of 1.8V can be applied instead of a crystal. The figure below illustrates the typical connection with an external crystal of 12 MHz and all required passive components. The values of the

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C1 R1
XSCO

12 MHz Crystal

Crystal Oscillator I/O Cells

XSCI

C2

Figure 5-5. External Clock Source for 12 MHz Instead of a crystal, an external clock source with 3.3 V level can be applied to XSCO pin. The figure below illustrates the example how an external clock source can be applied.

External clock source (3.3V level)

XSCI

Crystal Oscillator I/O Cells

XSCO

Figure 5-6. 5.1.4. 25 MHz Crystal

External Clock Source for 12 MHz

The 25 MHz oscillator provides the reference clock source for the 10/100 Ethernet PHY. An external clock source of 25 MHz at the level of 1.8V can be applied instead of a crystal. The values of the external passive components are suggested as follows: C1, C2 = 22pF R1 = 10 R2 = 1M
C1 R1
XTLP

25 MHz Crystal

R2

Crystal Oscillator I/O Cells

XTLN

C2

Figure 5-7. 25 MHz Crystal Instead of a crystal, an external clock source with 1.8V level can be applied to XTLP pin. The figure below illustrates the example how an external clock source can be applied.

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External clock source (1.8V level)

XTLN

Crystal Oscillator I/O Cells

XTLP

Figure 5-8. 5.1.5. Phase Locked Loop 1 (PLL1)

External Clock Source for 25 MHz

The PLL1 is the clock source of the AHB bus devices and APB bus devices. The PLL1 uses the XIN crystal as a reference and multiplies its frequency by programming the MS1 [8:0] and NS1 [8:0] bits in the PLL1CR0 register. The output frequency of PLL1 is defined by the following equation: PLL1s output frequency [MHz] = XIN [MHz] x (LOOP_DIV[8:0] / PRE_DIV[8:0]) Whereby PRE_DIV[8:0] and LOOP[8:0] are in the range of 1~300

The AHB bus clock will be the output of the core PLL frequency divided by 2, and the APB bus clock will be the AHB bus clock divided by 2. The PLL1 will not be supplied with power during the sleep mode. The table below lists the output clocks derived from PLL1 using 3.6864 MHz. Table 5-1. PLL1-based Clock Assignment Output clock Description PLL CPU_fclk CPU primary clock PLL1 AHB peripheral devices JEM_hclk JEMCore AHB clock PLL1 CPU_hclk Debug clock PLL1 AES_hclk AES AHB encryption clock PLL1 AHBC_hclk AHB clock PLL1 DMA_hclk DMA AHB clock PLL1 MEMC_hclk Static memory AHB clock PLL1 SDRAMC_hclk SDRAM controller AHB clock PLL1 EBI_hclk EBI AHB clock PLL1 LCD_hclk LCDC AHB clock PLL1 LCD_CLK LCD pixel clock PLL1 LCD_Scalar LCD scalar clock PLL1 BRG_hclk APB bridge clock PLL1 MAC_hclk Ethernet MAC AHB clock PLL1 USB_hclk USB AHB clock PLL1 MEDIA_hclk MediaCodec AHB clock PLL1 Capture_hclk Video capture AHB clock PLL1 VCAP0_ICLK Capture clock for port 0 VCAP0_ICLK pin VCAP1_ICLK Capture clock for port 1 VCAP1_ICLK pin
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Frequency [MHz] Fcpu= 160 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Up to 120 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80 Fcpu/2 = 80

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Technical Reference Manual VCAP2_ICLK Capture clock for port 2 DLLIN_out DLL AHB clock APB peripheral devices JEM_pclk JEMCore APB clock BRG_pclk APB bridge controller APB clock CFC_pclk Compact Flash controller APB clock SDC_pclk SD controller APB clock WDT_pclk Watch dog timer APB clock TM_pclk Timer APB clock INTC_pclk Interrupt controller APB clock GPIO_pclk GPIO APB clock PWMpclk Pulse width modulator APB clock I2Cpclk I2C APB clock SSP_pclk SSP APB clock I2SAC97_pclk I2S and AC97 APB clock UART1_pclk Full UART APB clock UART2_pclk Bluetooth UART APB clock UART3_pclk UART APB clock IrDA_pclk Irda APB clock RTC_pclk Real-time APB clock Special clocks IrDA_clk IrDA clock SSPCLK_SPI SSP clock I2SAC97_clk UART_clk Uart clock Note
O

VCAP2_ICLK pin PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 PLL2 PLL1, PLL3 PLL1, PPL3 PLL1,2,3

Fcpu/2 = 80 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 Fcpu/4 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40 = 40

47.923 (FIR) 24.576 49.152 18.432 (1,152Kbps)

The CPU clock is currently specified at 160 MHz, which is based on the worse-case condition (-45

C to 125O C), and junction temperature. It may run up to 180 MHz at the commercial temperature of (0 O

C to 70O C). 5.1.6. Peripheral Phase Locked Loop 2 (PLL2) The PLL2 generate the clock sources for IrDA and UARTS. The PLL1 uses the XIN oscillator as a reference and multiplies its frequency by programming the PLL2NS bits in the PDLLCR1 register. The output frequency of PLLs is defined by the following equation: PLL2s output frequency [MHz] = XIN [MHz]x (LOOP_DIV[8:0] / PRE_DIV[8:0]) Whereby PRE_DIV[8:0] and LOOP[8:0] are in the range of 1~300

The IrDA module must be provided with a 48 MHz frequency when operating in FIR mode. Output clock
irda_clk

Table 5-2. Description IrDA clock

PLL2 Clock Assignment Frequency [MHz] Fcpu/6

5.1.7. Peripheral Phase Locked Loop 3 (PLL3) The PLL3 generate the clock sources for many peripheral devices. The PLL3 uses the 3.6864 MHz
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Technical Reference Manual oscillator as a reference and multiplies its frequency by programming the PLL3NS bits in the PDLLCR0 register. The output frequency of PLLs is defined by the following equation: PLL3s output frequency [MHz] = 3.6864 MHz x (LOOP_DIV[8:0] / PRE_DIV[8:0]) Whereby PRE_DIV[8:0] and LOOP[8:0] are in the range of 1~300

These interfaces require a frequency of 18.432 MHz (UARTs), 24.576 MHz (SPI), and variable frequencies (I2S) through setting the I2SCLKDIV bit in the PDLLCR1 register. The generated frequency may not exactly match the required frequency due to the choice of crystal and the lack of a perfect Least Common Multiple between the units. The chosen frequencies keep each units clock frequency within its clock tolerance. If a crystal other than 3.6864 MHz is used, the clock frequencies to the peripheral blocks interfaces may not yield the desired baud rates (or other protocols rate). Output clock sspclk_i2sac97 sspclk_spi i2sac97_clk UARTclks 5.1.8. DLL The aJ-200 includes a DLL which is used to lock the phase of the internal HCLK and the clock output SDR_CLK, which drives the external SDRAM devices. The figure below illustrates the DLL scheme. A delay inserted between DLLIN-OUT and input of PLL (FREF) is to compensate the I/O and wire delay on the PLL clock feedback path. This ensures that SDR_CLK is in phase with the internal HCLK, which is used strobe in the data sourced from the external memory system.
HCLK
SDRAMHTC[3:0] FB_DLY

Table 5-3. PLL3 Clock Assignment Description Frequency [MHz] I2S/AC97 clock Fcpu/6 Synchronous serial channel clock Fcpu/6 I2S/AC97 clock Fcpu/6 UARTs clock Fcpu/6

Wire Delay CIN

I SDR_CLK

DLLIN_OUT

Delay (compensate delay on the feedback path)

FREF

PLL CKOUT

O MDATA[31:0]

RCLK

Q FFs

I/O

DQOUT_WCLK

FFs Q

CONTROL_WCLKs

D Control Q FFs

Control SIgnals O

Figure 5-9.
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Technical Reference Manual 5.2. Operation Modes The aJ-200 operates in four basic modes: Reset mode Normal mode Power saving mode RTC operation

5.2.1. Reset Mode The aJ-200 reset logic provides the ability to activate the reset of the aJ-200 logic via: Power-on-reset (POR) Cold reset pin Watch dog timer reset Software base command issues a reset via the JTAG test interface

The figure below illustrates the reset logic

RSTOU RESETOUT

CRSTn

JEMCore Reset (Activated via JTAG)

VCCK

1.8 V

Power-On Reset Circuitry

GNDK

WDT Reset

Figure 5-10. Reset Logic During power-on reset, all internal registers and units are in their defined reset conditions. The internal clocks are stopped and the chip is static. All pins return to their reset conditions. Since the memory controller receives a full reset, all dynamic RAM contents are lost during power-on reset. The following table shows the state of each unit after each type of reset. Table 5-4. Units CPU
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Power On Reset (POR) Reset

Power Supply 1.8V

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Technical Reference Manual Units AHBC SRAM controller SDRAM controller EBI Ethernet controller DMA APB bridge USB OTG controller AES CFC MediaCodec Video Capture SDC I2C PWM I2S / AC97 / SPI SPP IrDA/UART4 UART1,2,3 PINTC GPIO TIMERs WDT RTC 5.2.1.1. Power On Reset (POR) Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Hardware Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Preserved Watchdog Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Preserved Power Supply 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V Alive

Power-On Reset

The aJ-200 includes a Power-On Reset (POR) circuit that generates a high level reset signal once the core power system voltage of 1.8V rises above a 1.2V. It will take a typical time of 3.5 ms (Tport1) to raise the reset output high from the time the core voltage has reached 1.2V as illustrated in figure below. After the power drops to another specified level of 1.2V, it generates a logic low level reset signal after a typical time of 5 ms (Tfall).
1.8 V

VCCK

Power-On Reset Circuitry

GNDK

POR

Figure 5-11. Power-On Reset (POR)

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Figure 5-12. POR Timing Waveform 5.2.1.2. Cold Reset After power on reset, a cold reset (CRSTn) can initiate a reset externally as illustrated in the figure below. The minimum active reset time after the initial power-on reset is 8T (of XIN). CRSTn is typically connected to the master reset signal of the system. The CRSTn is an open-drain I/O pin and should only be connected to other open-drain (open-collector) devices. An inverted version of the CRSTn pin is provided by the RST output pin and may be used by devices requiring an active high reset.
8T

CRSTn
Figure 5-13. Cold Reset Timing Waveform Watchdog Timer Reset

5.2.1.3.

The Watchdog timer is used to prevent the system from the infinite loop, if the software gets trapped in a deadlock situation. The WDT reset output trigger a system reset and drives the reset low for 3.5 sec. 5.2.1.4. JTAG Reset

The aJ-200 provides an IEEE 1149.1 (JTAG) interface for performing the traditional board continuing tests and communicating with software development environment. It can issue a reset via a software command. 5.2.2. Normal Mode Normal mode is the aJ-200s active operating mode. All power supplies are enabled and all functionally enabled clocks are running. Normal mode is entered after any power mode, power sequence, or reset completes its sequence. After hardware reset, any integrated peripherals that is not used in an aJ-200 based system, their associated clocks can be disabled via software using the AHB or APB module clock registers respectively. This allows to cut down the power consumption associated with the unused peripherals like USBPHY, 10/100 Ethernet PHY. 5.2.3. Power Saving Modes
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Technical Reference Manual Fundamentally, the aJ-200 can be configured to operate in the two power saving modes including idle mode and the sleep mode. These modes are initiated with the JEMCore standby instruction. An interface to the standby instruction is available in the com.ajile.jem.raw_JEM package. These modes are further described in details as follows 5.2.3.1. Standby mode (idle)

The aJ-200 enters the standby mode, when the clock to the internal CPU core is deactivated. This will reduce the current associated with the CPU core. During the standby mode the internal peripherals operate normally. The CPU clock is re-activated and CPU execution resumes when any unmasked interrupt is activated. The unmasked interrupt can be initiated internally via any integrated devices (system software determine which device and how is used to initiate the interrupt request to wake up the CPU) or externally via any external logic via WAKn input. The aJ-200 will also exit the standby mode when the external wakeup input (WAKn) is activated (or a reset). The idle thread in the aJile runtime executes the standby instruction to place the CPU in the idle state. The idle thread is the lowest priority thread in the system and runs when no other threads are ready to run. 5.2.3.2. Sleep mode

The sleep mode of the aJ-200 deactivates the clock to the CPU core and all the internal peripherals. During sleep mode, the RTC continues to work and external SDRAM is preserved because it is in selfrefresh mode. This provides the maximum power reduction of the aJ-200. The sleep mode is initiated by executing the standby instruction. Clocking resumes when the WAKn input is activated (or a reset). The system software should take care to properly prepare system resources (peripherals) for this sleep state (ex: deactivate communication channels). Similar consideration should be given to re-starting these system resources when exiting the sleep mode. The system should also consider the power that may be consumed by pull-up and pull-down resistors in the system and in the aJ-200 I/O pads. To further minimize power the system may shut down the aJ-200s PLLs before entering the sleep mode and re-start the PLL on exiting sleep mode. 5.2.4. RTC operation The RTC is powered by either system power of 5V or an external lithium battery in the range of 3.6V to 4.2V as illustrated in the below figure below. The aJ-200 includes an on-chip internal voltage regulator and voltage detector (VDT), which is used to regulate the internal power supplier (1.8V) for RTC from an external power source. It generates the internal required 1.8V with enough current for driving the RTC circuitry, whereby the two external 3.3 pF capacitors between 1.8V and 3.3 V and ground are required. A power island surrounding the RTC is implemented, so that it is completely isolated from the aJ-200 core

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Technical Reference Manual and I/O power planes. This allows RTC to stay alive while an external Lithium battery can be used, when the power system is shut down.

5V
VCC5A

VCC5A

VCC18

VCCOK RTC

Li-ion Battery 3.6V

GND18

GNDK

Voltage Regulator & Detector

3.3 pF

3.3 pF VCC18

VCC33

VCC33

VCCK

1.8V Core Voltage

Isolated Power Plane aJ_102

Figure 5-14. Battery Backup for RTC 5.3. System Configuration Registers The following table shows a summary of the system configuration registers, whereby the base address is located at: 9800 0000h. Table 5-5. Base address =0x9800 0000H Offset Address +0x0080 +0x0084 +0x0088 +0x008C +0x0090 +0x0094 +0x0098 +0x009C +0x00A0 +0x00A4 +0x00A8 +0x00AC 5.3.1.1. Summary of System Configuration Registers Description PLL1 Control Register 0 PLL2 Control Register 1 PLL3 Control Register 2 DLL Control Register AHB Module Clock Off Control Register APB Module Clock Off Control Register Clock Control Register Multi-Function Port Setting Register 0 Multi-Function Port Setting Register 1 Driving Capability and Slew Rate Control Register 0 Driving Capability and Slew Rate Control Register 1 Driving Capability and Slew Rate Control Register 2 Reset Value 0X0000 0000 0x0000 0000 0X0000 0000 0X0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000

PLL1 Control Register 0 (Offset == 0x0000) Table 5-6. PLL1 Control Register 0 (PLL1CR0) Type Description Reset Value -

Bit 31:26

Name Reserved

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Technical Reference Manual Bit 25 24:22 Name PLLBP R/W LTOSEL[2:0] R/W Type Description This bit is used to bypass PLL1 0 Clock sourced by XIN 1 Clock provided by PLL Lock time output select. The lock timer delays the selection of the PLL1 clock output as the internal clock source. This delay allows the PLL1 to generate a stable output with the desired muliplication of XIN clock source as examplified in the table 10. These bits are used to control the clock output CLKO 00 Disable CLKO 01 HCLK/2 10 HCLK/4 11 HCLK/8 Power down mode setting for PLL1 0 Power down or disable PLL1 1 Enable PLL1 PLL1 output frequency range 0 20 MHz ~ 100 MHz 1 100 MHz ~ 300 MHz Programmable loop divider for PLL1. A programmable value of 1~300 is required Progammable pre-divider for PLL1. A programmable value of 1~300 is required Lock times for PLL1 5 MHz 3.072 2.458 1.843 1.229 0.614 0.410 0.205 10MHz 1.536 1.229 0.921 0.614 0.307 0.205 0.102 14.318MHz 1.0728 0.8582 0.6438 0.4291 0.2146 0.1430 0.0715 20MHz 0.512 0.4097 0.3072 0.2048 0.1024 0.0683 0.0341 Reset Value 0x0 0x0

21:20

CLKOSEL[1:0]

R/W

0x0

19 18 17:9 8:0

PDN FRANGE LOOP_DIV1 [8:0] PRE_DIV1 [8:0]

R/W R/W R/W R/W

0x1 0x0 0x0 0x0

Table 5-7. LTOSEL[2:0] 0 1 2 3 4 5 6 7 Note Hex 3C00 3000 2400 1800 0C00 0800 0400 0008 Decimal 15,360 12,288 9,216 6,144 3,072 2,048 1,024 8

The lock time of 7 is intended to allow software control over enabling the lock time of the PLL. Software can power on the PLL by setting the pre divider, loop divider, range and PLL enable bit fields and leave the PLL output enable bit (PLL_OUT_ENABLE) inactive. After a sufficient time the PLL output enable bit may be set and the PLL output will be used in 8 XIN cycles

5.3.1.2.

PLL2 Control Register 1 (Offset == 0x0004)

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Technical Reference Manual Table 5-8. Bit 31:26 25 24:22 Name Reserved PLLBP LTOSEL[2:0] PLL2 Control Register 1 (PLL2CR1) Type R/W R/W Description This bit is used to bypass PLL2 0 Clock sourced by XIN 1 Clock provided by PLL2 Lock time output select. The lock timer delays the selection of the PLL2 clock output as the internal clock source. This delay allows the PLL2 to generate a stable output with the desired muliplication of XIN clock source Power down mode setting for PLL2 0 Power down or disable PLL2 1 Enable PLL2 PLL2 output frequency range. 0 20 MHz ~ 100 MHz 1 100 MHz ~ 300 MHz Programmable loop divider for PLL2. A programmable value of 1~300 is required Progammable pre divider for PLL2. A programmable value of 1~300 is required Reset Value 0x0 0x0

21:20 19 18 17:9 8:0 5.3.1.3.

Reserved PDN FRANGE LOOP_DIV2 [8:0] PRE_DIV2 [8:0]

R/W R/W R/W R/W

0x1 0x0 0x0 0x0

PLL3 Control Register 2 (Offset == 0x0008) Table 5-9. PLL2 Control Register 3 (PLL2CR2) Type R/W R/W Description This bit is used to bypass PLL3 0 Clock sourced by XIN 1 Clock provided by PLL3 Lock time output select. The lock timer delays the selection of the PLL3 clock output as the internal clock source. This delay allows the PLL3 to generate a stable output with the desired muliplication of XIN clock source Reserved Power down mode setting for PLL3 0 Power down or disable PLL3 1 Enable PLL3 PLL3 output frequency range. 0 20 MHz ~ 100 MHz Reset Value 0x0 0x0

Bit 31:26 25 24:22

Name Reserved PLLBP LTOSEL[2:0]

20:20 19 18

PDN FRANGE R/W R/W

0x0 0x1 0x0

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Technical Reference Manual Bit 17:9 8:0 Name LOOP_DIV3 [8:0] PRE_DIV3 [8:0] Type R/W R/W Description 1 100 MHz ~ 300 MHz Programmable loop divider for PLL3. A programmable value of 1~300 is required Programmable pre divider for PLL3 A programmable value of 1~ 300 is required Reset Value 0x0 0x0

5.3.1.4.

DLL Control Register (Offset == 0x000C) Table 5-10. DLL Control Register (DLLCR) Description These bits control the DLL FREF input delay as follows: 0000 Lead 4.8ns 0001 Lead 4.2ns 0010 Lead 3.6ns 0011 Lead 3.0ns 0100 Lead 2.4ns 0101 Lead 1.8ns 0110 Lead 1.2ns 0111 Lead 0.6ns 1000 Same phase 1001 Lag 0.6ns 1010 Lag 1.2ns 1011 Lag 1.8ns 1100 Lag 2.4ns 1101 Lag 3.0ns 1110 Lag 3.6ns 1111 Lag 4.0ns Lock time output select. The lock timer delays the selection of the DLL clock output as the internal clock source. This delay allow the DLL to generate a stable output with the desired muliplication of HCLK clock source Reserved Power down mode setting for DLL 0 Power down or disable DLL 1 Enable DLL DLL output frequency range 0 20 MHz ~ 100 MHz 1 100 MHz ~ 300 MHz Programmable loop divider for DLL. A programmable value of 1~64 is required Progammable predivider for DLL.
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Name Reserved DLLFBSEL[3:0]

Type R/W

Reset Value 0x0

24:22

LTOSEL[2:0]

R/W

0x0

21:20 19 18 11:6 5:0

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R/W R/W R/W R/W

0x0 0x1 0x0 0x0 0x0

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Technical Reference Manual Bit Name Type Description A programmable value of 1~64 is required 5.3.1.5. AHB Module Clock Off Control Register (Offset == 0x0010) Table 5-11. Bit 31:18 17 16 15 14 13 12 11 10 9 8 7 6 5:3 2:1 Name Reserved DLLOFF USBDOFF MACOFF Reserved AESOFF LCDOFF MCPOFF VCAPOFF DMAOFF EBIOFF SDRAMOFF SMCOFF Reserved MCP_CLK_CTL[1:0] AHB Module Clock Off Control Register (AHBMCLKOFF) Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Control the clock of the DLL 0 Enable 1 Disable Control the clock of the USB OTG 0 Enable 1 Disable Control the clock of the Ethernet MAC 0 Enable 1 Disable Control the clock of the AES 0 Enable 1 Disable Control the clock of the LCD controller 0 Enable 1 Disable Control the HCLK of the MediaCodec 0 Enable 1 Disable Control the clock of the video capture ports 0 Enable 1 Disable Control the clock of the DMAC 0 Enable 1 Disable Control the clock of the EBI 0 Enable 1 Disable Control the clock of the SDRAMC 0 Enable 1 Disable Control the clock of the SMC 0 Enable 1 Disable MCP_CLK_CTl [0] selects the clock source for MCP_CLK Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset Value

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Technical Reference Manual Bit Name Type Description 0 fclk 1 hclk MCP_CLK_CTl [1] controls the MCP_CLK clock 0 Enable 1 Disable Reset Value

0 5.3.1.6.

Reserved

APB Module Clock Off Control Register (Offset == 0x0014) Table 5-12. APB Module Clock Off Control Register (APBMCLKOFF) Type Description R/W R/W PI-OSCMD controls PHY crystal (XTLP). It is active high for XTLN crystal alive. PI_PWRD controls the power-down mode of 10/100 PHY. Its used in the conjunction of PI_OSCMD bit. When PI_PWRD is set to high and PI_OSCMD is set to low, all the clocks and PHY blocks are off. The power consumption is the range of A. When PI_PWRD is set to high and PI_OSCMD is set to high all the XTLN is on and PHY blocks are off. The power consumption is the range of mA level. Note: The 10/100 PHY can be powered down by software using power down register. In this case, PLL, bandgap, XTLP (crystal) are alive except other clocks and blocks are off. The power consumption is in the range of mA. Control the clock of the IrDA/UART4 controller. 0 Enable 1 Disable Control the clock of the UART3 controller. 0 Enable 1 Disable Control the clock of the UART2 controller. 0 Enable 1 Disable Control the clock of the UART1 controller. 0 Enable Reset Value 0x0 0x1

Bit 31:26 25 24

Name Reserved PI_OSCMD PI_PWRD

23:20 16

Reserved IrDAOFF

R/W

0x0

15 14 13

UART3OFF UART2OFF UART1OFF

R/W R/W R/W

0x0 0x0 0x0

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Technical Reference Manual Bit 12 11 10 9 8 7 6 5 4 3 2 1 0 SDCLKSELT R/W Name I2S/AC97OFF SSPOFF I2COFF GPIOOFF PWMOFF TIMEROFF SDCPCLKOFF CFCOFF INTCOFF RTCOFF WDTOFF SDCOFF Type Description R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 Disable Control the clock of the I2S/AC97 controller 0 Enable 1 Disable Control the clock of the SSP controller. 0 Enable 1 Disable Control the clock of the I2C controller. 0 Enable 1 Disable Control the clock of GPIOA,B,C 0 Enable 1 Disable Control the clock of the PWM controller. 0 Enable 1 Disable Control the clock of the TIMER controller 0 Enable 1 Disable Control the PCLK of the SD controller 0 Enable 1 Disable Turn off the clock of the CF controller 0 Enable 1 Disable Control the clock of the interrupt controller 0 Enable 1 Disable Control the clock of the RTC controller 0 Enable 1 Disable Control the clock of the WDT controller 0 Enable 1 Disable Control the clock of SD controller 0 Enable 1 Disable Select clock of SD controller 0 HCLK 1 PCLK Reset Value 0x0 0x0 0x0

0x0 0x0 0x0 0x0 0x0 0x0 0x0

Note Switching the clock visa control register may cause glitches, users need to follow the following sequence: 1. Disable the clock 2. Switch clock 3. Enable clock

This will avoid glitches during the clock switching.

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Technical Reference Manual 5.3.1.7. Clock Control Register (Offset == 0x0018)

Switching the clock visa control register may cause glitches, users need to follow the following sequence: 1. Disable the clock 2. Switch clock 3. Enable clock This will avoid glitches during the clock switching. Table 5-13. Bit 31:30 29 28 Name Reserved USB_VDET_PWRDWN USB_PLLALIV Clock Control Register (CCR) Reset Value -

Type Description -

27

OSCOUTEN

26:24

LCDCLKSEL[2:0]

23:21

LCD_SCALE_CLKSEL[2:0]

20:18

AC97CLKSEL[2:0]

R/W Power down control for USB voltage detector 0 Normal 1 Power down USB voltage detector R/W Clock source enable signal 0 CLK48M is active only, if SuspendM is 1 and internal SUSCLK is inactive. 1 CLK48M and SUSCLK are active. R/W CLKOSCO clock output selection. Toggling OSCOUTEN will cause CLKOSCO, CLK60SYS, CLK, CLK48M or SUSCLK to generate glitches. CLKOSCO is powered down during suspend mode. CLKOSCO is active during suspend mode R/W LCDCLKSEL[1:0] selects clock source 00 FCLK/2 01 FCLK/4 10 FCLK/6 11 FCLK/8 LCDCLKSEL[2] controls clock of LCD 0 Enable 1 Disable LCD_SCALE_CLKSEL[1:0] selects the clock R/W source for LCD scalar 00 FCLK/2 01 FCLK/4 10 FCLK/6 11 FCLK/8 LCDCLKSEL[2] controls the clock of LCD scalar 0 Enable 1 Disable R/W AC97CLKSEL[1:0] selects clock source 00 PLL1 output frequency divided by 6 01 PLL3 output frequency divided by 3 10 PLL3 output frequency divided by 12
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0x0

0x1

0x0

0x0

0x0

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Technical Reference Manual Bit Name Type Description 11 Reserved AC97CLKSEL[2] controls the clock 0 Enable 1 Disable I2SCLKSEL[1:0] selects clock source for I2S/AC97/SPI 00 PLL1 output frequency divided by 96 01 PLL3 output frequency divided by 6 10 PLL1 output frequency divided by 4 11 PLL3 out frequency divided by 2 I2SCLKSEL[2] controls the clock 0 Enable 1 Disable SPICLKSEL [1:0] selects clock source for SSP channel 00 PLL1 output frequency divided by 96 01 PLL3 output frequency divided by 6 10 PLL1 output frequency divided by 4 11 PLL3 out frequency divided by 2 SPICLKSEL[2] controls the clock 0 Enable 1 Disable UART4Sel [1:0] selects the clock source 00 PLL1 output frequency divided by 6 01 PLL2 output frequency 10 PLL3 output frequency divided by 8 11 Reserved UART4SEL[2] controls the clock 0 Enable 1 Disable UART3SEL [1:0] selects the clock source 00 PLL1 output frequency divided by 6 01 PLL2 output frequency 10 PLL3 output frequency divided by 8 11 Reserved UART3SEL[2] controls the clock 0 Enable 1 Disable UART2SEL [1:0] selects the clock source 00 PLL1 output frequency divided by 6 01 PLL2 output frequency 10 PLL3 output frequency divided by 8 11 Reserved UART2SEL[2] controls the clock 0 Enable 1 Disable UART1SEL [1:0] selects the clock source
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17:15

I2SCLKSEL[2:0]

R/W

0x0

14:12

SPICLKSEL[2:0]

R/W

0x0

11:9

UART4SEL [2:0]

R/W

0x0

8:6

UART3SEL [2:0]

R/W

0x0

5:3

UART2SEL [2:0]

R/W

0x0

2:0
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R/W

0x0
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Technical Reference Manual Bit Name Type Description 00 PLL1 output frequency divided by 6 01 PLL2 output frequency 10 PLL3 output frequency divided by 8 11 Reserved UART2SEL [2] controls the clock 0 Enable 1 Disable 5.3.1.8. Bit 31 30 29 28 27 26 25 24 23 Multi-Function Port Setting Register 0 (Offset == 0x001C) Table 5-14. Name Reserved I2C _Enable PWM2B_Enable PWM2A_Enable PWM1B_Enable PWM1A_Enable PWM0B_Enable R/W PWM0A_Enable R/W VLIO_RDY_Enable R/W Multifunction Port Setting Register 0 (MFPSR0) Type Description R/W R/W R/W R/W R/W Configure I2C interface as 0 GPIOB[8:7] 1 I2C Configure PWM2B pin as 0 GPIOB18 1 PWM2B Configure PWM2A pin as 0 GPIOB17 1 PWM2A Configure PWM1B pin as 0 GPIOB16 1 PWM1B Configure PWM1A pin as 0 GPIOB15 1 PWM1A Configure PWM0B pin as 0 GPIOB14 1 PWM0B Configure PWM0A pin as 0 GPIOB13. 1 PWM0A Configure the VLIO_RDY input. The GPIOA7 input is connected with the internal VLIO_RDY of the SRAM controller. It can be used to extend the memory cycles, when it is enabled. 0 Disable, default 1 Enable Configure GPIOA[7:0] port as 00 PIX_DO[7:0] 01 GPIOA[7:0] 10 GPIO[7:2], SPELED, & FDXLED 11 GPIO[7:2], SPELED, & LINK
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Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0

0x0

22:21

GPIOA_Enable[1:0]

R/W

0x0

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Technical Reference Manual Bit 20 19 18 17 16 15 Name CS5n_Enable CS4n_Enable CS3&2n_Enable TIOB2_Enable TIOA2_Enable TCK2_Enable Type Description R/W R/W R/W R/W R/W R/W Configure CS5n pin as 0 GPIOC19. 1 CS5n Configure CS4n pin as 0 GPIOC18. 1 CS4n Configure CS[3:2]n and MADDR[24:23] as 0 NAND_WRn, NAND_REn, ALE, CE 1 CS[3:2]n and MADDR[24:23]. Configure TIOB2 pin as 0 GPIOC30. 1 TIOB2 Configure TIOA2 pin as 0 GPIOC17 1 TIOA2 This bit and GPIOA_Enable (22,21) to configure TCK2 pin as GPIOA_Enable[1:0] & TCK2_Enable 00 x TVCLK 01,10,11 0 GPIOC16 01,10,11 1 TCK2 Configure TIOB1 pin as 0 GPIOC29. 1 TIOB1 Configure TIOA1 pin as 0 GPIOC15 1 TIOA1 Configure TCK1 pin as 0 GPIOC14 1 TCK1 Configure TIOB0 pin as 0 GPIOC28 1 TIOB0 Configure TIOA0 pin as 0 GPIOC13 1 TIOA0 Configure TCK0 pin as 0 GPIOC12. 1 TCK0 Configure IrDA_TxD pin as 0 IrDA_TxD 1 TxD4 Configure IrDA_RxH pin as 0 IrDA_RxH 1 GPIOC27 Reset Value 0x0 0x0

0x0 0x0 0x0 0x0

14 13

TIOB1_Enable TIOA1_Enable

R/W R/W R/W

0x0 0x0 0x0 0x0 0x0 0x0 0x0

12 11 10 9 8 7

TCK1_Enable R/W TIOB0_Enable TIOA0_Enable TCK0_Enable Reserved UART4_Enable R/W R/W R/W

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Technical Reference Manual Bit Name Type Description Configure IrDA_RxL pin as 0 IrDA_RxL 1 RxD4 Configure UART3 data pins as 0 GPIOC[10:9]. 1 UART3 data pins Configure UART2 data pins as 0 GPIO[6:5]. 1 UART2 data pins Configure UART2 control pins as 0 GPIOC[8:7]. 1 UART2 control pins Configure UART1 data pins as 0 GPIOC[4:3] 1 UART1 Configure UART1 control pins as 0 GPIOC[2:0] & GPIOB[31:29] 1 UART1 control pins Configure I2S/AC97/SSP interface pins as 0 GPIOB [28:23] 1 I2S/AC97/SSP interface Configure SSP interface pins as 0 GPIOB [22:19] 1 SSP interface Reset Value

6 5 4 3 2 1 0

UART3_Enable UART2_Enable UART2_CTL_Enable UART1_Enable UART1_CTL_Enable I2S_AC97_Enable

R/W R/W R/W R/W R/W

0x0 0x0 0x0 0x0 0x0 0x0 0x0

R/W SSP_Enable R/W

Note: Some of the GPIOB and GPIOC pins can be selected at two different pins per software. To prevent an undeterministic input value, a logical OR of two input pins is internally implemented. 5.3.1.9. Bit 31:16 15:14 Multi-Function Port Setting Register 1 (Offset == 0x0020) Table 5-15. Name Reserved CF_Enable[1:0] Multi-Function Port Setting Register (MFPSR1) Type Description R/W Configure CF interface pins as 00 Video capture port 0 (VCAP0_VD[9:0], VCAP0_ICLK). Video capture port 1 (VCAP1_VD[9:0], VCAP1_ICLK). Video capture port 2 (VCAP2_VD[9:0], VCAP2_ICLK). VCAP_VSYNC & VCAP_HSYNC SDIO[3:0]. 01 CF card interface 1x GPIOB[31:13], GPIOB[11:0] & GPIOC31, GPIOC26, GPIOC11, &
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0x10

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Technical Reference Manual Bit Name Type Description GPIOC[1:0], & SDIO[3:0] Configure PWM3B pin as 0 GPIOC11 1 PWM2B Configure PWM3A pin as 0 GPIOC26 1 PWM2A Configure LCDD[23:18] pins as 0 GPIOA[31:26]. 1 LCDD[23:18] Configure LCDD[17:16] pins as 0 GPIOA[25:24] 1 LCDD[17:16] Select LCDD[15:8] pins as 0 GPIOA[23:16]. 1 LCDD[15:8] Select LCDD[7:0], & LCDPLK, LCDC/LCAC, LCDVS, LCDHS pins as 0 GPIOA[15:8], GPIOB12, & GPIOC[25:23]. 1 LCDD[7:0], LCDPLK, LCDC/LCAC, LCDVS, LCDHS Configure SMC_CS7n pin as 00 GPIOC21. 01 SMC_CS7n 10 SPELED output 11 Link output Configure SMC_CS6n pin as 00 GPIOC20 01 SMC_CS6n 10 FDEXLED output 11 LINK output Configure CLKO pin as 0 GPIOC22. 1 CLKO Configure CFC data pins[3:0] 0 CF DATA [3:0] 1 SDIO[3:0] Configure MMC/SD/SDIO Card interface pins as 0 GPIOB[6:3]. 1 SD/SDIO/MMC control signals Reset Value

13 12 11 10 9 8

PWM3B_Enable PWM3A_Enable LCD_Enable LCD_Enable2 LCD_Enable1 LCD_Enable0

R/W R/W R/W R/W R/W R/W

0x0 0x0 0x0 0x0 0x0 0x0

7:6

CS7n_Enable[1:0]

R/W

0x0

5:4

CS6n_Enable[1:0]

R/W

0x0

3 2 1 0

CLKO_Enable Reserved SD_DAT_Sel SD_CTL_Enable

R/W R/W R/W

0x0 0x1 0x0

Note: Some of the GPIOB and GPIOC pins can be selected at two different pins per software. To prevent an undeterministic input value, a logical OR of two input pins is internally implemented.

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Technical Reference Manual 5.3.1.10. Driving Capability and Slew Rate Control Register 0 (Offset == 0x0024) Table 5-16. Bit 31-28 Name EBICTRL_DCSR[3:0] Driving Capability and Slew Rate Control Register 0 (DCSRCR0) Type R/W Description Fine-tune the output driving capability of the MADDR [14:0], MBEn[3:0], MWEn, SMC_OEn. EBICTRL_DCSR[2:0] 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA EBICTRL_DCSR[3] controls the slew rate: 0 Fast 1 Slow Fine-tune the output driving capability of the MDATA [31:0]. EBIDATA_DCSR[2:0] 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA EBIDATA_DCSR[3] controls the slew rate: 0 Fast 1 Slow Fine-tune the output driving capability of the SDRAM chip select: SDR_CSn. SDRAMCS_DCSR[2:0] 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA SDRAMCS_DCSR[3] controls the slew rate 0 Fast 1 Slow Fine-tune the output driving capability of the
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27-24

EBIDATA_DCSR[3:0]

R/W

0xA

23-20

SDRAMCS_DCSR[3:0]

R/W

0xA

19-16
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Technical Reference Manual Bit Name Type Description SDRAMCs control pins: SDR_RASn, & SDR_CASn. SDRAMCTL _DCSR[2:0] 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA SDRAMCTL _DCSR[3] controls the slew rate: 0 Fast 1 Slow Fine-tune the output driving capability of the SDR_CLKEN pin. CKE_DCSR[2:0] 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA CKE _DCSR[3] controls the slew rate: 0 Fast 1 Slow Fine-tune the output driving capability of the SDRAMCs clock output pins. SDCLK_DCSR[2:0] 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA SDCLK _DCSR[3] controls the slew rate: 0 Fast 1 Slow Control the slew rate and output driving capability of the MADDR [24:15], SMC_CSn[7:0] pins.
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15-12

CKE_DCSR[3:0]

R/W

0xA

11-8 7-4

Reserved SDCLK_DCSR[3:0]

R/W

0xA

3-0

SRAM_DCSR[3:0]

R/W

0x1

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Technical Reference Manual Bit Name Type Description SRAM_DCSR[2:0] 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA SRAM_DCSR[3] controls the slew rate: 0 Fast 1 Slow 5.3.1.11. Driving Capability and Slew Rate Control Register 1 (Offset == 0x0028 Table 5-17. Bit 31-20 19-16 Name Reserved PWM_DCSR[3:0] Driving Capability and Slew Rate Control Register 1 (DCSRCR1) Type R/W Description Control the slew rate and driving capability of the PWM output pins. PWM_DCSR[2:0] control the output driving capability: 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA PWM_DCSR[3] controls the slew rate: 0 Fast 1 Slow Control the slew rate and driving capability of the CF controller output pins. CFC_DCSR[2:0] control the output driving capability: 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA
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Reset Value 0x1

15-12 11-8

Reserved CFC_DCSR[3:0]

R/W

0x1

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Technical Reference Manual Bit Name Type Description CFC_DCSR[3] controls the slew rate: 0 Fast 1 Slow Control the slew rate and driving capability of the GPIOA, B, C output pins. GPIO_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA GPIO_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the LCD output pins. LCD_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA GPIO_DCSR[3] controls the slew rate. 0 Fast 1 Slow Reset Value

7-4

GPIO_DCSR[3:0]

R/W

0x1

3:0

LCD_DCSR[3:0]

R/W

0x1

5.3.1.12.

Driving Capability and Slew Rate Control Register 2 (Offset == 0x002C) Table 5-18. Driving Capability and Slew Rate Control Register 2 (DCSRCR2) Type R/W Description Control the slew rate and driving capability of the SD controller output pins. SD_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA
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Name SD_DCSR[3:0]

Reset Value 0x1

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Technical Reference Manual Bit Name Type Description 100 10mA 101 12mA 110 14mA 111 16mA SD_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the SSP controller output pins. SSP_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA SSP_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the I2S / AC97 controller output pins. I2SAC97_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA I2SAC97_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the CRSTn, RSTOUTn, PDWn, WAKn, WRTSn pins. JEM_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA
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27-24

SSP_DCSR[3:0]

R/W

0x1

23-20

I2SAC97_DCSR[3:0]

R/W

0x1

19-16

JEM_DCSR[3:0]

R/W

0x1

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Technical Reference Manual Bit Name Type Description 101 12mA 110 14mA 111 16mA JEM_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the timer pins. Timer_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA Timer_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the I2C pins. I2C_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA I2C_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the IrDA/UART4 controller output pins. IrDA_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA
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15-12

TIMER_DCSR[3:0]

R/W

0x1

11-8

I2C_DCSR[3:0]

R/W

0x1

7-4

IrDA_DCSR[3:0]

R/W

0x1

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Technical Reference Manual Bit Name Type Description 111 16mA IrDA_DCSR[3] controls the slew rate. 0 Fast 1 Slow Control the slew rate and driving capability of the UART1,UART2 and UART3 output pins. UART_DCSR[2:0] control the output driving capability 000 2mA 001 4mA 010 6mA 011 8mA 100 10mA 101 12mA 110 14mA 111 16mA UART_DCSR[3] controls the slew rate. 0 Fast 1 Slow Reset Value

3-0

UART_DCSR[3:0]

R/W

0x1

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Technical Reference Manual

6. Java Processor
6.1. Overview The aJiles Java processor is the aJiles third generation of low-power, direct execution processor for Java JME platform, Java processor. Its designed to power the next generation of M2M internet embedded devices, and mobile internet appliances. The Java processor includes an enhanced JEMCore-II with byte, half word, word operation, a DSP data path, 32 KB of unified I&D cache, AHB bus interface, APB interface, and JTAG interface. The block diagram of the Java Processor is shown in figure below. Detailed description of each functional block can be found in the following sections.

JEMCore TM
JTAG Interface ExecutionUnit Fixed-point MAC MJM Microcode ROM Interrupt Control Microcode RAM 32 KB Unified I&D Cache 2 x 4048 x 52

AHB APB

Reset

Interrupt Interface

Figure 6-1. 6.2. JEMCore-II Processor Core

Java Processor Functional Block

JEMCore-II directly executes Java Virtual MachineTM (JVM) bytecode instructions, real-time Java threading primitives and a number of extended bytecode instructions for multimedia and networked embedded applications. The JEMCore-II improves Java execution efficiency by eliminating the Java interpreter layer and the RTOS kernel layer. Since JVM bytecode instructions are executed as native instructions, the JEMCores Java performance is similar to RISC processors executing compiled C. In addition, Java threading primitives (wait, yield, notify, monitor enter/exit) are implemented as extended bytecode instructions, eliminating the need for a traditional RTOS. The result is extremely low executive overhead with thread to thread context switch times of less than 1sec. For Java based multimedia-rich, servo motor, robotic applications, JEMCore-II has enhanced with a dedicated microcode-based DSP datapath to accelerate various algorithms for audio, embedded control, servo motor control, voice and hand writing recognition. The figure below illustrates the simplified block diagram of the enhanced JEMCore-II
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Technical Reference Manual

ADDRESS

CNTR PC Q MASK TOS SKLM VARS MARK

Mux

Shifter
Breakpint Logic

ALU
V00-V10 Register File Mux K L Mux
Y X

CLASS JVM RTIME THREAD

ALU
R S Mux

Read Register Intr. Reg Write Register

DATA

Mux

Mux

Barrel Shifter
Mux

Parser

R[5:0]
Mux A B Bus

Unified I&D Cache 32KB

AHB

APB

S[5:0] TAU Registers

Fetch/Read/Write

Bus Control MicroPC

Opcode

Microinstruction Register ROM Control Store 32KB Writeable Control Store (WCS) 32KB

Test Access Unit (TAU) Interrupt MJM &Thread Timers

1149 Interface MASK Int NMI

Figure 6-2. 6.3. Multiple JVM Manager (MJM)

Block Diagram of JEMCore-II

The multiple JVM feature of the aJ-200 allows up to two independent Java applications to execute with a deterministic, time-sliced schedule and with full memory protection. Within its bounded execution interval and memory space, each JVM environment can employ its own multi-threading and memory utilization policies without threat of intervention by faulty or malicious applications. The Multiple JVM Manger (MJM) provides timing resources and interrupts logic to ensure no JVM (applications) may interfere with the processing needs of the other JVMs. The MJM provides a timer to maintain the time slices allotted to each logical JVM. Separate timers are provided for each JVM (clock timer and piano timer) to maintain separate sleep queues and schedule periodic threads as illustrates in figure below.

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Technical Reference Manual

JVM0

JVM1

Thread Manager Linear Addressing Memory Timer Interrupt Unaccessible Memory for JVM0 Memory for JVM0 Fire Wall

Thread Manager Timer Interrupt Memory for JVM1 Unaccessible Memory for JVM1

Programmble Memory Protection

Global Memory Software Semaphore Synchronization

Figure 6-3. 6.4. JEMCore-II Register Description

Multiple JVM Management (MJM)

The table below shows the address memory map for the JEMCore-II registers. The base address is 0x9800 000h. Table 6-1. Summary of JEMCore-II Registers Descriptions Piano roll timer 0 reload Clock timer 0 reload JVM 0 piano roll and clock timer enable Piano roll timer 0 Clock timer 0 Piano roll timer 1 reload Clock timer 1 reload JVM 1 piano roll and clock timer enable Piano roll timer 1 Clock timer 1 Notes

Base address = 0x9800 0000 Offset Bits Acronym JMV0 Piano roll and clock timer registers 0x0020 16 PRT_RL0 0x0024 16 CT_RL0 0x0028 2 TMR_EN0 0x002C 16 PRT0 0x0030 16 CT0 JMV1 Piano roll and clock timer registers 0x0034 16 PRT-RL1 0x0038 16 CT_RL1 0x003C 2 TMR_EN1 0x0040 0x0044 JVM registers
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16 16

PRT1 CT1

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Technical Reference Manual 0x0100 4 0x0104 0x0108 16 0x010C 16 0x0110 16 0x0114 16 0x0118 3 0x011C 16 Interrupt control registers 0x0200 32 0x0204 0x0208 0x020C 0x0210 0x0214 0x0218 0x021C 0x0220 0x0224 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C 0x0240 0x0244 0x0248 0x024C 0x0250 0x0254 0x0258~0x0278 0x027C 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 JVM ABO ABO_RLR PSCL_RLR JSI_ALARM TMODE JSI PINTRO_ILTR SSP_ILTR AES_ILTR I2S_AC97_SPI_ILTR UART3_ILTR UART1_ILTR UART2_ILTR UART4_FIR_ILTR UART4_ILTR GPIOA_ILTR GPIOB_ILTR GPIOC_ILTR RTC_ILTR LCD_ILTR DMA_ILTR APB_ILTR ETHERNET_ILTR USB_ILTR TIMER0_ILTR Mediacodec_ILTR VCAP_ILTR VCAP_OV_ILTR Reserved PIR JVM register Reserved Abort timer Abort timer reload Prescaler reload JSI alarm timer reload Timer mode JSI Timer Peripheral interrupt output interrupt level translation(IRQ) SSP Interrupt Level Translation AES interrupt level translation I2C_AC97_SPI interrupt level translation UART3 interrupt level translation UART1 interrupt level translation UART2 interrupt level translation UART4 FIR interrupt level translation UART4 interrupt level translation GPIOA interrupt level translation GPIOB interrupt level translation GPIOC interrupt level translation RTC interrupt level translation LCD interrupt level translation DMA interrupt level translation APB interrupt level translation Ethernet interrupt level translation USB OTG interrupt level translation TIMER0 interrupt level translation MediaCodec interrupt leve; Video capture interrupt level Video capture DMA interrupt Pending Interrupt register

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Read only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

32 32 32
32 32

6.4.1. MJM Register Descriptions The MJM registers are summarized in the below table. The configuration of the MJM is performed using the JEMBuilder configuration and application build tool. JEM Builder will automatically generate the MJM initialization data used by the aJ-200 during the reset initialization sequence. Table 6-2. Base address = 0x9800 0000 Summary of MJM Registers

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Technical Reference Manual Offset Bits Acronym JMV0 Piano roll and clock timer registers 0x0020 16 PRT_RL0 0x0024 16 CT_RL0 0x0028 2 TMR_EN0 0x002C 16 PRT0 0x0030 16 CT0 JMV1 Piano roll and clock timer registers 0x0034 16 PRT-RL1 0x0038 16 CT_RL1 0x003C 2 TMR_EN1 0x0040 0x0044 JVM registers 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 6.4.1.1. 16 16 4 16 16 16 16 3 16 PRT1 CT1 JVM ABO ABO_RLR PSCL_RLR JSI_ALARM TMODE JSI Descriptions Piano roll timer 0 reload Clock timer 0 reload JVM 0 piano roll and clock timer enable Piano roll timer 0 Clock timer 0 Piano roll timer 1 reload Clock timer 1 reload JVM 1 piano roll and clock timer enable Piano roll timer 1 Clock timer 1 JVM register Reserved Abort timer Abort timer reload Prescaler reload JSI alarm timer reload Timer mode JSI Timer Notes

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Read only Read only

Read only

Read only

MJM JVM Register

The MJM JVM register is used exclusively by the aJ-200 microcode to activate a specific JVM context. The first JVM (typically JVM 0) is activated immediately after a successful reset initialization by the aJ-200 microcode. In response to the JVM switch interrupt (JSI), the microcode will set the next JVM number as part of the context switch to the next JVM. JVM context switches are performed entirely in microcode and are transparent to the application software. The assignment of JVM numbers is configured by JEM Builder configuration tool. Although there is a 4-bit JVM number to encode 16 JVMs, there are only two sets of system clock timers and piano roll timers that are enabled for specific JVM numbers. Set 0 is enabled for JVM 0 and JMV 8. Set 1 is enabled for JVM 1 and JVM 9. These timers are not available for the remaining JVM numbers. Offset : 0x0000 Bit position Field name Note Table 6-3. MJM JVM Register MJM JVM Register (JVM) 31:4 3:0 Unused JVM number

Accesses to the MJMJVM register are performed by microcode in trusted mode. Memory protection

logic, if implemented, should only allow access to this register when trusted mode is active.
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Technical Reference Manual 6.4.1.2. Abort Timer Register

The read-only abort timer is a watch dog timer to ensure the JSI interrupt is acknowledged within the abort time interval. The abort timer is activated when the JSI interrupt is generated. If the JSI interrupt is not acknowledged during the abort time interval, an internal abort signal is generated to force the aJ-200 to terminate and disable the current JVM execution and force a JVM context switch. The abort timer is a count-down timer in units of CPU clock ticks. Table 6-4. Offset : 0x0008 Bit position Field name 6.4.1.3. 31:16 Unused Abort Timer Register 15:0 Abort timer value

Abort Timer Register (ABO)

Abort Timer Reload Register

The abort timer reload register is used exclusively by the aJ-200 microcode to establish the abort time interval. The abort time interval is the time allowed for the aJ-200 to complete the last instruction of the current JVM activation time slice and acknowledge the JSI interrupt. The abort timer reload register is initialized by the aJ-200 microcode during reset IDB processing using the timeout value specified via the JEM Builder configuration tool. The abort timer is loaded with the contents of the abort timer reload register when the JSI alarm is generated. The abort timer reload value is specified in units of CPU clock ticks. Table 6-5. Offset : 0x000C Bit position Field name Note 31:16 Unused Abort Timer Reload Register 15:0 Abort timer reload value
Abort Timer Reload Register (ABO_RLR)

Accesses to the abort timer reload register are performed by microcode in trusted mode. Memory

protection logic, if implemented, should only allow access to this register when trusted mode is active (i.e., T/Un is asserted high). 6.4.1.4. Prescalar Reload Register

The prescalar reload register is used exclusively by the aJ-200 microcode to establish the clocking rate of the JSI timer and the JVM specific timer/counters. The prescalar is a continuous count-down timer that is driven by the CPU clock and generates a clock pulse for other timers upon reaching the zero count. Thereupon, the prescalar is automatically reloaded with the prescalar reload value to continue with the next count-down interval. The prescalar reload register is initialized by the aJ-200 microcode during reset IDB processing using the clock interval specified via the JEM Builder configuration tool. The prescalar reload value is specified in units of CPU clock ticks.

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Technical Reference Manual Table 6-6. Prescalar Reload Register Prescalar Reload Register (PSCL_RLR) 31:16 15:0 Unused Prescaler reload value

Offset : 0x0010 Bit position Field name

Note: Accesses to the prescalar reload register are performed by microcode in trusted mode. Memory protection logic, if implemented, should only allow access to this register when trusted mode is active (i.e., T/Un is asserted high). 6.4.1.5. JSI Alarm Register

The JSI alarm register is used exclusively by the aJ-200 microcode to establish the execution time slice for the activated JVM. The JSI timer is a continuous count-up timer that is driven by the prescalar clock and generates the JSI interrupt when the counter matches the JSI alarm value. Thereupon, the JSI timer is automatically reset to zero and continues counting. The JSI alarm register is loaded by the aJ-200 microcode during the activation of a JVM. The JVM execution time interval (JSI alarm value) is setup using the JEM Builder configuration tool. The JSI alarm value is specified in units of prescalar ticks. Table 6-7. Offset : 0x0014 Bit position Field name 31:16 Unused JSI Alarm Register 15:0 JSI alarm value

JSI Alarm Register (JSI_ALARM)

Note: Accesses to the JSI alarm register are performed by microcode in trusted mode. Memory protection logic, if implemented, should only allow access to this register when trusted mode is active (i.e., T/Un is asserted high). 6.4.1.6. Timer Mode Register

The timer mode register is used exclusively by the aJ-200 microcode to setup the MJM timers. The timer mode register is initialized during reset IDB processing depending on the configuration specified with the JEM Builder configuration tool. Table 6-8. Offset : 0x0018 Bit position Field name Prescaler enable 0 Disable Prescaler 1 Enable prescaler Abort enable 0 Disable abort timer 1 Enable abort timer
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Timer Mode Register 15:0 JSI enable Unused Abort Enable JSI alarm value Prescaler enable

Timer Mode Register (TMODE)

31:3 Unused

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Technical Reference Manual JSI enable 0 Disable JSI timer 1 Note: Enable JSI timer Accesses to the timer mode register are performed by microcode in trusted mode. Memory

protection logic, if implemented, should only allow access to this register when trusted mode is active (i.e., T/Un is asserted high). 6.4.1.7. JSI Timer Register

The read-only JSI timer register is used exclusively by the aJ-200 microcode to provide deterministic JVM scheduling. The JSI timer is a continuous count-up timer that is driven by the prescalar clock and generates the JSI interrupt when the counter matches the JSI alarm value. Upon reaching the JSI alarm value, the JSI timer is automatically reset to zero and continues counting. The JSI timer value is read in units of prescalar ticks. The JSI interrupt is handled by the aJ-200 microcode to perform a context switch to the next JVM. The JSI timer also triggers a watch dog timer (abort timer) to ensure the interrupt is acknowledged. Table 6-9. Offset : 0x001C Bit position Field name 31:16 Unused JSI Timer Register 15:0 JSI timer value
JSI TIMER Register (JSI)

Note: Accesses to the JSI timer register are performed by microcode in trusted mode. Memory protection logic, if implemented, should only allow access to this register when trusted mode is active (i.e., T/Un is asserted high). 6.4.1.8. Piano Roll Timer 0 Reload Register

The piano roll timer 0 reload register specifies the time interval when the piano roll is updated (periodic thread activation) for the JVM 0 context. The piano roll 0 timer is a continuous count-down timer that is driven by the prescalar clock, and generates the PTO interrupt upon reaching the zero count. Thereupon, the piano roll timer 0 is automatically reloaded with the piano roll timer 0 reload value to continue with the next count-down interval. The PTO interrupt is handled by the aJ-100 microcode during JVM 0 s execution to update the piano roll index and activate any readied periodic thread. The piano roll timer 0 reload register is setup by the aJ-200 runtime system during the initialization of JVM 0. The piano roll timer 0 reload value is specified in units of prescalar ticks. Table 6-10. Offset : 0x0020 Bit position
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Piano Roll Timer 0 Reload Register (PRT_RL0)

31:16

Technical Reference Manual Field name 6.4.1.9. Unused Clock Timer 0 Reload Register Piano roll timer 0 reload value

The clock timer 0 reload register specifies the time interval when the clock timer is updated (thread sleep queue) for the JVM 0 context. The clock timer is a continuous count-down timer that is driven by the prescalar clock and generates the TCO interrupt upon reaching the zero count. Thereupon, the clock timer 0 is automatically reloaded with the clock timer 0 reload value to continue with the next count-down interval. The TCO interrupt is handled by the aJ-200 microcode during JVM 0s execution to update the thread sleep queue and activate any readied threads. The clock timer 0 reload register is setup by the aJ-200 runtime system during the initialization of JVM 0. The clock timer 0 reload value is specified in units of prescalar ticks. Table 6-11. Offset : 0x0024 Bit position Field name 6.4.1.10. 31:16 Unused Clock Timer 0 Reload Register 15:0 Clock timer 1 reload value
Clock Timer 0 Register (CT0)

JVM 0 Timer Enable Register

The JVM 0 timer enable register is used to setup the JVM 0 specific timers. The JVM 0 timer enable register is initialized by the aJ-200 runtime system depending on the configuration specified with the JEM Builder configuration tool. Table 6-12. JVM 0 Timer Enable Register Timer Mode Register (TMODE) 31:2 1 0 Unused Clock timer 0 enable Piano roll timer 0 enable

Offset : 0x0028 Bit position Field name

Clock timer 0 enable 0 1 0 1 Disable clock timer 0 Enable clock timer 0 Disable piano roll timer 0 Enable piano roll timer 0 Piano Roll Timer 0 Register

Piano roll timer 0 enable

6.4.1.11.

The piano roll timer 0 register is used to provide deterministic periodic thread scheduling for the JVM 0 context. The piano roll 0 timer is a continuous count-down timer that is driven by the prescalar clock and generates the PTO interrupt upon reaching the zero count. Thereupon, the piano roll timer 0 is automatically reloaded with the piano roll timer 0 reload value to continue with the next count-down interval.
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Technical Reference Manual The piano roll timer 0 value is read in units of prescalar ticks. The PTO interrupt is handled by the aJ-200 microcode during JVM 0 s execution to update the piano roll index and activate any readied periodic thread. Table 6-13. Offset : 0x002C Bit position Field name 6.4.1.12. 31:16 Unused Piano Roll Timer 0 Register 15:0 Piano roll timer 0 value
Piano Roll Timer 0 Register (PRT0)

Clock Timer 0 Register

The clock timer 0 register is used to provide the 1 millisecond clock tick for the JVM 0 context. The clock timer is a continuous count-down timer that is driven by the prescalar clock and generates the TCO interrupt upon reaching the zero count. Thereupon, the clock timer 0 is automatically reloaded with the clock timer 0 reload value to continue with the next count-down interval. The clock timer 0 value is read in units of prescalar ticks. Table 6-14. Offset: 0x0030 Bit position Field name 6.4.1.13. 31:16 Unused Clock Timer 0 Register 15:0 Clock Timer 0 value

Clock Timer 0 Register (CT0)

Piano Roll Timer 1 Reload Register

The piano roll timer 1 reload register specifies the time interval when the piano roll is updated (periodic thread activation) for the JVM 1 context. The piano roll 1 timer is a continuous count-down timer that is driven by the prescalar clock, and generates the PTO interrupt upon reaching the zero count. Thereupon, the piano roll timer 1 is automatically reloaded with the piano roll timer 1 reload value to continue with the next count-down interval. The PTO interrupt is handled by the aJ-200 microcode during JVM 1 execution to update the piano roll index and activate any readied periodic thread. The piano roll timer 1 reload register is setup by the aJ-200 runtime system during the initialization of JVM 1. The piano roll timer 1 reload value is specified in units of prescalar ticks. Table 6-15. Offset: 0x0034 Bit position Field name 6.4.1.14. 31:16 Unused Piano Roll Timer 1 Reload Register 15:0 Piano roll timer 1 reload value
Piano Roll Timer 1 Reload Register (PRT_RL1)

Clock Timer 1 Reload Register

The clock timer 1 reload register specifies the time interval when the clock timer is updated (thread sleep queue) for the JVM 1 context. The clock timer is a continuous count-down timer that is driven by the prescalar clock, and generates the TCO interrupt upon reaching the zero count. Thereupon, the clock

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Technical Reference Manual timer 1 is automatically reloaded with the clock timer 0 reload value to continue with the next count-down interval. The TCO interrupt is handled by the aJ-200 microcode during JVM 1 execution to update the thread sleep queue and activate any readied threads. The clock timer 1 reload register is setup by the aJ200 runtime system during the initialization of JVM 1. The clock timer 1 reload value is specified in units of prescalar ticks. Table 6-16. Offset : 0x0038 Bit position Field name 6.4.1.15. 31:16 Unused Clock Timer 1 Reload Register 15:0 Clock timer 1 reload value

Clock Timer 1 Reload Register (CT_RL1)

JVM 1 Timer Enable Register

The JVM 1 timer enable register is used to setup the JVM 1 specific timers. The JVM 1 timer enable register is initialized by the aJ-200 runtime system depending on the configuration specified with the JEM Builder configuration tool. Table 6-17. Offset : 0x003C Bit position Field name 31:2 Unused JVM1 Timer Enable Register 1 Clock timer 1 enable 0 Piano roll timer 1 enable

JVM1 Timer Enable Register (TMR_EN1)

Piano roll timer 1 enable 0 1 0 1 6.4.1.16. Disable piano roll timer 1 Enable piano roll timer 1 Disable clock timer 1 Enable clock timer 1 Piano Roll Timer 1 Register

Clock timer1 enable

The piano roll timer 1 register is used to provide deterministic periodic thread scheduling for the JVM 1 context. The piano roll 1 timer is a continuous count-down timer that is driven by the prescalar clock. and generates the PTO interrupt upon reaching the zero count. Thereupon, the piano roll timer 1 is automatically reloaded with the piano roll timer 1 reload value to continue with the next count-down interval. The piano roll timer 1 value is read in units of prescalar ticks. The PTO interrupt is handled by the aJ-200 microcode during JVM 1 execution to update the piano roll index and activate any readied periodic thread. Table 6-18. Piano Roll Timer 1 Register Piano Roll Timer 1 Register (PRT1) 31:16 15:0

Offset : 0x0040 Bit position

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Technical Reference Manual Field name 6.4.1.17. Unused Clock Timer 1 Register Piano roll timer 1 value

The clock timer 1 register is used to provide the 1 millisecond clock tick for the JVM 1 context. The clock timer is a continuous count-down timer that is driven by the prescalar clock. and generates the TCO interrupt upon reaching the zero count. Thereupon, the clock timer 1 is automatically reloaded with the clock timer 1 reload value to continue with the next count-down interval. The clock timer 1 value is read in units of prescalar ticks. The TCO interrupt is handled by the aJ-200 microcode during JVM 1 execution to update the thread sleep queue and activate any readied threads. Table 6-19. Clock Timer 1 Register Clock Timer 1 Register (CT1) 31:16 15:0 Unused Clock timer 1 value

Offset 0x0044 Bit position Field name

6.4.2. Interrupt Controller The aJ-200 supports 32 falling-edge activated, asynchronous, mask-able, prioritized interrupts. Some of these interrupts may be used by logic integrated with the JEMCore-II processor core and others devoted to integrated peripheral devices and GPI/O pins. The four highest priority interrupts are non-maskable including an external NMI available to the application. The interrupt assignments are summarized in table 40. Servicing the interrupt controller is entirely controlled by aJ-200 s executive microcode. Upon recognition of an interrupt, the microcode will interrogate the interrupt controller for the highest priority interrupt. (Note: interrupt #0 is the highest priority interrupt.) The highest priority interrupt is cleared and the interrupt is either serviced internally (via microcoded interrupt handler) or the assigned software interrupt handler is invoked. (Interrupt handlers are assigned using the JEM Builder system build/configuration tool.) Priority Level 0 (Highest) aJ-200 Interrupt Assignments Name Description Transfer error (XERR) Non-maskable interrupt generated by external memory protection logic, when a memory access is attempted outside of the JVMs enabled memory space. MJM memory protection must be enabled to allow this interrupt generation. This interrupt is handled internally by the aJ-200s executive microcode and is fatal to the current JVM context. Power down warning Non-maskable interrupt generated by external logic to (PDW) signal power is going away. The power down handler for each JVM is checked and invoked if present to prepare for power interruption and halt the JVM. JVM switch interrupt (JSI) Non-maskable interrupt generated by the internal JSI
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Table 6-20.

2
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Technical Reference Manual timer to signal the context switch to the next JVM environment. This interrupt is handled internally by the aJ-200s executive microcode which performs the context switch to the next JVM. Non-maskable interrupt generated by the FIR of the peripheral interrupt controller (PINTC) Maskable interrupt (JVM specific) generated internally when an arithmetic error is detected during instruction execution. Arithmetic errors include integer arithmetic overflows (number cant be represented in the data type) and the detection / generation of floating point NaNs and infinities. (Note that Java only supports divide by zero detection.) Arithmetic error detection can be enabled for either JVM0 and/or JVM1. Maskable interrupt (JVM specific) generated internally when the internal timer/counter counts down to zero. The timer/counter alarm can be enabled for either JVM 0 and/or JVM 1. This interrupt is handled internally by the aJ-200s executive microcode to update the JVM specific sleep queue. Maskable interrupt (JVM specific) generated internally when the internal piano roll timer counts down to zero. The piano roll alarm can be enabled for either JVM 0 and/or JVM 1. This interrupt is handled internally by the aJ-100s executive microcode to update the JVM specific piano roll for periodic thread scheduling Standard interrupt request (IRQ) SSP interrupt request AES interrupt request I2S/AC97/SPI interrupt request UART3 interrupt request UART1 interrupt request UART2 interrupt request UART4/IrDA FIR request UART4/IrDA interrupt request GPIOA interrupt request GPIOB interrupt request GPIOC interrupt request Watch dog timer or RTC interrupt request LCD interrupt request DMA interrupt request APB bridge interrupt request Ethernet interrupt request

3 4 5

NMI Reserved Arithmetic error (OVR)

6 7

Reserved Timer/counter output (TCO)

Piano roll timer output (PTO)

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Reserved Peripheral standard interrupt request (IRQ) SSP interrupt request AES interrupt request I2S/AC97/SPI interrupt request UART3 interrupt request UART1 interrupt request UART2 interrupt request IrDA Interrupt 2 IrDA Interrupt 1 GPIOA_intr GPIOB_intr GPIOC_intr WDT_intr LCD_intr DMA_intr APB_intr Ethernet_intr

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Technical Reference Manual 27 28 29 30 31 6.4.2.1. USB_intr Timer/counter0_intr Mediacodec_intr Vcap_intr Vcap_ov_intr Interrupt Level Translation USB OTG interrupt request Timer/counter 0 interrupt request Media codec interrupt request Video capture interrupt request Video capture pdma and rdma

The aJ-200 allows the user to declare the priority level of each internal interrupt source. The aJ-200 interrupt architecture assigns interrupt 0 as the highest priority interrupt. Interrupts 0 through 9 are reserved for use by the Multiple JVM logic. The internal peripherals may be assigned a priority from 10 to 31 via the individual interrupt level translation registers. JEM Builder may be used to specify the interrupt levels. This will cause the level translation registers to be initialized as part of the aJ-200 reset process.

Address(Table6-22) 0 1

Table 6-21. JEMBuilder Interrupt Level Assignment Table 6-22. Interrupt Translation Registers Interrupt Translation Registers 31:4 3:0 Unused ILVL

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Technical Reference Manual Table 6-23. Offset 0x0200 0x0204 0x0208 0x020C 0x0210 0x0214 0x0218 0x021C 0x0220 0x0224 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C 0x0240 0x0244 0x0248 0x024C 0x0250 0x0254 0x0258~0x0278 0x027C 6.4.2.2. Name PINTRO_ILTR SSP_ILTR AES_ILTR I2S_AC97_SPI_ILTR UART3_ILTR UART1_ILTR UART2_ILTR UART4_FIR_ILTR UART4_ILTR GPIOA_ILTR GPIOB_ILTR GPIOC_ILTR WDT_RTC_ILTR LCD_ILTR DMA_ILTR APB_ILTR ETHERNET_ILTR USB_ILTR TIMER0_ILTR MEDIACODEC_ILTR VCAP_ILTR VCAP_OV_ILTR Reserved PIR Interrupt Controller Register Summary Description Peripheral interrupt output interrupt level translation(IRQ) SSP Interrupt Level Translation AES interrupt level translation I2C_AC97_SPI interrupt level translation UART3 interrupt level translation UART1 interrupt level translation UART2 interrupt level translation UART4 FIR interrupt level translation UART4 interrupt level translation GPIOA interrupt level translation GPIOB interrupt level translation GPIOC interrupt level translation WDT or RTC interrupt level translation LCD interrupt level translation DMA interrupt level translation APB interrupt level translation Ethernet interrupt level translation USB OTG interrupt level translation TIMER0 interrupt level translation MediaCodec interrupt level translation Video capture interrupt level translation Video capture overlay interrupt level translation Pending Interrupt register

Pending Interrupt Register

The pending interrupt register is used exclusively by the aJ-200 microcode to identify the highest priority pending interrupt and initiate the interrupt service routine. (Note: interrupt #0 is the highest priority interrupt.) The highest priority pending interrupt is cleared and the interrupt is either serviced internally (via microcoded interrupt handler) or the assigned software interrupt handler is invoked. (Interrupt handlers are assigned using the JEM Builder system build/configuration tool.) Offset: Bit positions Field name Table 6-24. Pending Interrupt Register Interrupt Translation Registers 31:26 25:0 Unused Interrupt bit field

Note: Accesses to the pending interrupt register are performed by microcode in trusted mode. Memory protection logic, if implemented, should only allow access to this register when trusted mode is active (i.e., T/Un is asserted high).

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Technical Reference Manual 6.5. Custom Instructions

The aJ-200 enables the use of custom microcode to implement new instructions. The new instructions can significantly increase the performance of frequently used algorithms. These instructions are downloaded into the 32 KB WCS from an external FLASH on the power-on-reset (POR). The power of custom instructions is reflected in the threading instructions of the JEMCore-II. For example, the yield instruction results in a thread-to-thread switch of less than one microsecond, while a typical RTOS written in a high level language that may take several milliseconds. For an example of where a custom instruction could be used consider the square root method in java.lang.Math. This method could be implemented with microcode and initiated via an instruction. When processing a class file, the aJile tools will replace invokes of java.lang.Math.sqrt with the custom sqrt instruction. The performance advantage of a custom instruction varies from 5x for simple algorithms to 50x for complex algorithms. 6.6. Instruction and Data Cache (I & D Cache)

The JEMCore-II cache unit contains a unified cache with an AHB interface. It supports the following features: 32 KB unified cache 16-deep cache line 2-way set associative Write-through 4-word burst access on read misses AMBA AHB master interface, AMBA slave APB interface

6.6.1. Register Description The initial configuration of the cache is performed using the JEM Builder configuration and application build tool. JEM Builder will automatically generate the initialization data used by the aJ-200 during the reset initialization sequence. These register are maintained by special microcode and should be hidden or abstracted from application software. The initial settings are configured by JEM Builder configuration tool. Table 6-25. Acronym CCR0 CCR1 Register Summary Description Cache configuration register Cache control register

Offset 0x0050 0x0054 6.6.1.1.

Bits 32 32

Cache Configuration Register 0 (CCR0) Table 6-26. Cache configuration register 0 (CCR0) Name Cache configuration register (CCR0) Field name Reserved 122 5/5/2010 Version 2.1

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Technical Reference Manual 29:28 27 26:24 23:20 19 16 15 14 13:6 18:16 15:4 3 2:0 6.6.1.2. LRR SN SETS SSIZE LR IB IP DP Reserved LSIZE Reserved M Reserved Cache replacement policy. 10 Least recently replaced (LRR) Cache snooping. Set if snooping is implemented Cache associativity. 001 Two-way associative Set size. Indicates the size in Kbytes of each cache set Set high Instruction burst fetch. This bit enables burst fill during instruction fetch Instruction cache flush pending. This bit is set when an instruction cache flush operation is in progress Data cache flush pending. This bit is set when an data cache flush operation is in progress Indicates the line size of each cache line Set to 0 -

Cache Control Register (CCR1)

The Cache Control register is maintained by special microcode and should be hidden or abstracted from application software. The initial settings are configured by JEM Builder configuration tool. Table 6-27. Cache Control Register Cache Control Register 1 (CACR1) Name Name Reserved DS Data cache snoop enable. If set, will enable data cache snooping FD Flush data cache. If set, will flush the data cache. Always reads as zero FI Flush instruction cache. If set, will flush the instruction cache. Always reads as zero Reserved IB Instruction burst fetch. This bit enables burst fill during instruction fetch IP Instruction cache flush pending. This bit is set when an instruction cache flush operation is in progress DP Data cache flush pending. This bit is set when an data cache flush operation is in progress Reserved DF Data cache freeze on interrupt. If set, the instruction cache will automatically be frozen when an asynchronous interrupt is taken IF Instruction cache freeze on interrupt. If set, the instruction cache will automatically be frozen when an
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Technical Reference Manual asynchronous interrupt is taken Data cache state. Indicates the current data cache state as follows: x0 Disabled 01 Frozen 11 Enabled Instruction cache state. Indicates the current instruction cache state as follows: x0 Disabled 01 Frozen 11 Enabled

3:2

DCS

1:0

ICS

6.6.2. Functional Description 6.6.2.1. Reset

After the assertion of hardware reset the cache must undergo a microcode reset sequence. During the cache reset sequence, the microcode performs any necessary cache testing, invalidates each cache entry, and then initializes each control register. A hardware reset will set all the cache control registers to zero. However, the SRAM contents of each cache entry in unknown after a hardware reset. Most importantly the valid bit of each cache entry is unknown after a hardware reset. The microcode needs to clear the valid bit (V-bit) of each cache entry before normal cache operation can begin after each reset. A simple way for the microcode to invalidate each cache entry is to write a 32-bit 0 to each locations, thereby clearing the valid bit, tag portion, and data portion of each cache entry. After invalidating each cache entry, the microcode initializes the cache control registers. 6.6.2.2. Enable/Disable

The microcode can enable or disable caching of instruction and/or data accesses at any time by setting the Instruction Cache State and Data Cache Sate of the CACR1 register respectively. A hardware reset will clear these enable bits to 0, thereby disabling caching of both instruction and data accesses. Therefore, to enable caching after reset, microcode must set either of these bits, or both. Microcode can set or clear these bits at any time. In addition to a reset routine, microcode might adjust these bits upon entering and exiting interrupt service routines.

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Technical Reference Manual

31 Tag 14 13 Index 4 3 2 1 0

Line size

Word offset Cachce DI [31:0]

Associative Set #1 1024 x 151 bits 150 LRR 18 V3 V2 V1 V0 145 TAG 128 127 Data 0 10

LRR

V3

V2

V1

V0

TAG 18 Tag Comparator

Data

32 V Comparator Cachce DO [31:0]

2:1

Encoder 32 V Comparator

Tag Comparator

150 LRR V3 V2 V1 V0

145 TAG

128

127 Data

150 LRR V3 V2 V1 V0

145 TAG

128

127 Data

Associative Set #2 1024 x 151 bits

Figure 6-4. 6.6.3. Bus Interface

Cache Organization

The JEMCore-II has both AHB and APB interface. The JEMCore-II is a master on the AHB. All JEMCore-II data and instruction accesses use the AHB. In addition, any memory-mapped resources internal to the

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Technical Reference Manual JEMCore-II are accessed through the APB interface. So, if the JEMCore-II accesses its internal memorymapped resources, it must initiate the transfer over the AHB to the APB bridge to the APB interface. And any return data must travel back through the APB bridge to the AHB, and then back to the JEMCore. 6.7. Test Interface The aJ-200 provides a test interface that is compliant with the IEEE 1149.1 boundary scan standard. This scan interface is commonly referred to as a JTAG interface. An overview of the test architecture is shown in below figure

Figure 6-5. Test Control Unit The Test Control Unit is accessed via an IEEE 1149.1 boundary scan interface, referred to as the JTAG interface. The JEMCore-II TCU contains the JTAG TAP controller, instruction register, and several data registers. The data registers are used by software development tools (Charade) to exchange information
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Technical Reference Manual with the processor. The TCUs allow for accessing memory and internal registers, CPU halt, CPU run, breakpoints, reset, and monitor operational status. The JEMCore-II provides access to the TCU to enable additional data registers to be placed outside of the JEMCore as illustrated in figure below. Common examples of external data registers would be the boundary scan data resister and the ID register

Figure 6-6. JEMCore-II 1149.1 Interface The current JTAG instruction is available via the jtagInst[3:0] output. The jtagTap-State[3:0] provides the TAP controller state. Using these signals in combination with the TCK and TDI inputs a SOC may easily construct data registers may be constructed. The JTAG instructions are listed Table 6-28. The TAP controller state machine output values are listed in table 6-28. The jemCoreConfiguration.vh file specifies several localparam values associated with the JTAG instructions and TAP controller. The TCU resetOut
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Technical Reference Manual signal should be used to reset the system. The resetOut signal is activated when the software development systems sends a reset command to the JEMCore. This allows a software engineer to easily reset the system from the software development tools. The resetOut signal can not be activated by software that runs on the JEMCore. The timerHalt signal is provided so that other system resources may be halted or paused while the CPU is halted. In general, this signal is only used by the timers internal to the JEMCore. The timerHalt pause the JEMCore system timers while the software developer has the JEMCore halted. Table 6-28. Boundary Scan Instruction Codes JtagTapState JemCoreCofniguration.vh Comment Localparam 00002 JTAG_USER_DEFINABLE_0 Access an external user definable data register. The instruction register encoding of all 0s is generally reserved for the JTAG EXTEST instruction 00012 JTAG_IDCODE_INST The 00012 instruction is defined by the 1149.1 specification to correspond to the IDCODE instruction 00102 JTAG_USER_DEFINABLE_2 Access an external user definable data register 01002 JTAG_USER_DEFINABLE_4 Access an external user definable data register 01012 JTAG_USER_DEFINABLE_5 Access an external user definable data register 01102 JTAG_USER_DEFINABLE_6 Access an external user definable data register 11102 JTAG_USER_DEFINABLE_E Access an external user definable data register 11112 JTAG_BYPASS_INST Access the JEMCore internal bypass register All other instruction encoding (01012, 01112, 10002, 10012, 10102, 10112,11002, 11012) are reserved for access of data registers internal to the JEMCore-II. Table 6-29. Boundary Scan Instruction Codes Tap Controller State JEMCoreCofniguration.vh localparam Test Logic Reset JTAG_TAP_TEST_LOGIC_RESET Run Test/Idle JTAG_TAP_RUN_TEST_IDLE Select DR Scan Capture DR JTAG_TAP_CAPTURE_DR Shift DR JTAG_TAP_SHIFT_DR Exit1 DR Pause DR Exit2 DR Update DR JTAG_TAP_UPDATE_DR Select IR Scan Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR

JTagTapState Value 11112 11002 01112 01102 00102 00012 00112 00002 01012 01002 11102 10102 10012 10112 10002 11012

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Technical Reference Manual 6.7.1. Reset Sequence This section describes the microcode reset sequence, which occurs after a hardware reset, but not until the startEnable signal is negated.

Figure 6-7. Data structure for reset sequence A brief description of these tables is as follows: Initialization Table HW Setup Table This table is the root data structure which is always at location 0. This table provides pointers to BIST signature data and configuration data. The table also defines the internal RAM size / address and the microcode RAM size/address/source. Configuration Table This table contains the settings to be applied to the internal chip select configuration
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Technical Reference Manual registers, the I/O configuration register, and the PLL configuration register. HW Store Table This table is used to store the overall status of the processor. Table entries are also reserved for storing BIST failure results and external RAM test patterns. 6.7.2. Reset Processing Steps Upon reset, the following summarizes the steps taken: 1. Setup configuration registers, 2. Perform BIST check and tests if enabled, 3. Perform external RAM tests, 4. Load microcode RAM, 5. Process reset Initialization Data Blocks (IDB)s, Details of these steps are provided in the following subsections. 6.7.2.1. Configuration register setup

The first entry in the Initialization Table (location 0x0000_0000) is read to retrieve the HW Setup ptr in the Initialization Table is null (=0), then the following information is stored in the HW Store Table and the processor terminates execution in an internal idle loop. Halt Code = 0x11 (Null HW setup ptr) Active VM = 0 The configuration table is found via following the pointers from the HW Setup ptr in the Initialization Table to the Config Table ptr in the HW Setup Table. The configuration table is setup to allow a block copy into the internal configuration registers starting at the internal register address Config Reg Addr and the Table size of 0xB words. Once the configuration registers are programmed, the HW Store ptr in the Initialization Table is checked for null (=0). If the ptr is not null, the Halt code and Active VM ptr fields in the HW StoreTable are initialized to zero to designate initialization in progress. Otherwise the processor terminates execution in an internal idle loop. BIST The BIST Sig ptr in the HW Setup Table is checked to determine if BIST is to be performed. A null pointer indicates that BIST is to be skipped. Otherwise, the BIST Sig ptr points to the 64-bit BIST signature to compare against. There are two basic BIST operations performed when BIST is enabled (1) ALU BIST and (2) internal RAM BIST. These processes are described in the following. ALU BIST The ALU BIST performs a series of operations on a specific data pattern to exercise all possible ALU operations. The resulting signature is compared to the 64-bit pattern stored at BIST Sig ptr. If the ALU BIST is successful, the RAM BIST is performed next. If the ALU BIST fails, then the following information is
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Technical Reference Manual stored in the HW Store Table and the processor terminates execution in an internal idle loop. Halt Code = 0x10 (BIST failure) BIST Fail Code = 1 BIST Fail Sig 1 BIST Fail Sig 2

RAM BIST The RAM BIST performs a simple stuck at 0 / stuck at 1 check of the internal RAM. The Internal RAM Size and Internal RAM Addr fields are extracted from the HW Setup Table to setup the memory test. The memory test checks each location of the specified RAM region via 5 passes of the following test patterns: First pass Fill internal RAM with the test pattern 0x55555555 starting from lowest address to highest address, Second pass Starting from the lowest address, check each location equal to 0x55555555 pattern and write out the complement (0xaaaaaaaa) before advancing to the next location Apply this read/write operation until the highest address is reached, Third pass Starting at the highest address, check each location equal to 0xaaaaaaaa pattern and write out the complement (0x55555555) before advancing to the next location. Apply this read/write operation until the lowest address is reached, Fourth pass Starting from the lowest address, check each location equal to 0x5555555 pattern and write out the complement (0xaaaaaaaa) before advancing to the next location. Apply this read/write operation until the highest address is reached, Fifth pass Starting at the highest address, check each location equal to 0xaaaaaaaa pattern and write out the complement (0x55555555) before advancing to the next location. Apply this read/write operation until the lowest address is reached. Upon successfully completing the RAM BIST, processing continues with the external RAM test. If any failures occur during RAM BIST, the failures are counted and the last failed address is saved. After completing all 5 passes, the following RAM BIST failure results are written to the HW Store Table and the processor terminates execution in an internal idle loop. Halt Code = 0x10 (BIST failure) BIST Fail Code = 3 BIST Fail Sig 1 = # of failures detected BIST Fail Sig 2 = address of last failure detected

External RAM Test The external RAM test is a simple test to check if RAM appears to be operational. There are seven
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Technical Reference Manual locations in the HW Store Table that are tested via writing the following test patterns and reading them back for comparison. RAM test 0 data = 0x0, RAM test 1 data = 0x7FFF8000, RAM test 2 data = 0x80000000, RAM test 3 data = 0x7F807F80, RAM test 4 data = 0x66666666, RAM test 5 data = 0x78787878, RAM test 6 data = 0x55555555,

Upon successfully completing the external RAM test, processing continues with loading the RAM control store. If any failures are detected during external RAM test, the following Halt Code is written to the HW Store Table and the processor terminates execution in an internal idle loop. Halt Code = 0x40 (External RAM test failure) Load Microcode RAM Control Store. At this stage of the reset process, the target system is assumed to be functional. The microcode RAM control store needs to be loaded next before additional processing can continue. The uCode RAM Size, uCode RAM Addr, and uCode RAM ptr fields are extracted from the HW Setup Table to setup the block copy as follows: uCode RAM ptr is the source address (typically 0x100 for aJ-100), uCode RAM Addr is the destination address (0xFF3E0000 for aJ-100), uCode RAM Size is the number of 64-bit microcode words (0x800 for aJ-100).

Process Reset Initialization Data Blocks (IDB)s. The final step in reset processing is initializing the memory and registers defined in the IDB chain. The IDB chain consists of a data blocks formatted as follows:

Figure 6-8. Data Blocks 6.7.3. Data Structure of Initialization Data Blocks (IDBs)

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Technical Reference Manual The IDBs can be used to initialize a region of memory to zero or initialize a memory region. If the 2-bit Type field is encoded as follows: 1 = Copy Size data entries from the IDB (in words) to Dest Addr (30-bit word address) 2 = Zero Size words starting at Dest Addr (30-bit word address)

The IDB chain starts with the Reset IDB ptr in the Initialization Table. If the Reset IDB ptr is null (=0), then the following Halt Code is written to the HW Store Table and the processor terminates execution in an internal idle loop. Halt Code = 0x12 (Null reset IDB ptr) If IDB processing encounters an invalid Type field (=0 or 3), then the following Halt Code is written to the HW Store Table and the processor terminates execution in an internal idle loop. Halt Code = 0x14 (Corrupt IDB) The IDB processing is completed when a null (=0) Next IDB ptr is encountered. At this point, reset processing is complete and the first application (VM) is to be activated. The details of activating a VM are beyond the scope of this document.

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Technical Reference Manual 7. AHB Controller

7.1. General Description The main purpose of an AHB Controller is to provide a mechanism to control the user rights for the AHB. The AHB controller includes an arbiter, a decoder, a multiplexer, and a register slave. The role of the arbiter in an AMBA system is to arbitrate which master has the right to access the bus. Each bus master has a REQUEST/GRANT interface to the arbiter and the arbiter uses a prioritization scheme to decide which AHB master is currently the highest priority master requesting the bus. The decoder in an AHB system is used to perform a centralized address decoding to select all integrated peripherals based on the system memory map. The multiplexer is used to route the control signals and write data from the masters to the slaves. It also routes the response signals and reads data from the slaves to the masters. The register slave contains some registers. Users can change the function of the AHB controller by programming these registers. It supports the following features

AMBA 2.0 compliant 32-bit AHB data bus Two-level round-robin priority arbitration Round-robin arbitration

The block diagram is shown in the figure below

AHB Master 0 Dummy Master AHB Master 1 APB Bridge AHB Master 3 DMA AHB Master 4 Ethernet AHB Master 5 JEMCore AHB Master 6 AES Engine AHB Master 7 USB OTG AHB Master 8 DMA Slave AHB Master 9 LCD AHB Master 11 Video Capture Register Channel

Arbiter

Register

MUX

Decoder

AHB Slave 0

AHB Slave 1

AHB Slave 18

Figure 7-1. Block Diagram of AHB Controller The AHB Controllers main building blocks are the arbiter, decoder and multiplexer. The following sections contain detailed descriptions of each building block.

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Technical Reference Manual 7.2. Arbiter The main function of the arbiter is to arbitrate data access requests from the AHB Master. If the masters requests are issued simultaneously, the arbiter uses a prioritized scheme to decide which bus master currently has the highest priority. The arbiter supports both multi-level and round robin functions. The multi-level supports a two-level algorithm, level 1 and level 0. Level 1 has a higher priority than level 0. When level 1s masters and level 0s masters simultaneously request the bus, the bus always grants the bus to levels 1 masters first. The round robin algorithm makes the currently granted master the lowest priority master in the next arbitration on the same level. All masters can be programmed to level 1 or level 0. 7.3. Register Slave The register slave includes several control registers of the AHB controller. Users can program these registers for specific system requirements via the AHB register port. The HSIZE should be WORD (3b2) when accessing registers if the system operates in the big-endian mode. 7.4. Decoder The decoder in an AMBA system is used to perform a centralized address decoding function. The main function of this block is to generate each AHB devices select signal, when the arbiter grants the bus to a master. The decoder decodes the masters address command, and then sends a select signal to the device that the master is accessing. 7.5. Multiplexer (MUX) The main function of this block is to serve as a multiplexer. All AHB masters signals grant multiplex to AHB slaves, and all AHB slaves response signals also select multiplex to AHB. 7.6. Programming Model

The following table shows the summary of the AHB Controller Registers Table 7-1. Summary of the AHB Controller Registers Offset address Type Description Reset Value Description +0x00 R/W AHB Slave 0 Base/Size Register 0x9010_0000 AHB +0x04 R/W AHB Slave 1 Base/Size Register 0x9050 0000 APB-to-AHB bridge +0x08 R/W AHB Slave 2 Base/Size Register 0x9800 0000 APB devices +0x0C R/W AHB Slave 3 Base/Size Register 0x9020 0000 SMC +0x10 R/W AHB Slave 4 Base/Size Register 0x0000 0000 SRAM/ROM/FLASH +0x14 R/W AHB Slave 5 Base/Size Register 0x9030 0000 SDMC registers +0x18 R/W AHB Slave 6 Base/Size Register 0x1000 0000 SDMC memory +0x1C R/W AHB Slave 7 Base/Size Register 0x9040 0000 DMAC +0x24 R/W AHB Slave 9 Base/Size Register 0x9060 0000 LCD +0x30 R/W AHB Slave 12 Base/Size Register 0x9090 0000 MAC +0x34 R/W AHB Slave 13 Base/Size Register 0x90A0 0000 AES +0x38 R/W AHB Slave 14 Base/Size Register 0x9080 0000 USB OTG
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Technical Reference Manual Offset address +0x3C +0x40 +0x44 +0x48 +0x4C +0x50 +0x54 +0x58 +0x80 +0x84 +0x88 Type R/W R/W R/W R/W R/W R/W R/W R/W Description AHB Slave 15 Base/Size Register Reserved AHB Slave 16 Base/Size Register AHB Slave 17 Base/Size Register AHB Slave 18 Base/Size Register Reserved AHB Slave 19 Base/Size Register Reserved Priority Control Register Idle Count Register Control Register Reset Value 0x90B0 0000 0x9070 0000 0x90C0 0000 0x9200 0000 0xA008 0000 0x0000 0000 0x0000 0000 0x0000 0000 Description EBI MediaCodec Video capture

7.6.1. Register Descriptions The following subsections describe the AHB controller registers in more detail. 7.6.1.1. Bit 31-20 AHB Slave n Base/Size Register (Offset == 0x00 ~ 0x58) Table 7-2. AHB Slave 0 Base/Size Register Name Type Description BaseAddr R/W Base Address [31:20] Size of Address Space is decoded as follows: SizeAddrr[19:16] Address space 0000 1M 0001 2M 0010 4M 0011 8M 0100 16M SizeAddr R/W 0101 32M 0110 64M 0111 128M 1000 256M 1001 512M 1010 1024M 1x11 Reserved --Reserved The BaseAddr/SizeAddr bits of all the slaves have the same format and the same definition

19-16

15-0 Notes:

as the bit fields. The reset value of the slave n is defined by (AHB_SLVn_BASE | AHB_SLAVEn_SIZE), where AHB_SLVn_BASE and the AHB_SLAVEn_SIZE are hardware-configured variables. The setting value of the base address must be a multiple of the space size setting value. For example, if the base address of [31: 20] is set to 0x002, it means the base address is 2M. Therefore, the space size must be 1M or 2M. That is to say, the space size must be 0 or 1. 7.6.1.2. Priority Control Register (Offset == 0x80)

The arbiter supports a two-level mechanism to arbitrate master requests. Each master can be

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Technical Reference Manual programmed to higher level or lower level. Table 7-4 shows the bit assignment of the priority control register Bit 31-16 15-1 0 Name -PLevel -Table 7-3. Priority Control Register Type Description -Reserved Bit n represents the level of master n. R/W 1: Higher level 0: Lower level -Reserved

The following table lists the mappings of AHB masters and Request / Grant pairs. Table 7-4. 11 10 9 8 7 6 5 4 3 2 1 0 7.6.1.3. AHB Master Request Routing Table Video capture Mediacodec LCD controller DMA Slave USB OTG AES JEMCore-II Ethernet controller DMA Master Reserved APB Bridge Dummy Master

Idle Control Register (Offset == 0x84)

The idle count means the maximum idle command cycles before the re-arbitration when a master is granted. The arbiter will re-arbitrate if a granted master doesnt issue a NON-SEQ command within the idle count period. Bit 31-6 5:0 7.6.1.4. Bit 31-25 24 Name -Idle count Table 7-5. Transfer Control Register Type Description -Reserved. R/W This parameter specifies the idle count cycles

Control Register (Offset == 0x88) Table 7-6. Interrupt Control Register Name Type Description --Reserved Interrupt Status IntrSts R/W 0: Interrupt does not occur 1: Interrupt occurs

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Technical Reference Manual Bit 23-22 Name -Type -Description The interrupt is cleared by writing zero to the register bit. Reserved Response Status. When decoder receives a non-existing address, the decoder responds to the register. 00 OK response 01 ERROR response (default) 10 RETRY response 11 Not Allowed Reserved Interrupt Mask. Enable and disable when default slave is selected. 0 Disable 1 Enable Burst length of INCR . When a master issues an INCR command, the arbiter will grant the master to transfer a total amount of (INCR+1) bursts. The default value is 0xF. Setting to 0 is not allowed. INCR Length Burst Length 0x1 0x2 0x2 0x3 0x3 0x4 0x4 0x5 0xff 0x100 Reserved Remap function, switch the base addresses of slave 4 and slave 6 1 Activate remap function. After applying the remap function, the new base address of slave 6 = the original base address of slave 4. The new base address of slave 4 = the original base address of slave 4 + the space size of slave 6. Note that the base address should be the boundary of the space size.

21-20

Response

R/W

19-17 16

-IntsMask

-R/W

15-8

INCRLenght

R/W

7-1

Remap

R/W

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8. DMA Controller (DMAC)

8.1. Overview The DMA controller is used to enhance the system performance, which allows the high-speed data transfer among the system and I/O devices without the processor intervention. The DMAC provides up to eight channels for memory-to-memory, memory-to-peripheral, peripheral-to-peripheral, and peripheral-tomemory transfer with the shared buffer. It supports the following features Memory-to-memory, memory-to-peripheral, peripheral-to-peripheral, peripheral-to-memory transfers Group Round Robin arbitration scheme with four priority levels Chain transfer 8/16/32-bit data width transaction 8-deep FIFO buffer

Figure below illustrates the functional block diagram of the DMA controller.

AHB Bus 0

AHB Master 0

AHB Slave

8-deep FIFO

DMA Core

Prioritizing Arbiter

Figure 8-1. 8.2. DMA Routing Table

DMA Controller Functional Block Diagram

The DMA source assignment of DMA [15:0] is shown in below table Table 8-1. DMA Routing Table Devices Reserved SD controller IrDA DMA channel IrDA receive channel IrDA transmit channel
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DMA Request and Acknowledge Signals 15 14 13 12 11

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Technical Reference Manual DMA Request and Acknowledge Signals 10 9 8 7 6 5 4 3 2 1 0 Devices UART3 receive channel UART3 transmit channel UART2 receive channel UART2 transmit channel UART1 receive channel UART1 transmit channel I2S/AC97/SPI receive channel I2S/AC97/SPI transmit channel SSP receive channel SSP transmit channel CF controller

The DMA controller consists of four main building blocks: Two AHB master interfaces, an AHB slave interface, a FIFO buffer, and a DMA core. 8.2.1. AHB Master Interface The DMA controller has two AHB master interfaces. They can transfer data between the system and the DMA FIFO. 8.2.2. AHB Slave Interface The DMA controller has a slave interface. The system can configure the DMA controller through this AHB slave interface. 8.2.3. FIFO Buffer The 8-deep FIFO buffer provides the buffer between the source and the destination. 8.2.4. DMA Core The DMA core is an eight-channel DMA engine. It supports data transfers between the two AHB interfaces. Each channel can be assigned a group priority level and channels on the same group priority are serviced in a round robin fashion. 8.3. Programming Model 8.3.1. General Description The DMA controller consists of up to eight DMA channels, a DMA engine, and a channel prioritizing arbiter. 8.3.2. Prioritizing Arbiter The DMA controller uses the 4-group priority and the round-robin scheme to select the next channel to serve. Arbitration is based on the priority level for each channel. But if the channels are on the same priority level, the arbitration will be performed in the round robin way. Each channel has a 2-bit priority value associated with it. A value of 3 indicates the highest priority level and a value of 0 indicates the lowest priority as shown in the Figure 8-2.
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Technical Reference Manual

Ch.0

Prioriting Arbiter

Ch.n

Priority 0 (lowest priority)

Ch.1

Ch.0 Priority 1 Ch.n MUX Ch.1 Next Channel

Priority 3 (highest priority)

Ch.0

Ch.n

Ch.1

Figure 8-2. 8.3.3. Chain Transfer

Arbitration Scheme

The DMA controller provides the chain transfer function. A specified block of data can be transferred consecutively without CPU processing after the end of the current data transfer. For each channel, after TOT_SIZE (designated in the Cn_SIZE) is transferred, the DMA will check whether linked list descriptor pointer (Cn_LLP) is zero or not. If it is not zero, before the next data transfer, the DMA controller will fetch the next channel link list descriptor from the memory attached to the AHB master interface 0 or AHB master interface 1 depending on the channel control status register (Cn_LLP [0]). The chain transfer operation is shown in the figure 8.3

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Cn_LLP

SrcAddr DstAddr LLP Control/TOT_SIZE

SrcAddr DstAddr LLP Control/TOT_SIZE

SrcAddr DstAddr LLP Control/TOT_SIZE

Figure 8-3. Chain Transfer Operation To configure the DMA controller for the chain transfer, refer to the program sequence in the appendix for detailed descriptions.
Source Address(SrcAddr) Destination Address(DstAddr) Linked List Pointer(LLP) Control TOT_SIZE

Reserved

Figure 8-4. Linked List Descriptor Each time the DMA controller fetches the Linked List Descriptor, SrcAddr is copied to the Cn_SrcAddr register, DstAddr is copied to the Cn_DstAddr register, LLP is copied to the Cn_LLP register, Total Transfer Size is copied to the TOT_SIZE field in the Cn_SIZE register, and Control is copied to in the Cn_CSR register. Detailed definition of the linked list descriptor is shown in tables 8.2 ~ 8.4 Table 8-2. Offset +0 +4 +8 +C Address Map for Linked List Descriptor (Base: Cn_LLP [31:2]) Width Description 32 Source Address 32 Destination Address 32 Linked List Pointer 32 Control and Total Transfer Size

Name SrcAddr DstAddr LLP Control

Bit 31:29 28 27-25 24-22 21-20

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Table 8-3. Control Field Definition in the Linked List Descriptor. Description DMA_FF_TH: DMA FIFO threshold value (Same as DMA_FF_TH in Cn_CSR TC_MSK: Channel terminal count status mask. (Same as TC_MSK in Cn_CSR) SRC_WIDTH: Source transfer width (Same as SRC_WIDTH in Cn_CSR) DST_WIDTH: Destination transfer width (Same as DST_WIDTH in Cn_CSR) SRCAD_CTL: Source address control (Same as SRCAD_CTL in Cn_CSR)
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Technical Reference Manual 19-18 17 16 15:0 DSTAD_CTL: Destination address control (Same as DSTAD_CTL in Cn_CSR) SRC_SEL: Source selection (Same as SRC_SEL in Cn_CSR) DST_SEL: Destination selection (Same as DST_SEL in Cn_CSR) Reserved Table 8-4. Total Transfer Size Definition in the Linked List Descriptor Description Total transfer size (Same as TOT_SIZE in Cn_SIZE) Table 8-5. Offset +0 +4 +8 +C Address Map for Linked List Descriptor (Base: Cn_LLP [31:2]) Width Description 32 Source Address 32 Destination Address 32 Linked List Pointer 32 Control and Total Transfer Size

Bit 21-0

Name SrcAddr DstAddr LLP Control

Bit 31:29 28 27-25 24-22 21-20 19-18 17 16 15:0

Table 8-6. Control Field Definition in the Linked List Descriptor Description DMA_FF_TH: DMA FIFO threshold value (Same as DMA_FF_TH in Cn_CSR TC_MSK: Channel terminal count status mask. (Same as TC_MSK in Cn_CSR) SRC_WIDTH: Source transfer width (Same as SRC_WIDTH in Cn_CSR) DST_WIDTH: Destination transfer width (Same as DST_WIDTH in Cn_CSR) SRCAD_CTL: Source address control (Same as SRCAD_CTL in Cn_CSR) DSTAD_CTL: Destination address control (Same as DSTAD_CTL in Cn_CSR) SRC_SEL: Source selection (Same as SRC_SEL in Cn_CSR) DST_SEL: Destination selection (Same as DST_SEL in Cn_CSR) Reserved Table 8-7. Total Transfer Size Definition in the Linked List Descriptor Description Total transfer size (Same as TOT_SIZE in Cn_SIZE)

Bit 21-0

8.4. DMA Hardware Handshake Mode In this mode, DMA controller will wait for the external DMA request to be asserted and starts the DMA transfer. Each time the DMA request (dma_req) is asserted, the controller will transfer SRC_BURST_SIZE (SRC_BURST_SIZE is set according to the SRC_SIZE in the Cn_CSR register) number of the transfer unit. When SRC_BURST_SIZE transfer is completed, the DMA controller will assert the acknowledge (dma_ack) and re-arbitrate among the DMA requests. When detecting the dma_ack, the device will deassert the dma_req and cause the DMA to deassert the dma_ack. After TOT_SIZE transfers have been completed, the DMA controller will assert a terminal count dma_tc and interrupt dmaint/dmaint_tc (if enabled). Figure 8.5 illustrates an example of the DMA transfer between different AHB interfaces in the hardware handshake mode. Figure 8.6 shows the hardware handshake protocol.

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TOT_SIZE Transfers

SRC_BURST_SIZE Transfers

SRC_BURST_SIZE Transfers

AHB interface 0

R0

Rn

R0

Rn

AHB interface 1

W0

Wn

W0

Wn

dma_req dma_ack dmaint

Figure 8-5.

Example for the Hardware Handshake Mode Transfer

HCLK sample dma_ack dma_req dma_ack dma_tc dmaint

Figure 8-6. 8.5. DMA Normal Mode

DMA Hardware Handshake Protocol

In this mode, no external DMA request is needed. The DMA controller will automatically generate a transfer request signal internally. Figure 8.7 illustrates an example for this type of transfer.

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TOT_SIZE Transfers

SRC_BURST_SIZE Transfers

In the case Transfer between different interface AHB interface 0 R0 Rn R0 Rn

AHB interface 1 dmaint

W0

Wn

W0

Wn

In the case Transfer on the same interface R0 dmaint Rn W0 Wn R0 Rn W0 Wn

Figure 8-7. 8.6.

Example for the DMA Normal Mode Transfer

Summary of the DMA Controller Registers

The following section describes all control and status registers in the DMA controller. Access field specifies the access type for the register. RW: read and write access RO: read only WO: write only ROC: read only and clear the bit after read RWC: read access and clear the bit after writing 1 All RESERVED bits should always be written with zero. Reading those bits will return an undefined value. Table 8-8. Offset Name Global Register 0x00 INT 0x04 INT_TC 0x08 INT_TC_CLR 0x0c INT_ERR/ABT 0x10 INT_ERR/ABT_CLR 0x14 TC 0x18 ERR/ABT 0x1c CH_EN 0x20 CH_BUSY
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Summary of the DMA Controller Registers Width Access Description 8 8 8 32 32 8 32 8 8 RO RO WO RO WO RO RO RO RO

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Interrupt Status Register Interrupt for Terminal Count Status Register Interrupt for Terminal Count Clear Register Interrupt for Error/Abort Status Register Interrupt for Error/Abort Clear Register Terminal Count Status Register Error/Abort Status Register Channel Enable Status Register Channel Busy Register Status Register
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Technical Reference Manual Offset Name 0x24 CSR 0x28 SYNC 0x30 DMAC_Revision 0x34 DMAC_Feature Channel 0 Registers 0x100 C0_CSR 0x104 C0_CFG 0x108 C0_SrcAddr 0x10c C0_DstAddr 0x110 C0_LLP 0x114 C0_SIZE Channel 1 Registers 0x120 C1_CSR 0x124 C1_CFG 0x128 C1_SrcAddr 0x12c C1_DstAddr 0x130 C1_LLP 0x134 C1_SIZE Channel 2 Registers 0x140 C2_CSR 0x144 C2_CFG 0x148 C2_SrcAddr 0x14c C2_DstAddr 0x150 C2_LLP 0x154 C2_SIZE Channel 3 Registers 0x160 C3_CSR 0x164 C3_CFG 0x168 C3_SrcAddr 0x16c C3_DstAddr 0x170 C3_LLP 0x174 C3_SIZE Channel 4 Registers 0x180 C4_CSR 0x184 C4_CFG 0x188 C4_SrcAddr 0x18c C4_DstAddr 0x190 C4_LLP 0x194 C4_SIZE Channel 5 Registers 0x1a0 C5_CSR 0x1a4 C5_CFG 0x1a8 C5_SrcAddr 0x1ac C5_DstAddr 0x1b0 C5_LLP 0x1b4 C5_SIZE Width 8 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access RW RW RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Description Main Configuration Status Register Sync Register DMAC Revision Register DMAC Fetaure Register Channel 0 Control Register Channel 0 Configuration Register Channel 0 Source Register Channel 0 Destination Register Channel 0 Linked List Pointer Register Channel 0 Transfer Size Register Channel 1 Control Register Channel 1 Configuration Register Channel 1 Source Register Channel 1 Destination Register Channel 1 Linked List Pointer Register Channel 1 Transfer Size Register Channel 2 Control Register Channel 2 Configuration Register Channel 2 Source Register Channel 2 Destination Register Channel 2 Linked List Pointer Register Channel 2 Transfer Size Register Channel 3 Control Register Channel 3 Configuration Register Channel 3 Source Register Channel 3 Destination Register Channel 3 Linked List Pointer Register Channel 3 Transfer Size Register Channel 4 Control Register Channel 4 Configuration Register Channel 4 Source Register Channel 4 Destination Register Channel 4 Linked List Pointer Register Channel 4 Transfer Size Register Channel 5 Control Register Channel 5 Configuration Register Channel 5 Source Register Channel 5 Destination Register Channel 5 Linked List Pointer Register Channel 5 Transfer Size Register

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Technical Reference Manual Offset Name Channel 6 Registers 0x1c0 C6_CSR 0x1c4 C6_CFG 0x1c8 C6_SrcAddr 0x1cc C6_DstAddr 0x1d0 C6_LLP 0x1d4 C6_SIZE Channel 7 Registers 0x1e0 C7_CSR 0x1e4 C7_CFG 0x1e8 C7_SrcAddr 0x1ec C7_DstAddr 0x1f0 C7_LLP 0x1f4 C7_SIZE Width 32 32 32 32 32 32 32 32 32 32 32 32 Access RW RW RW RW RW RW RW RW RW RW RW RW Description Channel 6 Control Register Channel 6 Configuration Register Channel 6 Source Register Channel 6 Destination Register Channel 6 Linked List Pointer Register Channel 6 Transfer Size Register Channel 7 Control Register Channel 7 Configuration Register Channel 7 Source Register Channel 7 Destination Register Channel 7 Linked List Pointer Register Channel 7 Transfer Size Register

8.6.1. Interrupt Status Register (Offset == 0x00) This register indicates the status of the DMA interrupts after masking. The function is listed in the following equation. INT[n] = INT_ERR[n] | INT_TC[n] Where n is channel number n, | is logic or, and INT_ERR / INT_TC is the DMA INT_ERR / INT_TC register. Bit 7 6 5 4 3 2 1 0 Name INT[7] INT[6] INT[5] INT[4] INT[3] INT[2] INT[1] INT[0] Table 8-9. INT Register Access Description Status of the DMA interrupts after masking RO 0: Channel 7 has no pending interrupt. 1: Channel 7 has a pending interrupt. Status of the DMA interrupts after masking RO 0: Channel 6 has no pending interrupt. 1: Channel 6 has a pending interrupt. Status of the DMA interrupts after masking RO 0: Channel 5 has no pending interrupt. 1: Channel 5 has a pending interrupt. Status of the DMA interrupts after masking RO 0: Channel 4 has no pending interrupt. 1: Channel 4 has a pending interrupt. Status of the DMA interrupts after masking RO 0: Channel 3 has no pending interrupt. 1: Channel 3 has a pending interrupt. Status of the DMA interrupts after masking RO 0: Channel 2 has no pending interrupt. 1: Channel 2 has a pending interrupt. Status of the DMA interrupts after masking RO 0: Channel 1 has no pending interrupt. 1: Channel 1 has a pending interrupt. Status of the DMA interrupts after masking RO 0: Channel 0 has no pending interrupt.
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Technical Reference Manual Bit Name Access Description 1: Channel 0 has a pending interrupt.

Value after Reset: 0000h 8.6.2. Interrupt for Terminal Count Status Register (Offset == 0x04) This register indicates the status of the DMA terminal count interrupts after masking. Bit 7 6 5 4 3 2 1 0 Name INT_TC[7] INT_TC[6] INT_TC[5 INT_TC[4] INT_TC[3] INT_TC[2] INT_TC[1] INT_TC[0] Table 8-10. INT_TC Register Access Description Status of the DMA terminal count interrupts after masking RO 0: Channel 7 has no pending interrupt. 1: Channel 7 has a pending interrupt. Status of the DMA terminal count interrupts after masking RO 0: Channel 6 has no pending interrupt. 1: Channel 6 has a pending interrupt. Status of the DMA terminal count interrupts after masking RO 0: Channel 5 has no pending interrupt. 1: Channel 5 has a pending interrupt. Status of the DMA terminal count interrupts after masking RO 0: Channel 4 has no pending interrupt. 1: Channel 4 has a pending interrupt. Status of the DMA terminal count interrupts after masking RO 0: Channel 3 has no pending interrupt. 1: Channel 3 has a pending interrupt. Status of the DMA terminal count interrupts after masking RO 0: Channel 2 has no pending interrupt. 1: Channel 2 has a pending interrupt. Status of the DMA terminal count interrupts after masking RO 0: Channel 1 has no pending interrupt. 1: Channel 1 has a pending interrupt. Status of the DMA terminal count interrupts after masking RO 0: Channel 0 has no pending interrupt. 1: Channel 0 has a pending interrupt.

Value after Reset: 0000h 8.6.3. Interrupt for Terminal Count Clear Register (Offset == 0x08) To clear INT_TC and TC status, write a 1 to this register. Bit 7 6 5 4 3 2 1 0
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Name INT_TC_CLR[7] INT_TC_CLR[6] INT_TC_CLR[5] INT_TC_CLR[4] INT_TC_CLR[3] INT_TC_CLR[2] INT_TC_CLR[1] INT_TC_CLR[0]

Table 8-11. Access WO WO WO WO WO WO WO WO

INT_TC_CLR Register Description Write 1 to clear the INT_TC[7] and TC[7] status Write 1 to clear the INT_TC[6] and TC[6] status Write 1 to clear the INT_TC[5] and TC[5] status Write 1 to clear the INT_TC[4] and TC[4] status Write 1 to clear the INT_TC[3] and TC[3] status Write 1 to clear the INT_TC[2] and TC[2] status Write 1 to clear the INT_TC[1] and TC[1] status Write 1 to clear the INT_TC[0] and TC[0] status
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Technical Reference Manual 8.6.4. Error/Abort Interrupt Status Register (Offset == 0x0C) INT_ERR is the status of the DMA error interrupts after masking. The mask bit of these interrupts is bit 1 (INT_ERR_MSK) of Channel Configuration Register (Cn_CFG). If this mask bit is set, the content of INT_ERR[n] of this register is always 0 whether there exists a pending DMA error interrupt or not. If an AHB ERROR response happens during DMA transfer, the DMA controller will stop the current DMA transfer and set ERR[n] (bits [3:0] of Error/Abort Status Register (ERR/ABT)) to 1. Then, if INT_ERR_MSK is not set, the DMA controller will set INT_ERR[n] to 1 and assert both dmaint_err and dmaint interrupt. Please note that dmaint_err is asserted by the DMA controller if at least one bit of INT_ERR [7:0] of this register is set. INT_ABT is the status of the DMA abort interrupts after masking. The mask bit of these interrupts is bit 2 (INT_ABT_MSK) of Channel Configuration Register (Cn_CFG). If this mask bit is set, the content of INT_ABT[n] of this register is always 0 whether there exists a pending DMA abort interrupt or not. If the ABT bit (bit 15 of Channel Control Register (Cn_CSR)) is set, the DMA controller will stop the current DMA transfer and set ABT[n] (bits [19:16] of Error/Abort Status Register (ERR/ABT)) to 1. Then, if INT_ABT_MSK is not set, the DMA controller will set INT_ABT[n] to 1 and assert dmaint interrupt. Bit 31-24 23 22 21 20 19 18 17 16 Name INT_ABT[7] INT_ABT[6] INT_ABT[5] INT_ABT[4] INT_ABT[3] INT_ABT[2] INT_ABT[1] INT_ABT[0] Table 8-12. INT_ERR Register Access Description Reserved Status of the DMA abort interrupts after masking RO 0: Channel 7 has no pending interrupt. 1: Channel 7 has a pending interrupt. Status of the DMA abort interrupts after masking RO 0: Channel 6 has no pending interrupt. 1: Channel 6 has a pending interrupt. Status of the DMA abort interrupts after masking RO 0: Channel 5 has no pending interrupt. 1: Channel 5 has a pending interrupt. Status of the DMA abort interrupts after masking RO 0: Channel 4 has no pending interrupt. 1: Channel 4 has a pending interrupt. Status of the DMA abort interrupts after masking RO 0: Channel 3 has no pending interrupt. 1: Channel 3 has a pending interrupt. Status of the DMA abort interrupts after masking RO 0: Channel 2 has no pending interrupt. 1: Channel 2 has a pending interrupt. Status of the DMA abort interrupts after masking RO 0: Channel 1 has no pending interrupt. 1: Channel 1 has a pending interrupt. Status of the DMA abort interrupts after masking RO 0: Channel 0 has no pending interrupt.
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Technical Reference Manual Bit 15-8 7 6 5 4 3 2 1 0 INT_ERR[7] INT_ERR[6] INT_ERR[5] INT_ERR[4] INT_ERR[3] INT_ERR[2] INT_ERR[1] INT_ERR[0] RO RO RO RO RO RO RO RO Name Access Description 1: Channel 0 has a pending interrupt. Reserved Status of the DMA error interrupts after masking 0: Channel 7 has no pending interrupt. 1: Channel 7 has a pending interrupt. Status of the DMA error interrupts after masking 0: Channel 6 has no pending interrupt. 1: Channel 6 has a pending interrupt. Status of the DMA error interrupts after masking 0: Channel 5 has no pending interrupt. 1: Channel 5 has a pending interrupt. Status of the DMA error interrupts after masking 0: Channel 4 has no pending interrupt. 1: Channel 4 has a pending interrupt. Status of the DMA error interrupts after masking 0: Channel 3 has no pending interrupt. 1: Channel 3 has a pending interrupt. Status of the DMA error interrupts after masking 0: Channel 2 has no pending interrupt. 1: Channel 2 has a pending interrupt. Status of the DMA error interrupts after masking 0: Channel 1 has no pending interrupt. 1: Channel 1 has a pending interrupt. Status of the DMA error interrupts after masking 0: Channel 0 has no pending interrupt. 1: Channel 0 has a pending interrupt.

Value after Reset: 0000h 8.6.5. Error/Abort Interrupt Status Clear Register (Offset == 0x10) Writing 1 to bits [3:0] of this register will clear both INT_ERR[n] and ERR[n]. Writing 1 to bits [19:16] of this register will clear both INT_ABT[n] and ABT[n]. Bit 31-24 23 22 21 20 19 18 17 16 15-8 7 6 Name INT_ABT_CLR[7] INT_ABT_CLR[6] INT_ABT_CLR[5] INT_ABT_CLR[4] INT_ABT_CLR[3] INT_ABT_CLR[2] INT_ABT_CLR[1] INT_ABT_CLR[0] INT_ERR_CLR[7] INT_ERR_CLR[6] Table 8-13. INT_ERR_CLR Register Access Description Reserved, write 0 WO Write 1 to clear the INT_ABT[7] and ABT[7] status. WO Write 1 to clear the INT_ABT[6] and ABT[62] status. WO Write 1 to clear the INT_ABT[5] and ABT[5] status. WO Write 1 to clear the INT_ABT[4] and ABT[4] status. WO Write 1 to clear the INT_ABT[3] and ABT[3] status. WO Write 1 to clear the INT_ABT[2] and ABT[2] status. WO Write 1 to clear the INT_ABT[1] and ABT[1] status. WO Write 1 to clear the INT_ABT[0] and ABT[0] status. Reserved WO Write 1 to clear the INT_ERR[7] and ERR[7] status WO Write 1 to clear the INT_ERR[6] and ERR[6] status

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Technical Reference Manual Bit 5 4 3 2 1 0 Name INT_ERR_CLR[5] INT_ERR_CLR[4] INT_ERR_CLR[3] INT_ERR_CLR[2] INT_ERR_CLR[1] INT_ERR_CLR[0] Access WO WO WO WO WO WO Description Write 1 to clear the INT_ERR[5] and ERR[5] status Write 1 to clear the INT_ERR[4] and ERR[4] status Write 1 to clear the INT_ERR[3] and ERR[3] status Write 1 to clear the INT_ERR[2] and ERR[2] status Write 1 to clear the INT_ERR[1] and ERR[1] status Write 1 to clear the INT_ERR[0] and ERR[0] status

8.6.6. Terminal Count Status Register (Offset == 0x14) This register shows the status of the DMA terminal count after masking. The mask bit for the DMA terminal count is bit 31 (TC_MSK) of Channel Control Register (Cn_CSR). If this mask bit of Cn_CSR is set, the TC[n] of this register is always 0 whether a DMA terminal count happens or not. Bit 7 6 5 4 3 3 2 1 0 Name TC[7] TC[6] TC[5] TC[40] TC[3] TC[3] TC[2] TC[1] TC[0] Table 8-14. TC Register Access Description Status of the DMA terminal count RO 0: Channel 7 has no terminal count status. 1: Channel 7 has a terminal count status. Status of the DMA terminal count RO 0: Channel 6 has no terminal count status. 1: Channel 6 has a terminal count status. Status of the DMA terminal count RO 0: Channel 5 has no terminal count status. 1: Channel 5 has a terminal count status. Status of the DMA terminal count RO 0: Channel 4 has no terminal count status. 1: Channel 4 has a terminal count status. Status of the DMA terminal count RO 0: Channel 3 has no terminal count status. 1: Channel 3 has a terminal count status. Status of the DMA terminal count RO 0: Channel 3 has no terminal count status. 1: Channel 3 has a terminal count status. Status of the DMA terminal count RO 0: Channel 2 has no terminal count status. 1: Channel 2 has a terminal count status. Status of the DMA terminal count RO 0: Channel 1 has no terminal count status. 1: Channel 1 has a terminal count status. Status of the DMA terminal count RO 0: Channel 0 has no terminal count status. 1: Channel 0 has a terminal count status.

Value after Reset: 0000h 8.6.7. Error/Abort Status Register (Offset == 0x18) ERR is the status of the DMA error. If an AHB ERROR response happens during DMA transfer, the DMA
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Technical Reference Manual controller will stop the current DMA transfer and set ERR[n] to 1. Then, if INT_ERR_MSK is not set, the DMA controller will set INT_ERR[n] to 1 and assert both dmaint_err and dmaint interrupt. ABT is the status of the DMA abort. If the ABT bit (bit 15 of Channel Control Register (Cn_CSR)) is set, the DMA controller will stop the current DMA transfer and set ABT[n] to 1. Then, if INT_ABT_MSK is not set, the DMA controller will set INT_ABT[n] to 1 and assert dmaint interrupt. Bit 31-24 23 22 21 20 19 18 17 16 15-8 7 6 5 4 3
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Name ABT[7] ABT[6] ABT[5] ABT[4] ABT[3] ABT[2] ABT[1] ABT[0]

ERR[7] ERR[6] ERR[5] ERR[4] ERR[3]

Table 8-15. ERR Register Access Description Reserved Status of the DMA abort RO 0: Channel 7 has no abort status. 1: Channel 7 has an abort status. Status of the DMA abort RO 0: Channel 6 has no abort status. 1: Channel 6 has an abort status. Status of the DMA abort RO 0: Channel 5 has no abort status. 1: Channel 5 has an abort status. Status of the DMA abort RO 0: Channel 4 has no abort status. 1: Channel 4 has an abort status. Status of the DMA abort RO 0: Channel 3 has no abort status. 1: Channel 3 has an abort status. Status of the DMA abort RO 0: Channel 2 has no abort status. 1: Channel 2 has an abort status. Status of the DMA abort RO 0: Channel 1 has no abort status. 1: Channel 1 has an abort status. Status of the DMA abort RO 0: Channel 0 has no abort status. 1: Channel 0 has an abort status. Reserved Status of the DMA error RO 0: Channel 7 has no error status. 1: Channel 7 has a error status. Status of the DMA error RO 0: Channel 6 has no error status. 1: Channel 6 has a error status. Status of the DMA error RO 0: Channel 5 has no error status. 1: Channel 5 has a error status. Status of the DMA error RO 0: Channel 4 has no error status. 1: Channel 4 has a error status. RO Status of the DMA error
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Technical Reference Manual Bit Name Access Description 0: Channel 3 has no error status. 1: Channel 3 has a error status. Status of the DMA error 0: Channel 2 has no error status. 1: Channel 2 has a error status. Status of the DMA error 0: Channel 1 has no error status. 1: Channel 1 has a error status. Status of the DMA error 0: Channel 0 has no error status. 1: Channel 0 has a error status.

2 1 0

ERR[2] ERR[1] ERR[0]

RO RO RO

Value after Reset: 0000h 8.6.8. Channel Enable Status Register (Offset == 0x1C) This register indicates the status of the DMA enable status. It is a read-only register. Bit 7 6 5 4 3 2 1 0 Name CH_EN[7] CH_EN[6] CH_EN[5] CH_EN[4] CH_EN[3] CH_EN[2] CH_EN[1] CH_EN[0] Table 8-16. CH_EN Register Access Description Status of the channel 7 CH_EN in the C7_CSR register. RO 0: CH_EN = 0 1: CH_EN = 1 Status of the channel 6 CH_EN in the C7_CSR register. RO 0: CH_EN = 0 1: CH_EN = 1 Status of the channel 5 CH_EN in the C5_CSR register. RO 0: CH_EN = 0 1: CH_EN = 1 Status of the channel 4 CH_EN in the C4_CSR register. RO 0: CH_EN = 0 1: CH_EN = 1 Status of the channel 3 CH_EN in the C3_CSR register. RO 0: CH_EN = 0 1: CH_EN = 1 Status of the channel 2 CH_EN in the C2_CSR register. RO 0: CH_EN = 0 1: CH_EN = 1 Status of the channel 1 CH_EN in the C1_CSR register. RO 0: CH_EN = 0. 1: CH_EN = 1. Status of the channel 0 CH_EN in the C0_CSR register. RO 0: CH_EN = 0 1: CH_EN = 1

Value after Reset: 0000h 8.6.9. Channel Enable Status Register (Offset == 0x20) This register indicates the status of the DMA busy status. It is a read-only register. Table 8-17.
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CH_BUSY Register
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Technical Reference Manual Bit 7 6 5 4 3 2 1 0 Name CH_BUSY[7] CH_BUSY[6] CH_BUSY[5] CH_BUSY[4] Access RO RO RO RO RO RO RO RO Description Status of the channel 7 BUSY in the C3_CFG register. 0: BUSY = 0 1: BUSY = 1 Status of the channel 6 BUSY in the C2_CFG register. 0: BUSY = 0 1: BUSY = 1 Status of the channel 5 BUSY in the C1_CFG register. 0: BUSY = 0 1: BUSY = 1 Status of the channel 4 BUSY in the C0_CFG register. 0: BUSY = 0 1: BUSY = 1 Status of the channel 3 BUSY in the C3_CFG register. 0: BUSY = 0 1: BUSY = 1 Status of the channel 2 BUSY in the C2_CFG register. 0: BUSY = 0 1: BUSY = 1 Status of the channel 1 BUSY in the C1_CFG register. 0: BUSY = 0 1: BUSY = 1 Status of the channel 0 BUSY in the C0_CFG register. 0: BUSY = 0 1: BUSY = 1

CH_BUSY[3] CH_BUSY[2] CH_BUSY[1] CH_BUSY[0]

Value after Reset: 0000h 8.6.10. Main Configuration Status Register (Offset == 0x24) Table 8-18. CSR Register Bit Name Access Description 7-3 RO Reserved Master 1 endianness configuration: 0 = little-endian mode 2 M1ENDIAN RW 1 = big-endian Reset value = 0 Master 0 endianness configuration: 0 = little-endian mode 1 M0ENDIAN RW 1 = big-endian Reset value = 0 DMA controller enable 0 = disable 0 DMACEN RW 1 = enable Reset value = 0 Value after reset: 0000h 8.6.11. Synchronization Register (Offset == 0x28) The sync register is designed for the synchronization of the hardware DMA request (dma_req) for internal

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Technical Reference Manual use. The user can disable the synchronization logic to see the hardware request earlier. Bit 7 6 5 4 3 2 1 0 Name SYNC[7] SYNC[6] SYNC[5] SYNC[4] SYNC[3] SYNC[2] SYNC[1] SYNC[0] Table 8-19. SYNC Register Access Description DMA Synchronization logic enable for channel 7 request: RW 0: Disable 1: Enable DMA Synchronization logic enable for channel 6 request: RW 0: Disable 1: Enable DMA Synchronization logic enable for channel 5 request: RW 0: Disable 1: Enable DMA Synchronization logic enable for channel 4 request: RW 0: Disable 1: Enable DMA Synchronization logic enable for channel 3 request: RW 0: Disable 1: Enable DMA Synchronization logic enable for channel 2 request: RW 0: Disable 1: Enable DMA Synchronization logic enable for channel 1 request: RW 0: Disable 1: Enable DMA Synchronization logic enable for channel 0 request: RW 0: Disable 1: Enable

Value after Reset: 0000h 8.6.12. DMAC Revision Register (DMAC_REVISION) (Offset = 0x30) This register shows the revision of the current DMA controller. Bit 31:24 23:16 15:8 7:0 Name MAJOR_REV MINOR_REV REL_REV Table 8-20. Access RO RO RO RO DMA Revision Register Description Reserved and read as 0 Major revision Minor revision Release number

Value after Reset: 0000h 8.6.13. DMAC Feature Register (DMAC_FEATURE) (Offset = 0x34) Table below shows the format of the feature register. Table 8-21. DMA Feature Register Access Description RO Reserved and read as 0

Bit 31:16

Name -

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Technical Reference Manual Bit 15:12 11 10 9 8 7:4 3:0 Name DMA_MAX_CHNO_N DMA_HAVE_BRIDGE DMA_HAVE-AHB1 DMA_FF_ADD_WIDTH Access Description DMA maximum channel number. N can be configured from RO 1 to 8 (default) RO Reserved and read as 0 0 DMA does not include a bulit-in bridge RO 1 DMA includes a bulit-in bridge 0 DMA has only AHB0 RO 1 DMA has AHB0 and AHB1 RO Reserved and read as 0 RO FIFO Ram address width

8.6.14. Channel 0 : 7 Control Register (Offset == 0x100, 0x120, 0x140, 0x160, 0x180, 0x1A0, 0x1C0, 0x1E0 ) The below table shows the bit assignment of the channel 0:7 control register. Bit 31 30-24 23-22 Name TC_MSK CHPRI Table 8-22. Cn_CSR Register Access Description Terminal Count Status Mask for Current LLP: 0: When Terminal Count, TC status register will be set. RW (default) 1: When Terminal Count, TC status register will not be set. RO Reserved Channel Priority Level: 3: highest priority RW 2: 2nd high priority 1: 3rd high priority 0: lowest priority (default) PROT: Protection information for cacheability[2] 0: Not cacheable (default) RW 1: Cacheable PROT: Protection information for bufferability[3] RW 0: Not bufferable (default) 1: Bufferable PROT: Protection information for the mode indication[4] 0: User mode (default) RW 1: Privileged mode Source burst size selection. 000: burst size = 1 (default) 001: burst size = 4 010: burst size = 8 RW 011: burst size = 16 100: burst size = 32 101: burst size = 64

21 20 19

PROT3 PROT2 PROT1

18-16

SRC_SIZE

[2] [3]

This bit controls the AHB HPROT[3]. This bit controls the AHB HPROT[2]. [4] This bit controls the AHB HPROT[1].
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Technical Reference Manual Bit Name Access Description 110: burst size = 128 111: burst size = 256 Note: Source burst size is not relative to the HBRUST (AHB signals); it just represents the number of transfers before the DMA re-arbitrates among active channels. If burst size = 1, SRC_WIDTH must be equal to DST_WIDTH. Source width = 8, Destination width = 16 or Source width = 8, Destination width = 32 or Source width = 16, Destination width = 32 are not allowed. Transaction abort. Writing a one to this bit will cause the DMA to stop its current transfer, set the ERR bit and assert interrupt. Reserved Source transfer width. The hardware automatically packs and unpacks the data as required. 000: Transfer width is 8 bits 001: Transfer width is 16 bits 010: Transfer width is 32 bits (default) Others: Reserved Note: If source transfer width > destination transfer width, DMA will pack input data. For example, if source transfer width = 8-bit, destination transfer width = 32-bit, then DMA will pack 4 8-bit source transfers and transfer 1 32-bit data. Limitation: Do not set SRCAD_CTL = 01(decrement source address) when the pack function works; otherwise DMA will take a wrong action. If source transfer width < destination transfer width, DMA will unpack input data. For example, if source transfer width = 32-bit, destination transfer width = 8-bit, then DMA will unpack source 32-bit data and transfer 4 8-bit data to destination. Destination transfer width. The hardware automatically packs and unpacks the data as required. 000: Transfer width is 8 bits 001: Transfer width is 16 bits 010: Transfer width is 32 bits (default) Others: Reserved Note: If source transfer width > destination transfer width, DMA will pack input data. For example, if source transfer width = 8-bit, destination transfer width = 32-bit, then DMA will pack 4 8-bit source transfers and transfer 1 32-bit data. Limitation: Do not set SRCAD_CTL = 01(decrement source address) when the pack function works; otherwise
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ABT

WO RW

13-11

SRC_WIDTH

RW

10-8

DST_WIDTH

RW

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Technical Reference Manual Bit Name Access Description DMA will take a wrong action. If source transfer width < destination transfer width, DMA will unpack input data. For example, if source transfer width = 32-bit, destination transfer width = 8-bit, then DMA will unpack source 32-bit data and transfer 4 8-bit data to destination. 0: Normal Mode (default) 1: Hardware Handshake Mode Source Address Control 00: Increment source address (default) 01: Decrement source address 10: Fixed source address 11: Reserved Note: If source transfer width > destination transfer width, DMA will pack input data. For example, if source transfer width = 8-bit, destination transfer width = 32-bit, then DMA will pack 4 8-bit source transfers and transfer 1 32-bit data. Limitation: Do not set SRCAD_CTL = 01 (decrement source address) when the pack function works; otherwise DMA will take a wrong action. If source transfer width < destination transfer width, DMA will unpack input data. For example, if source transfer width = 32-bit, destination transfer width = 8-bit, then DMA will unpack source 32-bit data and transfer 4 8-bit data to destination. Destination Address Control 00: Increment destination address (default) 01: Decrement destination address 10: Fixed destination address 11: Reserved Note: If source transfer width > destination transfer width, DMA will pack input data. For example, if source transfer width = 8-bit, destination transfer width = 32-bit, then DMA will pack 4 8-bit source transfers and transfer 1 32-bit data. Limitation: Do not set SRCAD_CTL = 01 (decrement source address) when the pack function works; otherwise DMA will take a wrong action. If source transfer width < destination transfer width, DMA will unpack input data. For example, if source transfer width = 32-bit, destination transfer width = 8-bit, then DMA will unpack source 32-bit data and transfer 4 8-bit data to destination. 0: AHB Master 0 is the source (default) 1: AHB Master 1 is the source 0: AHB Master 0 is the destination (default)

MODE

RW

6-5

SRCAD_CTL

RW

4-3

DSTAD_CTL

RW

4-3

DSTAD_CTL

RW

2 1

SRC_SEL DST_SEL

RW RW

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Technical Reference Manual Bit 0 Name CH_EN Access RW Description 1: AHB Master 1 is the destination Channel Enable 0: Disable (default) 1: Enable

Value after Reset: 0000_1200h 8.6.15. Channel 0:7 Configuration Register (Offset == 0x104, 0x124, 0x144, 0x164, 0x184, 0x1A4, 0x1C4, 0x1E4) Table below shows the bit assignment of the channel 0:7 configuration register. Table 8-23. Bit 31-9 8 7-2 1 0 Name BUSY INT_ERR_MSK INT_TC_MSK Access RO RO RO RW RW Cn_CFG Register Description Reserved The DMA channel is busy. Reserved Channel error interrupt mask 0: Do not mask interrupt 1: Mask interrupt (default) Channel terminal count interrupt mask 0: Do not mask interrupt 1: Mask interrupt (default)

Value after Reset: 0000_0003h 8.6.16. Channel 0:7 Source Address Register (Offset == 0x108, 0x128, 0x148, 0x168, 0x188, 0x1A8, 0x1C8, 0x1E8) Table below shows the bit assignment of the channel n source address register. Bit Name 31-0 Cn_SrcAddr Value after Reset: Undefined Table 8-24. Cn_SrcAddr Register Access Description RW Source Address

Note: When the DMA transaction is done, the value becomes the DMA source last address. 8.6.17. Channel 0:7 Destination Address Register (Offset == 0x10C, 0x12C, 0x14C, 0x16C, 0x18C, 0x1AC, 0x1CC, 0x1EC) Table below shows the bit assignment of the channel n destination address register. Bit Name 31-0 Cn_DstAddr Value after Reset: Undefined Table 8-25. Cn_DstAddr Register Access Description RW Destination Address

Note: When the DMA transaction is done, the value becomes the DMA destination last address. 8.6.18. Channel 0:7 Linked List Descriptor Pointer (Offset == 0x110, 0x130, 0x150, 0x160,

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Technical Reference Manual 0x180, 0x1A0, 0x1C0, 0x1E0) Table below shows the bit assignment of the channel n linked list descriptor pointer. Bit 31-2 1 0 Name Table 8-26. Cn_LLP Register Access Description RW Linked List Descriptor Pointer Address RW Reserved Master for loading the next LLP: RW 0: Load the next LLP from the AHB Master 0 (default) 1: Load the next LLP from the AHB Master 1

Value after Reset: 0000_0000h 8.6.19. Channel 0:7 Transfer Size Register (Offset == 0x114, 0x134, 0x153, 0x174, 0x194, 0x1B4, 0x1D4, 0x1F4) Table below shows the bit assignment of the channel n transfer size register. Bit 31-12 Name Table 8-27. Cn_SIZE Register Access Description RO Reserved Total transfer size. NOTE: The transfer unit depends on the source width. For example: RW SRC_WIDTH = 000, unit = 8-bit SRC_WIDTH = 001, unit = 16-bit SRC_WIDTH = 010, unit = 32-bit

11-0

TOT_SIZE

Value after Reset: Undefined Note: When the DMA transaction is done, the value becomes a zero. 8.7. Programming Sequence

Channel Initialization (Normal Mode, No Chain Transfer) Set CSR 0 1 2 3 Decide master 0 interface and master 1 endianness by setting M1ENDIAN and M0ENDIAN. Enable DMA controller by setting DMACEN to 1. Set SYNC to decide which channels synchronization logic need to be enabled. Set channel registers. Set Cn_CFG to decide which channels interrupt need to be enabled. Set transfer source address Cn_SrcAddr and destination address Cn_DstAddr. Set Linked List Pointer Cn_LLP to 0. Set transfer number Cn_SIZE to determine how many transfers are required in this DMA transaction. Set Cn_CSR to decide priority (CHIPRI), transfer burst size (SRC_SIZE), transfer width (SRC_WIDTH, DST_WIDTH), increment or decrement address, source or destination interface
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Technical Reference Manual (SRC_SEL, DST_SEL). Set MODE in the Cn_CSR to the Normal Mode. 4 1. 2. Start DMA transfer by setting CH_EN to 1 in the Cn_CSR. Fill the Link List description Set CSR. Decide master 0 interface and master 1 endianness by setting M1ENDIAN and M0ENDIAN. Enable DMA controller by setting DMACEN to 1. 3. 4. Set SYNC to decide whether channels synchronization logic need to be enabled. Set channel registers (1st Link List transfer). Set Cn_CFG to decide which channels interrupt need to be enabled. Set transfer source address Cn_SrcAddr and destination address Cn_DstAddr. Set Linked List Pointer Cn_LLP to the next starting address of the linked list descriptor. Set transfer number Cn_SIZE to determine how many transfers are required in current DMA transaction. Set Cn_CSR to decide priority (CHIPRI), transfer burst size (SRC_SIZE), transfer width (SRC_WIDTH, DST_WIDTH), increment or decrement address, source or destination interface (SRC_SEL, DST_SEL) (Cannot use auto-reload function (AUTORLD) in this case.) Set MODE in the Cn_CSR to the Normal Mode. 5. 1. Start DMA transfer by setting CH_EN to 1 in the Cn_CSR. Set CSR. Decide master 0 interface and master 1 endianness by setting M1ENDIAN and M0ENDIAN. Enable DMA controller by setting DMACEN to 1. 2. 3. Set SYNC to decide whether channels synchronization logic need to be enabled. Set channel registers. Set Cn_CFG to decide which channels interrupt need to be enabled. Set transfer source address Cn_SrcAddr and destination address Cn_DstAddr. Set Linked List Pointer Cn_LLP to 0. Set transfer number Cn_SIZE to determine how many transfers are required in this DMA transaction. 4. Set Cn_CSR to decide priority (CHIPRI), transfer burst size (SRC_SIZE), transfer width (SRC_WIDTH, DST_WIDTH), increment or decrement address, source or destination interface Channel Initialization (Hardware Handshake Mode, No Chain Transfer) Channel Initialization (Normal Mode, Chain Transfer)

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Technical Reference Manual (SRC_SEL, DST_SEL). Set MODE in the Cn_CSR to the Hardware Handshake Mode. 5. 1. 2. Start DMA transfer by setting CH_EN to 1 in the Cn_CSR. Fill the Link List description Set CSR. Decide master 0 interface and master 1 endianness by setting M1ENDIAN and M0ENDIAN. Enable DMA controller by setting DMACEN to 1. 3. 4. Set SYNC to decide whether channels synchronization logic need to be enabled. Set channel registers. Set Cn_CFG to decide which channels interrupt need to be enabled. Set transfer source address Cn_SrcAddr and destination address Cn_DstAddr. Set Linked List Pointer Cn_LLP to the starting address of the linked list descriptor. Set transfer number Cn_SIZE to determine how many transfers are required in this DMA transaction. Set Cn_CSR to decide priority (CHIPRI), transfer burst size (SRC_SIZE), transfer width (SRC_WIDTH, DST_WIDTH), increment or decrement address, source or destination interface (SRC_SEL, DST_SEL). Set MODE in the Cn_CSR to the Hardware Handshake Mode. 5. Start DMA transfer by setting CH_EN to 1 in the Cn_ CSR Channel Initialization (Hardware Handshake Mode, Chain Transfer)

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9. External Bus Interface (EBI)

9.1. Overview The EBI unit is the external bus interface to allow the static SRAM controller and SDRAM controller to request and share for the usage of the address and data bus. An internal arbiter is required to arbitrate the requests sent from different memory controllers. It supports the following features: Two internal devices o o Static memory controller (SMC) SDRAM controller (SDRC)

Programmable access times Non-preemptive grant stop handshaking 8-bit, 16-bit, and 32-bit accessibilities

The figure below shows the basic block diagram of EBI

M1REQ SRAM Controller M1GRT Control Address D [31:0] Address SDRAM Controller D [31:0] Control M0GRT M0REQ AHB Slave Interface Tri-state Mux EBI Arbiter

AHB

Registers

aJ-102
Figure 9-1. 9.2. Architecture Description The main building blocks of the EBI consist of the AHB slave interface, registers, address/data/byte
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Block Diagram of EBI

Technical Reference Manual enable/write enable multiplexer interface, and bus arbitration control. The detailed description of each building block is provided as follows 9.2.1. AHB Slave Interface This block acts as a slave interface between the AHB bus and EBI. The AHB slave receives the address and data from the AHB bus. It can decodes the address and read/write the data from/into the registers. 9.2.2. Tri-state Multiplexer Interface The EBI interface is used to receive the address/data/byte enable/write enable from different master devices and according to the arbitration scheme to grant one of the master devices. The owner of the EBI bus will be permitted to access the external memory device and the corresponding access signal will be outputted. 9.2.3. Registers The registers define the status and the operation mode of the controller. The CPU can access the registers via the AHB slave. 9.2.4. Arbitrator The arbitration mechanism is used to ensure that only one channel has the right to access the bus at the same time. The arbiter performs this function by observing a number of different requests to use the bus and deciding which channel will have the highest priority. The round robin and group algorithms are implemented to arbitrate the requests of all EBI channels. The following is the arbitration combinations: Two-level priority Group 0 has the higher priority than group 1. Low priority group act like a high priority master To prevent the discrete access of the commands Use the group concept to do a batch commands

Group priority

9.2.5. Summary of EBI Registers Offset 0x00 0x2C-0x04 0x30 0x3C-0x34 0x40 0x44 Type RO R/W R/W R/W Table 9-1. Summary of EBI Registers Description Version information Reserved Control register Reserved Grant window unit Min. master grant window size (3~0) Reset Value 0x0000_0000 0x8000_0000 0x0000_0000 0x0000_0000

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Technical Reference Manual 0x48 0x4C R/W Min. master grant window size (5~4) Reserved 0x0000_0000 0x4C

9.2.6. Register Description The following sections describe the EBI registers in details. 9.2.6.1. Bit 31:29 28 27 26 25 24 23:22 21:20 19:18 17:16 13:8 5:0 EBI Control Register (Offset = 0x30) Name m0hps_en sdcs_en smcs_en intturn_en arb_mode extturn Tgloeh Tghckeh gtc_en mgsel Table 9-2. EBI Control Register Type Description Reserved R/W Master 0 high priority signal enable R/W SDRAM bus share enable R/W SRAM bus share enable R/W Internal master turn-around enable R/W Arbitration mode 0 Group 0 as the high priority 1 Two-level Reserved R/W External turn-around time R/W Turn-around time from the grant low to the output enable high R/W Turn-around time from the grant high to cke high R/W Grant termination control enable (according to the number of masters) R/W Master group selection 1. Hardware configurable and Max. 6 masters 2. Set the desired bits in the mgsel register to 0 to group the master as the group 0, the remains would be grouped as the group 1.

9.2.6.2. Bit 31:8 7:0 9.2.6.3. Bit 31:24 23:16 15:8 7:0

Grant Window Unit Register (Offset = 0x40) Name Gwunit Table 9-3. Grant window unit register Type Description Reserved R/W Grant window unit

Min Grant Window Size of Masters (3~0) (Offset = 0x44) Table 9-4. Min grant window size of maters (3~0) register Name Type Description M3gw R/W Min grant window size of the master 3 M2gw R/W Min grant window size of the master 2 M1gw R/W Min grant window size of the master 1 M0gw R/W Min grant window size of the master 0

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Technical Reference Manual 9.2.6.4. Bit 31:24 23:16 15:8 7:0 Min Grant Window Size of Masters 7~4) (Offset = 0x48) Table 9-5. Min grant window size of maters (7~4) register Name Type Description M7gw R/W Min grant window size of the master 7 M6gw R/W Min grant window size of the master 6 M5gw R/W Min grant window size of the master 5 M4gw R/W Min grant window size of the master 4

9.3. Static Memory Controller (SMC) 9.3.1. Overview The SMC provides the interface to access ROM, FLASH and both asynchronous and synchronous SRAM. Each chip select can be individually programmed to an 8- or 16- or 32-bit wide data bus without additional external logic. It supports up to eight banks and each bank can address up to 32Mbytes. SMC shares the address and data bus with SDRAM controller. It supports the following features Seamless interface with ROM, burst-ROM Synchronous, asynchronous SRAM NOR and NAND Flash External memory-mapped I/O devices Zero-wait-state write 8-word data FIFO Wide address range up to 256 MBytes Eight banks Each bank can address up to 32 MB Eight external CSn [7:0] Programmable external memory bus width (8- or 16-, or 32-bit) Shadow first bank with other banks

Figure below shows the block diagram of static memory controller.

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AHB

AHB slave (Mem)

AHB slave (Reg)

Static memory control engine

ebi_gnt

ebi_req

Figure 9-2. 9.3.2. Interface Types

Block Diagram of Static Memory Controller

The static memory controller supports three major types of devices, asynchronous, synchronous, ZBT, and NAND memory. The following sections are an overview of the connection scheme. 9.3.2.1. devices Asynchronous Devices

Figure below shows the connection scheme of asynchronous devices using an asynchronous 2MB SRAM

MADDR[20:0] SMC_CS0n

A[20:0] CSn WEn OEn

aJ-102 MWEn
SMC_OEn MDATA[31:0]

SRAM 2MBx8

IO[8:1]

Figure 9-3.

8-bit Asynchronous Interface

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MADDR[21:0] MADDR22 SMC_CS0n MWEn

A[21:0] VCR CE# WE# OE# LB# HB# ADV# CLK DQ[15:0]

aJ-102

SMC_OEn MBE0n MBE1n

PSRAM 4MBx16 Vss Vss

MDATA[15:0]

Figure 9-4.
MADDR[21:0] MADDR22 SMC_CS0n MWEn SMC_OEn MBE0n MBE1n MBE2n MBE3n MDATA[31:0]

16-bit Asynchronous Interface

A[21:0] VCR CE# WE# OE# LB# HB# ADV# CLK DQ[15:0]

PSRAM 4MBx16 Vss Vss

aJ-102
A[21:0] VCR CE# WE# OE# LB# HB# ADV# CLK DQ[15:0]

PSRAM 4MBx16 Vss Vss

Figure 9-5.

32-bit Asynchronous Interface

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A[21:0] VCR CE# WE# OE#

MADDR[21:0] MADDR22 SMC_CS0n MWEn SMC_OEn RTSOUTn GPIOA0 GPIOA1 MDATA[31:0]

NOR FLASH

RESET# 4MBx16 RY/BY# WP#/ACC DQ[15:0]

aJ-102
A[21:0] VCR CE# WE# OE#

NOR FLASH

RESET# 4MBx16 RY/BY# WP#/ACC DQ[15:0]

Figure 9-6. 9.3.3. Synchronous Devices

Nor Flash Interface

Figure below shows the connection scheme of a synchronous 16 MB PSRAM device. The SMC does not support the burst feature of the syn-burst devices. SMC supports either pipelined or non-pipelined (also called flow-through) sync-burst devices and the connection schemes are identical. The major difference between these two is access timing. User has to specify the device type in configuration register to suit either pipelined or non-pipelined device.
MADDR[23:0] GPIO SMC_CS0n MWEn SMC_OEn MBE0n MBE1n MBE2n MBE3n A[23:0] PS# CS# WE# OE# LB# UB#

PSRAM 16MBx16

aJ-102

SDR_CLK MDATA[31:0]

CLK IO[15:0]

ADV#

Vss

A[23:0] PS# CS# WE# OE# LB# UB# CLK IO[15:0] ADV#

PSRAM 16MBx16

Vss

Figure 9-7.
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Technical Reference Manual 9.3.4. ZBTTM Devices Figure below shows the connection scheme of ZBT devices. Again the burst nature of ZBT devices is disabled by tying ADV / LD# to LOW.

MADDR[23:0] GPIO SMC_CS0n MWEn SMC_OEn

A[23:0] PS# CS# R/W# OE# BWA# BWB# BWC# BWD# CLK IO[31:0] MODE ADV/LD#

aJ-102

MBE0n MBE1n MBE2n MBE3n SDR_CLK MDATA[31:0]

256Kx 32 SRAM

Vss

Figure 9-8. 9.3.5. Memory bus width

Connection Scheme of ZBT Devices

The SMC provides programmable memory width as follows: 9.3.5.1. 32-bit bus width As shown in figure below, the 32-bit memory bus width can be built with four 8-bit, two 16-bit or one 32-bit devices and each 8-bit data is controlled by one byte-enable (MBEn[3:0]).

Figure 9-9. 32-bit Memory Connection If real bus width is narrower than 32-bits, device has to connect from the least significant bits. Table below shows the relationship between haddr [1:0] and MBEn [3:0]. Table 9-6. Address to MBEn translation (bus width= 16 & little endianess) CPU operation HAddr[1:0] (Two least significant address bits at AHB) MBEn [3:0] Word xx 0000 Halfword 1x 0011
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Technical Reference Manual X1 Byte 00 01 10 11 9.3.5.2. 16-bit bus width each 8-bit data is controlled by one byte-enable (MBEn[1:0]). 1100 1110 1101 1011 0111

As shown in figure below, the 16-bit memory bus width can be built with two 8-bit, one16-bit devices and

Figure 9-10. 16-bit Memory Connection Table 9-7. Address to MBEn translation (bus width= 16 & little endianess) CPU operation HAddr[1:0] (Two least significant address bits at AHB) MBEn [3:0] Word xx 1100 Halfword 1x 1100 0x 1100 Byte 00 1110 01 1101 10 1110 11 1101 9.3.5.3. 8-bit bus width As shown in figure below, the 8-bit memory bus width can be built with one 8-bit. 16-bit and 32-bit devices are npt allowed in this configuration and the 8-bit data is controlled by one byte-enable (MBE0n).

Figure 9-11. 8-bit Memory Connection

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Technical Reference Manual Table 9-8. Address to MBEn translation (bus width= 16 & little endianess) CPU operation HAddr[1:0] (Two least significant address bits at AHB) MBEn [3:0] Word xx 1110 Halfword 1x 1110 0x 1110 Byte 00 1110 01 1110 10 1110 11 1110 9.3.6. NAND Interface The aJ-200 includes a flash host controller that provides an 8-bit access to the NAND flash memory. Its based on the existing SRAM interface and is mapped into one of the available SRAM bank. The control and timing of the selected SRAM bank has been extended via the NAND logic interface, in order to provide the appropriate timing and signals required for the NAND interface. It provides the hardware-based NAND host controller so that the data can be transferred in the high speed mode. The ECC information will be automatically generated in the programming operation and will be checked in the read operation. It supports the following features: 8-bit data bus ECC for error detection and generation Sequential page program over one page Programmable flash timing parameters Sequential read over one page

The figure below illustrates the simplified block diagram of the NAND interface.

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AHB AHB Slave (MEM) AHB Slave (MEM) SDRC

Static Memory Control Core

NAND Control & Interface

9.3.6.1.

Figure 9-12. Simplified Block Diagram of the NAND Interface Command Set

The flash controller supports 12 commands/operations. These commands are microcoded and upload into the WCS on the POR from an external Flash memory. Function Read 1 Read 2 Read ID Reset Page Program Copy-Back Program Lock Unlock Lock-tight Read Block Lock Status Block Erase Read Status 9.3.6.2. 1st. cycle 01h 50h 90h FFh 80h 0h 2Ah 23h 2Ch 7Ah 60h 70h 2nd. cycle 10h 8Ah 24h D0h Acceptable Command during Busy

NAND Control and Interface

The control block of the NAND memory interface issues the commands to the memory modules according the control registers. For a write cycle, it loads the write address into the address latch phase and the write data into the data transfer phase. For a read cycle, it issues a read command to the memory module and then receives read data from the memory module and pushes them into the data register. The control

ebi_vlio_rdy CLE NAND_WRn ALE NAND_REn

ebi_gnt ebi_req EBI

MADDR[24:0]

MDATA[31:0]

MBE[3:0]

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Technical Reference Manual block of the memory interface determines the AC timing to access the memory module according to the content of the control registers. The following figures illustrate the timing waveforms
HCLK

tCS
SMC_CS[7:0]n

tCH

tALH
ALE

tCLS
CLE

tCLH

tALS
NAND_WRn

tWP

tDS
MDATA[7:0]

tDH

Command

Figure 9-13. Command Latch Cycle

HCLK tCS SMC_CS[7:0]n tALS ALE tCLS CLE tWP NAND_WRn tDS MDATA[7:0] Addr#1 tDH Addr#2 Addr#3 tALH tCH

Figure 9-14. Address Latch Cycle

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HCLK

SMC_CS[7:0]n tCS CLE tCLS NAND_WRn tWHR NAND_RDn tREA MDATA[7:0] CMD Status tCHZ tWP tCLP

Figure 9-15. Status Read Cycle

HCLK

SMC_CS[7:0]n

tALS
ALE

CLE

tWC
NAND_WRn

tWP

tCLH

MDATA[7:0]

DATA#0

DATA#1

DATA#2

Figure 9-16. Input Data Latch Cycle

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HCLK

SMC_CS[7:0]n

R/Bn

tRR
NAND_RDn

tRC tREA

MDATA[7:0]

Figure 9-17. Sequential Read Cycle

HCLK

SMC_CS[7:0]n

ALE

CLE tWP NAND_WRn tWC

NAND_RDn

MDATA[7:0]

Read Command

Column Address #n

Row Address #n

Row Address #n

Dout# n

Dout# n+1

Dout# n+2

R/Bn

Busy

Figure 9-18. Read 1 Operation Cycle

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HCLK

SMC_CS[7:0]n

ALE

CLE tWC NAND_WRn

NAND_RDn

MDATA[7:0]

Write Command=80h

Column Address

Row Address #1

Row Address #2

Dout# n

Dout# n+1

Programm

Dout# n+2

Status CMD

R/Bn

Busy

Figure 9-19. Read 1 Operation Cycle

HCLK

SMC_CS[7:0]n

ALE

CLE tWC NAND_WRn

NAND_RDn

MDATA[7:0]

Auto Block Erase

Page Row Address

Page Row Address

Erase Command

Read Status

0 or 1

R/Bn

Busy

Figure 9-20. Erase Cycle

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MDATA[7:0] SMC_CS1n ALE CLE

I/O[7:0] CEn ALE CLE WEn REn R/Bn

aJ-102

NAND_WEn NAND_REn GPIOA7

NAND FLASH 32MBx8

Figure 9-21. Interface between aJ-200 and NAND Memory 9.3.7. Summary of Static Memory Controller Registers The below table shows the summary of SMC control registers Table 9-9. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Static Memory Controller Register Summary Reset Value {30h0, ini_mbw[1:0]} 0xof1ff3ff 0x00000800 0x0f0ff3ff 0x00000800 0x0f0ff3ff 0x00000800 0x0f1ff3ff 0x00000800 0x0f1ff3ff 0x00000800 0x0f1ff3ff 0x00000800 0x0f1ff3ff 0x00000800 0x0f1ff3ff 0x0000_0000

Description Memory Bank 0 Configuration Register Memory Bank 0 Timing Parameter Register Memory Bank 1 Configuration Register Memory Bank 1 Timing Parameter Register Memory Bank 2 Configuration Register Memory Bank 2 Timing Parameter Register Memory Bank 3 Configuration Register Memory Bank 3 Timing Parameter Register Memory Bank 4 Configuration Register Memory Bank 4 Timing Parameter Register Memory Bank 5 Configuration Register Memory Bank 4 Timing Parameter Register Memory Bank 6 Configuration Register Memory Bank 6 Timing Parameter Register Memory Bank 7 Configuration Register Memory Bank 7 Timing Parameter Register Shadow Status Register

The following sections describe the details of static memory controller registers. 9.3.7.1. Memory Bank 0~7 Configuration Registers These registers contain the base, memory type, memory bus width and size of corresponding external memory bank. Table below shows the bit assignment of bank configuration register. Table 9-10. Bit
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Name

Type

Technical Reference Manual Bit 31-29 28 27-15 14-12 11 Name BNK_EN BNK_BASE -BNK_WPROT Type R/W R/W -R/W Description Reserved Bank enable flag. 0 Disabled 1 Enabled Bank base address. The value of this register equals the address bits 27 to 15 on AHB. Reserved. Writing to these bits takes no effect. Reading from these bits will return a value of zero. Bank write protect. 0 The corresponding bank can be read or written. 1 The corresponding memory bank cannot be written. Any write to protected banks will cause an ERROR response on AHB. Bank type 1. Indicate if the devices on the corresponding bank are synchronous or asynchronous 0 Asynchronous 1 Synchronous. Bank type 2 0 This bit indicates if the devices on the corresponding bank are general asynchronous devices or burst ROMs. 1 Indicates burst ROMs and 0 indicates general asynchronous devices. If BNK_TYP1 is set to 1, this bit indicates if the devices on the corresponding bank are pipelined or non-pipelined. Setting this register to 1 indicates pipelined devices and 0 indicates nonpipelined devices. Bank type 3 This bit is only valid when BNK_TYP1 is set to 1 and indicates if write latency exists on the corresponding devices (i.e. late-write). 0 Late-write is disabled. 1 Late-write is enabled and tAT1 will decide the depth of late-write. Bank size. The following encoding shows the size of bank. Bank size other than the following values may cause an unexpected error. 0000 1MB 0001 2MB 0010 4MB 0011 8MB 0100 16MB 0101 32MB 0110 Reserved : 1111 Reserved Reserved

10

BNK_TYP1

R/W

BNK_TYP2

R/W

BNK_TYP3

R/W

7-4

BNK_SIZE

R/W

3-2

--

--

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Technical Reference Manual Bit Name Type Description Memory bus width. This register indicates the bus size of external memory bus. Write values larger than 3 will modulo by 4. 00 Memory data width is 8 01 Memory data width is 16 10 Memory data width is 32 11 Reserved

1-0

BNK_MBW

R/W

Note: The initial value of BANK0 configuration register must be initialized properly to access boot ROM. 9.3.7.2. Memory Bank 0 ~ 7 Timing Parameter Registers

This register configures the access timing of corresponding external memory bank. The controller automatically inserts turn-around cycles to meet read followed by write timing specification even tTRNA is specified as zero. User specified turn-around cycles can be inserted by specifying tTRNA in bank timing register. Table below shows the bit assignment of timing control register. The default value of each bit depends on configuration. Bit 31-28 27-24 23-21 20 19-18 17-16 Table 9-11. Name Type ETRNA EAT1 -RBE AST CTW R/W R/W -R/W R/W R/W Memory Bank Timing Parameter Registers Description Extend turn-around time. The total turn-around time is the cascade of this register and the TRNA field. Extend access time 1. The total access time the static memory controller uses is the cascade of this register and AT1. Reserved Read byte-enable. If this bit is set to 1, byte-enable will be pulled LOW when read. Otherwise, byte-enable will be pulled LOW only for write operation. Address setup time. This register specifies the latency needed to assert chip-enable after address assertion. Chip-select to write-enable delay. This register specifies the latency needed to assert write-enable after chip-enable assertion. Access time 1. This register specifies the latency to latch (read) or change data (write) after write-enable assertion when general asynchronous device is specified. The value must be larger than zero. Setting this register to zero is acceptable but the behavior will be unpredictable. If the device is specified as burst ROM, this register indicates the read/write latency of first data. If BNK_TYPE1 is set as 1 (synchronous devices), this register indicates the depth of late-write and the maximum value of this value is 2 (value exceeding 2 will be reset to zero).
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AT1

R/W

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Technical Reference Manual Bit 11-10 9-8 Name -AT2 Type -R/W Description Reserved. Writing data to this register takes no effect and zero will be returned when read. Access time 2. This register specifies the latency needed to latch the burst read data. This register is only used when device type is specified as burst ROM. Write-enable to chip-select delay. This register specifies the latency needed to de-assert chip-enable after write-enable de-assertion. Address hold time. This register specifies the latency needed to de-assert address after chip-select de-assertion. Turn-around time. This register specifies the latency needed to re-drive data bus.

7-6 5-4 3-0

WTC AHT TRNA

R/W R/W R/W

Asynchronous devices timing waveform Figure below shows the write timing of asynchronous devices. Tables 9-9 ~ 9-14 show the register setting and actual write timing mapping relation.

HCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] MDATA[31:0] SMC_OEn

Figure 9-22. Timing diagram of SMC write to asynchronous devices Table 9-12. Address Setup Time Address Setup Time (AST) AST register value 0 1 2 3 tAST[hclk] 0 2 3 4 Table 9-13. Chip-select write-enable delay Chip-select to write-enable delay (CTW) 0 1 2

CTW register value

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Technical Reference Manual t CTW [hclk] 0 2 Table 9-14. Write Enable Width Write Enable Width 0 1 2 Not allowed 2 3 Not allowed 3 4 3 4

AT1 register value tAT1 (tWTC and that=0) [hclk] tAT1 (tWTC or that > 0) [hclk] Note:

3 4 5

N N+1 N+2

tWE(unit: hclk)=16*ETA1+AT1

Table 9-15. Write Enable to Chip Select Delay Write Enable To Chip Select Delay WTC register value 0 1 tWTC (tAHT =0) [unit:hclk] 0 1 tAT1 (tAHT > 0) [unit:hclk] 9 2 Table 9-16. Address Hold Time Address hold time 0 1 0 1 Table 9-17. Turn around time Turn around time 0 1 2 Not allowed 2 3

2 2 3

3 3 4

AHT register value tAHT [unit:hclk]

2 2

3 3

TRNA register value tTRNA [unit:hclk] Note:

3 4

N N+1

(ETRNA and TRNA = 0) tTR (hclk) = 1 tTR (hclk) = 16 x ETRNA + tTRNA Figure below shows the read timing of asynchronous devices. Table 9.15~ Table 9.20 show the register setting and actual read timing mapping relation.
HCLK MADDR[24:0] SMC_CS[7:0]n SMC_OEn MDATA[31:0] tAST

tCTW

tOE

tWTC

tAHT

tTR

Figure 9-23. Timing diagram of SMC read from asynchronous devices

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AST register value tAST[unit: hclk]

Table 9-18. Address Setup Time (AST) Address Setup Time (AST) 0 1 2 0 2 3 Table 9-19. Chip-select to write-enable delay (CTW) Chip-select to write-enable delay (CTW) 0 1 2 0 2 3

3 4

CTW register value t CTW [unit: hclk]

3 4

Table 9-20. Output Enable Width Output Enable Width AT1 register value 0 1 2 tAT1 (tWTC and that=0) [unit:hclk] Not allowed 2 3 Note: tOE (unit: hclk)=16*ETA1+tAT1 Table 9-21. Output Enable To Chip Select Delay Output Enable To Chip Select Delay WTC register value 0 1 tWTC (tAHT =0) [unit:hclk] 0 1 tAT1 (tAHT > 0) [unit:hclk] 9 2 Table 9-22. Address hold time Address hold time AHT register value 0 1 tAHT [unit:hclk] 0 1 Table 9-23. Turn around time Turn around time TRNA register value 0 1 2 tTRNA [unit:hclk] Not allowed 2 3 (ETRNA and TRNA = 0) tTR (unit: hclk) = 1 tTR (unit: hclk) = 16 x ETRNA + tTRNA Synchronous devices timing waveform The following two figures show the write timing of synchronous early write devices.

3 4

N N+1

2 2 3

3 3 4

2 2

3 3

3 4

N N+1

Note:

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HCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] SMC_OEn MDATA[31:0] MDATA1 MDATA2 MDATA3 tTR A1 A2 A3 A4

Figure 9-24. Timing diagram of SMC write to synchronous early write devices (ETRNA and TRNA = 0)

HCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] SMC_OEn MDATA[31:0] MDATA1 MDATA2 MDATA3 MDATA4 tTR A1 A2 A3 A4

Figure 9-25. Timing diagram of SMC write to synchronous early write devices (ETRNA or TRNA > 0) The following two figures show shows the write timing of synchronous late write devices.
HCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] SMC_OEn MDATA[31:0] MDATA1 MDATA2 MDATA3 MDATA4 tTR A1 A2 A3 A4

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Technical Reference Manual Figure 9-26. Timing diagram of SMC write to synchronous late write devices (ETRNA and TRNA = 0)
HCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] SMC_OEn MDATA[31:0] MDATA1 MDATA2 MDATA3 MDATA4 tTR A1 A2 A3 A4

Figure 9-27. Timing diagram of SMC write to synchronous late write devices (ETRNA or TRNA > 0) The next two following figures show the write timing of synchronous late-late write devices.
HCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] SMC_OEn MDATA[31:0] MDATA1 MDATA2 MDATA3 tTR MDATA4 A1 A2 A3 A4

Figure 9-28. Timing diagram of SMC write to synchronous late-late write devices (ETRNA and TRNA = 0)
HCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] SMC_OEn MDATA[31:0] MDATA1 MDATA2 MDATA3 tTR MDATA4 A1 A2 A3 A4

Figure 9-29. Timing diagram of SMC write to synchronous late-late write devices

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Technical Reference Manual (ETRNA or TRNA > 0) TRNA register setting mapping for synchronous devices Table 9-24. TRNA Register Turn around time 0 1 2 2 3 4

TRNA register value tTRNA [unit:hclk] Note:

3 5

N N+2

(ETRNA and TRNA = 0) tTR (unit:hclk) = 1 (ETRNA or TRNA > 0) tTR (unit:hclk )= 16 * ETRNA + tTRNA 9.3.7.3. Burst ROM access timing waveform Figure below shows the read timing diagram of burst ROMs, and tables 9-19~ 9-21 show the register setting mapping to actual burst ROM read timing.
HCLK MADDR[24:0] SMC_CS[7:0]n SMC_OEn MDATA[31:0] tRL1 DQ1 tAT2 DQ2 tAT2 DQ3 tAT2 DQ4 A1 A2 A3 A4

Figure 9-30. Timing Diagram of Burst ROMs Table 9-25. AT1 register setting mapping for burst ROM Read latency of the first Burst ROM data 0 1 2 3 2 3 4 5

AT1 register value tAT1 [unit:hclk]

N N+2

NotetRL11(unit: hclk) = 16 * EAT1 + tAT1 Table 9-26. AT2 register value tAT2 [unit:hclk] AT2 register setting mapping for burst ROM Read latency of the Burst ROM data 0 1 2 3 1 2 3 4

N N+1

9.3.8. Shadow Status Register (Offset == 0x40) Due to the access speed of boot ROM, most systems need to shadow fast SRAM to boot ROMs address space. The static memory controller proposes a shadow status register for user to switch bank 0 with
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Technical Reference Manual other banks. Bit 31-10 8 7-6 5 Name -SSR_STS -SSR_REQ Table 9-27. Shadow Status Register Type Description -Reserved Shadow status. If this bit is 1, it indicates controller is in bank switch mode. All R memory accesses to bank 0 will be re-directed to SSR_BNKNUM set in shadow status register and all memory accesses to BANKNUM will be redirected to bank 0. R Reserved Shadow request. If this register is set to 1, controller will try to switch the bank R/W/AC information of bank 0 and SSR_BNKNUM. Once done, this bit will be cleared to zero. Shadow request mode. If this register is set to 1, the corresponding request is requesting R/W for shadow enable function. Otherwise, shadow disable function is requested. -Reserved Shadow bank number. R/W If SSR_STS is set to 1, all memory accesses to SSR_BNKNUM will be re-directed to bank 0.

4 3 2-0

SSR_REQM -SSR_BNKNUM

If user wants to enable switch function, it has to set SSR_REQ to 1, SSR_REQM to 1 and the corresponding bank number to SSR_BNKNUM. Controller then will wait for suitable conditions to do bank switching. Once done, SSR_STS will be set to 1 and SSR_REQ will be cleared automatically. If switch function is to be disabled, SSR_REQ has to be set to 1, and SSR_REQM set to 0. Controller knows that it is currently in bank switching state, so it will wait for some conditions to recover the original bank information. SSR_BNKNUM will not reflect the write value immediately. It will be updated when bank switch conditions are met. Writing SSR_BNKNUM with SSR_REQ set to 0 takes no effect on SSR_BKNUM. 9.3.9. Programming Sequence This section depicts the initialization sequence of static memory controller. 9.3.9.1. Initializing Bank Configuration Register

SRC provides eight external memory banks. The user has to initialize the bank configuration register before the corresponding memory residing on external bank can be accessed. BNK_EN determines if the corresponding external bank can be accessed. If no physical memory exists on the corresponding banks, it can be disabled via this register and any access to this bank will get an ERROR response on AHB bus. BNK_BASE is the 13-bit base address of external bank. The 13 bits should equal bits 15 to 27 of the

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Technical Reference Manual address line of physical address. BNK_WPROT determines if the corresponding bank can be written. For example, any write to ROM is not expected. Any attempt to write to protected external bank will get an ERROR response on AHB bus. BNK_SIZE determines the bank size of the corresponding bank. The bank types 1 to 3 decide the physical memory type. As shown in Table 9-28, three main static memory types are supported. Table 9-28. Bank Type Setting {BNK_TYP1, BNK_TYP2, BNK_TYP3, BNK_TYP4, BNK_TYP5, BNK_TYP6, Memory Type BNK_TYP7} Asynchronous SRAM {0, 0, X} Burst ROM {0, 1, X} BNK_MWB determines the external memory bus width of corresponding banks. Because static memory controller may be used to control boot ROM, this registers value should be determined after reset completion immediately, that is, before any code can be executed. The static memory controller latches ini_mbw into bank0 configuration register from jumper setting pin. For other external banks, BNK_MBW can be properly programmed before access. 9.3.9.2. Initializing Bank Timing Register The bank timing register is used to control the access timing latency of corresponding memory type. The user has to refer to the specification of the memory type used and translate the corresponding timing parameter into the number of cycles needed. This timing register brings impacts on the correctness as well as performance of accesses. After the above two steps, the static memory can be accessed. 9.4. SDRAM Controller (SDRAMC) 9.4.1. General Description The SDRAM memory controller supports four 8-, 16-, 32-bit wide bank. The SDRAM controller performs auto-refreshing (CBR) during normal operation, and supports SDRAM self-refreshing in sleep mode. SDRAMC shares the address and data bus with Static Memory Controller (SMC). It supports the following features:

Rich SDRAM types and mobile SDRAM Wide address range up to 512 Mbytes Zero-wait-state writes Programmable refresh control Programmable refresh scheme (staggered / non-staggered) Six AHB channels
o

LCD controller

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o o o

DMA controller Three video capture ports MediaCodec

Four-word deep data FIFO Automatic power-down mode

The following figure shows the block diagram of SDRAM controller.

AHB slave (For control register) Refresh controller

Main AHB

AHB channel 0

SDRAM arbiter

Application specified AHB 1

AHB channel 1

Channel command Channel mux Controller engine

SDRAM interface

Application specified AHB 6

AHB channel 6

ebi_reg_r ebi_gnt_a

Figure 9-31. Block Diagram of SDRAM Controller The main building blocks of SDRAM controller are composed of AHB channel ports, refresh controller, arbiter and controller engine. The following sections contain detailed descriptions of each building block. 9.4.2. AHB Channel This block acts as an interface between the AHB and SDRAM controller engine. It comprises six independent AHB channels (used to access external SDRAM) and one AHB register slave (used to access the registers of SDRAM controller). In the read mode, command from AHB will be decoded and the memory read command will be issued by this block to SDRAM controller engine. Data from the SDRAM controller engine will be latched into the FIFO first and then pushed onto AHB. In the write mode, data and address will first be latched into the FIFO and the HREADY will be pulled high to end the bus cycle. AHB slave will write data to SDRAM later. The six AHB channels are fully independent and allow direct access to SDRAM as follows:
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AHB main for main AHB AHB channel 1 for DMA controller AHB channel 2 for LCD controller AHB channels 3, 4, 5 for Video capture ports AHB channel 6 for MediaCodec

9.4.3. Refresh Controller The refresh controller periodically issues auto-refresh command to prevent data in SDRAM from loss. The period of refresh command can be programmed and it depends on system clock speed and SDRAM specification. The refresh interval defined in SDRAM datasheet means all rows (row_num) should be refreshed completely in a specified time interval (Tref). The following formula helps user translate the period into number of clock cycles between refreshes.

REF _ INTV =

Tref Fclk row _ num

For example, some SDRAM with 4096 rows should be refreshed completely within 64 ms (Tref). Suppose that the system clock (Fclk) runs at 100 MHz, the calculated value of REF_INTV is 1562.5 cycles. That is, the refresh interval between two refreshes cannot be longer than 1562.5 cycles. Because the control register can only represent integer values, 1562 (0x61A) is set to REF_INTV of timing register 1. The refresh controller then knows when to refresh SDRAM to prevent data from loss. The other command issued by refresh controller is power down command. If the user sets the power down bit in SDRAM controller register or triggers the sdc_serf_req signal, power-down command will be issued by refresh controller to control engine and self-refresh command will be issued to SDRAM. 9.4.4. Arbiter The arbiter provides arbitration between AHB channels and refresh controller. Except the requests from refresh controller, the arbiter employs the round-robin arbitration scheme. That is, if the first channel is granted the right to access SDRAM, it will have the lowest priority after accessing the SDRAM. Normally, the arbiter will not remove grant from the currently granted channel until the channel request is released. To prevent other AHB channels from starvation, the grant window mechanism is provided. Every channel has its independently programmable grant window. After running out of the grant window, the grant will be removed from the currently granted channel and provided the grant to other channel, if any. The grant window unit is based on the SDRAM burst access (the burst length of SDRAM is fixed to 4). Presuming the read request from AHB is INCR16 with WORD, the bus width of SDRAM is 32 and the grant window of the corresponding channel is set to 2. In this case, the INCR16 access will be broken into four SDRAM accesses if there are other channels requesting to access the SDRAM as well. That is, the
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Technical Reference Manual channel grant is removed after the second grant, and restored after the access of other channel is completed (or running out of the grant window of channel request de-assertion). Due to the read/write ordering issues, the arbiter supports the flush request from any channel. If the flush request from the corresponding channel is asserted, the arbiter will remove the grant request of the currently granted channel even if the corresponding channel has not run out of its grant windows. Then the grant will park on the channel with the flush request. After the write data written into the write buffer are flushed before the flush flag is set, the flush request will be de-asserted. That is, the flush request only takes effect on the write data existing before the flush flag is set. Data written into the write buffer after the flush flag is set will not request for flush. 9.4.5. Control Engine Control engine is the functional block used to generate SDRAM accessing cycles, including memory read, memory write, pre-charge, self-refresh, and auto-refresh. Timing parameter will be used to control SDRAM signal to meet the SDRAM specification. Data read from SDRAM will be latched in control engine and returned to corresponding AHB channels. Control engine will automatically extend the channel command for different type of external memory bus width. For example, if the access command from AHB is WORD wide but the external memory bus width is only 8 bits, then the control engine will automatically extend the one channel command to four SDRAM access commands. Once the four extended commands are completed, control engine will signal the AHB channel to issue next command. The SDRAM controller also supports the power-down mode operation. If the user sets the power down bit (PWDN) in the SDRAM control register, the power-down command will be issued automatically by the controller engine as long as the SDRAM controller is at the idle state for a pre-defined period. Any read or write or auto-refresh command will cause the SDRAM controller to activate SDR_CLKEN and SDRAM to exit from the power-down mode. If the user sets the self refresh bit (SREF), the self-refresh command will be issued to SDRAM automatically when the SDRAM controller is at the idle state for a pre-defined period. Any read or write command will cause the SDRAM controller to activate SDR_CLKEN and SDRAM to exit from the self-refresh mode. These two bits must be programmed after the initialization of SDRAM is finish. The PWDN and SREF cannot be set to 1 at the same time. Setting the self-refresh bit causes the SDRAM controller to issue a self-refresh command. To enable sharing of the SDRAM address and data pins with the static memory controller, external bus REQ / ACK is used to request for use of address and data bus. 9.4.6. Programming Model 9.4.6.1. Summary of SDRAM Controller Registers

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Technical Reference Manual Table 9-29. SDRAM Controller Register Summary Offset Address Type Description 0x00 R/W SDRAM Timing Parameter 1 0x04 R/W SDRAM Timing Parameter 2 0x08 R/W SDRAM Configuration Register 1 0x0C R/W SDRAM Configuration Register 2 0x10 0x2C R/W External Bank1 Base / Size Register 0x30 R/W Read Arbitration Group Register 0x34 R/W Flush Request Register 0x38 R EBI Support Register 0x3C R/W Mobile SRAM Support Register 9.4.6.2. SDRAM Timing Parameter 1 (Offset = 0x00)

Reset Value 0x00022602 0x00480820 0x00001226 0x00000000 Case dependent 0x44444444 0x00000000 0x00000000 0x00000000

This register configures the access timing of SDRAM controller. Figure below shows the basic access timing of SDRAM. For more details about SDRAM access timing diagram, please refer to SDRAM module specification available from your provider.

HCLK CMD CMDACK DCMD ACT Trcd R ACT Tcl W PRC ACT R W

DQ

RD Twr Tras

WD Twr

Trp

Bank#0 Bank#1 Bank#2 Bank#3 IDLE Active Read Active Write PreCharge Active

Figure 9-32. Basic SDRAM Access Timing Table below shows the bit assignment of SDRAM timing parameter 0. Bit 31-20 Name Table 9-30. SDRAM Timing Parameter 1 Register Type Description Reserved

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Technical Reference Manual Bit 19-16 15 14-12 Name TRP TRCD Type R/W R/W Description Precharge cycle time. This parameter specifies the cycles needed by the precharge command. The next valid SDRAM command can be issued after the time specified in this parameter. Reserved for convenient read / write RAS-to-CAS delay. This parameter specifies the minimum period between active command and the following read / write command. The maximum allowed value is 3. Auto-refresh cycle time. This parameter specifies the time needed by SDRAM to execute auto-refresh command. The next valid SDRAM command can be issued after the time specified in this parameter. Reserved for convenient read / write Write-recovery time. This parameter specifies the period between PRECHARGE and last valid write data and the period between last read data out and WRITE command. Reserved for convenient read / write CAS-latency. This parameter specifies the time period between read command and first data out. Due to limitation of read pipeline, the allowed CAS latency is 4b0010(2) or 4b0011(3).

11-8 7-6 5-4 3-2 1-0

TRF TWR TCL

R/W R/W R/W

9.4.6.3.

SDRAM Timing Parameter 2 (Offset = 0x04)

The refresh and pre-charge commands should be issued after SDRAM is powered on. This register configures the initial refresh times and refresh period. Bit 31-24 23-20 19-16 15-0 9.4.6.4. Name INI_PREC INI_REFT REF_INTV Table 9-31. Type R/W R/W R/W SDRAM Timing Parameter 2 Register Description Reserved Initial pre-charge times. The default value of this register is 4. Initial refresh times. The default value of this register is 8. Refresh interval. One refresh command should be issued if refresh counter equals refresh interval.

SDRAM Configuration Register 1 (Offset = 0x08)

This register configures the status of SDRAM controller. Table 9-32. SDRAM Configuration Register Type Description R Reserved Double memory address cycle enable. If MA2T is set to 1, the command phase will occupy two clock R/W nd cycles but csb will be active at the 2 cycle only. This is used for
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Bit 31-17 16

Name MA2T

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Technical Reference Manual Bit Description heavy loading system. It is recommended to set MA2T to 0 except when the system adopts several external banks. Thus, a little performance penalty will take place while MA2T is set to 1, because it takes 2 cycles to issue each command R Reserved SDRAM data width. This field indicates the data width of the individual SDRAM devices 00 x4 device DDW R/W 01 x8 device 10 x16 device 11 x32 device R Reserved SDRAM size. This field indicates the density of SDRAM components 000 16 Mb DSZ R/W 001 64 Mb 010 128 Mb 011 256 Mb 100 512 Mb R Reserved Memory bus width. This field indicates the bus width of the external memory bus. 00 Memory data width is 8 MBW R/W 01 Memory data width is 16 10 Memory data width is 32 11 Reserved Bank size. The following encodings show the sizes of the bank (in bytes), that is, the sizes of all memories are attached to a single external bank of the controller. The bank sizes other than the following values may cause an unexpected error: 0001 2 MBytes 0010 4 MBytes BNKSIZE R/W 0011 8 MBytes 0100 16 MBytes 0101 32 MBytes 0110 64 MBytes 0111 128 MBytes 1000 256 MBytes 1001 512 MBytes SDRAM Configuration Register 2 (Offset = 0x0C) Table 9-33. SDRAM Configuration Register 2 Type Description Reserved RO SREF_MODE is set when the controller issues self refresh Name Type

15-14

13-12

11

10-8

7-6

5-4

3-0

9.4.6.5.

This register configures the status of SDRAM controller. Bit 31-21 20 Name SREF_MODE

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Technical Reference Manual Bit Name Type Description command to SDRAM and it is cleared when SDRAM is waked up by the controller. This bit is read only. CPU can read this bit to realize whether SDRAM is in the self-refresh mode or not. Reserved A pre-defined time period. When the SDRAM controller is at the idle state over this predefined time period, SDRAM controller will enter the power mode or self-refresh mode depending on the setting of PWDN and SREF bits. 0x0 0 cycle (default value) 0x1 1 cycle 0x2 2 cycles : 0x3ff 1023 cycles Reserved Address mapping table selector. If AMTSEL is set to 1, the bank address will be the upper part of an address from the AHB command. That is, the address mapping is as follow: haddr = { chip-sel, bank, ras, cas, byte-addr} If AMTSEL is set to 0, the bank address will be the middle part of an address. That is, the address mapping is as follow: haddr = { chip-sel, ras, bank, cas, byte-addr} The default setting is 0. Initial pre-charge Start Flag If IPREC is set to 1, the SDRAM controller will start pre-charging if SDRAM stays in the idle state. This flag will be cleared to 0 if the executed pre-charge command equals to the specified initial precharge counts. Writing a zero to this bit takes no effect. Initial Refresh Start Flag. If IREF is set to 1, the refresh controller will start sending the refresh command to the controller engine until the initial refresh times. This flag will be cleared if the executed refresh command equals to the specified initial refresh times. Writing a zero to this bit takes no effect. Start SET-MODE-REGISTER and SET-ENTENDED-MODEREGISTER commands. If ISMR is set to 1 and MOBILE is set to 1, the refresh controller will send the SET-MODE-REGISTER and SET-EXTENDEDMODE-REGISTER commands to the controller engine. If ISMR is set to 1 and MOBILE is set to 0, the refresh controller will send SET-MODE-REGISTER command to the controller engine only. This bit will be cleared if the command is done. Writing 0 to this bit takes no effect. Power-down operation mode. If this parameter is set to 1, the controller engine will pull CKE low to the suspend clock while the SDRAM controller is at the idle state over a pre-defined time period. Self-refresh mode.
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19-18

17-8

T_PDSR

R/W

7-6

AMTSEL

R/W

IPREC

R/W

IREF

R/W

ISMR

R/W

1 0
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PWDN SREF

R/W R/W

Technical Reference Manual Bit Name Type Description If this parameter is set to 1, the controller engine will send the self-refresh-entry command to SDRAM while the controller is at the idle state over a pre-defined time period.

9.4.6.6.

External Bank Configuration Register (Offset = 0x10 ~ 0x2C)

The number of external bank can be configured from one to eight, so the number of external bank configuration register may vary. Bit 31-13 12 11-0 9.4.6.7. Name EN BASE Table 9-34. External Bank Configuration Register Type Description Reserved Bank enable flag. R/W Enabled if BNK_EN = 1 Disabled if BNK_EN = 0 (default) 12-bit base address of external bank. R/W Default value is 0x800. The 12-bit equals haddr[31:20] of AHB address bus.

Arbiter Control Register (Offset = 0x30)

This register defines the arbitration grant window of each AHB channel. The grant window defines the maximum number of SDRAM commands on a specific channel. The practical value of the grant window is the setting value plus one. The arbiters behavior is different between the read command and the write command. The following describes the detail of the arbiter behavior. For read command Step1 Once the arbiter receives one AHB command from AHB bus. The arbiter will analyze the command type to decide how many SDRAM commands are needed to be issued to the SDRAM memory. The following is the mapping table of AHB command type and SDRAM command number needed.

Takes HSIZE = WORD and memory bus width = 32 bits as example. Each SDRAM command contains 4 words. SINGLE => 1 SDRAM command Incr4 => 1 SDRAM command Wrap4 => 1 SDRAM command Incr8 => 2 SDRAM commands Wrap8 => 2 SDRAM commands Incr16 => 4 SDRAM commands Wrap16 => 4 SDRAM commands

Step2

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Technical Reference Manual If the SDRAM command number is greater than the grant window value plus one, then the arbiter will rearbitrate when (grant window value + 1) SDRAM commands are issued to SDRAM memory, the remained SDRAM commands will be issued when the channel is granted next time. If the SDRAM command number is less than the grant window value plus one, the arbiter will re-arbitrate when all SDRAM commands are issued to the SDRAM memory. For write command Because the SDMC supports the post-write feature, the written data of AHB is stored at FIFO, and the SDMC will write the data to the SDRAM memory later. The write behavior is different from the read command. If the grant window value is 0 (or 1), the arbiter will re-arbitrate when 1 (or 2) write command is issued to SDRAM memory. For other grant window value, the arbiter will re-arbitrate when all FIFO data are written to the SDRAM memory. Bit 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0 9.4.6.8. Name CH8GW CH7GW CH6GW CH5GW CH4GW CH3GW CH2GW CH1GW Table 9-35. Arbiter Control Register Type Description Grant window value of Channel 8 R/W The valid value ranges from 0 to 7. Grant window value of Channel 7 R/W The valid value ranges from 0 to 7. Grant window value of Channel 6 R/W The valid value ranges from 0 to 7. Grant window value of Channel 5 R/W The valid value ranges from 0 to 7. Grant window value of Channel 4 R/W The valid value ranges from 0 to 7. Grant window value of Channel 3 R/W The valid value ranges from 0 to 7. Grant window value of Channel 2 R/W The valid value ranges from 0 to 7. Grant window value of Channel 1 R/W The valid value ranges from 0 to 7.

Flush Request Register (Offset = 0x34)

This register defines the flush request from the AHB channel. Table 9-36. Bit 31-4? 3 2-0 Name FLUSHCMPLT FLUSHCHN Type R/W R/W Arbiter Control Register

Description Reserved and read as as 0 Flush Request Flag If this bit is set to 1, the flushing starts. Once the flush is completed, this bit is cleared to 0. Flush Channel Number These bits specify the number of channels to be flushed. 0 Channel 1

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Technical Reference Manual 1 9.4.6.9. Channel 2 and so on

Mobile SDRAM Support Register (Offset = 0x3C)

The following register defines the setting value while the controller issues the SET-EXTENDED-MODEREGISTER command to mobile SDRAM memory. Table 9-37. Mobile SDRAM Support Register Type Description R Reserved and read as as 0 Mobile SDRAM support enable R/W This bit is set to 1 to support mobile SDRAM. Set partial array self refresh The value will be programmed into the mobile SDRAM extended mode register via the SET-EXTENDED-MODE-REGISTER R/W command. The value defines the amount of memories that will be refreshed during self refresh. PASR is used for mobile SDRAM only. Set driver strength The value will be programmed into the mobile SDRAM extended R/W mode register via the SET-EXTENDED-MODE-REGISTER command. The value defines the SDRAM I/O driver strength. DS is used for mobile SDRAM only.

Bit 31-9 8

Name Mobile

6-4

PASR

1-0

DS

9.4.6.10.

Controller Revision Register (Offset = 0x100)

This register defines the current version of SDRAM controller. Table 9-38. Controller Revision Register Type Description R Reserved and read as as 0 R Major version number R Minor version number R Revision mumber

Bit 31-24 23-16 15-8 70 9.4.6.11.

Name Major_Ver Minor_Ver Rev_Ver

Controller Feature Register (Offset = 0x104)

This register defines the current configuration of the SDRAM controller. Bit 31 30 29 28
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Table 9-39. Controller Feature Register (Offset = 0x104) Name Type Description This bit shows the configured FIFO depth of channel 8 and is CH8_FDEPTH R valid only when channel 8 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is 2.. This bit shows the configured FIFO depth of channel 7 and is CH7FDEPTH R valid only when channel 7 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is 2. This bit shows the configured FIFO depth of channel 6 and is CH6FDEPTH R valid only when channel 6 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is 2. CH5FDEPTH R This bit shows the configured FIFO depth of channel 5 and is
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Technical Reference Manual valid only when channel 5 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is 2. This bit shows the configured FIFO depth of channel 4 and is valid only when channel 4 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is 2. This bit shows the configured FIFO depth of channel 3 and is valid only when channel 3 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is This bit shows the configured FIFO depth of channel 2 and is valid only when channel 2 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is 2. This bit shows the configured FIFO depth of channel 1 and is valid only when channel 1 is configured. A 1 indicates the FIFO depth is 4. A 0 indicates the FIFO depth is 2. Reserved and read as zero External Bus Interface (EBI) If this bit shows a 1, the SDRAM is configured with EBI. If this bit shows a 0, no EBI exists. AHB Channel Bit 8 maps to channel 1, bit 9 maps to channel 2, and so on. If the corresponding bit equals to 1, then the corresponding channel is configured in the controller. AHB Channel Bit 8 maps to channel 1, bit 9 maps to channel 2, and so on. If the corresponding bit equals to 1, then the corresponding channel is configured in the controller.

27 26 25 24 23-17 16

CH4FDEPTH CH3FDEPTH CH2FDEPTH CH1FDEPTH EBI

R R R R R R

15-8

CHN

7-0

EBNK

9.4.7. Address Mapping The SDRC provides two kinds of the address mapping tables. That is, the BanK Address (BA) can be decoded from the upper part of AHB bus address or middle part of AHB bus address. The user can program AMTSEL bit to select which address mapping table to use. SDRC also provides memory bus width configurations. For different memory bus widths, different address decoding schemes must be provided. Table 9.34 ~ Table 9.36 show the address mapping tables with memory bus width being 32, 16, and 8 when AMTSEL is programmed to be 0. Table 9.37~Table 9.39 show the address mapping tables with the memory bus width being 32, 16, and 8 when AMTSEL is programmed to be 1. Table 9-40.
Type 16Mbx16 16Mbx8 16Mbx4 64Mbx32 64Mbx16 64Mbx8 Nr. of SDRAMS 2 4 8 1 2 4 Total Size 4MB 8MB 16MB 8MB 16MB 32MB

Address Decoding with Memory Bus Width Being 32 (AMTSEL = 0)

BS 10 11 12 11,10 11,10 12,11 Row Address 21~11 22~12 23~13 22~12 23~12 24~13 Column Address 12 x x x x x x 11 x x x x x x 10 AP AP AP AP AP AP 9 x x 11 x x x 8 x 10 10 x x 10 7 9 9 9 9 9 9 6 8 8 8 8 8 8 5 7 7 7 7 7 7 4 6 6 6 6 6 6 3 5 5 5 5 5 5 2 4 4 4 4 4 4 1 3 3 3 3 3 3 0 2 2 2 2 2 2

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Nr. of SDRAMS 8 1 2 4 8 1 2 4 8 2 4 8 Total Size 64MB 16MB 32MB 64MB 128MB 32MB 64MB 128MB 256MB 128MB 256MB 512 MB Row Address 25~14 23~12 24~13 25~14 26~15 24~13 25~13 26~14 27~15 26~14 27~15 28~16 Column Address 12 x x x x x x x x x X X 13 11 x x x x 12 x x x 12 X 12 12 10 AP AP AP AP AP AP AP AP AP AP AP AP 9 11 x x 11 11 x x 11 11 11 11 11 8 10 x 10 10 10 10 10 10 10 10 10 10 7 9 9 9 9 9 9 9 9 9 9 9 9 6 8 8 8 8 8 8 8 8 8 8 8 8 5 7 7 7 7 7 7 7 7 7 7 7 7 4 6 6 6 6 6 6 6 6 6 6 6 6 3 5 5 5 5 5 5 5 5 5 5 5 5 2 4 4 4 4 4 4 4 4 4 4 4 4 1 3 3 3 3 3 3 3 3 3 3 3 3 0 2 2 2 2 2 2 2 2 2 2 2 2

Type 64Mbx4 128Mbx32 128Mbx16 128Mbx8 128Mbx4 256Mbx32 256Mbx16 256Mbx8 256Mbx4 512Mbx16 512Mbx8 512Mbx4

BS 13,12 11,10 12,11 13,12 14,13 11,10 12,11 13,12 14,13 13,12 14,13 15,14

(x indicates dont care) Table 9-41.

Type 16Mbx16 16Mbx8 16Mbx4 64Mbx16 64Mbx8 64Mbx4 128Mbxb16 128Mbx8 128Mbx4 256Mbx16 256Mbx8 256Mbx4 512Mbx16 512Mbx8 512Mbx4 Nr. of SDRAMS 1 2 4 1 2 4 1 2 4 1 2 4 1 2 4 Total Size 2MB 4MB 8MB 8MB 16MB 32MB 16MB 32MB 64MB 32MB 64MB 128MB 64 MB 128 MB 256 MB

Address Decoding with Memory Bus Width Being 16 (AMTSEL=0)

BS 9 10 11 10,9 11,10 12,11 11,10 12,11 13,12 11,10 12,11 13,12 12,11 13,12 14,13 Row Address 20~10 21~11 22~12 22~11 23~12 24~13 23~12 24~13 25~14 24~12 25~13 26~14 25~13 26~14 27~15 Column Address 12 x x x x x x x x x x x x X X 12 11 x x x x x x x x 11 x x 11 X 11 12 10 AP AP AP AP AP AP AP AP AP AP AP AP AP AP AP 9 x x 10 x x 10 x 10 10 x 10 10 10 10 10 8 x 9 9 x 9 9 9 9 9 9 9 9 9 9 9 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

(x indicates dont care) Table 9-42.

Type 16Mbx8 16Mbx4 64Mbx8 64Mbx4 128Mbx8 Nr. of SDRAM 1 2 1 2 1 Size 2MB 4MB 8MB 16MB 16MB

Address Decoding with Memory Bus Width Being 8 (AMTSEL=0)

BS 9 10 10,9 11,10 11,10 Row Address 20~10 21~11 22~11 23~12 23~12 Column Address 12 x x x x x 11 x x x x 10 10 AP AP AP AP AP 9 X 9 x 9 9 8 8 8 8 8 8 7 7 7 7 7 7 6 6 6 6 6 6 5 5 5 5 5 5 4 4 4 4 4 4 3 3 3 3 3 3 2 2 2 2 2 2 1 1 1 1 1 1 0 0 0 0 0 0

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128Mbx4 256Mbx8 256Mxb4 512Mbx8 512Mbx4 2 1 2 1 2 32MB 32MB 64MB 64MB 128 MB 12,11 11,10 12,11 12,11 13,12 22~11 24~12 25~13 25~13 26~14 x x x x 11 10 x 10 10 10 AP AP AP AP AP 9 9 9 9 9 8 8 8 8 8 7 7 7 7 7 6 6 6 6 6 5 5 5 5 5 4 4 4 4 4 3 3 3 3 3 2 2 2 2 2 1 1 1 1 1 0 0 0 0 0

(x indicates dont care) Table 9-43.

Type 16Mbx16 16Mbx8 16Mbx4 64Mbx32 64Mbx16 64Mbx8 64Mbx4 128Mbx32 128Mbx16 128Mbx8 128Mbx4 256Mbx32 256Mbx16 256Mbx8 256Mbx4 512Mbx16 512Mbx8 512Mbx4 Nr. of SDRAMS 2 4 8 1 2 4 8 1 2 4 8 1 2 4 8 2 4 8 Total Size 4MB 8MB 16MB 8MB 16MB 32MB 64MB 16MB 32MB 64MB 128MB 32MB 64MB 128MB 256MB 128MB 256MB 512 MB

Address Decoding with Memory Bus Width Being 32 (AMTSEL = 1)

BS 21 22 23 22,21 23,22 24,23 25,24 23,22 24~23 25,24 26,25 24,23 25,24 26,25 27,26 26,25 27,26 28,27 Row Address 20~10 21~11 22~12 20~10 21~10 22~11 23~22 21~10 22~11 23~12 24~13 22~11 23~11 24~12 25~13 24~12 25~13 26~14 Column Address 12 x x x x x x x x x x x x x x x X X 13 11 x x x x x x x x x x 12 x x x 12 X 12 12 10 AP AP AP AP AP AP AP AP AP AP AP AP AP AP AP AP AP AP 9 x x 11 x x x 11 x x 11 11 x x 11 11 11 11 11 8 x 10 10 x x 10 10 x 10 10 10 x 10 10 10 10 10 10 7 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

(x indicates dont care) Table 9-44.

Type 16Mbx16 16Mbx8 16Mbx4 64Mbx16 64Mbx8 64Mbx4 128Mbxb16 128Mbx8 128Mbx4 256Mbx16 256Mbx8 No. of SDRAMS 1 2 4 1 1 2 1 2 4 1 2 Total Size 2MB 4MB 8MB 8MB 8MB 16MB 16MB 32MB 64MB 32MB 64MB

Address Decoding with Memory Bus Width Being 16 (AMTSEL=1)

BS 20 21 22 22,21 23,22 24,23 23,22 24,23 25,24 24,23 25,24 Row Address 19~9 20~10 21~11 20~9 21~10 22~11 21~10 22~11 23~12 22~10 23~11 Column Address 12 x x x x x x x x x x x 11 x x x x x x x x 11 x x 10 AP AP AP AP AP AP AP AP AP AP AP 9 x x 10 x x 10 x 10 10 x 10 8 x 9 9 x 9 9 9 9 9 9 9 7 8 8 8 8 8 8 8 8 8 8 8 6 7 7 7 7 7 7 7 7 7 7 7 5 6 6 6 6 6 6 6 6 6 6 6 4 5 5 5 5 5 5 5 5 5 5 5 3 4 4 4 4 4 4 4 4 4 4 4 2 3 3 3 3 3 3 3 3 3 3 3 1 2 2 2 2 2 2 2 2 2 2 2 0 1 1 1 1 1 1 1 1 1 1 1

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256Mbx4 512Mbx16 512Mbx8 512Mbx4 4 1 2 4 128MB 64 MB 128 MB 256 MB 26,25 25,24 26,25 27,26 24~12 23~11 24~12 25~13 x X X 12 11 X 11 11 AP AP AP AP 10 10 10 10 9 9 9 9 8 8 8 8 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1

(x indicates dont care) Table 9-45.

Type 16Mbx8 16Mbx4 64Mbx8 64Mbx4 128Mbx8 128Mbx4 256Mbx8 256Mxb4 512Mbx8 512Mbx4 No. of SDRAM 1 2 1 2 1 2 1 2 1 2 Size 2MB 4MB 8MB 16MB 16MB 32MB 32MB 64MB 64MB 128 MB

Address Decoding with Memory Bus Width Being 8 (AMTSEL=1)

BS 20 21 22,21 23,22 23,22 24,23 24,23 25,24 25,24 26,25 Row Address 19~9 20~10 20~9 21~10 21~10 22~11 22~10 23~11 23~11 24~11 Column Address 12 x x x x x x x x x 11 11 x x x x x 10 x 10 10 10 10 AP AP AP AP AP AP AP AP AP AP 9 X 9 x 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

9.4.8. Programming Sequence This section contains the initialization sequence of the SDRAM controller. Step 1 Wait 200 s After power-on, SDRAM module requires some time to get into stable state. This value varies with different SDRAM modules. The user has to check SDRAM specification and ensure this timing is met before starting to program SDRAM controller. Step 2 Set timing register 1 This register is relevant to SDRAM operations and heavily depends on SDRAM specifications. Properly specifying this timing register can enhance the SDRAM controller performance. The following table shows the typical value of timing register 0 when PC133 SDRAM is used and system clock runs at 133 MHz. Table 9-46. Typical Value of Timing Parameter 0 Timing Parameter Typical Value TRP 3 cycles TRCD 3 cycles TRF 10 cycles TWR 1 cycle TCL 2 cycles Again, the above timing is relevant to actual SDRAM specification and controller performance. Please refer to SDRAM specification to obtain the actual value of timing parameter. Table 9-43 is just a suggestion and there is no assurance that the suggested timing will work on your system.

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Technical Reference Manual Step 3 Set timing register 2

Three timing parameters are defined in this register. The first two parameters are the initial pre-charge and initial refresh times. First, SDRAM module should be pre-charged and refreshed several times before it can be accessed. These two parameters specify the timing needed by the SDRAM module, and they also vary when different SDRAM modules are employed. If the SDRAM specification does not specify these two timing parameters, the user can set them to the maximum value. The third timing parameter specifies the clock cycles between two refresh cycles. This parameter is very important to the SDRAM operation. Step 4 Set configuration register 1 The configuration register 1 defines the SDRAM related parameters, including the SDRAM type, memory bus width, and external bank size. The pair, {DDW, DSZ}, specifies the type of the SDRAM modules residing on the external bank. The MBW specifies the width of the memory bus of the corresponding external banks. {DDW, DSZ, MBW} determines the address mapping table of the SDRAM controller. The BNKSIZE specifies the total size of the corresponding external bank. Whether done by auto-sizing program or manual specification, this configuration of the registers setting should match the physical SDRAM status. Improper programming may cause SDRAM controller to work unexpectedly. Step 5 Set mobile SDRAM support register If the mobile SDRAM is employed, the MOBILE bit should be set to 1. The PTASR and DS should be set according to the mobile SDRAM specification. If the mobile SDRAM is not employed, the user can skip this step. Step 6 Set configuration register 2 to select MA table and to start the initial refresh and Set-Mode-Register Select MA table for the address mapping mechanism based on the S/W requirement. As for the SDRAM initialization, bits 3 and 4 correspond to the initial refresh and initial pre-charge operations. Once these two bits are set to 1, the numbers of the pre-charge commands and refresh commands are issued to the SDRAM for initialization. After initialization is completed, bits 3 and 4 are cleared to zero automatically. If bit 2 is set to 1, the Set-Mode-Register command will synchronize the operational mode between the SDRAM module and SDRAM controller (only CAS latency in SDRC can be changed; other parameters are fixed. That is, the burst length is fixed at 4 and the burst type is fixed at sequential). The user should wait until all these three bits (ISMR,IREF,IPREC) go back to 0 to ensure the corresponding operation is complete. Step 7 Automatically entering the power-down mode Set PWDN or SREF bit to have the SDRAM controller automatically issuing the power down command or self refresh command while the SDRAM controller is stayed at the idle state for a pre-defined time. Skip

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Technical Reference Manual this step if you dont want SDRAM to enter the power-down mode automatically. Step 8 Set the external bank configuration register

Before starting to access the SDRAM controller, the address and type of SDRAM modules on each bank should be determined. The SDRAM controller has been configured to support up to 4 banks internally, but only a single bank is supported externally. If the user wants to enable the corresponding banks, the BNK_EN should be set to 1. The base address specifies the base address of the corresponding bank. The address requires totally 12 bits (bit 31 to bit 20 of the physical address). After the above sequence, the user can start to access SDRAM. Note that the Set-Mode-Register flag cannot be set while the SDRAM controller is in the normal operation. Otherwise the SDRAM controller will operate unexpectedly. 9.4.9. Example This section shows an example how aJ-200 interfaces with a SDRAM. In this example, two SDRAM components organized as 512KBx16x2 are used to implement a 16Bytes SDRAM memory system.
MADDR[14:0] SSDR_CSn SDR_RASn SDR_CASn MWEn SDR_CLK SDR_CLKEN MBE0n MBE1n MBE2n MBE3n MDATA[31:0] DQ[15:0] A[10:0] BA CS# RAS# CAS# WE# CLK CKE LDQM UDQM

SDRAM 512KBx16x2

aJ-102
A[10:0] BA CS# RAS# CAS# WE# CLK CKE LDQM UDQM

SDRAM 512KBx16x2

DQ[15:0]

Figure 9-33. 32-bit SDRAM Memory System

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1 SDR_CLK SDR_CLKEN MADDR[14:0] RA CB CC 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CA

RB

SDR_CSn Trp SDR_RASn

Trcd

SDR_CASn MWEn

MBEn[3:0] Tcl MDATA[31:0] QA DB Tcl QC

Row Activate

Read

Write

Read

Precharge

Figure 9-34. Single Read-Write-Cycle

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10. LCD Controller (LCDC)

10.1. Overview The LCD controller is a TFT LCD controller compliant with the Advanced Micro-controller Bus Architecture (AMBA) 2.0 protocol. It provides all the necessary control signals for various TFT LCD panels. This LCD controller is especially useful for the portable devices that includes personal digital assistants (PDAs), smart-phones, handhelds, portable color game terminals, and POS terminals. It supports the following features LCD panel interface o o o o o o TFT color displays with up to 24-bit bus interface Resolution programmable up to 1280 x 1280 Pixel clock rate up to 120 MHz Programmable polarity/duration for output enable, vertical sync, horizontal sync, pixel clock Data/Synchronization on/off control Swap function for red and blue channel RGB 12(4:4:4)/16(5:6:5)/15(5:5:5)/24(8:8:8) bpp Palette (1/2/4/8 bit pixel) YcbCr422 (16-bit per pixel) YcbCr420 (separate memory location) Little-endian, big-endian 256 entries 16 bit RGB color palette RAM Programmable Contrast, Brightness, Sharpness, Saturation and Hue Control Three channel Gamma Correction Dithering Maximum two PIP windows to display Resolution of PIP window is up to the same as main window size 4 bit blending level

Input mode o o o o

Data Format o Palette o Color Management o o o o

Picture In Picture (PiP) o o o

Picture out of Picture (PoP)

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Technical Reference Manual o 4 in 1 windows PoP display. The scaler is divided into the down scaling stage and the up scaling stage The down scaling ration is from 1/256 x 1/256 to 1x1 The up scaling stage can be arbitrary ration between 1x1 and 2x2 Three interpolation mode for up scaling calculation nearly bilinear interpolation, threshold nearly bilinear interpolation, most neighborhood interpolation Output Format o o o RGB parallel (18/24 bits) and serial (8 bits) output Swap of parallel RGB and BGR. TU-R BT. 656 output. Master bus error Frame status FIFO under-run Memory base update

Scalar o o o o

Interrupt control o o o o

The simplified block diagram is illustrated in the figure below

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Figure 10-1. Block Diagram of LCD Controller 10.2. Application The below figure illustrates an example application for LCD controller. The LCD controller reads image data from SDRAM via SDRAM controller for display on the TFT display panel. Java CPU controls the

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Technical Reference Manual whole system including programming registers of each controller and updating the frame buffer content of SDRAM. By transforming the output data stream of the pixel data port, this system can also provide video signals for TV associated terminals.
AHB0

Slave AHB0

Master AHB

LCD Interface

TFT LCD Display Panel

SDRAM

SDRAM Controller AHB1 Slave AHB_register Slave AHB1

LCD Controller
PIX_D0[7:0] Video Display Controller TV

Slave AHB_register

Java CPU

aJ-102
Figure 10-2 10.3. Architecture Overview 10.3.1. AHB Slave Interface The AHB interface can be divided into two blocks: the AHB slave interface and the AHB master interface. The AHB slave interface connects the LCD controller and AMBA AHB bus and allows the AHB master on the AMBA system to access the control registers and palette RAM. The interface of the AHB slave can accept all AMBA AHB read/write accesses using WORD size transfers and OK responses only. The AMBA AHB master interface fetches the image data from the frame buffer and places the data into the FIFO inside the LCD controller. It can assert undefined bursts and will assert the master error interrupt if an error occurs during the accessing process. When a retry response is received, a retry procedure will be asserted. 10.3.2. FIFO Controllers and FIFOs Data fetched from external memory by AHB master interface are placed into FIFO. Only one controller / FIFO will be required except when YCbCr420 mode is enabled. The YCbCr420 mode needs three channels for Y, Cb and Cr components, respectively, and each component belongs to a different memory location. The FIFO is 32-bits wide and the depth is 5 words. The input port of the FIFO is connected to the AMBA AHB master output and its output port is connected to the pixel data unpack controller. If the bus bandwidth capability cannot afford the pixel rate, some unpredictable image distortion will happen. So the FIFO controller provides an interrupt signal called under-run interrupt. This signal will ask the microExample Application for LCD Controller

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Technical Reference Manual controller to solve the bus congestion problem. 10.3.3. Pixel Data Unpack The data stored in the FIFO are 32-bit and can be packed in 1-, 2-, 4-, 8-, 16- or 24-bit pixel format depending on the pixel format setting. When YCbCr420 or YCbCr422 mode is enabled, fixed packing format is preset and cannot be changed. The pixel data can be used to address color palette RAM or form the raw color value and can be directly applied to the LCD panel, depending on the operation mode. The following tables show a simple example to describe the format of packed data. The LCD controller provides 1, 2, 4, 8, 16 and 24 bits per pixel (bpp) formats that can be big-endian byte and big-endian pixel, little-endian byte and big-endian pixel, or little-endian byte and little-endian pixel. Table 10-1.
BPP 1BPP Bit# 2BPP Bit# 4BPP Bit# 8BPP Bit# 16BPP Bit# 24BPP Bit# x x x x x x x x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 pix31 0 30 pix30 0 pixel 15 0 1 pixel 7 1 0 3 pixel 3 3 2 1 0 7 pixel 1 7 pixel 0 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 6 5 4 2 29 pix29 0 28 pix28 0 pixel 14 0 1 27 pix27 0

Little Endian Byte, Little Endian Pixel

FIFO Bit Number
26 pix26 0 25 pix25 0 1 pixel 6 1 0 3 2 24 pix24 0 pixel 12 0 1 23 pix23 0 22 pix22 0 pixel 11 0 1 pixel 5 1 0 3 pixel 2 3 2 1 0 2 21 pix21 0 20 pix20 0 pixel 10 0 1 19 pix19 0 18 pix18 0 pixel 9 0 1 pixel 4 1 0 17 pix17 0 16 pix16 0 pixel 8 0

pixel 13 0

FIFO Bit Number

BPP 1BPP Bit# 2BPP Bit# 4BPP Bit# 8BPP Bit# 16BPP Bit# 24BPP Bit# 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 pix15 0 14 pix14 0 pixel 7 0 1 pixel 3 1 0 3 pixel1 3 2 1 0 7 pixel 0 7 pixel 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 2 13 pix13 0 12 pix12 0 pixel 6 0 1 11 pix11 0 10 pix10 0 pixel 5 0 1 pixel 2 1 0 3 2 9 pix9 0 8 pix8 0 pixel4 0 1 7 pix8 0 6 pix6 0 pixel3 0 1 pixel1 1 0 3 pixel 0 3 2 1 0 2 5 pix5 0 4 pix4 0 pixel2 0 1 3 pxi3 0 2 pix2 0 pixel 1 0 1 pixel 0 1 0 1 pxi1 0 0 pxi0 0 pixel 0 0

Table 10-2.
BPP 1BPP 31 pix0 30 pix1 29 pix2 28 pix3 27 Pix4 26 pix5

Big Endian Byte, Big Endian Pixel

FIFO Bit Number 25 pix6 24 pix7 23 pix8 22 9ix9 21 pix10 20 pix11 19 pix12 18 pix13 17 pix14 16 pix15

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Bit# 2BPP Bit# 4BPP Bit# 8BPP Bit# 16BPP Bit# 24BPP Bit# BPP 1BPP Bit# 2BPP Bit# 4BPP Bit# 8BPP Bit# 16BPP Bit# 24BPP Bit# 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X 15 pix1 6 0 x 14 pix17 0 pixel 8 0 1 pixel 4 1 0 3 Pixel2 3 2 1 0 7 pixel 1 7 pixel 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 2 x 13 pix18 0 x 12 pix19 0 pixel 9 0 1 x 11 pix20 0 x 10 pix21 0 pixel10 0 1 pixel 5 1 0 3 2 x 9 pix22 0 x 8 pix23 0 pixel11 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 pixel 0 0 1 pixel 0 1 0 3 pixel 0 3 2 1 0 7 pixel 0 7 pixel 0 23 7 pix24 0 22 6 pix25 0 pixel12 0 1 pixel6 1 0 3 pixel 3 3 2 1 0 2 21 5 pix26 0 20 4 pix27 0 pixel13 0 1 19 3 pxi28 0 18 2 pix29 0 pixel14 0 1 pixel7 1 0 17 1 pix30 0 16 0 pix31 0 pixel 15 0 FIFO Bit Number 6 5 4 3 2 1 0 6 5 4 2 0 0 pixel 1 0 1 0 0 pixel 2 0 1 pixel 1 1 0 3 2 0 0 pixel 3 0 1 0 0 pixel4 0 1 pixel 2 1 0 3 pixel 1 3 2 1 0 2 0 0 Pixel5 0 1 0 0 pixel 6 0 1 pixel 3 1 0 0 0 pixel 7 0

Table 10-3.
BPP 1BPP Bit# 2BPP Bit# 4BPP Bit# 8BPP Bit# 16BPP Bit# 24BPP Bit# BPP 1BPP Bit# 2BPP Bit# 4BPP 1 X 15 pix8 0 x 14 pix9 0 pixel 4 0 1 pixel 2 x 13 pix10 0 x 12 pix11 0 pixel 5 0 1 x 11 pix12 0 x 10 15 14 13 12 11 10 7 6 5 4 3 2 1 31 pix24 0 30 pix25 0 pixel 12 0 1 pixel 6 1 0 3 pixel 3 3 2 2 29 pix26 0 28 pix27 0 pixel 13 0 1 27 pix28 0 26

Little Endian Byte, Big Endian Pixel

FIFO Bit Number 25 pix30 0 1 pixel 7 1 1 9 x 9 pix14 0 1 pixel 3 0 0 8 x 8 pix15 0 pixel 7 0 1 3 7 pixel 1 7 pixel 0 23 7 pix0 0 22 6 pix1 0 pixel 0 0 1 pixel 0 21 5 pix2 0 20 4 pix3 0 pixel 1 0 1 19 3 pix4 0 18 2 pix5 0 pixel 2 0 1 pixel 1 17 1 pix6 0 16 0 pix7 0 pixel 3 0 FIFO Bit Number pix13 0 6 5 4 3 2 1 0 2 6 24 pix31 0 pixel 15 0 1 23 pix16 0 22 Pix17 0 pixel 8 0 1 pixel 4 1 5 0 4 3 pixel 2 3 2 1 0 2 21 Pix18 0 20 Pix19 0 pixel 9 0 1 19 Pix20 0 18 Pix21 0 Pixel108 0 1 pixel 5 1 0 17 Pix22 0 16 Pix23 0 Pixel11 0 pix29 0

pixel 14 0

pixel 6 0

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Bit# 8BPP Bit# 16BPP Bit# 24BPP Bit# 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 pixel 1 3 2 1 0 7 pixel 0 7 pixel 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 2 1 0 3 2 1 0 3 pixel 0 3 2 1 0 2 1 0

10.4.

Data Mode

10.4.1. Raw RGB Mode Raw data RGB mode supports 16 and 24 BPP. The data stream does not require transformation but reordering for different panel resolutions is necessary. A simple mapping table is shown below: Table 10-4. Mapping for Raw RGB Mode 16 BPP B G R B D15-11,000 D10-5,00 D4-0,000 D23-16 D15-11,0 D10-5 D4-0,0 D23-18 24 BPP G D15-8 D15-10

24-bit panel 18-bit panel

R D7-0 D7-2

10.4.2. YCbCr422 Mode The BPP value is 16 and cannot be changed when YCbCr422 mode is enabled. The pixel sequence is given in the following table. Table 10-5. Y Pixle 2N Pixel 2N+1 10.4.3. YCbCr420 Mode Under the YCbCr420 operation mode, the BPP value must be 8. In addition, the memory locations for storing the three components Y, Cb and Cr are separate. An example of the component location/sequence is shown in the following table. The base address of three frame buffers can be programmed in register files separately. When YCbCr420 data are read out from each individual FIFO, it is necessary to recover the chrominance values at each missed line. A line buffer is employed to store previous data and interpolate vertically to estimate the absent chrominance value. Then a converted YCbCr422 data stream is outputted to the next stage. Table 10-6. Component Y Component Location/Sequence for YCbCr420 Mode Sequence Y00, Y01, Y02, Y03, Y04, Y05,. Y10, Y11, Y12, Y13, Y14, Y15,. Y20, Y21, Y22, Y23, Y24, Y25,. .
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Pixel Sequence for YCbCr422 Mode Cb D(2N) 7-0 ---Cr ----D(2N)7-0

D(2N )15-8 D(2N+1)15-8

Address Offset Image0_Base

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Technical Reference Manual Cb00, Cb02 Cb04, Cb06, Cb08, Cb20, Cb22 Cb24, Cb26, Cb28, Cr00, Cr02, Cr04, Cr06, Cr08, Cr20, Cr22, Cr24, Cr26, Cr28,

Cb Cr 10.4.4. RGB Palette Mode

Image1_Base Image2_Base

To enhance application flexibility, the controller provides a remapping operation mode. The following figure depicts the basic concept. This scheme allows for trade-off between color variety and bandwidth or memory space requirement. There are 4 types available, that is 1, 2, 4 and 8 bpp. And a palette RAM is utilized to store the look-up table to regenerate the preferred RGB components. The palette RAM holds up to 256x16-bit color values. It is physically structured as 128x32-bit. The following table describes the palette RAM entries. The pixel data from the FIFO are used to address an individual palette location: 1-bit pixel data address the first 2 entries, 2-bit pixel data address the first 4 entries, 4-bit pixel data address the first 16 entries, and 8-bit pixel data can select any one of the 256 palette entries. In 16-bit or 24-bit pixel mode, the palette RAM is not used and can be removed to reduce hardware cost
LUT entry 0 LUT entry 1 Pixel raw data stream 8 16 Pixel RGB data stream

LUT entry 254 LUT entry 255

Figure 10-3. Palette Remapping Operation Bit 31-27 26-21 20-16 15-11 10-5 4-0 Table 10-7. 10.5. Color Management Content Description B[4:0] Blue palette data for index 1 G[5:0] Green palette data for index 1 R[4:0] Red palette data for index 1 B[4:0] Blue palette data for index 0 G[5:0] Green palette data for index 0 R[4:0] Red palette data for index 0 Palette RAM Data Structure (for Entry 0)

The Color Management block performs image enhancement so that the image can be seen more clearly. Main functions of image color management are as follows: 10.5.1. Contrast Control This function makes bright of image brighter and dark of image darker. This is achieved as the block sorts
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Technical Reference Manual out the colors being displayed on the screen and displays the image with the color calculated through the contrast processing. 10.5.2. Brightness Contrast

The whole screen can be adjusted brighter or darker.

10.5.3. Sharpness The sharpness can strengthen the edges of picture. As the figure below shows, the left side is the original picture without any process. The right side is the picture with sharpness process.

Figure 10-4. Sharpness 10.5.4. Hue & Saturation LCD controller provides more flexible user to adjust the hue and saturation of picture depended on users hobbies. 10.5.5. Gamma Correction The gamma correction block performs gamma compensation to complement the TFT-LCD panel features. Three channels of gamma correction can separately adjust RGB channel compensation. 10.5.6. Dither Controller This programmable dither control makes the image to look smoother when the pixel depth 8 bits, but the LCD resolution is 6~2 bits of each color component TFT 8 to 6, 8 to 5. 10.6. Image Controller

10.6.1. Picture In Picture (PIP) The LCD controller can support two PiP windows. With original main window, users can see three windows in a panel. The PiP windows size can be up to same as frame size. A four-bit alpha blending control can let three windows overlap easily. When the alpha blending turn on, DMA have to read all overlap pixels. The AHB bandwidth will be the total pixel numbers of the three windows. When PiP turn on, all windows can only be one of the input color format RGB888, RGB565, RGB555, RGB444, YCbCr422.

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Figure 10-5. PiP 10.6.2. Picture Out of Picture (POP) LCD controller can merge four quarter windows in one frame. The quarter window size is limited to frame. For each of four channels, LCD controller also provides the size down machine to re-size the resolution of picture to 1/2x1/2. When PoP turn on, all quarter windows can only be one of the input color format RGB888, RGB565, RGB555, RGB444, YCbCr422.

Figure 10-6. PoP 10.7. On-Screen Display (OSD)

10.7.1. Font Based Architecture OSD window is composed of fonts. These fonts are generated from the database preloaded into the dedicated RAM. Each font database entry contains a 12 x 16 matrix describing the font dot appearance. Since these databases are stored in RAM, they can be modified easily to meet different requirements, such as icons and multi-language applications. The RAM size for storing font database is 4Kx12, so it can provide up to 256 fonts.
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Figure 10-7. Font Structure (12x16 Dots Per Font) 10.7.2. Attribut Description Each displayed font in the OSD window owns a unique attribute description. It is a 12-bit-wide entry and can be programmed based on the users preference. The following table shows the font attribute structure. The value I7-0 specifies which font is selected among the 256 ones for display on the window. The value F1-0 selects the foreground color from the 4-entry 8-bit color palette. The value B1-0 is used to handle background color in a manner similar to the foreground color selection. However, when B is equal to zero, it implies that a transparent operation is enabled. In such a case, no more color mapping is necessary; the font background makes the original image partially visible on the screen, and so only 3 palette color entries are utilized to control the background color. The transparency level could be 25%, 50%, 75% and 100% for the original image. Table 10-8. Font Index I7 I6 I5 I4 I3 I2 I1 Font Attribute Structure Foreground Color I0 F1 F0 Background Color B1 B0

10.7.3. OSD Window Control The OSD engine also provides some functions to enhance the application flexibility. The window position of the screen is fully programmable, for both horizontal and vertical directions. An upscaling function is implemented to control the font size. This is achieved by independently duplicating the font dot horizontally and vertically, based on the values of the control register. The upscaling factor could be 1, 2, 3 or 4. The dimensions are also user programmable to adjust the window aspect to meet user requirements.

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OSD position

LCD screen OSD font

OSD MENU BRIGHTNESS CONTRAST POSITION

OSD Y dimension

OSD X dimension

Figure 10-8. OSD Basic Operation Description 10.8. Scalar The figure below illustrates the simplified block diagram of the scalar

Figure 10-9. Block Diagram of Scaler 10.8.1. Box Filter The box filter is a 128-tap FIR is responsible for the first stage downscaling function in the horizontal direction by the linear interpolation process to the pixel data in the same line with selectable coefficient from 1/2,1/3,1/4.to 1/128. 10.8.2. 1024x24 Line Buffer The line buffer stores one line pixel data after 128-tap FIR processed. 10.8.3. 1024x24 Line Buffer Controller The line buffer controller controls line buffer data access. The read out data from line buffer is feedback to input port in order to perform the linear interpolation process with the next line pixel data i.e. the vertical interpolation process. 10.8.4. 2048x24 Line Buffer The line buffer is a ping-pong structure memory which is combined with two 1024 by 24-bit single-port SRAM. Since our upscaling methodology is based on bilinear algorithm and the upscaling ratio is limited
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Technical Reference Manual in two in the vertical direction. Therefore, the ping-pong structure offers a simultaneous read and write mechanism that we can shrink the line buffer memory size to only one line pixel data amount. 10.8.5. 2048x24 Line Buffer Controller The line buffer controller provides the necessary address and control signals to the ping-pong structure line buffer to make sure the RGB pixel data can be written into and read from line buffer simultaneously and correctly. Besides the line buffer control function, the line buffer controller is also responsible for the write access interface with external LCD controller. 10.8.6. Vertical Scalar FIR The vertical scaler FIR is a 2 tap FIR which implements a multiply-add calculation (y[n] = ax[n] + (1-a) x[n-1]) to the current line pixel data (x[n]) and previous line pixel data (x[n-1]) where y[n] is FIR output ,a and 1-a are FIR coefficient. Since the RGB pixel data is processed independently, each color pixel data process needs two 8-bit multiply 9-bit multiplier and a 17bit adder. 10.8.7. Vertical Scalar Coefficient Generator The vertical scaler coefficient generator can be divided into upscaling coefficient generator and downscaling coefficient generator. Both the upscaling and downscaling coefficient generator generates a 9-bit coefficient which the most significant bit is integer and the others are fraction by the scaling ratio which is programmable through the input image vertical resolution field and output image vertical resolution field. 10.8.8. Scalar Data FIFO The data FIFO is a pixel data FIFO for the vertical scaler module to push the output data and the horizontal scaler module to pop the data for the next horizontal pixel data process. The depth of the data FIFO is eight. 10.8.9. Horizontal Scalar FIR The horizontal scaler FIR is a 2-tap FIR which implements a multiply-add calculation (y[n] = ax[n] + (1-a)x[n-1]) to the current pixel data (x[n]) and previous pixel data (x[n-1]) where y[n] is FIR output ,a and 1-a are FIR coefficient. Since the RGB pixel data is processed independently, each color pixel data process needs two 8-bit multiply 9-bit multiplier and a 17-bit adder. 10.8.10. Horizontal Scalar Coefficient Generator

The horizontal scaler coefficient generator can be divided into upscaling coefficient generator and downscaling coefficient generator. Both the upscaling and downscaling coefficient generator generates a 9-bit coefficient, which the most significant bit is integer and the others are fraction by the scaling ratio

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Technical Reference Manual which is programmable through the input image horizontal resolution field and output image horizontal resolution field. 10.9. TFT Panel Interface

The following figure shows the basic timing of the TFT interface. The relationship between horizontal and vertical signals is fully programmable. The user can adjust these parameters to meet different panel requirements. The figure below explains the pin ordering difference between 18-bit and 24-bit panels.
Frame timing LC_VS LC_HS LC_DE LC_DATA Line timing LC_HS LC_DE LC_CLK LC_DATA // // // // // // // //

Panel Interface 24 bit 18 bit

Figure 10-10. Basic TFT Interface Timing Diagram Table 10-9. LCD 18-Bit and 24-Bit Interface Blue Green LC_DATA23-16 LC_DATA15-8 LC_DATA17-12 LC_DATA11-6

Red LC_DATA7-0 LC_DATA5-0

10.10. Interrupt Controller The interrupt controller receives four internal interrupt signals: AHB master error interrupt, FIFO under-run interrupt, vertical duration interrupt and frame base address updated interrupt. It then combines those signals to generate a global interrupt signal. The four interrupt signals can be enabled or disabled via programming the enable bit of the interrupt enable register. The combined interrupt will be asserted, if any of the four interrupts is enabled and brought to occur. 10.11. Programming Model 10.11.1. Summary of LCD Control Registers Table 10-10. Control Register Summary Reset Value Name Description LCD_function_en LCD_panle_pixel LCD function enable LCD panle pixel parameter

Address Type Width LCD Global Parameters 000H R/W 13 00H 004H R/W 16 00H

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Technical Reference Manual 008H R/W 5 00H 00CH W 5 00H 010H R 5 00H 014H R/W 12 00H 018H R/W 30 00H 024H R/W 30 00H 030H R/W 30 00H 03CH R/W 30 00H 048H R/W 24 00H 04CH R/W 32 04040404H 050H R/W 16 00H LCD Timing and Polarity Parameters 100H R/W 32 00000000H 104H R/W 26 00000000H 108H R/W 8 0000H 10CH R/W 10 00000000H LCD Output Format Parameters 200H R/W 6 00H 204H R/W 3 00H LCD Image Parameters 300H R/W 10 00H 304H R/W 22 00H 308H R/W 22 0000H 30CH R/W 22 00H 310H R/W 22 0000H LCD Image Color Management 400H R/W 14 2000H 404H R/W 14 1000H 408H R/W 24 00H 40CH R/W 18 8000H LCD Gamma Correction 600HW 32 -6FCH 700HW 32 -7FCH 800HW 32 -8FCH LCD Palette Accessing Port A00HW 32 -BFCH Scalar Control Registers 1100H R/W 12 00H 1104H R/W 12 00H 1108H R/W 14 00H 110CH R/W 14 00H 1110H R/W 9 00H 1114H R/W 9 00H 1118H R/W 9 00H
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LCD_intr_mask LCD_intr_clr LCD_intr_status LCD_frame_buffer LCD_im0frm0base LCD_im1frm0base LCD_im2frm0base LCD_im3frm0base LCD_patbarcolor LCD_fifoth GPIOControl LCD_hortiming LCD_vertimg0 LCD_vertimg1 LCD_polarity LCD_serialpanel LCD_ccir656 LCD_pipblend LCD_pip1pos LCD_pip1dim LCD_pip2pos LCD_pip2dim LCD_colorman0 LCD_colorman1 LCD_colorman2 LCD_colorman3 LCD_GaRdLUT LCD_GaGnLUT LCD_GaBuLUT PaletteWritePort Scal_hor_no_in Scal_ver_no_in Scal_hor_no_out Scal_ver_no_out Scal_misc Scal_hor_high_th Scal_hor_low_th
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LCD interupt enable mask LCD interrupt status clear LCD interrupt status LCD frame buffer parameter LCD panel image0 frame0 base address LCD panel image1 frame0 base address LCD panel image2 frame0 base address LCD panel image3 frame0 base address LCD pattern generator LCD fifo threshold GPIO control LCD horizontal timing control LCD vertical timing control 0 LCD vertical timing control 1 LCD polarity control LCD serial panel pixel parameters LCD CCIR656 parameters LCD pip parameters PIP sub-picture 1 position PIP sub-picture 1 dimension PIP sub-picture 2 position PIP sub-picture 2 dimension LCD color management parameter 0 LCD color management parameter 1 LCD color management parameter 2 LCD color management parameter 3 LCD Gamma Red Lookup table LCD Gamma Green Lookup table LCD Gamma Blue Lookup table LCD palette RAM write accessing port Scalar horizontal resolution input Scalar vertical resolution input Scalar horizontal resolution output Scalar vertical resolution output Scalarmiscellanuos control register Horizontal upscaling high threshold Horizontal upscaling low threshold
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Technical Reference Manual 111CH R/W 9 00H 1120H R/W 9 00H 112CH R/W 16 00H Simple OSD Control Registers 2000H R/W 15 00H 2004H R/W 23 00H 2008H R/W 32 00H 200CH R/W 32 00H 8000H~B R/W 12 -FFCH Scal_ver_high_th Scal_hor_low_th Scal_hor_ver_num Osd_ctrl0 Osd_ctrl1 Osd_forecolor Osd_backcolor OSDFont accessing port Vertical upscaling high threshold Vertical upscaling low threshold Scaler resolution parameter OSD control register 0 OSD control register 1 OSD fore color register OSD back color register OSD font RAM accessing port

10.11.2.

Register Description 10.11.2.1. LCD Global Parameter 10.11.2.2. LCD Function Enable (offset 0000H) Table 10-11. LCD Function Enable Bit Name Type Description 12-11 Patgen R/W Test Pattern Generator. When pattern generator enables, the LCDC controller will automatically send out different patterns to panel depended on the programmed value. 00 Pattern Generator disable 01 Single Color 10 Color bar generator 10-9 PiPEn R/W Picture In Picture mode. When PiPEn is set, the LCD controller can support picture in picture function. The PIP function can support two or three pictures which are from two or three different frame buffer. 00 PIP disable 01 Single PIP window 10 Double PIP window 8 BlendEn R/W Alpha Blending enable. When this bit is set, the PIP can support Alpha Blending function. The blending level is depended on the pipblend values. 0 Blending function disable 1 Blending function enable 7 PoPEn R/W Picture Out of Picture mode. When this bit is set, the LCD controller can support picture out of picture function. The PoP function can only divide four quarters in one screen. 0 PoP function disable 1 PoP function enable 6 DitherEn R/W Dither Enable. When this bit is set, the LCD controller can support dithering function. The dithering type is depended on the value of Dither-Type. 0 Dithering function disable 1 Dithering function enable 5 ScalerEn R/W Scalar Enable. When this bit is set, the LCD controller can support scaling function. The detail scaling
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Technical Reference Manual dimension is depended on the scaler control registers. 0 Scaling function disable 1 Scaling function enable OSD Enable. When this bit is set, the LCD controller can support OSD function. The displaying type of OSD is depended on programming OSD control register. 0 On Screen Display disable 1 On Screen Display enable YCbCr input mode control. When this bit is set, it informs the LCD controller the data type in frame buffer is YCbCr format. 0 YCbCr format 1 RGB format YCbCr420 input mode control. When this bit is set, it informs the LCD controller the data type in frame buffer is YCbCr420 format. 0 YCbCr422 mode input 1 YCbCr420 mode input This mode only functions when EnYCbCr is set to 1 LCD screen on/off control 0 Screen disable (all data output pins are force to 0) 1 Screen enable (normal operation) LCD controller enable control 0 Disable controller and force all LCD signals including synchronization, and data to zero. 1 Enable controller (normal operation)

OSDEn

R/W

EnYCbCr

R/W

EnYCbCr420

R/W

1 0

LCDon LCDen

R/W R/W

10.11.2.3. Bit 15 14 13-12

LCD panel pixel parameters (offset 0004H) Table 10-12. LCD Panel Pixel Parameters Name LRST HRST DitherType Type R/W R/W R/W Description LC_CLK domain reset. The signal can reset all status in LCD clock domain. This register must be cleared by user. HCLK domain reset. The signal can reset all status in HCLK domain. This register must be cleared by user. Dithering Type. The value decides which dithering algorithm to be used. The value is valid when DitherEn is set. 00 Transfer 888 to 565 01 Transfer 888 to 555 10 Transfer 888 to 444 TFT panel color depth selection. This value selects the color depth of output format. 0 6-bit per channel 1 8-bit per channel Generate interrupt at: 00 Start of vertical sync
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PanelType

R/W

10-9

Vcomp

R/W

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Technical Reference Manual 01 Start of vertical back porch 10 Start of vertical active image 11 Start of vertical front porch RGB Input Format This bit indicates the input RGB format when BppFifo == 100. 00 RGB 565 input 01 RGB 555 input 10 RGB 444 input Frame buffer data endian control 00 Little endian byte little endian pixel 01 Big endian byte big endian pixel 10 Little endian byte big endian pixel (WinCE) RGB of BGR format selection: 0 RGB normal output 1 BGR red and blue swapped This bit drive directly the output pin LC_PWROFF. Pixel format in FIFO. The value informs which data format in each ahb buffer. (bit per pixel) 000 1 bpp 001 2 bpp 010 4 bpp 011 8 bpp 100 16 bpp 101 24 bpp

8-7

RGBTYPE

R/W

6-5

Endian

R/W

4 3 2:0

BGRSW PWROFF BppFifo

R/W R/W R/W

10.11.2.4. Bit 3

LCD Interrupt enable mask (offset 0008H) Table 10-13. LCD Interrupt Enable Mask Name Type Description IntBusErrEn R/W AHB master error interrupt enable. This bit is set to enable bus error interrupt. 1 Enable 0 Disable IntVstatusEn R/W Vertical duration comparison interrupt enable. This bit is set to enable vertical status interrupt. 1 Enable 0 Disable IntNxtBaseEn R/W Next frame base address updated interrupt enable. This bit is set to enable update base address successfully interrupt. 1 Enable 0 Disable IntFIFOUdnEn R/W FIFO under-run interrupt enable. This bit is set to enable fifo underrun interrupt. 1 Enable 0 Disable LCD interrupt status clear (offset 000CH)

10.11.2.5.

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Technical Reference Manual Table 10-14. LCD Interrupt Status Clear Type Description W Set it to 1 will clear AHB master error interrupt status, set 0 will take no effect. W Set it to 1 will clear the interrupt status of vertical duration comparison, set 0 will take no effect. W Set it to 1 will clear frame buffer base address update interrupt status, set to 0 will take no effect. R/W Set it to 1 will clear FIFO under-run interrupt status, set to 0 will take no effect.

Bit 3 2 1 0 10.11.2.6. Bit 3 2 1 0

Name ClrBusErr ClrVstatus ClrNxtBase ClrFIFOUdn

LCD interrupts status (offset 0010H) Table 10-15. LCD Interrupt Status Name Type Description IntBusErr R AHB master error status, set when the AMBA AHB master encounters a bus error response from a slave. IntVstatus R Vertical comparison, set when one of the four vertical durations, selected via the LCD Control registers, is reached. IntNxtBase R Frame buffer base address update, set when the current base address registers have been successfully update by the next address registers. ClrFIFOUdn R FIFO under-run, set when DMA FIFO has been read accessed when empty causing an under-run condition to occur. Frame Buffer Parameter (offset 0014H) Table 10-16. Frame Buffer Parameter Name Type Description Im3ScalDown R/W Scaling down for image 3. The register is valid when POP enable. The image from LCDImage0FrameBase can be scaling down depended on the value. 00 Disable. 01 The image 0 will be scaling down to X 10 The image 0 will be scaling down to X 1 Im2ScalDown R/W Scaling down for image 2. The register is valid when POP enable. The image from LCDImage2FrameBase can be scaling down depended on the value. 00 Disable. 01 The image 0 will be scaling down to X 10 The image 0 will be scaling down to X 1 Im1ScalDown R/W Scaling down for image 1. The register is valid when POP enable. The image from LCDImage1FrameBase can be scaling down depended on the value. 00 Disable. 01 The image 0 will be scaling down to X 10 The image 0 will be scaling down to X 1. Im0ScalDown R Scaling down for image 0. The register is valid when POP enable. The image from LCDImage0FrameBase
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10.11.2.7. Bit 15-14

13-12

11-10

9-8

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Technical Reference Manual can be scaling down depended on the value. 00 Disable. 01 The image 0 will be scaling down to X 10 The image 0 will be scaling down to X 1 -

7-0 10.11.2.8. Bit 31-2

Reserved

LCD Panel Image0 Frame0 base address (offset 0018H) Table 10-17. LCD Panel Image0 Frame0 base address Name Type Description LCDImage0FrameBase R/W LCD frame0 base address of Image0. This is the start address of the frame data in memory. The two LSB bits are default 0. The total occupied memory address range is described below: Starting address: {LCDImage0Frame0Base,0,0} LCD Panel Image1 Frame0 base address (offset 0024H) Table 10-18. LCD Panel Image 1 Frame0 base address Name Type Description LCDImage1FrameBase R/W LCD frame0 base address of Image1. This is the start address of the frame data in memory. The two LSB bits are default 0. The total occupied memory address range is described below Starting address: {LCDImage1Frame0Base,0,0} Panel Image2 Frame0 base address (offset 0030H) Table 10-19. Panel Image2 Frame0 base address Name Type Description LCDImage2FrameBase R/W LCD frame0 base address of Image2. This is the start address of the frame data in memory. The two LSB bits are default 0. The total occupied memory address range is described below: Starting address: {LCDImage2Frame0Base,0,0} LCD Panel Image3 Frame0 base address (offset 003CH) Table 10-20. LCD Panel Image3 Frame0 base address Name Type Description LCDImage3FrameBase R/W LCD frame0 base address of Image3. This is the start address of the frame data in memory. The two LSB bits are default 0. The total occupied memory address range is described below: Starting address: {LCDImage3Frame0Base,0,0}

10.11.2.9. Bit 31-2

10.11.2.10. Bit 31-2

10.11.2.11. Bit 31-2

1.1.1.1.1. PatGen Pattern Bar Distance (offset 0048H) Table 10-21. PatGen Pattern Bar Distance Bit Name Type Description 31-8 Reserved 7-6 Img3PatGen R/W Paterrn Generator of Image 3. LCD controller will generator the different test pattern of ahb buffer3 dependen on the value.
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Technical Reference Manual 00 Vertical color bar 01 Horizontal color bar 10 Single color Paterrn Generator of Image 2. LCD controller will generator the different test pattern of ahb buffer2 dependent on the value. 00 Vertical color bar 01 Horizontal color bar 10 Single color Paterrn Generator of Image 1. LCD controller will generator the different test pattern of ahb buffer1 dependent on the value. 00 Vertical color bar 01 Horizontal color bar 10 Single color Paterrn Generator of Image 0. LCD controller will generator the different test pattern of ahb buffer0 dependent on the value. 00 Vertical color bar 01 Horizontal color bar 10 Single color

5-4

Img2PatGen

R/W

3-2

Img1PatGen

R/W

1-0

Img0PatGen

R/W

10.11.2.12. Bit 31-24 23-16 15-8 7-0

FIFO Threshold control (Offset 004CH) Table 10-22. FIFO Threshold Control Name Type Description Buf3Threshold R/W AHB Buffer 3 threshold. The buffer 3 will assert request for master to fetch data in when the buffer3s empty count is larger than this value. Buf2Threshold R/W AHB Buffer 2 threshold. The buffer 2 will assert request for master to fetch data in when the buffer2s empty count is larger than this value. Buf1Threshold R/W AHB Buffer 1 threshold. The buffer 1 will assert request for master to fetch data in when the buffer1s empty count is larger than this value. Buf0Threshold R/W AHB Buffer 0 threshold. The buffer 0 will assert request for master to fetch data in when the buffer0s empty count is larger than this value. GPI/GPO Control l (offset 0050H) Table 10-23. GPI/GPO Control I Name Type Description LCDGPO W Direct drive the level of the eight general output ports LCDGPI R Return the status of the eight general purpose input ports

10.11.2.13. Bit 15-8 7-0 10.11.3. 10.11.3.1. Bit 31-24

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LCD Timing and Polarity Parameter LCD horizontal timing control (offset 0100H) Table 10-24. LCD Horizontal Timing Control Name Type Description HBP R/W Horizontal back porch, is the number of LC_PCLK periods between
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Technical Reference Manual the falling edge of LC_PCLK and the start of active data, program with value minus 1. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been de-asserted, the value in HBP is used to count the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1 to 256 pixel clock cycles.. Horizontal front porch, is the number of LC_PCLK periods between the end of active data and the rising edge of LC_HS, program with value minus1. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD clock is pulsed. Once a complete line of pixels is transmitted to the LCD driver, the value in HFP is used to count the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1 to 256 pixel clock cycles.. Horizontal synchronization pulses width, is the width of the LC_HS signal in LC_PCLK periods. Program with value minus1. The 8-bit HW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Pixels-per-line. Actual pixels-per-line = 16*(PL+1). The PL bit field specifies the number of pixels in each line of row of the screen. PL is a 6-bit value that represents between 16 and 2048 PL. PL is used to count the number of pixel clock that occur before the HFP is applied (program the value require divided by 16, minus 1)

23-16

HFP

R/W

15-8

HW

R/W

7-0

PL

R/W

10.11.3.2. Bit 31-24

23-22 21-16

15-12 11-0

LCD vertical timing control (offset 0104H) Table 10-25. LCD Vertical Timing Control Name Type Description VFP R/W Vertical front porch is the number of inactive lines at the end of frame, before vertical synchronization period. The 8-bit VFP field is used to specify the number of line clocks to insert at the end of each frame. Once a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed the vertical synchronization (LC_VS) signal is asserted. VFP generates from 0255 line clock cycles. Revised VW R/W Vertical synchronization pulse width is the number of horizontal synchronization lines. Program to the number of lines required minus one. The 6-bit VW field is used to specify the pulse width of the vertical synchronization pulse. The register is programmed with the number of line clocks in vertical synchronization period minus one. Number of horizontal synchronization lines. Program to the number of lines required minus 1. Revised LF R/W Lines-per-frame is the number of active lines per frame. The LF field specifies the total number of lines or rows on the LCD panel being controlled. LF is a 11-bit value allowing between 1 and 2048 lines
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Technical Reference Manual 10.11.3.3. Bit 7-0 LCD vertical timing control (offset 0108H) Table 10-26. LCD Vertical Timing Control Name VBP Type R/W Description Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. The 8-bit VBP field is used to specify the number of line clocks inserted at the beginning of each frame. The VBP count starts just after the vertical synchronization signal for the previous frame has been negated for active mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates form 1-256 extra line clock cycles. Program to the number of lines required minus 1.

1.1.1.1.2. LCD polarity control (offset 010CH) Table 10-27. LCD Polarity Control Bit Name Type Description 14-8 DivNo R/W LCD panel clock divisor control. The actual divisor value is equal to (DivNo+1) 7-5 Revised 4 IPWR R/W This bit is used to select the active polarity of the output pin LC_PWROFF 0 LC_PWROFF output is active HIGH. 1 LC_PWROFF output is active LOW. 3 IDE R/W The invert output enable bit is used to select the active polarity of the output enable signal. 0 LC_DE/LC_VM output pin is active HIGH 1 LC_DE/LC_VM output pin is active LOW 2 ICK R/W The ICK bit is used to select the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 Data is driven on the LCD data lines on the rising-edge of LC_PCLK 1 Data is driven on the LCD data lines on the falling-edge of LC_PCLK 1 HIS R/W The invert horizontal sync bit is used to select the active polarity of the horizontal sync signal. 0 LC_HS/LC_VL pin is active HIGH and inactive LOW 1 LC_HS/LC_VL pin is active LOW and inactive HIGH 0 IVS R/W The invert vertical sync bit is used to select the active polarity of the vertical sync signal. 0 LC_VS/LC_VF pin is active HIGH and inactive LOW 1 LC_VS/LC_VF pin is active LOW and inactive HIGH 10.11.4. 10.11.4.1. LCD Output Format Parameters LCD Serial panel pixel parameters (offset 0200H)

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Technical Reference Manual Table 10-28. LCD Serial Panel Pixel Parameters Bit Name Type Reset Value Description AUO052 mode 5 AUO0 52 R/W 00H 0 Dont support AUO052 1 Support AUO052 Left Shift Rotate 0 Even line sequence form through Odd line 4 LSR R/W 00H rotating right. 1 Even line sequence form through Odd line rotating left. Color Sequence of Odd line. The value decides the sub-pixel sequence of odd line. 3:2 ColorSeq R/W 00H 00 RGB 01 BRG 10 GBR Delta Type Arrangement Color Filter 0 Odd line and Even line have the same data 1 DeltaType R/W 00H sequence. 1 Odd line and Even line have different data sequence. RGB serial output mode 0 SerialMode 0 RGB parallel format output 1 RGB serial format output Configuration Table for Delta Type of Serial Panel DeltaType 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 ColorSeq 00 01 10 00 01 10 00 01 10 00 01 10 00 01 10 00 01 10 BGRSW 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 LSR 0 0 0 1 1 1 0 0 0 1 1 1 Odd line, Even line RGB, RGB BRG, BRG GBR, GBR BGR, BGR BGR, BGR RBG, RBG RGB, BRG BRG, GBR GBR, RGB RGB, GBR BRG, RGB GBR, BRG BGR, RBG GRB, BGR RBG, GRB BGR, GRB GRB, RBG RBG, BGR

10.11.4.2. LCD CCIR656 parameters (offset 0204H) These registers are valid when cciren is set.
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Technical Reference Manual Table 10-29. LCD CCIR656 Parameters Type Description TVE clock phase R/W 0 TV clock is the same as LC_PCLK 1 TV clock is the inversion of LC_PCLK 720 Pixels Per Line R/W 0 640 pixels per line 1 720 pixels per line NTSC/PAL Select R/W 0 PAL 1 NTSC

Bit 2 1 0

Name Phase P720 NTSC

Programming Sequence When using TV as display device, programmer should take care of some restrictions: The input resolution is 720x480 or 640x480 for NTSC system. The input resolution is 720x576 or 640x480 for PAL system. VBP+VW programming value should follow the following value NTSC 0 0 1 1 P720 0 1 0 1 VBP + VW 91 43 43 43

User can take the following table for example NTSC 0 0 1 1 10.11.5. 10.11.5.1. P720 0 1 0 1 LCD Image Parameters LCD PIP Parameter (offset 0300H) 0x0100H 0x07CF0727 0x0284072C 0x02D20327 0x027E072C 0x0104H 0x350A01DF 0x0510023F 0x011101DF 0x011001DF 0x0108H 0x50 0x1A 0x19 0x1A

When PIP is enable, the following restrict must be noted. PiPBlend1 + PiPBlend2 16 The output pixel value can be divided into three case: Case 1: Case 2: Case 3:
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when the pixel covers Image0, Image1 and Image2 output pixel value = (Image1 x PiPBlend1 + Image2 x (16 PiPBlend1)) / 16 when the pixel covers Image0 and Image1 output pixel value = (Image1 x PiPBlend1 + Image0 x (16 PiPBlend1)) / 16 when the pixel covers Image0 and Image2
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Technical Reference Manual output pixel value = (Image2 x PiPBlend2 + Image0 x (16 PiPBlend2)) / 16 Bit 12-8 7-5 4-0 10.11.5.2. Bit 26-16 15-11 10-0 10.11.5.3. Bit 26-16 15-11 10-0 10.11.5.4. Bit 26-16 Name PiPBlend2 PiPBlend1 Type R/W R/W Table 10-30. LCD PIP Parameters Description Alpha Blending Level of PiPs image Image2. Revised Alpha Blending Level of PiPs image Image1

PIP Sub-Picture1 position (offset 0304H)

When PIP is enable, the following restricts must be noted. PiP1HPos + PiP1HDim < the horizontal resolution of panel. PiP1VPos + PiP1VDim < the vertical resolution of panel. PiP2HPos + PiP2HDim < the horizontal resolution of panel PiP2VPos + PiP2VDim < the vertical resolution of panel. Name PiP1HPos PiP1VPos Table 10-31. PIP SubPicture1 Position Type Description Specifies the horizontal position of the PIPs sub-picture1. The reference original position is the left boundary of the LCD screen. R/W The valid value is ranged form 1 to 2048. Note: When the register bit EnYCbCr420 is enabled, the value must be odd. Revised Specifies the vertical position of the PIPs sub-picture1. R/W The reference original position is the up boundary of the LCD screen. Valid value is ranged form 1 to 2048.

PIP Sub-Picture1 Dimination (offset 0308H) Table 10-32. PIP Subpicture Dimination Name Type Description Specifies the horizontal position of the PIPs sub-picture1. The reference original position is the left boundary of the LCD screen. PiP1HDim R/W The valid value is ranged form 1 to 2048. Note: When the register bit EnYCbCr420 is enabled, the value must be odd. Revised PiP1VDim R/W Specifies the vertical dimination of the PIPs sub-picture 1. PIP Sub-Picture2 position (offset 030CH) Table 10-33. PIP Sub-Picture2 Position Name Type Description Specifies the horizontal position of the PIPs sub-picture2. The reference original position is the left boundary of the LCD screen. PiP2HPos R/W The valid value is ranged form 1 to 2048. Note: When the register bit EnYCbCr420 is enabled, the value must be odd.
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Technical Reference Manual Description Revised Specifies the vertical position of the PIPs sub-picture2. 10-0 PiP2VPos R/W The reference original position is the up boundary of the LCD screen. Valid value is ranged form 1 to 2048. 10.11.5.5. PIP Sub-Picture2 Dimination (offset 0310H) Table 10-34. PIP Sub-Picture2 Dimination Bit Name Type Description Specifies the horizontal dimination of the PIPs sub-picture2. 26-16 PiP2HDim R/W Note: When the register bit EnYCbCr420 is enabled, the value must be odd. 15-11 Revised 10-0 PiP2VDim R/W Specifies the vertical dimination of the PIPs sub-picture2. 10.11.6. 10.11.6.1. Bit 13-8 7 6-0 10.11.6.2. LCD Image Color Management LCD Color Management Parament0 (offset 0400H) Table 10-35. LCD Color Management Parament0 Name Type Description Saturation Value SatValue R/W Cb(sat) = Cb(org) * (SatValue/32) Cr(sat) = Cr(org) * (SatValue/32) Sign bit of Brightness value BrightSign 0 The value of Brightness is positive 1 The value of Brightness is negative Birghtness Level Brightness R/W The range of Brightness Level is from 0~127 LCD Color Management Parament1 (offset 0404H) Bit 15-11 Name Type -

This register defines the coefficient of Hue operation. Cb(hue) = Cb(org)*cos Cr(org)*sin. Cr(hue) = Cb(org)*sin + Cr(org)*cos. Bit 14 Table 10-36. LCD Color Management Parament1 Name Type Description Sign bit of HuCosValue SigHuCos R/W 0 The value of HuCosValue is positive 1 The value of HuCosValue is negative Hue Value of cofficnce Cos HuCosValue is the value of cos. The cofficence of cos is (HuHuCosValue R/W CosValue/32) is the rotating degree from -180 ~ 180 Reserved Sign bit of HuSinValue SigHuSin R/W 0 The value of HuSinValue is positive 1 The value of HuSinValue is negative

13-8 7 6

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Technical Reference Manual Bit 5-0 Name Type Description Hue Value of cofficnce Sin HuSinValue is the value of sin. The cofficence of sin is (HuSinValue/32) is the rotating degree from -180 ~ 180

HuSinValue R/W

10.11.6.3.

LCD Color Management Parament2 (offset 0408H) Table 10-37. LCD Color Management Parament2

This register defines the coefficient of Sharpness operation. Bit 23-20 19-16 15-8 7-0 10.11.6.4. Name K1 K0 ShTh1 ShTh0 Type R/W R/W R/W R/W Description Sharpness weight value1. The value decides the first weight of sharpness. The total value is (K1 /2) Sharpness weight value0. The value decides the first weight of sharpness. The total value is (K0 /2) Sharpness Threshold Value1. The value decides the second threshold value of sharpness. Sharpness Threshold Value0. The value decides the first threshold value of sharpness.

LCD Color Management Parament3 (offset 040CH)

This register defines the coefficient of Contrast operation. Table 10-38. LCD Color Management Parament3 Bit 31-21 20-16 Name Contr_slope Type R/W Description Reserved Contrast cure slope. The value decides the slope of contrast cure. The real slope is the value divided by 4. Note: This value can not program to 0. Contrast offset sign. The value is defined as below. 1 When (Contr_slope x 128) > 512 0 When (Contr_slope x 128) < 512 Sharpness Threshold Value0. The value decides the first threshold value of sharpness.

12 7-0 10.11.7. 10.11.7.1. Bit 31-0 31-0 31-0 31-0

Contr_offset_sign R/W ShTh0 R/W

LCD Gamma Correction LCD Gamma Red Lookup Table (offset 0600H) Table 10-39. LCD Gamma Red Lookup Table Name Offset Description GaRdLUT0 0x00 The corresponding output values of Red component (0, 1, 2, 3) GaRdLUT1 0x04 The corresponding output values of Red component (4, 5, 6, 7) GaRdLUT2 0x08 GaRdLUT3 0x0C

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Technical Reference Manual Bit 31-0 31-0 Name GaRdLUT4 GaRdLUT5 Offset 0x10 0x14 Description

31-0 10.11.7.2. Bit 31-0 31-0 31-0 31-0 31-0 31-0

GaRdLUT63

0xFC

The corresponding output values of Green component (252, 253, 254, 255)

LCD Gamma Green Lookup Table (offset 0700H) Table 10-40. LCD Gamma Green Lookup Table Name GaGnLUT0 GaGnLUT1 GaGndLUT2 GaGnLUT3 GaGndLUT4 GaGndLUT5 Offset 0x00 0x04 0x08 0x0C 0x10 0x14 Description The corresponding output values of Red component (0, 1, 2, 3) The corresponding output values of Red component (4, 5, 6, 7)

31-0

GaGndLUT63

0xFC

The corresponding output values of Green component (252, 253, 254, 255)

1.1.1.1.3. LCD Gamma Blue Lookup Table (offset 0800H) Table 10-41. LCD Gamma Blue Lookup Table Bit 31-0 31-0 31-0 31-0 31-0 31-0 Name GaBuLUT0 GaBuLUT1 GaBudLUT2 GaBudLUT3 GaBuLUT4 GaBuLUT5 Offset 0x00 0x04 0x08 0x0C 0x10 0x14 Description The corresponding output values of Red component (0, 1, 2, 3) The corresponding output values of Red component (4, 5, 6, 7)

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Technical Reference Manual Bit Name Offset Description

31-0

GaBuLUT63

0xFC

The corresponding output values of Green component (252, 253, 254, 255)

10.11.7.3. LCD Palette RAM write accessing port (offset 0A00H~0BFCH) Example for address 0A00H( for the index value 0 and 1 ) Table 10-42. LCD Palette RAM Write Accessing Port Bit Name Type Description Not available for YCbCr mode, because the data in frame buffer represent raw YcbCr components and cannot be remapped. This 16-bits value is used to remap color when the index value equal to 1. And the format is described as below: D31-27, form the MSB of blue component and the remaining LSB will be filled with 0, D26-21, form the MSB of green component and the remaining LSB will be filled with 0, D20-16 form the MSB of red component and the remaining LSB will be filled with 0 This 16-bits value is used to remap color when the index value equal to 0. The operation is similar to previous one. D15-11, form the MSB of blue component and the remaining LSB will be filled with 0, D10-5 form the MSB of green component and the remaining LSB will be filled with 0, D4-0 form the MSB of red component and the remaining LSB will be filled with 0

31-16

PaletteEty1

R/W

15-0

PaletteEty0

R/W

10.11.8. 10.11.8.1. Bit 31-12 11-0 10.11.8.2. Bit 31-12 11-0 10.11.8.3.

Scalar Control Registers

Horizontal resolution register of scalar input (offset 1100H) Table 10-43. Horizontal Resolution Register of scalar Input Name Type Description Revised This field identifies the input image horizontal resolution and must be programmed a nonzero value before scalar active. Program to Hor_no_in R/W the number of hor_no_in required minus 1. The value is 1 ~ 2047. Vertical resolution register of scalar input (offset 1104H) Table 10-44. Vertical resolution register of scalar input Name Type Description Revised This field identifies the input image horizontal resolution and must be programmed a nonzero value before scalar active. Program to Ver_no_in R/W the number of hor_no_in required minus 1. The value is 1 ~ 2047. Horizontal resolution register of scalar output (offset 1108H) Table 10-45. Horizontal resolution register of scalar output
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Technical Reference Manual Bit 31-12 11-0 10.11.8.4. Name Hor_no_out Type R/W Description Revised This field identifies the output image horizontal resolution and must be programmed a nonzero value before scalar active. The value is 1 ~ 4096.

Vertical resolution register of scalar output (offset 110CH) Table 10-46. Vertical resolution register of scalar output

Bit 31-12 11-0 10.11.8.5. Bit 31-14

Name -

Type -

Description

Revised This field identifies the output image horizontal resolution and Ver_no_out R/W must be programmed a nonzero value before scalar active. The value is 1 ~ 4096. Miscellaneous control register (offset 1110H) Table 10-47. Miscellaneous control register Name Type Description

8-6

4-3

2-1

0 10.11.8.6.

Revised The scaling ratio selection of 1st stage scalar. 000 bypass 1st stage scalar 001 scalng down 1/2x1/2 010 scaling down 1/4x1/4 011 scaling down 1/8x1/8 Fir_sel R/W 100 scaling down 1/16x1/16 101 scaling down 1/32x1/32 110 scaling down 1/64x1/64 111 scaling down 1/128x1/128. Partial Display function active bit Partial_dis_on R/W 0 Disable 1 Enable. The horizontal interpolation mode. 00 Nearly bilinear mode 01 Threshold nearly bilinear mode.. Hor_inter_mode R/W 10 Most neighborhood mode. 11 Reserved The vertical interpolation mode. 00 Nearly bilinear mode. Ver_inter_mode R/W 01 Threshold nearly bilinear mode. 10 Most neighborhood mode. 1x user define mode. This bit identifies the 2nd stage scalar bypass mode and default the scalar is bypassed, this bit must be set in the initial state. Bypass_mode R/W Once it sets, it should not be changed. That means that users must clear this bit to make scalar active. Horizontal high threshold register (offset 1114H) Table 10-48. Horizontal high threshold register
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Technical Reference Manual Bit 31-9 8-0 10.11.8.7. Bit 31-9 8-0 10.11.8.8. Bit 31-9 8-0 10.11.8.9. Bit 31-9 8-0 10.11.8.10. Name Hor_high_th Type R/W Description Revised Horizontal upscaling high threshold register. The upscaling coefficient is high limited by this threshold value in the horizontal direction. The real value equal to Hor_high_th/256

Horizontal low threshold register (offset 1118H) Table 10-49. Horizontal low threshold register Name Hor_low_th Type R/W Description Revised Horizontal upscaling low threshold register. The upscaling coefficient is low limited by this threshold value in the horizontal direction. The real value equal to Hor_low_th / 256

Vertical high threshold register (offset 111CH) Table 10-50. Vertical high threshold register Name Ver_high_th Type R/W Description Revised Vertical upscaling high threshold register. The upscaling coefficient is high limited by this threshold value in the vertical direction. The real value equal to Ver_high_th / 256

Vertical low threshold register (offset 1120H) Table 10-51. Vertical low threshold register Name Ver_low_th Type R/W Description Revised Vertical upscaling low threshold register. The upscaling coefficient is high limited by this threshold value in the vertical direction. The real value equal to Ver_high_th / 256

Scaler resolution parameters (offset 112CH)

The parameter scal_hor_num and scal_ver_num are calculated as the formula below, where ver_no_in/hor_no_in is either the input image resolution register value if the 1st scaler is bypassed or the output image resolution of 1st scaler minus one if 1st scaler is involved. Scaling up : Scal_ver_num = [mod((ver_no_in_1)x2/ver_no_out)]x256/(ver_no_in+1) Scal_hor_num = [mode((hor_no_in1)x2/hor_no_out)x256/(hor_no_in+1) Scaling down : Scal_ver_num = [mod((ver_no_in+1)/ver_no_out)]x256/ver_no_out Scal_hor_num = [mod((hor_no_in+1)/hor_no_out)]x256/hor_no_out Table 10-52. Scalar resolution parameters Bit 31-16 Name Type Description Revised

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Technical Reference Manual Bit 15-8 7:0 10.11.9. 10.11.9.1. Bit 31-18 17-12 11-9 8-4 Name Scal_hor_num Scal_ver_num Type R/W R/W Description The initial numberator value of 2nd stage scaler coefficient in horizontal direction. The initial numerator value of 2nd stage scaler coefficient in vertical direction.

OSD Control Registers OSD Scaling and Dimension Control (offset 2000H) Table 10-53. OSD scaling and dimension control Name OSDHdim OSDVdim Type R/W R/W Description Revised Specify the horizontal dimension of the OSD window, that is, the total font number of each row. Revised Specify the vertical dimension of the OSD window, that is, the total vertical font number. Define the horizontal up-scaling factor. This will duplicate the dot several times, based on the set valu below. 00 Original horizontal size. 01 Enlarge the window 2 times horizontally. 10 Enlarge the window 3 times horizontally. 11 Enlarge the window 4 times horizontally. Define the vertical up-scaling factor. This will duplicate the line several times, based on the set value below. 00 Original vertical size. 01 Enlarge the window 2 times vertically. 10 Enlarge the window 3 times vertically. 11 Enlarge the window 4 times vertically.

3-2

OSDHScal

R/W

1:0

OSDVScal

R/W

10.11.9.2. Bit 31-24 23-12 11 10-0 10.11.9.3.

OSD Position Control (offset 2004H) Table 10-54. OSD position control Name OSDHPos OSDVpos Type R/W R/W Description Revised Specify the horizontal position of the OSD window. The reference original position is the left boundary of the LCD screen. The valid range is from 1 to 1280. However, there is a fixed offset value of 3 between OSDHPos and the actual window position. Revised Specify the vertical position of the OSD window. The reference original position is the upper boundary of the LCD screen. The valid value range is from 1 to 1280.

OSD Foreground Color Control (offset 2008H) Table 10-55. OSD foreground color control

Note: The content of Palette must be programmed to Y, Cb, Cr component.

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Technical Reference Manual Bit 31-24 23-16 15-8 7-0 10.11.9.4. Name OSDFrPal3 OSDFrPal2 OSDFrPal1 OSDFrPal0 Type R/W R/W R/WR/W Description OSD foreground color palette entry 3. The format is as follows: {D31-30, 6{& D31-30}} forms the MSB of the Y component. {D2927, 5{D29-27}} forms the MSB of the Cb componet. {D26-24, 5{ D26-24}}forms the MSB of the Cr component. OSD foreground color palette entry 2. The operation is similar to entry 3. OSD foreground color palette entry 1. The operation is similar to entry 3. OSD foreground color palette entry 0. The operation is similar to entry 3.

OSD Background Color Control (offset 200CH)

Note: The content of Palette must be programmed to Y, Cb, Cr component. Table 10-56. OSD Background color control Description OSD foreground color palette entry 3. The format is as follows: {D31-30, 6{& D31-30}} forms the MSB of the Y component. {D2931-24 OSDBgPal3 R/W 27, 5{D29-27}} forms the MSB of the Cb componet. {D26-24, 5{ D26-24}}forms the MSB of the Cr component. OSD foreground color palette entry 2. The operation is similar to 23-16 OSDBgPal2 R/W entry 3. OSD foreground color palette entry 1. The operation is similar to 15-8 OSDBgPal1 R/Wentry 3. 7-2 Revised OSD background transparency control 00 25% transparency 01 50% transparency 1-0 OSDTrans R/W 10 75% transparency 11 100% transparency 10.11.9.5. OSD Font Database Write Accessing Port (offset 8000H ~ BFFCH) Each fonts database is stored as a 12x16 matrix in font RAM. The RAM is organized as 12-bit in width. So Bit Name Type it requires 16 entries (192-bit) to record the font content. A bit equaling 1 refers to the foreground and a bit equaling 0 refers to background. The total size of font memory is 4Kx12, so the total number of fonts that can be loaded is 256. There is an example for a font 1 at the location 8000H ~ 803CH Table 10-57. OSD Font Database Write Accessing Port Address 0x8000 (0) 0x8000 (1) 0x8000 (2)
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Bit 11-0 11-0 11-0

Type R/W R/W R/W D11 0 0 0 D10 0 0 0 D9 0 0 0 D8 0 0 0 D7 0 0 1

Description D6 0 1 1 D5 0 1 1 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 0 0

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Address 0x8000 (3) 0x8000 4] 0x8000 (5) 0x8000 (6) 0x8000 (7) 0x8000 (8) 0x8000 (9) 0x8000 (10) 0x8000 (11) 0x8000 (12) 0x8000 (13) 0x8000 (14) 0x8000 (15)

Bit 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0

Description 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

10.11.9.6. OSD Window Attribute Write Accessing Port (offset C000H ~ C7FCH) Fonts are used to build an OSD window. The font dimension can be defined by programming the associated registers. Each font in the window owns a unique attribute to describe its behavior. The format is a 12-bit wide entry as mentioned earlier. These attributes are saved in an attribute RAM, and are sequentially placed from the up-left corner, left to right, and row by row. The offset address of the first attribute entry is C000H and the last one is C7FCH. Table 10-58. OSD Window Attribute Write Accessing Port Address Bit Type Description D11 D10 0xC000 11-0 H .. .. R/W .. R/W D9 D8 D7 D6 D5 D4 D3 D2 Foreground palette index of 1st font .. Foreground palette index of last fontb D1 D0 Backgroun d palette index of 1st font .. Backgroun d palette index of last font

Font index of 1st font0 Font index of lasssttt font0

0xC7FC 11-0 H 10.11.10. Bit

LCD Horizontal Timing Control (Offset == 0x00) Table 10-59. LCD Horizontal Timing Control Name Type Reset Value Description

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Technical Reference Manual Bit Name Type Reset Value Description Horizontal back porch: The number of LC_PCLK periods between the falling edge of LC_PCLK and the start of active data, which is programmed with the value minus 1. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the LC_HS for the previous line has been de-asserted, the value in HBP is used to count the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1 to 256 pixel clock cycles. Horizontal front porch: The number of LC_PCLK periods between the end of active data and the rising edge of LC_HS, which is programmed with the value minus 1. The 8bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD LC_HS is pulsed. Once a complete line of pixels is transmitted to the LCD driver, the value in HFP is used to count the number of pixel clocks to wait before asserting the LC_HS. HFP can generate a period of 1 to 256 pixel clock cycles. Horizontal synchronization pulse width: The width of the LC_HS signal in the LC_PCLK periods, which is programmed with the value minus 1. The 8-bit HW field specifies the pulse width of LC_HS. Pixels-per-line. Actual pixels-per-line = 16*(PL+1). The PL bit field specifies the number of pixels in each line or row of the screen. PL is a 6-bit value that represents 16 to 1024 pixels-per-line. PL is used to count the number of pixel clocks that occur before the HFP is applied. (Program the value required divided by 16, minus 1.)

31-24

HBP

R/W

00H

23-16

HFP

R/W

00H

15-8

HW

R/W

00H

7-2

PL

R/W

00H

10.11.11.
Bit

LCD Vertical Timing Control (Offset == 0x04) Name Type Table 10-60. LCD Vertical Timing Control Reset Value Description Vertical back porch: The number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field is used to specify the number of LC_HS inserted at the beginning of each frame. The VBP count starts just after 00H the LC_VS for the previous frame has been negated. After this has occurred, the count value in VBP sets the number of LC_HS periods inserted before the next frame. VBP generates 0 to 255 extra LC_HS cycles.

31-24

VBP

R/W

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Technical Reference Manual Bit Name Type Reset Value Description Vertical front porch: The number of inactive lines at the end of a frame, before the LC_VS period. The 8-bit VFP field is used to specify the number of line clocks to be inserted at the end of each frame. Once a complete frame of pixels is transmitted 00H to the LCD display, the value in VFP is used to count the number of LC_HS periods to wait. After the count has elapsed, the LC_VS signal is asserted. VFP generates 0 to 255 line clock cycles. LC_VS pulse width: The number of LC_HS, which is programmed to the number of lines required minus 1. The 600H bit VW field is used to specify the pulse width of the LC_VS. This register is programmed with the number of LC_HS in the LC_VS period minus 1. Lines-per-frame: The number of LC_DE per frame, which is programmed to the number of lines required minus 1. LF is a 000H 10-bit value allowing 1 to 1024 lines. This register is programmed with the number of lines per LCD panel minus 1.

23-16

VFP

R/W

15-10

VW

R/W

9-0

LF

R/W

10.11.12.
Bit

15

14

13

12

11

LCD Clock and Signal Polarity Control (Offset == 0x08) Table 10-61. LCD Clock and Signal Polarity Control Name Type Reset Value Description Adaptive pixel rate control (available only when DivNo > 0) 0 Disable 1 Enable This function will reduce the pixel rate when bandwidth congestion occurs. It may avoid distortion appearing on the ADPEN R/W 0H LCD screen, but when an unstable frequency operation is applied, some unpredictable situations might happen. So a safe margin must be considered between bandwidth and pixel rate. This is the fundamental solution for such a problem. This bit is used to select the active polarity of the output enable signal. IDE R/W 0H 0 LC_DE output pin is active HIGH 1 LC_DE output pin is active LOW This bit is used to select the edge of the panel clock on which pixel data are driven out onto the LCD data lines. 0 Data are driven on the LCD data lines on the rising edge ICK R/W 0H of LC_PCLK 1 Data are driven on the LCD data lines on the falling edge of LC_PCLK This bit is used to select the active polarity of the horizontal sync signal. IHS R/W 0H 0 LC_CLK pin is active HIGH and inactive LOW 1 LC_CLK pin is active LOW and inactive HIGH This bit is used to select the active polarity of the vertical sync signal. IVS R/W 0H 0 LC_CLK pin is active HIGH and inactive LOW 1 LC_CLK pin is active LOW and inactive HIGH
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Technical Reference Manual Bit 10-6 5-0 10.11.13. Bit 31-6 Name -DivNo Type R/W R/W Reset Value Description -Reserved LCD panel clock divisor control. The actual divisor value is 00H equal to (DivNo+1).

5-2

LCD Panel Frame Base Address (Offset == 0x10) Table 10-62. LCD Panel Frame Base Address Name Type Reset Value Description LCD frame base address. This is the start address of the frame data in memory. The six LSB bits are LCDFrameBase R/W 0000000H fixed to 0. When YCbCr420 format is enabled, the value will be used to define the base address of component Y. Frame buffer size selection for YCbCr420 mode. All values are valid except 0. The user can adjust this register to optimize memory utilization. The total memory address range occupied is described Frame420Size R/W 00H below: Starting address: {LCDFrameBase,0,0,0,0,0,0} Ending address: Starting address + 1.5 * {Frame420Size, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} LCD Interrupt Enable Mask (Offset == 0x18) Table 10-63. LCD Interrupt Enable Mask Name IntBusErrEn IntVstatusEn IntNxtBaseEn IntFIFOUdnEn Type R/W R/W R/W R/W Reset Value Description AHB master error interrupt enable 0H 1 Enable 0 Disable Vertical duration comparison interrupt enable 0H 1 Enable 0 Disable Next frame base address updated interrupt enable 0H 1 Enable 0 Disable FIFO under-run interrupt enable 0H 1 Enable 0 Disable

10.11.14. Bit 4 3 2 1 10.11.15. Bit 18

17

LCD Panel Pixel Parameters (Offset == 0x1C) Table 10-64. LCD Panel Pixel Parameters Name Type Reset Value Description YCbCr input mode control EnYCbCr R/W 0H 0 Disable 1 Enable This mode only functions when EnYCbCr is set to 1. YCbCr420 input mode control EnYCbCr420 R/W 0H 0 Disable 1 Enable

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Technical Reference Manual Bit 16 Name FIFOThresh Type R/W Reset Value Description LCD DMA FIFO threshold level 0 HBUSTREQM is raised when DMA FIFO has 0H four or more empty locations 1 HBUSTREQM is raised when DMA FIFO has eight or more empty locations TFT panel color depth selection 0H 0 6-bit per channel 1 8-bit per channel Generate interrupt at: 00 Start of vertical sync 0H 01 Dtart of vertical back porch 10 Start of vertical active image 11 Start of vertical front porch LCD screen on/off control 0 Screen disable (all data output pins are 0H forced to 0) 1 Screen enable (normal operation) Frame buffer data endian control 00 Little endian byte, little endian pixel 0H 01 Big endian byte, big endian pixel 10 Little endian byte, big endian pixel (WinCE) RGB of BGR format selection 0H 0 RGB normal output 1 BGR red and blue swapped -Reserved 0 Disable TFT panel 0H 1 Enable TFT panel Frame buffer pixel format 000 1 BPP 001 2 BPP 0H 010 4 BPP 011 8 BPP 100 16 BPP 101 24 BPP LCD controller enable control 0 Disable controller and force all LCD signals 0H including synchronization and data to zero. 1 Enable controller (normal operation)

15

PanelType

R/W

13-12

Vcomp

R/W

11

LCDon

R/W

10-9

Endian

RW

8 7-6 5

BGR -TFT

R/W R/W R/W

3-1

BPP

R/W

0 10.11.16. Bit 4 3

LCDen

R/W

LCD Interrupt Status Clear (Offset == 0x20) Table 10-65. LCD Interrupt Status Clear Name Type Reset Value Description Setting this bit to 1 will clear AHB master error StatusBusErr W -interrupt status, and setting it to 0 will take no effect. Setting this bit to 1 will clear the interrupt status of StatusVstatus W -vertical duration comparison, and setting it to 0 will take no effect.
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Technical Reference Manual Setting this bit to 1 will clear the frame buffer base address updated interrupt status, and setting it to 0 will take no effect. Setting this bit to 1 will clear the FIFO under-run interrupt status, and setting it to 0 will take no effect.

2 1 10.11.17. Bit 4 3

StatusNxtBase StatusFIFOUdn

W W

---

LCD Interrupt Status (Offset == 0x24) Table 10-66. LCD Interrupt Status Name Type Reset Value Description AHB master error status, set when the AMBA AHB IntBusErr R 0H master encounters a bus error response from a slave. Vertical duration comparison, set when one of the IntVstatus R 0H four vertical durations, selected via the LCDControl registers, is reached. Frame buffer base address update, set when the current base address registers have been successfully updated by the new address value. IntNxtBase R 0H This bit can be set only if the host has previously asserted a write access to the frame base address register. FIFO under-run, set when FIFO being read is not IntFIFOUdn R 0H ready. This may arise as a result of bus congestion. OSD Scaling and Dimension Control (Offset == 0x34) Table 10-67. OSD Scaling and Dimension Control Type Reset Value Description Specify the horizontal dimension of the OSD R/W 00H window, that is, the total font number of each row. Specify the vertical dimension of the OSD window, R/W 00H that is, the total row number of the window. Define the horizontal up-scaling factor. This will duplicate the dot several times, based on the set value below. R/W 0H 00 Original horizontal size 01 Enlarge the window 2 times horizontally 10 Enlarge the window 3 times horizontally 11 Enlarge the window 4 times horizontally Define the vertical up-scaling factor. This will duplicate the line several times, based on the set value below. R/W 0H 00 Original vertical size 01 Enlarge the window 2 times vertically 10 Enlarge the window 3 times vertically 11 Enlarge the window 4 times vertically

10.11.18.

Bit 15-10 9-5

Name OSDHdim OSDVdim

4-3

OSDHScal

2-1

OSDVScal

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Technical Reference Manual Bit 0 Name OSDen Type R/W Reset Value Description Control the on/off of the OSD window 0H 0 OSD window off 1 OSD window on

10.11.19.
Bit

19-10

9-0 10.11.20. Bit

OSD Position Control (Offset == 0x38) Table 10-68. OSD Position Control Name Type Reset Value Description Specify the horizontal position of the OSD window. The reference original position is the left boundary of the LCD screen. The valid value range is from 1 OSDHPos R/W 000H to 1023. However, there is a fixed offset value of 3 between OSDHPos and the actual window position. Specify the vertical position of the OSD window. The reference original position is the upper OSDVPos R/W 000H boundary of the LCD screen. The valid value range is from 1 to 1023. OSD Foreground Color Control (Offset == 0x3C) Table 10-69. OSD Foreground Color Control Name Type Reset Value Description OSD foreground color palette entry 3. The format is as follows: RGB mode: D31-29 forms the MSB of the blue component and the remaining LSB will be filled with 0. D28-26 forms the MSB of the green component and the remaining LSB will be filled with 0. D25-24 forms the MSB of the red component and the remaining LSB will be filled OSDFrPal3 R/W 00H with 0. YCbCr mode: D31-30 forms the MSB of the Y component and the remaining LSB will be filled with 0. D29-27 forms the MSB of the Cb component and the remaining LSB will be filled with 0. D26-24 forms the MSB of the Cr component and the remaining LSB will be filled with 0. OSD foreground color palette entry 2. The OSDFrPal2 R/W 00H operation is similar to that of entry 3. OSD foreground color palette entry 1. The OSDFrPal1 R/W 00H operation is similar to that of entry 3. OSD foreground color palette entry 0. The OSDFrPal0 R/W 00H operation is similar to that of entry 3. OSD Background Color Control (Offset == 0x40) Table 10-70. OSD Background Color Control Name Type Reset Value Description OSDBgPal3 R/W 00H OSD background color palette entry 3. The format
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31-24

23-16 15-8 7-0

10.11.21.
Bit 31-24
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Technical Reference Manual Bit Name Type Reset Value Description is as follows: RGB mode: D31-29 forms the MSB of the blue component and the remaining LSB will be filled with 0. D28-26 forms the MSB of the green component and the remaining LSB will be filled with 0. D25-24 forms the MSB of the red component and the remaining LSB will be filled with 0. YCbCr mode: D31-30 forms the MSB of the Y component and the remaining LSB will be filled with 0. D29-27 forms the MSB of the Cb component and the remaining LSB will be filled with 0. D26-24 forms the MSB of the Cr component and the remaining LSB will be filled with 0. OSD foreground color palette entry 2. The 00H operation is similar to that of entry 3. OSD foreground color palette entry 1. The 00H operation is similar to that of entry 3. OSD background transparency control. 00 25 % transparency 0H 01 50 % transparency 10 75 % transparency 11 100 % transparency

23-16 15-8

OSDBgPal2 OSDBgPal1

R/W R/W

5-4

OSDTrans

R/W

10.11.22. Bit 7-4 3-0

GPI/GPO Control (Offset == 0x44) Table 10-71. GPI/GPO Control Name Type Reset Value Description LCDGPO W Directly drive the level of the four general purpose 0H output ports. LCDGPI R Return the status of the four general purpose input -ports.

10.11.23.

LCD Palette RAM Accessing Port (Offset == 0x200 ~ 0x3FC) Example for address 0200H (for index values 0 and 1) Bit Name Table 10-72. LCD Palette RAM Accessing Port Type Reset Value Description

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Technical Reference Manual Bit Name Type Reset Value Description Not available for YCbCr mode, since the data in the frame buffer represent raw YCbCr components and cannot be remapped. This 16-bit value is used to remap color when the index value is equal to 1. The format is as below: -D31-27 forms the MSB of the blue component and the remaining LSB will be filled with 0. D26-21 forms the MSB of the green component and the remaining LSB will be filled with 0. D20-16 forms the MSB of the red component and the remaining LSB will be filled with 0. This 16-bit value is used to remap color when the index value is equal to 0. The operation is similar to that of entry 1. D15-11 forms the MSB of the blue component and the remaining LSB will be filled with 0. D10-5 forms the -MSB of the green component and the remaining LSB will be filled with 0. D4-0 forms the MSB of the red component and the remaining LSB will be filled with 0.

31-16

PaletteEty1

15-0

PaletteEty0

10.11.24.

OSD Font Database Write Accessing Port (Offset == 0x8000 ~ 0xBFFC)

Each fonts database is stored as a 12x16 matrix in font RAM. The RAM is organized as 12-bit in width. So it requires 16 entries (192-bit) to record the font content. A bit equaling 1 refers to the foreground and a bit equaling 0 refers to the background. The total size of font memory is 4Kx12, so the total number of fonts that can be loaded is 256. There is an example for a font 1 at the location 8000H~803CH. Table 10-73. OSD Font Database Write Accessing Port
Address Offset 8000H 8004H 8008H 800CH 8010H 8014H 8018H 801CH 8020H 8024H 8028H 802CH 8030H 8034H Bit 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 Type W W W W W W W W W W W W W W Description D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 0 0 0 0 0 1 D4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 D5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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8038H 803CH 11-0 11-0 W W 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0

10.11.25.

OSD Window Attribute Write Accessing Port (Offset == 0xC000 ~ 0xC7FC)

Fonts are used to build an OSD window. The font dimension can be defined by programming the associated registers. Each font in the window owns a unique attribute to describe its behavior. The format is a 12-bit-wide entry as mentioned earlier. These attributes are saved in an attribute RAM, and are sequentially placed from the up-left corner, left to right, and row by row. The offset address of the first attribute entry is C000H and the last one is C7FCH. So it is possible to display an OSD window with up to 512 fonts regardless of the window aspect. Since the total font variety is 256, some fonts will be reused to build such a big window. Table 10-74. OSD Window Attribute Write Accessing Port
Address C000H | C7FCH Bit 11-0 | 11-0 Type W | W Font index of last font Description D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 foreground palette index of first font | | foreground palette index of last font background palette index of first font | Background palette index of last font

Font index of first font

10.12. Application The below figure illustrates the application example

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11. Ethernet 10/100 Controller

11.1. Overview The aJ-200 includes a high quality single-chip 10/100 Ethernet controller. It includes AHB wrapper, DMA engine, on-chip memory (TX FIFO and RX FIFO), MAC, and analog 10/100 PHY. The Ethernet controller provides AHB master capability and full compliance with IEEE 802.3 100 Mb/s and 10 Mb/s specification. The DMA controller handles all data transfers between system memory and on-chip memory. With the DMA engine, it can reduce CPU loading, maximize performance and minimize FIFO size. The Ethernet Controller has on-chip memory for buffering, so external local buffer memory is not needed. It supports the following features DMA engine for transmitting and receiving packets Programmable AHB burst size Transmit and receive interrupt mitigation Two independent TX/RX FIFO (2KBytes) Half and full duplex modes Flow control for full duplex and backpressure for half duplex Integrated analog 10/100 Ethernet PHY o Fully compliant with 100BASE-TX and 10BASE-T PMD level standards (IEEE 802.3u, FDDI-TPPMD and IEEE 802.3) The block diagram is shown in the figure below
AHB BUS TXFIFO MII

TXDMA AHB_MASTER (AHBM) (TXD) DMA_ARBITER RXDMA (RXD)

TXMAC (TXMAC) RXMAC (RXMAC) 10/100 Ethernet PHY RXIP/N

TXOP/N

RXFIFO

PWR_MANAGE (PM)

AHB_SLAVE (AHBS) REGIST (REG)

Figure 11-1. Ethernet Controller Block Diagram

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Technical Reference Manual 11.2. Functional Block Description

11.2.1. AHB_MASTER The AHB_MASTER implements the AHB master function of the MAC controller. When the TXDMA wants to move transmit packets from the transmit buffer into the TX FIFO, the TXDMA would request the DMA_ARBITER to use the DMA channel. After the DMA_ARBITER gives the DMA channel to the TXDMA, it would initiate a burst transfer to the AHB_MASTER through the DMA_ARBITER and the AHB_MASTER would initiate a read operation to AHB bus. Then the AHB_MASTER would pass the transmit packet data from the transmit buffer to the TXDMA. When the RXDMA wants to move receive packets from the RX FIFO to the receive buffer, the RXDMA would request the DMA_ARBITER to use the DMA channel. After the DMA_ARBITER gives the DMA channel to the RXDMA, it would initiate a burst transfer to the AHB_MASTER through the DMA_ARBITER and the AHB_MASTER would initiate a write operation to AHB bus. Then the AHB_MASTER would pass the receive packet data from the RXDMA to the receive buffer. 11.2.2. AHB_SLAVE The AHB_SLAVE implements the AHB slave function of the MAC controller. When other AHB master wants to write data to the registers in the MAC controller, it would initiate a write operation to AHB bus, and the AHB_SLAVE would respond to the operation. Then the AHB_SLAVE would pass the write data to the REGIST. If other AHB master wants to read data from the registers in the MAC controller, it would initiate a read operation to AHB bus, and the AHB_SLAVE would respond to the operation. Then the AHB_SLAVE would pass the read information to the REGIST and get the read data. Finally it passes the read data to AHB bus and the read operation is finished. The AHB_SLAVE only responds to AHB bus with OKAY or ERROR message. When in normal condition, it would respond with OKAY. When it detects error in the AHB transaction, it would respond with ERROR. 11.2.3. DMA_ARBITER The DMA_ARBITER acts as the bridge between the two sets of control signal from the TXDMA and the RXDMA, and the control signal to AHB_MASTER. It would act as the arbiter to decide if the TXDMA or the RXDMA is entitled to use the AHB_MASTER. 11.2.4. TXDMA The three main functions of the TXDMA are: 1. Read the transmit descriptor and write transmit status back to the transmit descriptor; 2. Move the transmit packet data from the transmit buffer to the TX FIFO and 3. Control the read / write action of the TX FIFO. When there is a packet to be transmitted to Ethernet, the TXDMA would first fetch the transmit descriptor

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Technical Reference Manual to get the descriptors information and transmit buffer base address and size. Second, the TXDMA would move the transmit packet data from the corresponding transmit buffer to the TX FIFO. Third, the TXDMA would request the TXMAC to send the packet to the network. Fourth, the TXMAC would read the transmit packet data with the help of the TXDMA, and send it to the network. After finishing the transmission of the packet, the TXMAC would send the transmit status to the TXDMA. Then the TXDMA would write the transmit status back to the transmit descriptor. 11.2.5. RXDMA The three main functions of the RXDMA are: 1. Read the receive descriptor and write receive status to the receive descriptor; 2. Move the receive packet data from the RX FIFO to the receive buffer; and 3. Control the read / write action of the RX FIFO. When there is a packet to be sent to the MAC controller, it would first be received by the RXMAC and saved in the RX FIFO. Second, the RXDMA would detect there are packets in the RX FIFO, and move the received packets from the RX FIFO to the receive buffer. Then the RXDMA would write the receive status to the receive descriptor. 11.2.6. TXMAC The TXMAC would transmit packets from TX FIFO to Ethernet. The TXMAC includes CRC, preamble, jam generator and transmit state machine. When there is a packet to be transmitted, the TXMAC would detect the Ethernets status, and would not start the transmission until the Ethernet is idle. Then the TXMAC would add preamble and CRC to this packet, and send the packet to Ethernet. If the TXMAC detects collision when transmitting the packet, it would send the jam to Ethernet, and wait back off time to retransmit the packet. Figure below is the transmit frame control flow of the TXMAC.

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Transmit frame

no

Transmit Enable ?

yes

Assemble Frame

yes

Ethernet busy?
no

Delay to start of next slot Start Transmission

no

Collision Detect?

yes

Send Jam Transmission Done ?

yes yes no

Increment collision counter

Collision counter>=16?
no

Compute backoff Done: Transmit Disable Done: Transmit OK Done: Excessive Collision Error Wait backoff time

Figure 11-2. Transmit Frame Control Flow of TXMAC 11.2.7. RXMAC The RXMAC would receive packets from Ethernet to RX FIFO. The RXMAC includes address recognition circuit, CRC check circuit, and receive state machine. When there is a packet incoming from Ethernet, the RXMAC would acknowledge the RXDMA and the RXDMA would pass the received packet data to RX FIFO from RXMAC. After the RXMAC finishes receiving the packet, it would check if the receive packet address is correct and if CRC check is successful or not. If the result is correct, it would acknowledge the RXDMA to save the packet in RX FIFO, otherwise the packet would be discarded. Figure below is the receive frame control flow of the RXMAC.

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Receive Frame

no

Receive Enable ?

yes

Start Receive

Recognize Address ?
yes

no

Check Frame too long or short ?

no

yes

Check CRC ?
no

yes

Check CRC ?

yes

no

Done: Receive OK Done: Receive Disabled

Done: Report Frame message

Done: Report CRC message

Done: Report CRC and Frame message

Figure 11-3. Receive Frame Control Flow of RXMAC 11.2.8. REGIST The REGIST stores the registers of the MAC controller. Other AHB master could read or write these registers with the help of the AHB_SLAVE. 11.2.9. PWR_MANAGE The PWR_MANAGE manages the power control logic of the MAC controller. When in normal mode, the PWR_MANAGE would turn on AHB bus clock, transmit clock and receive clock. If software forces the MAC controller into power down mode, the PWR_MANAGE would turn off AHB bus clock, transmit clock and receive clock to some modules to reduce power consumption. 11.2.10. 10/100 T-Base Ethernet PHY The Ethernet PHY is a highly integrated 10/100BASE-TX (twisted-pair cable) transceiver module, which provides high performance that can be integrated in a wide variety of Ethernet applications. It is fully

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Technical Reference Manual compliant with 10/100BASE-TX Ethernet standards such as IEEE 802.3, 802.3u, and ANSI X3.263-1995 (FDDI-TP-PMD). It supports the following features: Full-duplex and half-duplex modes Over-sampling mixed-signal transmit driver complies with 10/100BASE-TX transmit waveshaping/slew-control requirements MDI/MDIX auto crossover function (Auto-MDIX) Parallel/Serial Control Interface Less than 360 mW power consumption in 100BASE-TX mode (including transmit current) Less than 500 mW power consumption in 10BASE-T mode (including transmit current) Less than 200 W power consumption in power down mode DSP-based highly integrated embedded Ethernet twisted-pair symbol transceiver solution DSP-based adaptive line equalizer, providing superior immunity to near end crosstalk and intersymbol interference Fully compliant with 100BASE-TX, and 10BASE-T PMD level standards (IEEE 802.3u, FDDI-TPPMD and IEEE 802.3) DSP-controlled symbol timing recovery circuit Baseline wander corrective circuits to compensate data dependent offset due to AC coupling transformers Multi-functional LED outputs

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11.2.10.1.

Figure 11-4. Block Diagram of 10/100Base PHY Adaptive Equalizer

The cables amplitude and phase distortion will cause inter-symbol interference (ISI) which can make clock and data recovery impossible. It eliminates these distortions by automatically adjusting the weights of feedback equalizer and feed forward equalizer to match the inverse of cable impulse response. 11.2.10.2. Baseline Compensation

The transmitter sends DC and AC signals. The receiving side and transmitting side each has a transformer that blocks DC signals. When the AC signal loses its DC component, the AC signal becomes distorted. It provides a circuit that restores the DC component to the AC signal and delivers it as a complete signal to the receiver. 11.2.10.3. Link Monitor / Signal Detect

When a signal is received by the receiver, the receiver will detect the signals level. If the signal level is above 400mV in 100BASE-TX mode, the receiver will send a Signal Detect (SD) signal to the MII. If the level is below 400mV, the SD signal will then be de-asserted in 722 s.
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Technical Reference Manual 11.2.10.4. Carrier Detect

The Physical Coding Sublayer (PCS) checks Physical Medium Attachment (PMA) data to see if the packets meet IEEE 802.3-defined preamble (J / K / packets in 100BASE-TX) standards. If the packets are correct, the PCS sublayer will start to process the data and send it to the MII. 11.2.10.5. 4B / 5B Coding The Physical Coding Sublayer (PCS) converts received / transmitted data according to IEEE 802.3-defined coding standards, such as 4B / 5B and scrambling / de-scrambling. 11.2.10.6. MII Serial Management Interface The MII serial management interface (SMI) is an IEEE-802.3-defined serial control interface. Every register in this IP can be read or written through this interface. 11.2.10.7. Auto negotiation This PHY can automatically negotiate its operating modes with other PHY devices over twisted pair cable connections. Clause 28 of the IEEE 802.3u defines the auto negotiation mechanism. 11.3. MAC Function Description

The following paragraph describes the Ethernet MAC in details 11.3.1. Half-Duplex (CSMA/CD Access Protocol) Half-Duplex Ethernet is the traditional form of Ethernet that uses the CSMA/CD (Carrier Sense Multiple Access with Collision Detection) protocol with two or more CSMA/CD stations sharing a common transmission medium. To transmit a frame, a station must wait for an idle period on the medium when no other station is transmitting. It then transmits the frame by broadcasting it over the medium such that it is heard by all the other stations on the network. If another device tries to send data at the same time, a collision is said to occur. The transmitting station then intentionally transmits a jam sequence to ensure all stations are notified of the frame transmission failure due to a collision. The station then remains silent for a random period of time before attempting to transmit again. This process is repeated until the frame is eventually transmitted successfully. The basic rules for transmitting a frame are as follows: The network is monitored for a carrier, or presence of a transmitting station. This process is known as carrier sense. If an active carrier is detected, then transmission is deferred. The station continues to monitor the network until the carrier ceases. If an active carrier is not detected, and the period of absence of carrier is equal to or greater than the interframe gap, then the station immediately begins transmission of the frame. If a collision is detected while sending the frame, the transmitting station stops sending the frame data and sends a 32-bit jam sequence. If the collision is detected when transmitting the frame preamble, the transmitting station will complete sending of the frame preamble before starting transmission of the jam sequence. The jam sequence is transmitted to ensure that the length of the collision is sufficient to be
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Technical Reference Manual noticed by the other transmitting stations. After sending the jam sequence, the transmitting station waits a random period of time chosen using a random number generator before starting the transmission process. This process is called back off. Having the colliding stations wait a random period of time before retransmitting reduces the probability of a repeated collision. If repeated collisions occur, then transmission is repeated, but the random delay is increased with each attempt. This further reduces the probability of another collision. This process repeats until a station transmits a frame without collision. Once a station successfully transmits a frame, it clears the collision counter used to increase the back off time after each repeated collision. 11.3.2. Full-Duplex Ethernet The release of the IEEE 802.3x standard defined a second mode of operation for Ethernet, called fullduplex, that bypasses the CSMA/CD protocol. The CSMA/CD protocol is half-duplex. This implies that a station may either transmit data, or receive data, but never both at the same time. Full-duplex mode allows two stations to simultaneously exchange data over a point-to-point link that provides independent transmit and receive paths. Since each station can simultaneously transmit and receive data, the aggregate throughput of the link is effectively doubled. A 10 Mb/s station operating in full-duplex mode provides a maximum bandwidth of 20 Mb/s. A full-duplex 100 Mb/s station provides 200 Mb/s of bandwidth. Full-duplex operation is restricted to links which meet the following criteria The physical medium must be capable of supporting simultaneous transmission and reception without interference. Media specifications which meet this requirement are 10BASE-T, 10BASE-FL, 100BASE-TX, 100BASE-FX, 100BASE-T2, 1000BASE-CX, 1000BASE-SX, 1000BASE-LS, and 1000BASE-T. The following media specifications do not support full duplex: 10BASE5, 10BASE2, 10BASE-FP, 10BASE-FB, and 100BASET4. Full-duplex operation is restricted to point-to-point links. Since there is no contention for a shared medium, collisions cannot occur and the CSMA/CD protocol is unnecessary. Frames may be transmitted back-to-back with the interval of the minimum interframe gap. Both stations on the link must be capable of, and be configured for, full-duplex operation. Throughput is doubled by permitting simultaneous transmission and reception. The efficiency of the link is improved by eliminating the potential for collisions. Segment lengths are no longer limited by the timing requirements of half-duplex Ethernet that ensure collisions are propagated to all stations within the required 512 bit times. For example, 100BASE-FX is limited to 412-meter segment length in half-duplex mode, but may support
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Full-duplex operation offers several major advantages

Technical Reference Manual segment lengths as long as 2 km in full-duplex mode. 11.3.3. Loop Back When the MAC controller is configured in the Loop Back mode, the MAC controller would loop the transmit data back through MII interface; then the MAC controller would receive the data it transmits. Users can test the control circuit and data path in this mode. 11.3.4. Transmit Descriptors and Data Buffers The MAC controller uses the descriptor ring to manage the transmit buffers. The transmit descriptors and buffers are all in system memory. The MAC controller moves the transmit packet data from the transmit buffers in system memory to the TX FIFO inside the MAC controller and then transmits the packet to Ethernet. The transmit descriptors that reside in the system memory act as pointers to the transmit buffers. There is one descriptor ring for transmission. The base address of the transmit ring is in the Transmit Ring Base Address Register (TXR_BADR, offset: 20h ~ 23h). Each transmit descriptor contains a transmit buffer. A transmit buffer consists of either an entire frame or part of a frame, but it cannot exceed a single frame. The transmit descriptor contains transmit buffer status and the transmit buffer can only contain the transmit data.
MAC register
TXDMA-OWN

Transmit Ring Status Tx buffer size

System Memory

TXR_BADR (Transmit Ring Base Address)

Descriptor 1

Control

Tx Buffer base address

Tx Buffer : : : : : Tx buffer size

Descriptor n

EDOTR=1(End Descriptor of Transmit Ring)

Figure 11-5. Transmit Ring Descriptor Structure The transmit descriptor structure is as follows. Note that the start address of each transmit descriptor must be 16-byte alignment.

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Technical Reference Manual Table 11-1. Transmit Descriptor TXDMA_OWN Status Control TX buffer size TX buffer base address

TXDES0 TXDES1 TXDES2

TXDES0: contains the transmit frame status and descriptor ownership information. Table 11-2. TXDES0 Bit Name Description TXDMA ownership bit When set, it indicates that the descriptor is owned by the MAC 31 TXDMA_OWN controller. When reset, it indicates that the software owns the descriptor. The MAC controller clears this bit when it completes the frame transmission. 30-2 Reserved When set, it indicates that the frame transmission is aborted after 16 1 TXPKT_EXSCOL collisions. It is valid only when FTS = 1. When set, it indicates that the frame transmission is aborted due to late 0 TXPKT_LATECOL collision. It is valid only when FTS = 1. TXDES1: contains the control bits and transmit buffer size. Bit 31 Name EDOTR Table 11-3. TXDES1 Description End Descriptor of Transmit Ring When set, it indicates that the descriptor is the last descriptor of the transmit ring. Transmit Interrupt on Completion. When set, the MAC controller would assert transmit interrupt after the present frame has been transmitted. It is valid only when FTS = 1 and bits 8 ~ 14 (TXINT_THR, TXINT_CNT) of Interrupt Timer Control Register = 0. Transmit to FIFO Interrupt on Completion. When set, the MAC controller would assert transmit interrupt after the present frame has been moved into the TX FIFO. It is valid only when FTS = 1. First Transmit Segment descriptor. When set, it indicates that this is the first descriptor of a TX packet. Last Transmit Segment descriptor. When set, it indicates that this is the last descriptor of a TX packet. Reserved Transmit buffer size in byte. When the size is 0, the descriptor is discarded.

30

TXIC

29 28 27 26-11 10-0

TX2FIC FTS LTS TXBUF_SIZE

TXDES2: contains transmit buffer base address. Bit 31-0 Name TXBUF_BADR Description Transmit buffer base address

11.3.5. Receive Descriptors and Data Buffers

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Technical Reference Manual The MAC controller uses a descriptor ring to manage the receive buffers. The receive descriptors and buffers are all in system memory. The MAC controller first stores the packet received from the network in the RX FIFO and then moves the received packet data to the receive buffers in system memory. The receive descriptors that reside in the system memory act as pointers to the receive buffers. There is one descriptor ring for reception. The base address of the receive ring is in the Receive Ring Base Address Register (RXR_BADR, offset: 24h ~ 23h). Each receive descriptor contains a receive buffer. A receive buffer consists of either an entire frame or part of a frame, but it cannot exceed a single frame. The receive descriptor contains receive buffer status and the receive buffer can only contain the receive packet data.
MAC register RXDMA_OWN RXR_BADR (Receive Ring Base Address) Descriptor 1 Control System Memory

Receive Ring Status Rx buffer size

Rx Buffer base address

Rx Buffer : : : : : Rx buffer size

Descriptor n

EDORR=1(End Descriptor of Receive Ring)

Figure 11-6. Receive Ring Descriptor Structure The receive descriptor structure is as follows: Note that the start address of each receive descriptor must be 16-byte alignment. RXDES0 RXDES1 RXDES2 Table 11-4. Receive Descriptor RXDMA_OWN Status Control RX buffer size (DW boundary) RX buffer base address (DW boundary)

RXDES0: contains the receive frame status and descriptor ownership information. Table 11-5. RXDES0 Bit Name Description

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Technical Reference Manual Bit Name Description RXDMA_OWN - RXDMA ownership bit When set, it indicates that the descriptor is owned by the MAC controller. When reset, it indicates that the descriptor is owned by the software. The MAC controller clears this bit when it completes the frame reception or when the receive buffer of the receive descriptor is full. Reserved FRS FRS - First Receive Segment descriptor. When set, it indicates that this is the first descriptor of a received packet. LRS - Last Receive Segment descriptor. When set, it indicates that this is the last descriptor of a received packet. Reserved RX_ODD_NB RX_ODD_NB - Receive Odd Nibbles When set, it indicates receiving a packet with odd nibbles. RUNT - Runt packet. When set, it indicates that the received packet length is less than 64 bytes. Bits 23 ~ 0 are valid only when the FRS = 1. FTL - Frame Too Long When set, it indicates that the received packet length exceeds 1518 bytes. CRC_ERR - CRC error When set, it indicates that a CRC error occurs on the received packet. RX_ERR - Receive error When set, it indicates that a receive error happens when receiving a packet. BROADCAST - Broadcast frame. When set, it indicates that the received packet is a broadcast frame. MULTICAST - Multicast frame. When set, it indicates that the received packet is a multicast frame. Reserved RFL - Receive Frame Length

31

RXDMA_OWN

30 29

28 27-23 22

LRS

21

RUNT

20 19 18 17 16 15-11 10-0

FTL CRC_ERR RX_ERR BROADCAST MULTICAST

RXDES1: contains the control bits and receive buffer size. Bit 31 Name EDORR Table 11-6. RXDES1 Description EDORR - End Descriptor of Receive Ring. When set, it indicates that the descriptor is the last descriptor of the receive ring.

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Technical Reference Manual Bit 30-11 10-0 Name RXBUF_SIZE Description Reserved Receive buffer size. The unit is 1 byte. Receive buffer size must be double-word boundary (4-byte aligned).

RXDES2: contains receive buffer base address. Table 11-7. RXDES2 Bit Name Description Receive buffer base address. Receive buffer base address must be 31-0 RXBUF_BADR double-word boundary (4-byte aligned). 11.3.6. Transmitting Packets When the software wants to transmit a packet to Ethernet, it would move the packet data into the transmit buffer first. Then the software writes the packets length and position into the transmit descriptor and triggers the MAC controller to send the packet. After the entire packet has been moved into the TX FIFO, the MAC controller begins to transmit it to Ethernet. When the packet has been transmitted; the MAC controller would assert an interrupt to notify software that the packet has been transmitted successfully. 11.3.7. Receiving Packets When there is a packet incoming, the MAC controller would first save the received packet in the RX FIFO if both CRC result and address check result are correct. After the incoming packet is successfully saved in RX FIFO, the MAC controller would initiate Direct Memory Access (DMA) function to move the received packet data from the RX FIFO to the system memory. Then the MAC controller would assert an interrupt to notify software that the packet has been received successfully. 11.3.8. Zero-Copy With the Ethernet zero-copy function, system needs not to perform data movement for packet header alignment. The ethernet DMA will place the first segment of incoming packet from 2-byte-aligned address, regardless of the buffer address assigned in receive descriptor. If there are more segments (Packet size > receive buffer size), they will be placed from 4-byte-aligned address. Figure below shows an example of packet placement in a little-endian system. The system can determine the start address of valid data by FRS flag in receive descriptor.

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Technical Reference Manual

Figure 11-7. Example of incoming packet placement 11.3.9. Ethernet Address Filtering The MAC controller can be set up to recognize any one of the Ethernet receive address groups described in the following table. o o o o RX_BROADPKT: bit 17 of MAC Control Register (offset: 88h) RX_MULTIPKT: bit 16 of MAC Control Register (offset: 88h) RCV_ALL: bit 12 of MAC Control Register (offset: 88h) HT_MULTI_EN: bit 9 of MAC Control Register (offset: 88h) Table 11-8.
RCV_ALL RX_MULTIPKT RX_BROADPKT

Ethernet Address Filtering

HT_MULTI_EN Group Description

The MAC controller receives the following frame: The frames destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller.

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Technical Reference Manual

RCV_ALL RX_MULTIPKT RX_BROADPKT HT_MULTI_EN Group Description

1 11.3.10.

X DMA Arbitration Scheme

The MAC controller receives the following frames: The frames destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller. The frames destination address is a multicast address. Pass the address filtering of the multicast address hash table in the MAC controller. The MAC controller receives the following frames: The frames destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller. The frames destination address is a broadcast address. The MAC controller receives the following frames: The frames destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller. The frames destination address is a multicast address. Pass the address filtering of the multicast address hash table in the MAC controller. The frames destination address is a broadcast address. The MAC controller receives the following frames: The frames destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller. The frames destination address is a multicast address. The MAC controller supports reception of all frames on the network regardless of their destination address.

The DMA arbitration scheme is decided by RX_THR_EN (bit 9 of DMA Burst Length and Arbitration

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Technical Reference Manual Control Register, offset: 30h ~ 33h). When RX_THR_EN = 0, the DMA arbitration scheme would do a fair arbitration between the TXDMA and RXDMA. The last one using the DMA channel has lower priority to get the DMA channel when both TXDMA and RXDMA request the DMA channel at the same time. When RX_THR_EN is set, if the used space in the RX FIFO is larger than or equal to the RXFIFO_HTHR (bits 8 ~ 6 of DMA Burst Length and Arbitration Control Register, offset: 30h ~ 33h), the RXDMA has higher priority than the TXDMA for using the DMA channel. The RXDMA keeps the higher priority until the used space in the RX FIFO is less than or equal to the RXFIFO_LTHR (bits 5 ~ 3 of DMA Burst Length and Arbitration Control Register, offset: 30h ~ 33h). Then the TXDMA gets higher priority than the RXDMA. So software must set RXFIFO_HTHR to be larger than RXFIFO_LTHR to keep the MAC controller work correctly. 11.3.11. Wake-On-LAN

MAC supports the Wake-On-LAN function. The Wake-On-LAN function supports 3 wake-up events: link status change, magic packet and wake-up frame. 11.3.11.1. Link Status Change Link status change refers to the event where the link state to Ethernet changes. PHY would offer a phy_linksts signal. If the link state to Ethernet changes, the state of phy_linksts would also change. Once MAC has been put into power saving mode and link status change mode is enabled, link status change would be treated as a wake-up event. 11.3.11.2. Magic Packet A magic packet contains a specific sequence consisting of 16 duplications of network adaptors node address without breaks. The specific sequence must be preceded by 6 bytes of FFh. So the format of a magic packet goes DA+SA++ 6*(8hFFh)+ +16*(network adaptors node address)+ Once FTMAC100 has been put into power saving mode and magic packet mode is enabled, a magic packet would be treated as a wake-up event. 11.3.11.3. Wake-up Frame The purpose of wake-up frame is to wake up the system when another machine on the network needs to communicate with this system. It does not require the application running on the remote machine to send a special wakeup frame pattern. Instead, when MAC is in wake-up frame mode, it tries to identify certain interesting frames that are sent by existing network protocols. Some examples are NETBIOS name lookups and ARP requests. Before putting MAC into wake-up frame mode, the system would pass to the driver a list of wake-up frames that could wake-up the system; and the driver passes the information to MAC by writing the

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Technical Reference Manual corresponding register. Then MAC identifies if a packet is a wake-up frame according to the information. Before putting MAC into wake-up frame mode, the system should pass to the driver a list of wake-up frames and corresponding byte masks. Each byte mask defines which bytes of the incoming frames should be compared with the corresponding wake-up frame in order to determine whether or not to accept the incoming frames as a wake-up event. Table 11-9. Wake-up frame format Wake-up Frame Format 25 67 90 44 0 0 1 1

Byte content Byte mask in MAC Exact matching

00 0

A3 0

6C 1

...

There are two ways to identify if the received packet is a wake-up frame or not. Signature matching is used

MAC would need many registers to store all byte content and byte mask for each wake-up frame. When a packet arrives from the network, it would check those bytes of the incoming frame that correspond to bits that are set to 1 in the byte mask for each wake-up frame. If the check result is ok for any wake-up frame and if the incoming frame passes the standard CRC check, MAC would treat it as a wake-up event. Signature matching MAC needs a CRC generation circuit and registers to save all byte mask and 4- byte CRC register for each wake-up frame. The driver calculates a CRC value based on those bytes of the wake-up frame that correspond to bits that are set to 1 in the byte mask. The driver stores the resulting value and corresponding byte mask into MAC. When wake-up frame mode is enabled as a frame arrives from the network, each CRC generator calculates a CRC value based on those bytes of the incoming frame that correspond to bits that are set to 1 in that CRC generator byte mask. If the calculated value matches the stored value for any wake-up frame and the incoming frame passes the standard CRC check, MAC would treat it as a wake-up event. 11.3.12. Power Down Mode

MAC100 has one power-down mode that significantly reduces power dissipation when its power state is not programmed into D0 power state. The following lists some brief features of the power-down mode: 1. MAC100 doesnt assert interrupt when in the power-down mode. 2. MAC100 doesnt transmit packets to Ethernet. 3. MAC100 doesnt save received packets in the RX FIFO. 4. MAC100 would assert WOL when a wake-up event happens. 11.4. Flow Control
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Technical Reference Manual The MAC controller implements flow control function. It supports IEEE802.3x flow control for full-duplex mode and backpressure for half-duplex mode. The IEEE802.3x flow control is used in full-duplex mode. When A and B are transmitting and receiving packets with each other in full-duplex mode, if the RX FIFO in B is nearly full, B would send a pause frame to A in order to avoid received packet loss. Then A would be inhibited from transmitting packets for a specified period of time. B would consume the received data during the specified period of time. A would continue to send packets to B after the pause time has lapsed. Brief features of the flow control in full-duplex mode are as follows: The software could configure the pause time of the pause frame. The MAC controller could send the pause frame according to the low / high threshold of RX FIFO. The software could send the pause frame by writing the register. The back pressure mode is used in half-duplex mode. When A is transmitting and receiving packets in half-duplex mode, if the RX FIFO in A is nearly full, A would send a jam pattern to generate collisions to avoid packets from being saved into the RX FIFO when there are packets coming. A would consume the received data as soon as possible during the period of time. A would not send a jam pattern to receive packets again when the RX FIFO is not nearly full. Brief features of the back pressure mode are as follows: 11.5. The software could configure the length of the jam. The MAC controller could send the jam according to the low / high threshold of RX FIFO. Programming Model

11.5.1. Summary of the MAC Controller Registers The table below lists the MAC controller registers. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 Table 11-10. MAC controller Register Summary Register Name Interrupt Status Register Interrupt Mask Register MAC Most Significant Address Register MAC Least Significant Address Register Multicast Address Hash Table 0 Register Multicast Address Hash Table 1 Register Transmit Poll Demand Register Receive Poll Demand Register Transmit Ring Base Address Register Receive Ring Base Address Register Interrupt Timer Control Register Automatic Polling Timer Control Register DMA Burst Length and Arbitration Control Register Revision Register Reset Value 0x0000_0010 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 -

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Technical Reference Manual Offset 0x38 0x34 ~ 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xB0 0xB4 0xB8 0xB8 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 Register Name Feature Register Reserved MAC Control Register MAC Status Register PHY Control Register PHY Write Data Register Flow Control Register Back Pressure Register Wake-on-LAN Control Register Wake-on-LAN Status Register Wake-up Frame CRC Register Wake-up Frame Byte Mask 1st Double Word Register Wake-up Frame Byte Mask 2st Double Word Register Wake-up Frame Byte Mask 3st Double Word Register Wake-up Frame Byte Mask 4st Double Word Register Test Seed Register DMA/FIFO State Register Test Mode Register Reserved TX_MCOL and TX_SCOL Counter Register RPF and AEP Counter Register XM and PG Counter Register RUNT_CNT and TLCC Counter Register CRCER_CNT and FTL_CNT Counter Register RLC and RCC Counter Register BROC Counter Register MULCA Counter Register RP Counter Register XP Counter Register Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_A400 0x0000_0400 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000

11.5.2. Register Descriptions The following abbreviations are used for register definitions: R/W: Read/Write RC: Read Clear RO: Read Only R/W1C: Read/Write 1 Clear 11.5.2.1. Bit 31-10 9 8 7 6
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Interrupt Status Register (Offset == 0x00) Table 11-11. Interrupt Status Register Type Default Value Name Description Reserved RC 0x0 PHYSTS_CHG PHY link status change RC 0x0 AHB_ERR AHB error RC 0x0 RPKT_LOST Received packet lost due to RX FIFO full RC 0x0 RPKT_SAV Packets received into RX FIFO successfully
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Technical Reference Manual 5 4 3 2 1 0 11.5.2.2. Bit 31-10 9 8 7 6 5 4 3 2 1 0 11.5.2.3. RC RC RC RC RC RC 0x0 0x0 0x0 0x0 0x0 0x0 XPKT_LOST XPKT_OK NOTXBUF XPKT_FINISH NORXBUF RPKT_FINISH Packets transmitted to Ethernet lost due to late collision or excessive collision Packets transmitted to Ethernet successfully Transmit buffer unavailable TXDMA has moved data into the TX FIFO Receive buffer unavailable RXDMA has received packets into RX buffer successfully

Interrupt Enable Register, IMR (Offset == 0x04 ~0x07h) Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 11-12. Interrupt Mask Register Default Value Name Description Reserved 0x0 PHYSTS_CHG_M Interrupt enable of ISR [9] 0x0 AHB_ERR_M Interrupt enable of ISR [8] 0x0 RPKT_LOST_M Interrupt enable of ISR [7] 0x0 RPKT_SAV_M Interrupt enable of ISR [6] 0x0 XPKT_LOST_M Interrupt enable of ISR [5] 0x0 XPKT_OK_M Interrupt enable of ISR [4] 0x0 NOTXBUF_M Interrupt enable of ISR [3] 0x0 XPKT_FINISH_M Interrupt enable of ISR [2] 0x0 NORXBUF_M Interrupt enable of ISR [1] 0x0 RPKT_FINISH_M Interrupt enable of ISR [0]

MAC Most Significant Address Register (Offset == 0x08) Table 11-13. MAC Most Significant Address Register Bit Type Default Value Name Description 31-16 Reserved 15-0 R/W 0x0000 MAC_MADR The most significant two bytes of MAC address 11.5.2.4. MAC Least Significant Address Register (Offset == 0x0C) Table 11-14. MAC Least Significant Address Register Bit Type Default Value Name Description 31-0 R/W 0x00000000 MAC_LADR The least significant 4 bytes of MAC address 11.5.2.5. Bit 31-0 11.5.2.6. Multicast Address Hash Table 0 Register (Offset == 0x10) Table 11-15. Multicast Address Hash Table 0 Register Type Default Value Name Description Multicast address hash table bytes 3 ~ 0 (Hash R/W 0x00000000 MAHT0 table 31:0)

Multicast Address Hash Table 1 Register (Offset == 0x14) Table 11-16. Multicast Address Hash Table 1 Register Bit Type Default Value Name Description Multicast address hash table bytes 3 ~ 0 (Hash 31-0 R/W 0x00000000 MAHT1 table 63:32) 11.5.2.7. Transmit Poll Demand Register (Offset == 0x18)
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Technical Reference Manual Table 11-17. Transmit Poll Demand Register. Default Value Name Description When writing any value to the register, the MAC controller would read transmit descriptor process 0x00000000 TXPD and check the txdma_own bit, if txdma_own = 1, then move transmit buffer data into the TX FIFO. The read value of the register is always 0.

Bit 31-0

Type WO

11.5.2.8. Bit

31-0

Receive Poll Demand Register (Offset == 0x1C~1Fh) Table 11-18. Receive Poll Demand Register Type Default Value Name Description When writing any value to the register, the MAC controller would read receive descriptor process and check the rxdma_own bit, if rxdma_own = 1, then move the receive packet data from the RX WO 0x00000000 RXPD FIFO into the receive buffer in the system memory. The read value of the register is always 0. Transmit Ring Base Address Register (Offset == 0x20~23h) Table 11-19. Transmit Ring Base Address Register Type Default Value Name Description Base address of the transmit ring. The base address must be 16-byte aligned. The MAC R/W 0x00000000 TXR_BADR controller would treat base address bits 3 ~ 0 as 0 when reading descriptors if bits 3 ~ 0 are not zero. Receive Ring Base Address Register (Offset == 0x24) Table 11-20. Receive Ring Base Address Register Type Default Value Name Description Base address of the receive ring. The base address must be 16-byte aligned. The MAC R/W 0x00000000 RXR_BADR controller would treat base address bits 3 ~ 0 as 0 when reading descriptors if bits 3 ~ 0 are not zero. Interrupt Timer Control Register (Offset == 0x28) Table 11-21. Interrupt Timer Control Register Type Default Value Name Description Reserved This field defines the period of TX cycle time. When set, TX cycle time is 100Mbps mode 81.92 s TXINT_TIME_ R/W 0x0 10Mbps mode 819.2 s SEL When cleared, TX cycle time is 100Mbps mode 5.12 s 10Mbps mode 51.2 s R/W 0x0 TXINT_THR This field defines the maximum number of
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11.5.2.9. Bit 31-0

11.5.2.10. Bit 31-0

11.5.2.11. Bit 31-16

15

14-12
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Technical Reference Manual Bit Type Default Value Name Description transmit interrupts that can be pending before an interrupt is generated. When TXINT_THR is not equal to 0, the MAC controller would issue a transmit interrupt when the transmit packet number transmitted by the MAC controller reaches TXINT_THR. When TXINT_THR = 0 and TXINT_CNT = 0, issuing a transmit interrupt or not depends on TXIC in TXDES1. This field defines the maximum wait time to issue transmit interrupt after a packet has been transmitted by the MAC controller. The time unit is 1 TX cycle time. When TXINT_CNT = 0, the function would be disabled. When TXINT_THR = 0 and TXINT_CNT = 0, issuing a transmit interrupt or not depends on TXIC in TXDES1. This field defines the period of RX cycle time. When set, RX cycle time is 100Mbps mode 81.92 s 10Mbps mode 819.2 s When cleared, RX cycle time is 100Mbps mode 5.12 s 10Mbps mode 51.2 s This field defines the maximum number of receive interrupts that can be pending before an interrupt is generated. When RXINT_THR is not equal to 0, the MAC controller would issue a receive interrupt when the receive packet number received by the MAC controller reaches RXINT_THR. If RXINT_THR = 0 and RXINT_CNT = 0, a receive interrupt will be issued when the MAC controller finishes receiving a receive packet. This field defines the maximum wait time to issue receive interrupt after a packet has been received by the MAC controller. The time unit is 1 RX cycle time. When RXINT_CNT = 0, the function would be disabled. If RXINT_THR = 0 and RXINT_CNT = 0, a receive interrupt will be issued when a packet is received by the MAC controller.

11-8

R/W

0x0

TXINT_CNT

R/W

0x0

RXINT_TIME_ SEL

6-4

R/W

0x0

RXINT_THR

3-0

R/W

0x0

RXINT_CNT

Recommended value = 32h0000_1010 The Interrupt Timer Control Register allows the software driver to reduce the number of transmit interrupt (ISR[4]) and receive interrupt (ISR[0]) by setting the register. This could lower CPU utilization for handling a large number of interrupts.
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Technical Reference Manual The register defines 2 threshold values for the receive packet number and transmit packet number, and two associated timers. The threshold value defines the maximum number of receive or transmit interrupts that can be pending before an interrupt is generated. The timer defines the maximum wait time to issue transmit / receive interrupt after a packet has been transmitted / received by the MAC controller. The threshold value and timer combination allows for the batching of several packets into a single interrupt with a limit for how long it can be pending. This can prevent throughput from being impeded in heavy traffic, while the time limit prevents resources from being held for too long in low traffic. The mitigation mechanism is similar for both receive and transmit interrupts. There is a counter (TXPKT_CNT) inside the MAC controller to count the packets transmitted by the MAC controller. When the counter reaches TXINT_THR and TXINT_THR is not equal to 0, the MAC controller would issue transmit interrupt. There is also a counter (RXPKT_CNT) in the MAC controller to count the packets received by the MAC controller. When the counter reaches RXINT_THR and RXINT_THR is not equal to 0, the MAC controller would issue receive interrupt. TXPKT_CNT is cleared when transmit interrupt is issued. RXPKT_CNT is cleared when receive interrupt is issued. The following is the condition for the MAC controller to issue a transmit interrupt. Table 11-22. Transmit Interrupt TXINT_THR = 0 TXINT_CNT = 0 MAC Controller Action 1. Issues transmit interrupt after packet is transmitted and TXIC of True True the packet is set. 2. Clears TXPKT_CNT. 1. Issues transmit interrupt after a packet is transmitted and timer True False reaches the value of TXINT_CNT. 2. Clears TXPKT_CNT. 1. Issues transmit interrupt if TXPKT_CNT = TXINT_THR. False True 2. Clears TXPKT_CNT. 1. Issues transmit interrupt if the following condition holds: TXPKT_CNT = TXINT_THR False False TXPKT_CNT = 1 and timer reaches the value of TXINT_CNT 2. Clears TXPKT_CNT. The following is the condition for the MAC controller to issue a receive interrupt. Table 11-23. Receive Interrupt RXINT_THR = 0 RXINT_CNT = 0 MAC Controller Action 1. Issues receive interrupt after packet is received by the MAC True True controller. 2. Clears RXPKT_CNT. 1. Issues receive interrupt after packet is received by the MAC True False controller and timer reaches the value of RXINT_CNT. 2. Clears RXPKT_CNT.

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Technical Reference Manual RXINT_THR = 0 RXINT_CNT = 0 False True MAC Controller Action 1. Issues receive interrupt if RXPKT_CNT = RXINT_THR. 2. Clears TXPKT_CNT. 1. Issues receive interrupt if the following condition holds: RXPKT_CNT = RXINT_THR RXPKT_CNT = 1 and timer reaches the value of RXINT_CNT 2. Clears RXPKT_CNT.

False

False

11.5.2.12.

Automatic Polling Timer Control Register (Offset == 0x2C)

The Automatic Polling Timer Control Register allows the MAC controller to automatically poll the descriptors. This could lower CPU utilization. When transmit automatic poll function is enabled, the MAC controller would automatically poll the transmit descriptor when transmit automatic poll timer expires. If the function is disabled, software needs to write Transmit Poll Demand Register (Offset: 18h ~ 1Bh) to trigger the MAC controller to read transmit descriptors after software prepared the transmit packets in transmit buffers. When receive automatic poll function is enabled, the MAC controller would automatically poll the receive descriptor when receive automatic poll timer expires. If the function is disabled, software needs to write Receive Poll Demand Register (Offset: 1Ch ~ 1Fh) to trigger the MAC controller to read receive descriptors after software released the receive descriptors to the MAC controller Bit 31-13 Type -Table 11-24. Automatic Polling Timer Control Register Default Value Name Description --Reserved This field defines the period of TX poll time. When set, TX poll time is 100Mbps mode 81.92 s 1h0 TXPOLL_TIME_SEL 10Mbps mode 819.2 s When cleared, TX poll time is 100Mbps mode 5.12 s 10Mbps mode 51.2 s This field defines the period of transmit automatic polling time. The unit is 1 TX poll time. When TXPOLL_CNT is not equal to 0, 4h0 TXPOLL_CNT the MAC controller would poll the transmit descriptor automatically. If TXPOLL_CNT = 0, the MAC controller would not poll the transmit descriptor automatically. --Reserved This field defines the period of RX poll time. When set, RX poll time is 100Mbps mode 81.92 s 1h0 RXPOLL_TIME_SEL 10Mbps mode 819.2 s When cleared, RX poll time is 100Mbps mode 5.12 s 10Mbps mode 51.2 s
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12

R/W

11-8

R/W

7-5

--

R/W

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Technical Reference Manual Bit Type Default Value Name Description This field defines the period of receive automatic polling time. The unit is 1 RX poll time. When RXPOLL_CNT is not equal to 0, the MAC controller would poll the receive descriptor automatically. If RXPOLL_CNT = 0, the MAC controller would not poll the receive descriptor automatically.

3-0

R/W

4h0

RXPOLL_CNT

Recommended value = 32h0000_0001 11.5.2.13. DMA Burst Length and Arbitration Control Register (Offset == 0x30) Table 11-25. DMA Burst Length and Arbitration Control Register Bit Type Default Value Name Description 31:16 Reserved This field defines the maximum data byte count of a burst when MAC issues an INCR burst command in the AHB bus. 2b0x: No limitation 2b10: The maximum data byte count is 32x4 bytes. 2b11: The maximum data byte count is 64x4 bytes. Reserved Enable RX FIFO threshold arbitration.

15:14

R/W

0x0

INCR_SEL

13:10 9

R/W

0x0

RX_THR_EN

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Technical Reference Manual Bit Type Default Value Name Description The RX FIFO high threshold value for arbitration. When the used space in the RX FIFO is larger than or equal to the RX FIFO high threshold value, the RXDMA has higher priority than the TXDMA when using the DMA channel. The RXDMA keeps the higher priority until the used space in the RX FIFO is less than or equal to the RX FIFO low threshold value. Then the TXDMA gets higher priority than the RXDMA. So software must set RXFIFO_HTHR larger than RXFIFO_LTHR to keep the MAC controller work correctly. The unit is 256 bytes. 3d0: Threshold = 0 3d1: Threshold = 1/8 space of RX FIFO, 256 bytes 3d2: Threshold = 2/8 space of RX FIFO, 512 bytes 3d3: Threshold = 3/8 space of RX FIFO, 768 bytes 3d4: Threshold = 4/8 space of RX FIFO, 1024 bytes 3d5: Threshold = 5/8 space of RX FIFO, 1280 bytes 3d6: Threshold = 6/8 space of RX FIFO, 1536 bytes 3d7: Threshold = 7/8 space of RX FIFO, 1792 bytes

8-6

R/W

3h0

RXFIFO_HTHR

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Technical Reference Manual Bit Type Default Value Name Description The RX FIFO low threshold value for arbitration. When the used space in the RX FIFO is less than or equal to the RX FIFO low threshold value, the TXDMA has higher priority than the RXDMA when using the DMA channel. The unit is 256 bytes. 3d0: Threshold = 0 3d1: Threshold = 1/8 space of RX FIFO, 256 bytes 3d2: Threshold = 2/8 space of RX FIFO, 512 bytes 3d3: Threshold = 3/8 space of RX FIFO, 768 bytes 3d4: Threshold = 4/8 space of RX FIFO, 1024 bytes 3d5: Threshold = 5/8 space of RX FIFO, 1280 bytes 3d6: Threshold = 6/8 space of RX FIFO, 1536 bytes 3d7: Threshold = 7/8 space of RX FIFO, 1792 bytes This field defines if the MAC controller could use INCR16 burst command in AHB bus. This field defines if the MAC controller could use INCR8 burst command in AHB bus. This field defines if the MAC controller could use INCR4 burst command in AHB bus.

5:3

R/W

0x0

RXFIFO_LTHR

2 1 0

R/W R/W R/W

0x0 0x0 0x0

INCR16_EN INCR8_EN INCR4_EN

Recommended value = 32h0000_0390 There are some limitations for use of INCR4, INCR8, and INCR16. The user must observe these limitations, as follows: AHB Bus Clock Range 25MHz (25MHz not included) ~ 15MHz 50MHz (50MHz not included) ~ 25MHz Limitation on AHB Bus Side of SDRAM Controller hready must assert low at least 1 AHB bus clock during every 3 data phases.

hready must assert low at least 1 AHB bus clock during every 7 data phases. hready must assert low at least 1 AHB bus clock during every 75MHz (75MHz not included) ~ 50MHz 15 data phases. hready must assert low at least 1 AHB bus clock during every 100MHz (100MHz not included) ~ 75MHz 21 data phases. hready must assert low at least 1 AHB bus clock during every 125MHz (125MHz not included) ~ 100MHz 31 data phases. hready must assert low at least 1 AHB bus clock during every 133MHz ~ 125MHz 39 data phases.
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Technical Reference Manual Because the MAC controller always uses WORD as the transfer size on AHB bus, the above limitation on the data phases applies only to WORD-size transfer. If the system cannot meet the limitation, INCR4 / INCR8 / INCR16 will not be enabled when using the MAC controller. In that case, the MAC controller can only use INCR to transfer data in such system. The user must ensure that the above limitation is met in the system before enabling INCR4 / INCR8 / INCR16 when using the MAC controller. 11.5.2.14. Bit 31:24 23:16 15:8 7:0 Revision Register, REVR (Offset = 0x34) Table 11-26. Revision Register Type Default Value Name Description Reserved RO REV_B1 The 1st digit of reversion tag. Example: If the revision tag is version_1_2_r3, then the field is 1. RO REV_B2 The 2nd digit of reversion tag. Example: If the revision tag is version_1_2_r3, then the field is 2 RO REV_B3 The 3rd digit of reversion tag. Example: If the revision tag is version_1_2_r3, then the field is 3. Feature Register, FEAR (Offset = 0x38) Table 11-27. Feature Register Type Default Value Name Description RO Reserved RO Half Supports the half-duplex feature RO FULLF Supports the full-duplex feature RO WOLF Supports Wake-on-LAN feature MAC Control Register (Offset == 0x88) Table 11-28. MAC Control Register Type Default Value Name Description ---Reserved Speed mode R/W 0x0 SPEED_100 0 10mbps 1 100 mbps R/W 0x0 RX_BROADPKT Receive broadcast packet. R/W 0x0 RX_MULTIPKT Receive all multicast packets. R/W 0x0 FULLDUP Full duplex R/W 0x0 CRC_APD Append CRC to transmitted packet. -0x0 -Reserved R/W 0x0 RCV_ALL Not check incoming packets destination address 0x0 Store incoming packet even if its length is great R/W RX_FTL than 1518 bytes. 0x0 Store incoming packet even if its length is less R/W RX_RUNT than 64 bytes. 0x0 Enable storing incoming packet if the packet R/W HT_MULTI_EN passes hash table address filtering and is a multicast packet.
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11.5.2.16. Bit 31-19 18 17 16 15 14 13 12 11 10 9

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Technical Reference Manual Bit 8 7 6 5 4 3 2 1 0 Type R/W -R/W R/W R/W R/W R/W 0x0 R/W 0x0 R/W XDMA_EN RDMA_EN Default Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Name RCV_EN -ENRX_IN_ HALFTX XMT_EN CRC_DIS LOOP_EN SW_RST Description Receiver enable Reserved Enable packet reception when transmitting packet in half duplex mode. Transmitter enable Disable CRC check when receiving packets. Internal loop-back. Software reset. Writing 1 to this bit would enable software reset. Software reset would last 64 AHB bus clocks, and then activate auto-clear. Enable receive DMA channel. If this bit is zero, reception is stopped immediately. Enable transmit DMA channel. If this bit is zero, transmission is stopped immediately.

11.5.2.17. Bit 31-12 11 10 9 8 7 6 5 4 3 2 1 0

MAC Status Register (Offset == 0x8C) Table 11-29. MAC Status Register Type Default Value Name Description ---Reserved RC 0x0 COL_EXCEED Collision amount exceeds 16. RC 0x0 LATE_COL Transmitter detects late collision. 0x0 Packets transmitted to Ethernet lost due to late RC XPKT_LOST collision or excessive collision. RC 0x0 XPKT_OK Packets transmitted to Ethernet successfully. RC 0x0 RUNT Receiver detects a runt packet. RC 0x0 FTL Receiver detects a frame that is too long. 0x0 Incoming packets CRC check result is invalid, RC CRC_ERR unless the CRC_DIS bit is set. RC 0x0 RPKT_LOST Received packets lost due to RX FIFO full. RC 0x0 RPKT_SAVE Packets received into RX FIFO successfully. RC 0x0 COL Incoming packet dropped due to collision. RC 0x0 BROADCAST Incoming packet for broadcast address. RC 0x0 MULTICAST Incoming packet for multicast address.

11.5.2.18. Bit 31-28 27 26 25-21

PHY Control Register (Offset == 0x90) Table 11-30. PHY Control Register Type Default Value Name Description ---Reserved 0x0 Initialize a write sequence to PHY by setting this R/W MIIWR bit to 1. This bit would be auto cleared after the write operation is finished. 0x0 Initialize a read sequence to PHY by setting this bit R/W MIIRD to 1. This bit would be auto cleared after the read operation is finished. R/W 0x0 REGAD PHY register address
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Technical Reference Manual Bit 20-16 15-0 Type R/W RO Default Value Name 0x0 PHYAD 0x0 MIIRDATA Description PHY address Read data from PHY.

11.5.2.19. Bit 31-16 15-0

PHY Write Data Register (Offset == 0x94) Table 11-31. PHY Write Data Register Type Default Value Name Description ---Reserved R/W 0x0 MIIWDATA Write data to PHY.

11.5.2.20. Bit 31-16

15-12

11-8 7-5 4 3 2 1 0

Flow Control Register (Offset == 0x98) Table 11-32. Flow Control Register Type Default Value Name Description Pause time in pause frame. The unit is 512 bit times. The 512 bit times is R/W 0x0 PAUSE_TIME 100Mbps mode 5.12s 10Mbps mode 51.2s RX FIFO free space high threshold. Send a pause frame with pause time = 32h0000 R/W 0x0 FC_HIGH when RX FIFO free space is larger than the high threshold. The unit is 128 bytes. Default value is 4hA. RX FIFO free space low threshold. Send a pause frame with pause time set in bits 31 R/W 0x0 FC_LOW ~ 16 when RX FIFO free space is lower than the low threshold. The unit is 128 bytes. Default value is 4h4. ---Reserved RC 0x0 RX_PAUSE Receive pause frame. Packet transmission is paused due to receive RO 0x0 TXPAUSED pause frame. Enable flow control threshold mode. Enable R/W 0x0 FCTHR_EN transmit pause frame for high / low threshold. Transmit pause frame. Software can set this bit R/W 0x0 TX_PAUSE to send pause frame. Auto cleared after pause frame has been transmitted. R/W 0x0 FC_EN Flow control mode enable Back Pressure Register (Offset == 0x9C) Table 11-33. Back Pressure Register Type Default Value Name Description ---Reserved RX FIFO free space low threshold. MAC would generate the jam pattern when RX R/W 0x0 BK_LOW FIFO free space is lower than the low threshold while packets are incoming. The unit is 128 bytes. Default value is 4h4. Back pressure jam length. R/W 0x0 BKJAM_LEN 4h0: 4 bytes 4h6: 256 bytes
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7-4

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Technical Reference Manual Bit Type Default Value Name Description 4h1: 8 bytes 4h7: 512 bytes 4h2: 16 bytes 4h8: 1024 bytes 4h3: 32 bytes 4h9: 1518 bytes 4h4: 64 bytes 4hA: 2048 bytes 4h5: 128 bytes Other: 4 bytes Reserved Back pressure address mode. 1: Generate jam pattern when packet address matches. 0: Generate jam pattern when any packet is incoming. Back pressure mode enable

3-2 1 0

-R/W R/W

-0x0 0x0

-BK_MODE BK_EN

11.5.2.22. Bit 31-26 25-24 23-19 18

17-16

15-14

13-7 6 5 4 3 2 1 0

Wake-On-LAN Control Register, (Offset == 0xA0) Table 11-34. Wake-On-LAN Register Type Default Value Name Description ---Reserved WOL output signal type 2b00: Active high R/W 0x0 WOL_TYPE 2b01: Active low 2b10: Positive pulse 2b11: Negative pulse --Reserved R/W 0x0 SW_PDNPHY Software power down PHY Wake-up frame select. It is used to select the wake-up frame when the driver accesses wake-up frame CRC or wake-up frame byte mask register. 2b00: Select wake-up frame 1 R/W 0x0 WAKEUP_SEL 2b01: Select wake-up frame 2 2b10: Select wake-up frame 3 2b11: Select wake-up frame 4 Power state. This 2-bit field is used to determine the current power state. The definition of the field values is given below. R/W 0x0 POWER_STATE 2b00: D0 2b01: D1 2b10: D2 2b11: D3 ---Reserved R/W 0x0 WAKEUP4_EN Wake-up frame 4 event enable R/W 0x0 WAKEUP3_EN Wake-up frame 3 event enable R/W 0x0 WAKEUP2_EN Wake-up frame 2 event enable R/W 0x0 WAKEUP1_EN Wake-up frame 1 event enable R/W 0x0 MAGICPKT_EN Magic packet event enable R/W 0x0 LINKCHG1_EN Link change to 1 event enable R/W 0x0 LINKCHG0_EN Link change to 0 event enable

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Technical Reference Manual 11.5.2.23. Bit 31-7 6 5 4 3 2 1 0 Wake-On-LAN Status Register, (Offset == 0xA4) Table 11-35. Wake-On-LAN Status Register Type Default Value Name Description ---Reserved R/W 0x0 WAKEUP4_STS Wake-up frame 4 event status R/W 0x0 WAKEUP3_STS Wake-up frame 3 event status R/W 0x0 WAKEUP2_STS Wake-up frame 2 event status R/W 0x0 WAKEUP1_STS Wake-up frame 1 event status R/W 0x0 MAGICPKT_STS Magic packet event status R/W 0x0 LINKCHG1_STS Link change to 1 event status R/W 0x0 LINKCHG0_STS Link change to 0 event status Wake- Up Frame CRC Register, (Offset == 0xA8) Table 11-36. Wake-Up Frame CRC Register Type Default Value Name Description Wake-up frame CRC value. When WAKEUP_SEL = 2b00, the write value is to be stored in wake-up frame 1 CRC register. The read value is from wake-up frame 1 CRC register. When WAKEUP_SEL = 2b01, the write value is to be stored in wake-up frame 2 CRC register. The read value is from wake-up frame 2 CRC R/W 0x0 WFCRC register. When WAKEUP_SEL = 2b10, the write value is to be stored in wake-up frame 3 CRC register. The read value is from wake-up frame 3 CRC register. When WAKEUP_SEL = 2b11, the write value is to be stored in wake-up frame 4 CRC register. The read value is from wake-up frame 4 CRC register.

11.5.2.24. Bit

31-0

11.5.2.25. Bit

31-0

Wake-up Frame Byte Mask 1st Double Word Register, (Offset == 0xB0) Table 11-37. Wake-up Frame Byte Mask 1st Double Word Register Type Default Value Name Description Wake-up frame byte mask 1st double word. It stores the byte mask of the wake-up frame from byte 1 to byte 32. Bit 0 is byte 1 mask and Bit 31 is byte 32 mask. When WAKEUP_SEL = 2b00, the write value is R/W 0x0 WFBM1 to be stored in wake-up frame 1 byte mask 1st double word register. The read value is from wake-up frame 1 byte Mask 1st double word register. When WAKEUP_SEL = 2b01, the write value is to be stored in wake-up frame 2 byte mask 1st
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Technical Reference Manual Bit Type Default Value Name Description double word register. The read value is from byte mask 1st double Word register of wake-up frame 2. When WAKEUP_SEL = 2b10, the write value is to be stored in wake-up frame 3 byte mask 1st double word register. The read value is from byte mask 1st double word register of wake-up frame 3. When WAKEUP_SEL = 2b11, the write value is to be stored in wake-up frame 4 byte mask 1st double word register. The read value is from byte mask 1st double Word register of wake-up frame 4.

11.5.2.26. Bit

31-0

Wake-up Frame Byte Mask 2st Double Word Register, (Offset == 0xB4) Table 11-38. Wake-up Frame Byte Mask 1st Double Word Register Type Default Value Name Description Wake-up frame byte mask 2nd double word. It stores the byte mask of the wake-up frame from byte 33 to byte 64. Bit 0 is byte 33 mask and Bit 31 is byte 64 mask. When WAKEUP_SEL = 2b00, the write value is to be stored in wake-up frame 1 byte mask 2nd double word register. The read value is from byte mask 2nd double word register of wake-up frame 1. When WAKEUP_SEL = 2b01, the write value is to be stored in wake-up frame 2 byte mask 2nd double word register. The read value is from byte R/W 0x0 WFBM2 mask 2nd double word register of wake-up frame 2. When WAKEUP_SEL = 2b10, the write value is to be stored in wake-up frame 3 byte mask 2nd double word register. The read value is from byte mask 2nd double word register of wake-up frame 3. When WAKEUP_SEL = 2b11, the write value is to be stored in wake-up frame 4 byte mask 2nd double word register. The read value is from byte mask 2nd double word register of wake-up frame 4. Wake-up Frame Byte Mask 3st Double Word Register, (Offset == 0xB8) Table 11-39. Wake-up Frame Byte Mask 1st Double Word Register Type Default Value Name Description Wake-up frame byte mask 3rd double word. It R/W 0x0 WFBM3 stores the byte mask of the wake-up frame from

11.5.2.27. Bit 31-0

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Technical Reference Manual Bit Type Default Value Name Description byte 65 to byte 96. Bit 0 is byte 65 mask and Bit 31 is byte 96 mask. When WAKEUP_SEL = 2b00, the write value is to be stored in wake-up frame 1 byte mask 3rd double word register. The read value is from byte mask 3rd double word register of wake-up frame 1. When WAKEUP_SEL = 2b01, the write value is to be stored in wake-up frame 2 byte mask 3rd double word register. The read value is from byte mask 3rd double word register of wake-up frame 2. When WAKEUP_SEL = 2b10, the write value is to be stored in wake-up frame 3 byte mask 3rd double word register. The read value is from byte mask 3rd double word register of wake-up frame 3. When WAKEUP_SEL = 2b11, the write value is to be stored in wake-up frame 4 byte mask 3rd double word register. The read value is from byte mask 3rd double word register of wake-up frame 4.

11.5.2.28. Bit

31-0

Wake-up Frame Byte Mask 4st Double Word Register, (Offset == 0xBC) Table 11-40. Wake-up Frame Byte Mask 4st Double Word Register Type Default Value Name Description Wake-up frame byte mask 4th double word. It stores the byte mask of the wake-up frame from byte 97 to byte 128. Bit 0 is byte 97 mask and Bit 31 is byte 128 mask. When WAKEUP_SEL = 2b00, the write value is to be stored in wake-up frame 1 byte mask 4th double word register. The read value is from byte mask 4th double word register of wake-up frame 1. When WAKEUP_SEL = 2b01, the write value is to be stored in wake-up frame 2 byte mask 4th R/W 0x0 WFBM4 double word register. The read value is from byte mask 4th double word register of wake-up frame 2. When WAKEUP_SEL = 2b10, the write value is to be stored in wake-up frame 3 byte mask 4th double word register. The read value is from byte mask 4th double word register of wake-up frame 3. When WAKEUP_SEL = 2b11, the write value is to be stored in wake-up frame 4 byte mask 4th double word register. The read value is from byte mask 4th double word register of wake-up frame 4. Test Seed Register (Offset == 0xC4)
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Technical Reference Manual Table 11-41. Test Seed Register Default Value Name Description --Reserved 0x0 Test_seed Test seed

Bit 31-14 13-0

Type -R/W

11.5.2.30. Bit 31 30 29 28 27 26 25-15 14-12 11-8 7 6-4 3-0

DMA/FIFO State Register (Offset == 0xC8) Table 11-42. DMA/FIFO State Register Type Default Value Name Description RO 0x0 TXD_REQ TXDMA request RO 0x0 RXD_REQ RXDMA request RO 0x0 DARB_TXGNT TXDMA grant RO 0x0 DARB_RXGNT RXDMA grant RO 0x1 TXFIFO_EMPTY TX FIFO is empty RO 0x1 RXFIFO_EMPTY RX FIFO is empty ---Reserved RO 0x0 TXDMA2_SM TXDMA 2 state machine RO 0x0 TXDMA1_SM TXDMA 1 state machine ---Reserved RO 0x0 RXDMA2_SM RXDMA 2 state machine RO 0x0 RXDMA1_SM RXDMA 1 state machine Test Mode Register (Offset == 0xCC) Table 11-43. Test Mode Register Type Default Value Name Description ---Reserved Single packet mode. The TXDMA would only R/W 0x0 SINGLE_PKT move a packet into the TX FIFO at one time. R/W 0x0 PTIMER_TEST Automatic polling timer test mode R/W 0x0 ITIMER_TEST Interrupt timer test mode ---Reserved Test seed select. When set, the least significant TEST_SEED_SE 14 bits of MAC_LADR (0Ch ~ 0Fh) are used as the R/W 0x0 L seed. When cleared, Test_seed in TS register (C4h ~ C7h) is used as the seed. Seed select. When set, internal counter is used as R/W 0x0 SEED_SEL the seed. When cleared, external data are used as the seed. R/W 0x0 TEST_MODE Transmission test mode R/W 0x0 TEST_TIME Transmission back off time test R/W 0x0 TEST_EXCEL Excessive collision test for transmission ---Reserved TX_MCOL and TX_SCOL Counter Register (Offset == 0xD4) Table 11-44. TX_MCOL and TX_SCOL Counter Register Default Value Name 0x0 TX_MCOL Description Counter for counting packets transmitted OK with 2 ~ 15 collisions

11.5.2.31. Bit 31-27 26 25 24 23 22

21 20 19-10 9-5 4-0

11.5.2.32. Bit 31-16 Type RO

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Technical Reference Manual Counter for counting packets transmitted OK with single collision. 11.5.2.33. RPF and AEP Counter Register (Offset == 0xD8) Table 11-45. RPF and AEP Counter Register Bit Type Default Value Name Description 31-16 RO 0x0 RPF Receive pause frame counter. Counter for counting packets with alignment error. 15-0 RO 0x0 AEP The counter is to count packets with CRC error and no-octet-boundary discarded by the MAC controller. 15-0 RO 0x0 TX_SCOL 11.5.2.34. Bit 31-16 15-0 Type RO RO XM and PG Counter Register (Offset == 0xDC) Table 11-46. XM and PG Counter Register Default Value Name 0x0 0x0 XM PG Description Counter for counting packets failed in transmission (due to late collision or collision count >=16) Counter for counting packets failed in transmission (due to collision count >=16)

11.5.2.35. Bit 31-16 15-0 Type RO RO

RUNT_CNT and TLCC Counter Register (Offset == 0xE0) Table 11-47. RUNT_CNT and TLCC Counter Register Default Value Name 16h0 RUNT_CNT 16h0 TLCC Description Counter for counting received runt packets. Late collision counter.

11.5.2.36. Bit 31-16 15-0 Type RO RO

CRCER_CNT and FTL_CNT Counter Register (Offset == 0xE4) Table 11-48. CRCER_CNT and FTL_CNT Counter Register Default Value Name 0x0 0x0 CRCER_CNT FTL_CNT Description CRC error packet counter. The counter counts the number of octet-boundary frames discarded because of a CRC error. Counter for counting received FTL (packet length >1518 bytes) packets.

11.5.2.37. Bit 31-16 15-0 Type RO RO

RLC and RCC Counter Register (Offset == 0xE8) Table 11-49. RLC and RCC Counter Register Default Value Name 0x0 0x0 RLC RCC Description Counter for counting loss of received packets (due to RX FIFO full) Receive collision counter

11.5.2.38. Bit 31-0 Type RO

BROC Counter Register (Offset == 0xEC) Table 11-50. BROC Counter Register. Default Value Name BROC Description Counter for counting received broadcast packets

11.5.2.39.
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Technical Reference Manual Table 11-51. MULCA Counter Register Bit 31-0 Type RO Default Value Name MULCA Description Counter for counting received multicast packets

11.5.2.40. Bit 31-0 Type RO

RP Counter Register (Offset == 0xF4) Table 11-52. RP Counter Register. Default Value Name RP Description Counter for counting packets received successfully

11.5.2.41. Bit 31-0 Type RO

XP Counter Register (Offset == 0xF8) Table 11-53. XP Counter Register Default Value Name XP Description Counter for counting packets transmitted successfully

11.5.3. Phy Register Description Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 13h Reset value 1: Set to logic 1 0: Set to logic 0 X: No pre-set value Pin#: Value latched from pin # at reset time Access type RO: Read only RW: Read or write OB: Output to PIN_IO[8:0] bus OR: Output to MII of register 18h Attribute SC: Self-clearing
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Register Name BMCR BMSR PHYIDR1 PHYIDR2 ANAR ANLPAR ANER Reserved Reserved

Reset Value Basic mode control register, basic register Basic mode status register, basic register PHY identifier register 1, extended register PHY identifier register 2, extended register Auto-negotiation advertisement register, extended register Auto-negotiation link partner ability register, extended register Auto-negotiation expansion register, extended register Reserved and currently not supported IEEE 802.3u reserved

Technical Reference Manual PS: Value is permanently set LL: Latch to level low LH: Latch to level high 11.5.3.1. Basic Mode Control Register (Offset 00h) All of the following registers are already set to their optimal values, so please do not change the value of these registers unless you are sure of the results. Bit 15 14 13 12 11 10 9 8 7 6:0 Table 11-54 Basic Mode Control Register (BMCR) Default Value Name Description Reset 0, RW/SC Reset Loopback 0, RW Loopback Speed selection 1, RW Speed select Auto-negotiation enable 1, RW Auto negotiation enable Power down 0, RW Power down Isolate (PHYAD = 00000) Isolate RW 1 Isolate 0 Normal operation Restart auto negotiation 0, RW/SC Restart auto negotiation 1 = Restart auto negotiation 0 = Normal operation Duplex mode 1, RW Duplex mode 1 = Full duplex operation 0 = Normal operation Collision test 0, RW Collision test 1 = Collision test enabled 0 = Normal operation Reserved X, RO Reserved Write as 0, read as dont care Basic Mode Status Register (Offset 01h) Table 11-55 Basic Mode Status Register (BMSR) Default Value Name Description 100BASE-T4 0, RO/PS 100BASE-T4 capable 0 = Not perform in the 100BASE-T4 mode. 1 = Perform in the 100BASE-T4 mode. 100BASE-TX full duplex 1, RO/PS 100BASE-TX full-duplex capable 0 = This IP is not able to perform in the 100BASE-TX full-duplex mode. 1 = This IP is able to perform in the 100BASE-TX full-duplex mode. 100BASE-TX half 1, RO/PS 100BASE-TX half-duplex capable duplex 0 = This IP is not able to perform in the 100BASE-TX half-duplex mode. 1 = This IP is able to perform in the 100BASE-TX half-duplex mode 10BASE-T full duplex 1, RO/PS 10BASE-T full-duplex capable
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13

12
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Technical Reference Manual Bit Default Value Name Description 0 = This IP is not able to perform in the 10BASE-T full-duplex mode. 1 = This IP is able to perform in the 10BASET full-duplex mode 10BASE-T half-duplex capable 0 = This IP is able to perform in the 10BASET half-duplex mode. 1 = This IP is able to perform in the 10BASET half-duplex mode Reserved Write as a 0, read as dont care Management frame preamble suppression 0 = This IP will not accept management frames with preamble suppressed. 1 = This IP will accept management frames with preamble suppressed. Auto-negotiation complete 0 = Auto negotiation process is not complete. 1 = Auto negotiation process is complete. Remote fault 0 = No remote fault condition detected 1 = Remote fault condition detected (Cleared on read or by a chip reset) Auto configuration ability 0 = This IP is not able to perform autonegotiation. 1 = This IP is able to perform autonegotiation. Link status 0 = Link is not established. 1 = Valid link is established (100 Mbps or 10 Mbps operation). Jabber detect 0 = No Jabber condition is detected. 1 = Jabber condition is detected. Extended capability 0 = Basic register capable only 1 = Extended register capable

11

10BASE-T half duplex

1, RO/PS

10:7 6

Reserved MF preamble suppression

0, RO 0, RO/PS

Auto negotiation complete Remote fault

0, RO

0, RO/LH

Auto negotiation ability 1, RO/PS

Link status

0, RO/LL

1 0

Jabber detect Extended capability

0, RO/LH 1, RO/PS

11.5.3.3. Bit 15:0

PHY Identifier Register 1 (Offset 02H) Table 11-56 PHY Identifier Register 1 Default Value Name Description OUI_MSB Customer-defined, RO/PS This register stores bits 3 to 18 of the OUI to bits 15 to 0 of this register respectively. The most significant two bits of the OUI are

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Technical Reference Manual Bit Default Value Name Description ignored. This register is programmable by setting PHYIDRG2[15:0] and PHYIDRG3[15:0]. Please refer to Section 3.1 for more detail.

11.5.3.4. Bit 15:10

9:4

3:0

PHY Identifier Register 2 (Offset 03h) Table 11-57 PHY Identifier Register 2 Default Value Name Description OUI_LSB Customer-defined, Least significant bits of OUI RO/PS Bits 19 to 24 of the OUI are mapped to bits 15 to 10 of this register respectively. This register is programmable by setting PHYIDRG2[15:0] and PHYIDRG3[15:0]. VNDR_MDL Customer-defined, Vendor model number RO/PS The 6 bits of Faraday model number are mapped to bits 9 to 4 (Most significant bit to bit 9). This register is programmable by setting PHYIDRG2[15:0] and PHYIDRG3[15:0]. MDL_REV Customer-defined, Model revision number RO/PS The 4 bits of Faraday revision number are mapped to bits 3 to 0 (most significant bit to bit 3). This field will be increased for all major PHY device changes. This register is programmable by setting PHYIDRG2[15:0] and PHYIDRG3[15:0]. Auto-Negotiation Advertisement Register (Offset 04h) Table 11-58 Auto-Negotiation Advertisement Register (ANAR) Default Value Name Description NP 0, RO/PS Next page indication 0 = No next page available 1 = Next page available The PHY does not support the next page function. ACK 0, RO Acknowledge 0 = Not acknowledged 1 = Link partner ability data reception acknowledged RF 0, RW Remote fault (Not supported) 0 = No fault detected 1 = Fault condition detected and advertised Reserved X, RW Reserved Write as a 0, read as dont care Pause 0, RW Pause 0 = Pause operation is not enabled. 1 = Pause operation is enabled for the full290 5/5/2010 Version 2.1

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14

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Technical Reference Manual Bit 9 8 Default Value T4 TX_FD Name 0, RO/PS 1, RW Description duplex links. 100 BASE-T4 support 0 = 100BASE-T4 is not supported. 1 = 100BASE-T4 is supported. 100BASE-TX full-duplex support 0 = 100BASE-TX full-duplex is not supported by this device. 1 = 100BASE-TX full-duplex is supported by this device. 100BASE-TX half-duplex support 0 = 100BASE-TX half-duplex is not supported by this device. 1 = 100BASE-TX half-duplex is supported by this device 10BASE-T full-duplex support 0 = 10BASE-T full-duplex is not supported by this PHY. 1 = 10BASE-T full-duplex is supported by this PHY. 10BASE-T half-duplex support 0 = 10BASE-T half-duplex is not supported by this PHY. 1 = 10BASE-T half-duplex is supported by this PHY. RW Protocol selection bits These bits contain the binary encoded protocol selector supported by this PHY. [0 0001] indicates that this PHY supports IEEE 802.3 CSMA/CD.

TX_HD

1, RW

10_FD

1, RW

10_HD

1, RW

4:0

Selector

[0 0001],

11.5.3.6. Auto Negotiation Link Partner Ability Register (Offset 05h) Table 11-59. Definitions for Auto-Negotiation Link Partner Ability Register (ANLPAR) Bit Default Value Name Description 15 NP 0, RO Next page indication 0 = Link partner is not next page enable. 1 = Link partner is next page enable. 14 ACK 0, RO Acknowledge 0 = Not acknowledged 1 = Link partner reception of data word acknowledged 13 RF 0, RO Remote fault 0 = No remote fault indicated by the link partner 1 = Remote fault indicated by the link partner 12:11 Reserved X, RO Reserved Write as a 0, read as dont care

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Technical Reference Manual Bit 10 Default Value Pause Name 0, RO Description Pause 0 = Pause operation is not supported by the link partner. 1 = Pause operation is supported by the link partner. 100BASE-T4 support 0 = 100BASE-T4 is not supported by the link partner. 1 = 100BASE-T4 is supported by the link partner. 100BASE-TX full-duplex support 0 = 100BASE-TX full-duplex is not supported by the link partner. 1 = 100BASE-TX full-duplex is supported by the link partner. 100BASE-TX half-duplex support 0 = 100BASE-TX half-duplex is not supported by the link partner. 1 = 100BASE-TX half-duplex is supported by the link partner. 10BASE-T full-duplex support 0 = 10BASE-T full-duplex is not supported by the link partner. 1 = 10BASE-T full-duplex is supported by the link partner. 10 BASE-T half-duplex support 0 = 10BASE-T half-duplex is not supported by the link partner. 1 = 10BASE-T half-duplex is supported by the link partner. Protocol selection bits Link the binary encoded protocol selector of the partner

T4

0, RO

TX_FD

0, RO

TX_HD

0, RO

10_FD

0, RO

10_HD

0, RO

4:0

Selector

[0 0000], RO

11.5.3.7. Bit 15:5 4

3 2

Auto-Negotiation Expansion Register (Offset 06h) Table 11-60 Auto-Negotiation Expansion Register (ANER) Default Value Name Description Reserved 0, RO Reserved Write as a 0, read as dont care PDF 0, RO/LH Parallel detection fault 0 = No fault detected 1 = Fault detected via the parallel detection function LP_NP_AB 0, RO Link partner next page enable 0 = Link partner is not next page enable. 1 = Link partner is next page enable. NP_AB 0, RO/PS PHY next page enable

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Technical Reference Manual Bit 1 0 Default Value Page_RX LP_AN_AB Name 0, RO/LH 0, RO Description 0 = PHY is not next page enable. 1 = PHY is next page enable. New page received 0 = New page is not received. 1 = New page is received. Link partner auto-negotiation enable 0 = Link partner auto-negotiation is not supported. 1 = Link partner auto-negotiation is supported.

11.6.

Programming Guide

11.6.1. PHY Configuration The following procedure is required for speed selection. Get PHY speed information by manipulating PHY control register (PHYCR, offset: 90h ~ 93h). Set speed mode of MAC (SPEED_100; MACCR[18], offset: 88 ~ 8Bh) 11.6.2. Frame Transmitting Procedure The frame transmitting procedure is as follows: Initialization 1. 2. 3. 4. 5. 6. 7. 8. 9. Allocate system memory for the transmit descriptor ring and transmit buffer. Initialize the transmit descriptor ring. Set Transmit Ring Base Address Register (offset: 20h) to the base address of the transmit descriptor ring in the system memory. Set Interrupt Mask Register (offset: 04h). Set MAC Address Register (offset: 08h). Set Multicast Address Hash Table Register (offset: 10h). Set Interrupt Timer Control Register (offset: 28h) to select the manner of the transmit interrupt. Set Automatic Polling Timer Control Register (offset: 2Ch) to select the manner of transmit poll. Set MAC Control Register (offset: 88h) to set valid configuration for the MAC controller and enable transmit channel. Transmit procedures 1. 2. 3. 4. The software checks if the remainder of the transmit descriptors is enough for the next packet transmission. If not enough, the software needs to wait until the transmit descriptors are enough. Prepare the transmit packet data to the transmit buffer. Set the transmit descriptor. Write Transmit Poll Demand Register (offset: 18h) to trigger the MAC controller to poll the transmit

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Technical Reference Manual descriptor if necessary. 5. Wait for interrupt. When interrupt occurs, the software checks if it is a transmit interrupt. If ISR [4] = 1, it means the packet has been transmitted to network successfully. If ISR [5] = 1, it means the packet has been aborted during transmission due to late collision or excessive collision. Note: When setting the transmit descriptor, TXDES0 must be set last. Thus, the setting procedure should be either of the following two: Procedure A 1. 2. 3. 1. 2. 3. Set TXDES2 Set TXDES1 Set TXDES0 Set TXDES1 Set TXDES2 Set TXDES0

Procedure B

When preparing a transmit packet which contains more than one transmit descriptors, the first transmit descriptor must be the last set descriptor of the transmit packet. 11.6.3. Frame Receiving Procedure The receiving frame procedure is as follow: Initialization: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Allocate system memory for the receive descriptor ring and receive buffer. Initialize the receive descriptor ring. Set Receive Ring Base Address Register (offset: 24h) to the base address of the receive descriptor ring in the system memory. Set Interrupt Mask Register (offset: 04h). Set MAC Address Register (offset: 08h). Set Multicast Address Hash Table Register (offset: 10h). Set Interrupt Timer Control Register (offset: 28h) to select the manner of the receive interrupt. Set Automatic Polling Timer Control Register (offset: 2Ch) to select the manner of receive poll. Set MAC Control Register (offset: 88h) to set valid configuration for the MAC controller and enable receive channel. Write Receive Poll Demand Register (offset: 1Ch) to trigger the MAC controller to poll the receive

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Technical Reference Manual descriptor. Receive procedures 1. 2. Wait for interrupt. When interrupt occurs, the software checks if it is a receive interrupt. If ISR [0] = 1, it means the packet has been moved to the receive buffer successfully. Then software needs to fetch the receive descriptor to get the received packet until the owner bit of the next receive descriptor does not belong to the software. 3. 4. The software needs to release the receive descriptors to the MAC controller after accessing the received packet. If receive automatic poll function is disabled, software needs to write Receive Poll Demand Register (offset: 1Ch) to trigger the MAC controller to poll the receive descriptor. 11.6.4. Procedures to enter and exit the power down mode Procedures to enter the power down mode 1. 2. 3. 4. 5. 6. 7. Set XDMA_EN (88h.0) = 0. Poll DMA/FIFO State Register (C8h) to wait for TX FIFO empty. Set XMT_EN (88h.5) = 0 to stop transmission. Set RCV_EN (88h.8) = 0. Poll DMA/FIFO State Register (C8h) to wait for RX FIFO empty. Set RDMA_EN (88h.0) = 0 to stop reception. Program Wake-up Frame CRC Register (A8h), Wake-up Frame Byte Mask 1st Double Word Register (B0h), Wake-up Frame Byte Mask 2nd Double Word Register (B4h), Wake-up Frame Byte Mask 3rd Double Word Register (B8h), and Wake-up Frame Byte Mask 4th Double Word Register (BCh), if software wants to support wake-up frame event in power saving mode. 8. 9. 10. 1. 2. 3. 4. Write 32hFFFF_FFFF to clear Wake-On-LAN Status Register (A4h). Program the requested wake-up events and power state into Wake-On-LAN Register (A0h) to let MAC100 go into the power saving mode. Set RCV_EN (88h.8) = 1 to enable reception. Wait for occurrence of wake-up events. Set RCV_EN (88h.8) = 0 to stop reception. Read Wake-On-LAN Status Register (A4h) to check which wake-up event happened. Program Wake-On-LAN Register (A0h) to let MAC100 exit the power saving mode. Procedures to exit the power down mode

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Technical Reference Manual 5. 6. 7. 11.7. Set SW_RST (88h.2) = 1 to reset MAC100. Check SW_RST (88h.2) = 0 to make sure that MAC100 has finished reset. Re-initialize MAC100 to transmit and receive packets.

Application

The below figure illustrates the basic schematics for the Ethernet port. The aJ-200 ethernet PHY has been tested with the following 10/10 transformers: YCL PH163539 (www.ycl.tw.com) Bothhand (http://www.bothhand.com.tw) TS6121 (no support for auto mdix, and require to wire jump) Bothhand LU1S041xLF connector module (RJ45+transformer)

Other 10/100 transformers can be used with aJ-200 PHY if the transformers can meet the following conditions. Turn ratio 1:1 Symmetrical TX and RX channels for auto mdi/mdix capability.

Figure 11-8. 10/10 Ethernet Port Schematics The following are some recommendations for better performance. 1. The differential signals on both TXOP&TXON and RXIP&RXIN should be equal in length if possible. 2. The differential signals on both TXOP&TXON and RXIP&RXIN should be as close to each other as possible. 3. There should not be any noisy signals near the differential signals on both TXOP&TXON and RXIP&RXIN There should not be any noisy signals near the bias resistor and the crystal. 4. The de-coupled capacitance should be placed as close to the aJ-200 Ethernet pins as possible. 5. In the PCB power plane, it is recommended to separate the analog power and digital power as well as
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Technical Reference Manual the analog ground and digital ground.

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Technical Reference Manual

12. AES-DES Engine (AES-DES)

12.1. Overview The AES-DES Cipher Coprocessor provides an efficient hardware implementation of DES/Triple-DES/AES algorithm for high performance encryption and decryption which can be applied to various applications. In DES/Triple-DES configuration, the AES-DES engine supports four block cipher modes, including ECB, CBC, CFB and OFB. In AES configuration, it supports five block cipher modes, including ECB, CBC, CTR, CFB and OFB. The AES-DES Cipher Coprocessor provides DMA function which can reduce the overhead on processor for data transfer and improve system performance. It supports the following features: DES/Triple-DES encryption/decryption compliant with NIST standard AES 128/192/256-bit encryption/decryption compliant with NIST standard Block cipher modes o DES/Triple-DES o AES ECB mode CBC mode CFB mode OFB mode CTR mode ECB mode CBC mode CFB mode OFB mode

DMA function

The simplified block diagram is shown in the below figure below

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Figure 12-1. AES Engine 12.1.1. AHB Slave and Control Register This block provides AHB bus interface and several sets of status and control registers. Users can program these registers for appropriate application through AHB bus. 12.1.2. AHB Master The main function of AHB Master is to transfer data through AHB bus. This design is complaint with AMBA AHB 2.0 specification. The burst type of AHB Master is incrementing burst of unspecified length (INCR). The data size may be word or byte depending on the number of remaining total transfer size. If total transfer size is larger than 4 bytes, the data size will be word; otherwise, it will be byte. 12.1.3. DMA Engine The DMA block supports the function of transferring data from source address to destination address. Users have to program related registers such as source address, destination address, and total transfer size before enabling DMA. When the DMA engine completes total transfer size, interrupt will be triggered. Users can set DMAStop bit of DMACtrl register to disable DMA function. When DMAStop bit is set, FIFO will be reset and DMA stop interrupt will be triggered. 12.1.4. Data FIFO The data FIFO is composed of input FIFO, INFIFO, and output FIFO, OUTFIFO. DMA reads data from AHB bus and pushes it into INFIFO. DMA pops data from OUTFIFO and writes it to AHB bus. When security engine is active, it pops original data from INFIFO and pushes the result data into OUTFIFO. The status of data FIFO can be read from FIFOStatus register.

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Technical Reference Manual 12.1.5. Security Engine The security engine supports three cipher algorithms, AES, DES and Triple-DES, and up to five operation modes for these algorithms (ECB, CBC, CTR, CFB, OFB). For AES, it provides five operation modes (ECB, CBC, CTR, CFB, OFB) and three key sizes, 128 bits, 192 bits and 256 bits, which is determined by register setting. For DES and Triple-DES, it provides four operation modes (ECB, CBC, CFB, OFB). The key size of DES is 64 bits. The key size of Triple-DES is 192 bits. Users can program EncrypControl register to set specific value for different applications. When DMA is enabled and the data in FIFO is ready, the security engine will encrypt or decrypt data from INFIFO and return the resultant data to OUTFIFO. For each encryption/decryption cycle, one block size of data will be processed. It repeats this operation until total transfer is completed. The block size for each mode is shown below. Algorithm Mode Block size Block Size of each mode AES DES ECB/CBC/OFB/CTR ECB/CBC/OFB 16 bytes 8 bytes Table 12-1. AES/DES CFB 1 byte

Below is the clock cycles of one cipher operation of different algorithms. Table 12-2. Cipher Operation Cycle Cipher Operation Cycle. Algorithm AES Triple-DES Clock cycle 12 16 12.2. Memory Map / Register Definition

DES 18

Table below summarizes the control registers. Detailed information on the control registers is described in the following subsections. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 TYPE R/W --R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 12-3. Memory map/register definition Name Description EncryptControl Encryption/decryption control register --Reserved FIFOStatus IN/OUT FIFO status information PErrStatus Parity error information Key0 The 0th 32 bits of key stream Key1 The 1st 32 bits of key stream Key2 The 2nd 32 bits of key stream Key3 The 3rd 32 bits of key stream Key4 The 4th 32 bits of key stream Key5 The 5th 32 bits of key stream Key6 The 6th 32 bits of key stream Key7 The 7th 32 bits of key stream IV0 The 0th 32 bits of Initial Vector stream IV1 The 1st 32 bits of Initial Vector stream IV2 The 2nd 32 bits of Initial Vector stream
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Reset Value 00000000 -00000005 00FFFFFF 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

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Technical Reference Manual 0x3C 0x40 0x44 0x48 0x4c 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 0x88 0x8C 12.3. R/W ----R/W R/W R/W R/W R/W R/W R R W --R R ----R R R R Register Descriptions The 3rd 32 bits of Initial Vector stream Reserved Reserved DMA source address DMA destination address DMA total transfer size DMA control register FIFO threshold Interrupt enable bit Interrupt source information before mask MaskedIntrStatus Interrupt status after mask IntrClr Interrupt clear register --Reserved REVSION Version register FEATURE Feature register --Reserved --Reserved LAST_IV0 Last block IV output for next block LAST_IV1 Last block IV output for next block LAST_IV2 Last block IV output for next block LAST_IV3 Last block IV output for next block IV3 ----DMASrc DMADes DMATrasSize DMACtrl FIFOThold IntrEnable IntrSrc 00000000 --00000000 00000000 00000000 00000000 00000010 00000000 00000000 00000000 00000000 ----------

12.3.1. Encryption Control Register (offset==0x00 EncryptControl) This register stores information to control the function of security engine. Table 12-4. Bit 31-9 8 Name --pchk first Type --R/W R/W Encryption control register

6-4

emode

R/W

3-1

method

R/W

Description Reserved Parity check bit, only used in DES mode 1: Enable parity check 0: Disable parity check Specifies the first data block to load initial vector: When operating in CBC, CTR, CFB or OFB mode, users should specify the first block to load initial vector for cipher operation. 1: Specify the first block of cipher operation 0: Non-first block This bit returns to 0 automatically when finishing one cipher operation. Operation mode select: 3b000: ECB mode 3b001: CBC mode 3b010: CTR mode 3b100: CFB mode 3b101: OFB mode Encryption algorithm select: 3b000: DES

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Technical Reference Manual 3b001: Triple-DES 3b100: AES-128 (key size = 128 bits) 3b101: AES-192 (key size = 192 bits) 3b110 :AES-256 (key size = 256 bits) Decryption or encryption stage: 1: Decryption stage 0: Encryption stage

decrypt

R/W

12.3.2. Reserved Register (offset==0x04 Reserved) Bit Assignment of Reserved Register. Table 12-5. Reserved register Bit Name Type 31- 0 -----

Description Reserved

12.3.3. FIFO Status Register (offset==0x08 FIFOStatus) This register stores information of FIFO which reflects the current entities in INFIFO and OUTFIFO. Table 12-6. FIFO status register Bit Name Type Description 31-24 of_entity R OUT FIFO entity count 23-16 If_entity R IN FIFO entity count 15-4 ----Reserved 3 Offull R OUT FIFO is full 2 ofempty R OUT FIFO is empty 1 Iffull R IN FIFO is full 0 ifempty R IN FIFO is empty 12.3.4. Parity Error Register (offset==0x0c PErrStatus) This register stores information on the result of parity check. Bit 31 30-24 23-0 Name perr --perrb Type R --R Table 12-7. Parity error register Description Parity error Reserved Parity error bits of each byte of DES Keys KMC_QA

12.3.5. Security Key N Register (offset == 0x10 ~ 0x2c) These registers (0x10 ~ 0x2c) store information of security key stream for cipher operation. For AES-128, the key stream is 128 bits (Key0 ~ Key3). For AES-192, the key stream is 192 bits (Key0 ~ Key5). For AES-256, the key stream is 256 bits (Key0 ~ Key7). For DES, the key stream is 64 bits (Key0 ~Key1). For Triple DES, the key stream is three 64 bits ({Key0, Key1}, {Key2, Key3}, {Key4, Key5}). Table 12-8. Bit 31- 0 Name Key N Type R/W Security key N register Description The Nth 32 bits of key stream

12.3.6. Initial Vector N Register (offset==0x30 ~ 0x3c)

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Technical Reference Manual These registers (0x30 ~ 0x3c) store information of initial vector for cipher operation. For AES, the initial vector is 128 bits (IV0 ~ IV3). For DES/Triple-DES, the initial vector is 64 bits (IV0 ~ IV1). Table 12-9. Bit 31- 0 Name IV N Type R/W Initial vector N register Description The Nth 32 bits of Initial Vector stream

12.3.7. Reserved Register (offset==0x40 Reserved) Bit 31- 0 Name --Type --Description Reserved

12.3.8. Reserved Register (offset==0x44 Reserved) Bit 31- 0 Name --Type --Description Reserved

12.3.9. DMA Source Address Register (offset==0x48 DMASrc) This register stores information of DMA source address from which DMA reads data into INFIFO for cipher operation. Table 12-10. DMA source address register Bit Name Type Description 31- 0 DMASrc Source address of DMA 12.3.10. DMA Destination Address Register (offset==0x4c DMADes) This register stores information of DMA destination address to which DMA writes data from OUTFIFO for cipher operation. Table 12-11. DMA destination register Bit Name Type Description 31- 0 DMADes Destination address of DMA 12.3.11. DMA Transfer Size Register (offset==0x50 DMATrasSize) This register stores information of total transfer size which DMA will transfer. The unit of the value is byte. Table 12-12. DMA transfer size register Bit Name Type Description 31 12 ----Reserved 11- 0 TranSize R/W Total byte sizes of DMA transfer, in the range of 0~4095. The byte sizes must be a multiple of the block size which is determined by the modes of cipher operation specified in EncryptControl. The block size for all modes of AES except CFB mode is 16 bytes (128 bits). The block size for all modes of DES except CFB mode is 8 bytes (64 bits). The block size of CFB mode of AES and DES is 1 byte (8 bits). 12.3.12. DMA Control Register (offset==0x54 DMACtrl)

The information in this register is used to enable or disable DMA function. When writing 1 to DmaStop bit, the encryption/decryption action will be stopped immediately, and the interrupt (StopIntr, Register 0x60[2])

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Technical Reference Manual will be asserted. The hardware will automatically clear the DmaStop bit to 0 when users clear that interrupt (ClrStopIntr, Register 0x68[2]). Bit 31-3 11- 0 2 Name --TranSize DMAStop Table 12-13. DMA control register Type Description --Reserved R/W W 1: Stop DMA 0: No effect R 1: DMA stop operation 0: No DMA stop operation --Reserved W 1: Enable DMA 0: No effect R 1: DMA enable 0: DMA disable

1 0

--DMAEn

12.3.13.

FIFO Threshold Register (offset==0x58 FIFOThold) Table 12-14. FIFO threshold register Description Reserved Water mark of OUTFIFO data count which activates the engine to pop data from OUTFIFO and to write them into memory. Unit: Bytes Water mark of INFIFO data count which activates the engine to read data from memory and to push them into INFIFO. Unit: Bytes

This register stores information of threshold used as the condition to activate read or write transfer of DMA. Bit 31-16 15- 8 7- 0 Name --OUTFIFOThold INFIFOThold Type --R/W R/W

12.3.14.

Interrupt Enable Register (offset==0x5c IntrEnable)

This register stores information to enable or disable interrupt source. Bit 31- 3 2 7- 0 1 0 12.3.15. Name --StopIntrEn INFIFOThold ErrIntrEn DoneIntrEn Table 12-15. Interrupt enable register Type Description --Reserved R/W 0: Disable DMA Stop Interrupt source R/W Water mark of INFIFO data count which activates the engine to read data from memory and to push them into INFIFO. Unit: Bytes R/W 0: Disable DMA Receives hresp Error Interrupt source 1: Enable DMA Transfer Done Interrupt source R/W 0: Disable DMA Transfer Done Interrupt source 1: Enable DMA Transfer Done Interrupt source

Interrupt Source Register (offset==0x60 IntrSrc)

This register stores information of interrupt source.

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Technical Reference Manual Table 12-16. Interrupt source register Bit 31- 3 2 1 0 12.3.16. Name --StopIntrEn ErrIntr DoneIntr Type --R R R Description Reserved DMA Stop Interrupt source before mask DMA Receives hresp Error Interrupt source before mask DMA Transfer Done Interrupt source before mask

Masked Interrupt Status (offset==0x64 MaskedIntrStatus) Table 12-17. Masked interrupt status

This register stores information of interrupt after mask. Bit 31- 3 2 1 0 12.3.17. Name --StopIntrMsk ErrIntrMsk DoneIntrMsk Type --R R R Description Reserved DMA Stop Interrupt after mask DMA Receives hresp Error after mask DMA Transfer Done Interrupt after mask

Interrupt Clear Register (offset==0x68 IntrClr) Table 12-18. Interrupt clear register

This register is used to clear interrupt Bit 31- 3 2 1 0 12.3.18. Name --ClrStopIntr ClrErrIntr ClrDoneIntr Type --w w w Description Reserved 0: No effect 1: Clear DMA Stop Interrupt 0: No effect 1: Clear DMA Receives hresp Error Interrupt 0: No effect 1: Clear DMA Transfer Done Interrupt

Revision Register (offset==0x70 REVISION)

This register stores information of revision. Table 12-19. Revision register Bit 31 - 0 12.3.19. Name REVISION Type R Description The revision number

Feature Register (offset==0x74 FEATURE) Table 12-20. Feature register

This register stores information of hardware feature. Bit 31 - 8 7-0 12.3.20. Name -FIFO_DEPTH Type -R Description Reserved The In/Out FIFO depth. Unit: Byte

Last Initial Vector N Register (offset==0x80 ~ 0x8c)

These registers (0x80 ~ 0x8c) store information of initial vector of last block size for cipher operation. For
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Technical Reference Manual AES, the initial vector is 128 bits (IV0 ~ IV3). For DES/Triple-DES, the initial vector is 64 bits (IV0 ~ IV1). Note that for some modes, for example, EBC mode, or the IV2~3 for DES/Triple-DES, the register value is 0. Bit 31- 0 Name Last_IV N Table 12-21. Last initial vector N register Type Description R The Nth 32 bits of Last Initial Vector stream

12.3.21. Initialization / Application Information The programming sequence consists of the following steps. 1. 2. Set EncryptControl register for encryption/decryption operation. Set Initial Vector IV for some mode of cipher algorithm such as CBC, CTR, CFB, or OFB. There are four 32-bit registers (IV0 ~IV3) for initial vector setting. For AES algorithm, IV is16 bytes (IV0 ~ IV3). For DES algorithm, IV is 8 bytes (IV0~IV1). One IVn register is for four bytes of initial vector. The byte sequence is in most-significant-bit-first order. Below is the initial vector for different cipher algorithms: DES/Triple-DES: IV[63:0] = {IV0, IV1} AES: IV[127:0] = {IV0, IV1, IV2, IV3} IV Register Byte Sequence IV[63:0] IV0 0 1 Table 12-22. Byte Sequence of Initial Vector IV1 IV2 2 3 4 5 6 7 8 9 Initial Vector IV3 12

10

11

3. Set Key value for different cipher algorithms such as AES, DES, and Triple-DES. There are eight 32-bit registers (Key0~ Key7) for key value setting. For AES-128 algorithm, key value is 16 bytes (Key0 ~ Key3). For AES-192 algorithm, key value is 24 bytes (Key0 ~ Key5). For AES256 algorithm, key value is 32 bytes (Key0 ~Key7). For DES algorithm, key value is bytes (Key0 ~ Key1). For Triple-DES algorithm, there are three 8-byte ({Key0,Key1}, {Key2,Key3}, {Key4,Key5}) key values. The byte sequence is in mostsignificant-bit-first order. Below is the key value for different cipher algorithms: AES-128 algorithm AES-128key[127:0] = {Key0, Key1, Key2, Key3} AES-128Key[127:96] = Key0 AES-128Key[95:64] = Key1 AES-128Key[63:0] = Key2 AES-128Key[31:0] = Key3 Table 12-23. AES-128 Key Stream of Byte Sequence

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Technical Reference Manual Key Register Byte Sequence key[127:0] Key0 0 1 Key1 4 5 Key2 6 7 8 9 AES-128 Key Value Key3 12

10

11

AES-192 algorithm AES-192key[191:0] = {Key0, Key1, Key2, Key3, Key4, Key5} AES-192Key[191:160] = Key0 AES-192Key[159:128] = Key1 AES-192Key[127:96 ] = Key2 AES-192Key[95:64] = Key3 AES-192Key[63:0] = Key4 AES-192Key[31:0] = Key5 Key Register Byte Sequence Key[191:0] Table 12-24. AES-192 Key Stream of Byte Sequence Key0 Key1 Key2 0 1 2 3 4 5 6 7 8 9 10 AES-192 Key Value Key5 ... 23

AES-256 algorithm AES-256: key[255:0] = {Key0, Key1, Key2, Key3, Key4, Key5, Key6, Key7} AES-256Key[255:224] = Key0 AES-256Key[223:192] = Key1 AES-256Key[191:160] = Key2 AES-256Key[159:128] = Key3 AES-256Key[127:96 ] = Key4 AES-256Key[95:64] = Key5 AES-256Key[63:0] = Key6 AES-256Key[31:0] = Key7 Key Register Byte Sequence Key[255:0] Table 12-25. AES-256 Key Stream of Byte Sequence. Key0 Key1 Key2 1 2 3 4 5 6 7 8 9 10 AES-256 Key Value Key7 ... 31

DES algorithm DESkey[63:0] = {Key0, Key1} DESkey[63:32] = Key0 DESkey[31:0] = Key1 Key Register
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Table 12-26. DES Key Stream of Byte Sequence. Key0 Key1 Key2
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Technical Reference Manual Byte Sequence key[63:0] 0 1 2 3 4 5 DES Key Value 6 7 8 9 10 11 Reserved 12

Triple-DES algorithm Triple-DESKey1[63:0] = {Key0, Key1} Triple-DESKey1[63:32] = Key0 Triple-DESkey1[31:0] = Key1 Triple-DESKey2[63:0] = {Key2, Key3} Triple-DESKey2[63:32] = Key2 Triple-DESKey2[31:0] = Key3 Triple-DESKey3[63:0] = {Key4, Key5} Triple-DESKey3[63:32] = Key4 Triple-DESKey3[31:0] = Key5 Key Register Byte Sequence Key[191:0] 1. Table 12-27. Triple-DES Key Stream of Byte Sequence Key0 Key1 Key2 Key5 1 2 3 4 5 6 7 8 9 10 23 Triple-DES Key1 Triple-DES Key

Locate memory space for input/output data block. Prepare input data block in specific memory space. The cipher or plain text is represented in byte sequence order, b0, b1, b2, b3, b4and so on. The index indicates the address offset. For example, b0 indicates data b0 resides in offset 0, b1 resides in offset 1 and so on. The endianness in this design is little endianness. In order for the system to function correctly, all modules accessing the memory should be of the same endianness.

2. 3.

Set DMA related register: Set DMASrc register for source address, DMADes for destination address, DMATrasSize for total data transfer size from source to destination. The value of DMATrasSize represents the byte count and should be a multiple of the block size that is determined by cipher algorithm.

4.

Set FIFOThold register to specify FIFO threshold for DMA to activate read/write transfer from memory. Users can set two watermarks in FIFOThold register as the condition to activate read or write transfer. For read transfer, it has to meet the condition that the entities of INFIFO are less than the value of INFIFOThold or one block size. For write transfer, it has to meet the condition that the entities of OUTFIFO are more than the value of OUTFIFOThold or one block size.

5. 6.

Set IntrEnable register to enable interrupt signal or not. Set DmaEn bit of DMACtrl to 1 to activate DMA engine and security engine.
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Technical Reference Manual 7. After total transfer size is completed, interrupt will be triggered and DMA will be stopped.

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13. USB 2.0 OTG Controller (USBC)

13.1. Overview The USBC is a single-chip Universal Serial Bus (USB) 2.0 On-The-Go (OTG) controller integrated with a USB OTG PHY. It can play a dual-role, a host or peripheral device. When USBC acts as a host, it contains the USB host controller that supports all speed transactions. Without the software intervention, the host controller can deal with a transaction-based data structure to offload the CPU and automatically transmit and receive data on the USB bus. When it acts as a peripheral device, each endpoint, except endpoint 0, accepts the programmable HS/FS transfer type to provide a flexibility that is suitable for all kinds of applications. In addition, complying with the OTG standards means both the Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) are supported. The system bus is AHB 32-bit bus interface. The transceiver interface is UTMI+ level 2, which supports HS/FS/LS transfers without a hub. It supports the following features: Compliant with USB specification revision 2.0 Compliant with On-The-Go supplement to USB 2.0 specification revision 1.0 OTG SRP and HNP Point-to-point communications with one HS/FS/LS device HS/FS hub Hardware configurable endpoints as HS/FS device Both host and device support isochronous/interrupt/control/bulk transfers Compatible with EHCI data structures Embedded the DMA access to FIFO Suspend mode, remote wake-up, and resume USB OTG software subsystem 2KB FIFO Integrated USB OTG PHY

The figure below illustrates the simplified block diagram of USB-OTG

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USB OTG PHY

12 MHz Crystal

DP/DM

Figure 13-1. USB OTG Block Diagram

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Technical Reference Manual 13.2. Architecture Overview

The USBC is composed of eight major sub-blocks: DMA Controller Host Controller Host Register File Microprocessor Interface Controller FIFO Controller Device Register File OTG Register File Device Controller Parallel Interface Engine OTG Bus Monitor OTG PHY

13.2.1. DMA Controller The main function of the DMA controller is to actively transfer data between this controller and memory. Figure below shows the block diagram of the DMA controller. Two asynchronous clock domains, a system clock (SCLK) and a USB clock (UCLK), are present in the DMA controller. The USB lock (UCLK) is limited by the UTMI physical layer to 30 MHz and the system clock must be faster than 15 MHz. A speed matching buffer is employed to synchronize the data between the SCLK and UCLK. Several synchronizers are employed to synchronize the control signals between these two clock domains. Four types of transfers are defined: 1. M2F (memory to FIFO) 2. F2M (FIFO to memory) 3. H2M (host to memory) 4. M2H (memory to host). If the current role of the USBC is peripheral, and an OUT transaction is requested, the DMA controller will be initialized to move data from the FIFO to memory. If an IN transaction is requested, the DMA controller will be initialized to move data from the memory to FIFO. The transfer length and memory starting address are given during DMA transfer initialization. If USBC is a host, the DMA controller will be initialized as the M2H while the host controller is processing the transfer list. If the IN transaction is found in the transfer list, the DMA controller will be initialized by the host controller to move the data from the FIFO to memory if the FIFO controller had received data. If the OUT transaction is found in the transfer list, the DMA controller will be initialized by the host controller to
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Technical Reference Manual move data from memory to the FIFO for the PIE to send data to the device. The transfer length and memory starting address are given during the DMA transfer initialization. The H2M transfer will be initialized if the host controller needs to update the transfer list in the memory. The DMA controller provides an I/O transfer style by setting the DMA_IO bit in DMA Controller Parameter Setting 1 register to 1. If this bit is set, the DMA transfer address that followed will be fixed to the DMA_MADDR setting in the DMA Controller Parameter Setting 2 register. Moreover, the data will be read/written from/to the fixed address until the length counts up.

Figure 13-2. DMA Controller Block Diagram 13.2.2. Host Controller The USB OTG is a one-port EHCI-compatible host controller that supports all compliant USB 2.0 low-/full/high-speed devices except split transactions for a USB 2.0 hub. As defined in EHCI, the EHCI provides a simple, asynchronous interface for software to provide the host controller with parameterized work items that the host controller uses to execute transactions on the USB. This interface allows software to asynchronously add work to the interface while the host controller is executing. Unlike the USB 2.0 host controller specified in the EHCI, which states A USB 2.0 host controller includes one high-speed mode host controller and 0 or more USB 1.1 host controllers, there is only one host controller in the USB OTG to deal with all three device speeds and the USB OTG implements an EHCI interface. The USB OTG contains the isochronous transfer descriptor (iTD), queue head, and queue element transfer descriptor (qTD) data structure interface to support isochronous/interrupt/control/bulk transfers. As shown in Figure below, the two hexagons (iTD & QH) represent the work items to be parsed
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Technical Reference Manual and executed and the two (periodic and asynchronous schedule) processing state machines take care of the operation of the work items. Before activating the processing state machine to parse the work items, these work items must be prepared in the system memory and chained together by the system software. In addition, by using the operational register files, the USBC can control the schedule processing state machine and be aware of all status types for the host and USB. Once the USB OTG starts to traverse the schedule, the first thing the host controller will do is to fetch the data structures via the DMA controller, then parse these fetching work items for the corresponding USB behavior, and use the transaction level control signals between host and PIE to execute USB transactions. During the transaction, the FIFO will be used as temporary storage between the USB and system memory. Finally, the USB transactions on the work items are all executed and recorded, then written back to the system memory.

Figure 13-3. Host Control Block Diagram 13.2.3. Register Files There are three major register files existing in the USBC, including the host controller register file, the OTG controller register file, and the device controller register file. Each register file (RGF) contains registers for
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Technical Reference Manual all the system configurations and status controls between the CPU (microprocessor) and the internal blocks. These registers are accessed by the microprocessor on the system bus via the microprocessor interface. These register files are located in different clock domains. The host controller register file uses the same clock domain as a system clock since the host controller uses the system clock. The device and the OTG register files use the USB clock as their operation frequency since both controllers use the USB clock for operations. For the device, the register files record the auto-configuration setting of each FIFO, the status of each IN/OUT endpoint, the DMA control and status, the interrupt status, the test setting, and so on. It also communicates with the PIE for information about USB transfers. For the OTG controller, the register file contains the control and status to fulfill the role change operation of the USB, and interrupt status information. For the host, the register file serves as the interface between the hardware and software. The system software can use the operation registers to control the host and read the status of transaction results, interrupts, and the port status. 13.2.4. Microprocessor Interface Controller The function of the microprocessor interface controller is to act both as a slave controller of the system bus and as an interface converter between the system bus and other buses. This function has the simple purpose of decoding the cycles on the system bus toward the USB controller register space and interpreting the cycles to the related read/write operation to target registers. Every cycle responded to by the microprocessor interface will be a single cycle. The input signal t_eop acts as if it were tied to high. The USBC provides the AMBA AHB bus. When using the AHB system bus, the wrapper between the AMBA AHB bus and the PVCI system bus will be a simple 32-bit to 32-bit cycle converter, without any FIFO. 13.2.5. FIFO Controller The block diagram of the FIFO Controller (FIFOCTL) is shown in figure below. The FIFO controller contains a 2 KB + 64B SRAM block and several control blocks. The 64-byte memory is dedicated for device control transfers. The other 2 KB memory space is divided into four 512-byte blocks. The endpoint number can be configured and the maximum endpoint number is 8.

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Figure 13-4. FIFOCTL Block Diagram The FIFOCTL can mainly be divided into several parts. First is the interface control block. There are two interface control blocks: Interface to PIE (PIEINF) Interface to DMA (DMAINF)

These two interface control blocks have their own state machines and use self-defined protocols. The second part is the FIFO address counter and the FIFO control related blocks. The FIFO address counter grabs the FIFO configuration information including the endpoint mapping, the packet size, the FIFO pointer, and the firmware done set operation to the FIFO from the related blocks. The FIFO address counter also keeps track of the byte count stored in each FIFO and uses the grabbed information to generate SRAM address. The TIMGEN block generates an even/odd clock to arbitrate whether the PIE or DMA can access the SRAM in the current clock cycle. Two Muxes are used, one is for the muxing address generated by

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Technical Reference Manual either the FIFOADR or CXF, another is for the muxing data input either from the DMA or PIE. When the USBC acts in the role of a host, the FIFO configuration is fixed as two 1024-byte spaces with ping-pong architecture. When the USBC acts as the role of a device, the 2K SRAM is divided into four FIFOs (FIFO 0-FIFO 3) and each contains 512 bytes. As well, an endpoint can be mapped to a single, double, or triple FIFO and an ISO or high-speed interrupt endpoint can combine two 512-byte FIFOs to accommodate maximum packet size larger than 512 bytes. If the transfers on two endpoints are not overlapped, for example, in a mass storage application, the IN transfer will always happen after all OUT transfers have finished. Then these two endpoints can be mapped to the same FIFO(s). Thus four FIFOs can accommodate eight endpoints at maximum. FIFO 4 is an additional 64-byte memory space dedicated for control transfers. While the USBC plays the role of a host, FIFO 0 and FIFO 1 are combined to constitute a 1 KB memory space. FIFO 2 and FIFO 3 are also combined to constitute a 1 KB memory space and ping-pong with another 1 KB memory. Both of these 1 KB memory spaces are bi-directional. 13.2.6. Device Endpoint 0 Control Transfer Controller (CXF) The block diagram of the device endpoint 0 control transfer controller of the USBC is shown in figure below. The CXF contains two major sub-blocks: the Finite State Machine (FSM) and FIFO Status Controller (FIFOSTAT). The FSM keeps track of the USB control transfer transaction information sent from the PIE, CPU operations from Device RGF, CPU read/write information from the FIFOCTL, and the FIFO empty information from FIFOSTAT. Since the CXF does not contain a memory itself, the CXF shares a 64-byte SRAM space in the FIFOCTL to store the control transfer data. The FIFOSTAT is used to keep track of the FIFO status such as byte count, address pointer location (both USB side and AP side), and FIFO full or empty information.

Figure 13-5. CXF Block Diagram

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Technical Reference Manual Interrupts generated by the CXF are listed in an interrupt source group 0. The 8-byte setup command can be read directly by CPU through the register 1D0h as a setup command port. Other control transfer data is transferred by the DMA from memory to the FIFO or from the FIFO to the memory 13.2.7. Parallel Interface Engine (PIE) The block diagram of the PIE is shown in figure below, PIE operates in the 16-bit parallel data streams with a universal transceiver macro interface - UTMI. The PIE runs on a 30 MHz clock provided by the transceiver. When the USBC plays the role of a device according to the current role status from the OTG block, the PIE decodes the token and the data packets issued by the USB host. When the USBC plays the role of a host, the PIE sends out any packet which the host controller asks and returns the status that device replies. Then, it generates internal signals based on the decoded packets to other sub-module of the USBC. The CRC 5/CRC 16 generation and checking for packets transferred from/to the USB host are also performed by the PIE. After the chirp mode, the PIE operates in either a high-speed or full-speed mode informed by PWE. The communication between the PIE and CXF is for information about control transfers. The information for bulk, ISO and interrupt transfers is passed on the communication channel between the PIE and PAM. The message passed between the PIE and RGF controls the operation of PIE. Some information, for example start-of-frame, is sent to RGF by PIE for later processing by AP. Please note that only the interconnection among PIE, PAM and CXF is shown in below figure the communication paths among PIE, PWE, and RGF are not displayed.

Figure 13-6. PIE Block Diagram

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Technical Reference Manual 13.2.8. OTG Bus Monitor

Figure 13-7. OTG Bus Monitor Block Diagram The bus monitor block includes two sub-modules for host and device so that the USBC can behave as a dual-role OTG device. First, after detecting the input u_iddig from the UTMI+ interface, if its value is logic 0, then USBC will function as a host; otherwise the USBC will function as a device. The output otg_cur_role_r informs PIE that the current operating role is a host or device. Simply by monitoring the Vbus and two data lines, the bus monitor block can execute a low level electrical handshake protocol with the opposite end, such as reset speed handshake, suspend detection, resume signaling detection, and also OTG HNP and SRP. To be able to communicate with another device of a different speed, the bus monitor block needs to properly control the OTG PHY via the UTMI+ level 2 interface. By HNP, it can switch the current role between the host and device. When acting as a host, the software needs first to set the OTG control register fields a_bus_drop and a_bus_req to 2b01 to turn on Vbus. Once the host detects the connection of a device, otg_p_attach_r is asserted. After the AP receives the port_chg_detect interrupt from RGF and ensures the connection of the device, it will set the bit port_reset of the host control register to 1 to start reset process. The host status state machine sees the signal r_hpo_reset from the RGF and starts the reset process. If detecting chirp K from device, it must then drive bm_chirp[1:0] to PIE, so that it can toggle chirp K and chirp J of the specified timing on the data line until the reset process is terminated by AP. After the host status state machine sees the assertion of r_hreset_term from the RGF, the output signal bm_chirpend will be asserted to inform PIE to stop driving chirp signal to device. After the reset process, host indicates to PIE which speed type of device is attached by the output signal bm_speed[1:0]. If a host no longer uses the bus and intends to suspend the bus, it may just set the port_suspend bit of the
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Technical Reference Manual host control register. Here are two methods of resume from the suspend state for the host. One is to have the host directly to drive resumed signaling to device. The other is to have the device remote wakeup and have the host to reflect the resumed signal to device. In either method, the software needs first to set f_po_resm bit of the host control register. The host status state machine will determine the correct bm_chirp[1:0] depending on the speed type of the device. Then the PIE will drive resume signal to device according to the signal bm_chirp[1:0] until the input r_hresm_term to the bus monitor block is asserted. AP sets f_po_resm bit of host control register to 0 to terminate the resume process. SRP pulsing from the B-device allows A-device to turn on Vbus. If the AP wants to enable the SRP detection capability, then a_srp_det_en bit of the OTG control register needs to be set to 1. Also, the host can select to detect data pulsing or Vbus pulsing according to the setting of a_srp_resp_type bit of OTG control register. The HNP allows A-device to change the role between the host and device. After the Adevice enters the suspend state and detects the disconnection of the B-device, A-device will successfully become the device. The AP just sets a_set_b_hnp_en bit of the OTG control register, then the HNP capability of the A-device is enabled. When acting as a device, the USB OTG is also capable of identifying the speed type of the host it is attached to by using a reset handshake. The device must identify the reset signaling under three cases: (1) It must detect a SE0 no less than 2.5 s during the suspend state, (2) it must detect a SE0 of 2.5 s in non-suspended FS mode, and (3) it must detect a reset in HS mode. After detecting an idle state for no more than 3.125 ms, the HS device reverts to the FS mode to see if the bus remains in the SE0 state. If any of the above three cases occurs, the device must enter the reset handshake state at once. After driving bm_chirp[1:0] to PIE, it should drive the chirp K to host for about 1 ms until the signal bm_chirpend is asserted. If the host is HS, the device should receive at least 3 pairs of chirp K and chirp J; otherwise, only the SE0 state appears on the data lines. The device status state machine can distinguish the speed type of the host from the difference of the reset behavior. As soon as the reset is detected, the output signal bm_usbrst is asserted. The signal bm_usbrst can be used to reset the corresponding registers in the other modules. The signal bm_speed[1:0] can also be applied to the device to represent the speed of the host. The device detects the suspend state in the HS or FS mode. After the AP receives a suspend interrupt event, the AP must set the GOSUSP bit of device control register and the idle_cnt[2:0] of device idle_count register in 10 ms. From the time when the signal r_dgosus is asserted, once the idle_cnt[2:0] counts up to the specified rdsusp_cnt[2:0] in the RGF, the device will assert u_susp_n of UTMI+. Afterwards, the 30 MHz USB clock will be gated until USB reset or resume event occurs. AP will set cap_rmwakup bit of the device control register to enable the remote wakeup capability of the device. After the device stays in the
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Technical Reference Manual power-up state for at least 5 ms, the PIE will drive a remote wakeup resume signaling to the host for about 10 ms. After the Vbus is turned off, the AP can write b_bus_req bit of the OTG control register to issue an SRP pulsing to request the A-device to turn on the Vbus. The B-device needs first to issue data pulsing followed by Vbus pulsing. After accepting the set feature command to enable HNP capability of the B-device, the AP will set the b_hnp_en bit of the OTG control register. Once the B-device enters the suspend state and removes the pull-up resistor on the D+, the B-device will change its role as host until it detects the connection of an A-device. Then the B-device will control the bus from the A-device. 13.2.9. Register Files (RGF) The block diagram of RGF is shown in figure below. RGF contains registers for all the system configuration and status control between CPU and the internal blocks. It records the auto-configuration setting of each FIFO, the status of each IN/OUT endpoint, interrupt status, test setting, and so on. RGF also communicates with PIE for information about USB transfers. The interconnection between RGF and PAM provides PAM with configuration for non-control transfer endpoints. PAM passes information for each transfer from non-control endpoints to RGF and vice versa to let AP read that information for further processing. The information for control transfer is transmitted between CXF and RGF. RGF talks with PWE for detection and support of speed emulation, power-down, USB reset and timeout. Finally, RGF adopts AMBA protocol to let AP access the information recorded in the registers of USB OTG
RGF HBS PIE control registers interrupt registers PWE

endpoint configuration and status registers PAM

test registers

CXF

13.2.10.
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Figure 13-8. RGF Block Diagram Power Management and Speed Emulation (PWE)
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Technical Reference Manual The block diagram for PWE is shown in figure below. PWE controls the switching of USBC speedoperating mode: High / Full speed mode. For power management, PWE monitors u_linesta to detect the idle state of transaction on USB. If there is no traffic for more than 3ms, PWE will assert power-save signal to let AP know the idle event. PWE will assert the suspend signal to let the transceiver enter suspend mode if AP allows PWE to enter suspend mode. PWE also monitors u_linesta to achieve the detection of USB reset and resume.
UTMI CXF
2 u_opmode u_xcvsel u_termsel wakeup

PWE
pw_usbrst pw_resume

PAM

Line - State
u_susp_n 2 u_linesta

pw_hs pw_save r_go_susp r_cap_rmwkup

Check

RGF

T0(timer) T1(timer)
pw_timeout pw_normal(operation

RX PIE

p_timeout

13.2.11.

Figure 13-9. PWE Block Diagram AHB SPLIT-Capable Slave (HBS)

The HBS of USBC is an AMBA 2.0 compliant slave that supports multiple split transfers. It is the interface between AHB buffer (HBF) or RGF and external AHB masters. Before a USB packet is completely transferred to the destination, any AHB masters attempting to access another endpoints FIFO will be split. The number of split AHB masters will be recorded. After a USB packet is transferred, HBS recalls all split masters to re-attempt the transfer by asserting proper bit of HSPLIT[15:0] to arbiter and so on. 13.2.12. AHB Buffer (HBF)

Data written to or read from CXF and PAM will be stored in HBF first. In the case of AP write, the data in HBF will be sent to the FIFOs of CXF or PAM only when the HBF is full or contains the last data payload of a USB packet. In the case of AP read, the HBS will not accept any cycle by SPLIT response until the HBF is full or contains the last data payload of a USB packet. In the case of AP write, the FIFO done bit (0BH bit0 for CXF, A0H~AFH bit3 for PAM) should be set properly after sending a packet in the following cases: 1. A short packet is sent. 2. The packet length is not a multiple of the HBF size. The done bit is used to flush the HBF data and finish a

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Technical Reference Manual packet. 3. AP intends to read FIFO after sending the packet. 4. The next packet is sent by another AHB master. After setting the FIFO done bit, firmware should make sure that HBF is emptied by 28H bit0 before sending the next packet to the USB OTG Data written to or read from RGF will not be buffered; they are transferred directly between HBS and RGF. 13.2.13. AHB Buffer Controller (BFC) BFC assumes the responsibility of data flow between HBF and PAM or CXF. In AP write case, BFC moves the HBF data to the target FIFO when HBF is full or when the FIFO done bit is set. In AP read case, BFC moves the data from FIFO to HBF when HBF is empty. 13.3. USB Reset and Power Saving Mode 13.3.1. USB Reset
*1 u_vbus (AP) D+ Du_usbrst (FUSB220) *3 *2 one clk cycle 2.5 gs min pw_hs (FUSB220) *1. After a time-span of 50ms until the UNPLUG bit in phy_tms register with offset 08 is cleared, the FUSB220 will turn on the Rpu (1.5K), and puts it in Full-Speed mode. *2. After host drives D+/D- as SE0 state for at least 2.5s, PIE will see it as "USB reset", then issues one pulse signal, u_usbrst" for 30MHz to back-end block. *3. The high-speed handshake sequence: FUSB220 issues K state to host first, then host issues the KJKJKJ sequence to indicate that it is HS host. SOF

Figure 13-10. USB Reset and High-Speed Detection Handshake Timing Chart When a device (AP) plugs into the host / hub, the device must detect the Vbus information from USB cable, then asserts the u_vbus to USB OTG to show that the device has been attached to the downstream port of the hub, including the root hub on the host. It is important that the device takes care of this action when it operates in self-power mode. On the other hand, if the device operates in bus-power mode, the u_vbus can be tied to high directly. This is for back-drive voltage consideration in USB2.0 compliance test. After a time-span of 50ms, until the UNPLUG bit in phy_tms register with offset 08H is cleared, the USB OTG will turn on the Rpu (1.5K), and puts it in Full-Speed mode, so the J state will assert on USB. The USB OTG also spends at least 15ms to cover the debounce interval. After that, anytime the device observes no
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Technical Reference Manual bus activity, it must obey the rules of going into suspend mode. If the SE0 state on USB has been detected for at least 2.5s at this moment, the USB OTG will assert one pulse signal, u_usbrst to backend blocks. For a while, the USBOTG will assert Chirp K on USB, then the host will detect this event and respond to the device with the KJKJKJ sequence. However, the USB OTG does not assert the indication for operating in HS mode, pw_hs, until the first SOF packet is asserted on USB. 13.4. Power Saving Mode

hwrst_n

*1 0 min.

u_vbus

D+/D-

u_susp_n 50 min. clk_gating *3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 *2 *4

*1. This interval depends on customer's design. *2. The AP guarantees a minimum of 3ms for the recovery time of back-voltage. *3/*4. The integrator can use some glue logic to combine both u_susp_n and clock-masked control provided by AP to turn on or turn off the clock from PHY, such as "clk_gating" timing.

Figure 13-11. USB OTG Asserts u_susp_n to Turn Off the PLL in PHY USB OTG provides a u_susp_n signal to turn on / off clock, u_clk, from PHY. However, in some cases, users may want to turn the clock on / off by their own AP instead of using USB OTG. That means the integrator can use some glue logic (e.g. an AND gate) to combine both u_susp_n and clock-masked control provided by AP to turn on / off the clock from PHY. Figure above shows the timing relationship for u_susp_n between u_vbus and D+/D-. Here is an explanation of what happens at each tn: t0 t1 t2 t3 System reset, such as power on or hardware reset occurs, but the device is not plugged into upstream facing port. FUSB220 drives u_susp_n to high state since now. The device is plugged into upstream facing port, such as root hub. USBCis initially attached as a full-speed device, and the J state asserted on USB by Rpu(1.5K). Host drives reset on USB.
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Technical Reference Manual t4 t5 t6 t7 t8 t9 t10 USBC operates in high-speed mode. Communication occurs on USB between host and FUSB220. There is no traffic since now. USBC detects no traffic on USB for more than 3ms, then asserts u_susp_n to low state to turn off PLL in PHY. Host resumes USBC, then u_susp_n is de-asserted. The device is unplugged from upstream facing port. u_vbus is de-asserted because of the detachment. The u_susp_n still remains in High state; however, for power consumption in self-power operation with battery, the integrator can create another signal, clk_gating, to turn off the clock from PHY.

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u_clk PHY turns off u_clk pw_save (FUSB220) go_suspend (AP/FUSB220) tsusp_delay u_susp_n (FUSB220) host resume / 20ms *1 D+ Dresume (FUSB220) D+ Du_usbrst (FUSB220) *1. The idle state in HS mode is SE0, and J state in FS mode. If FUSB220 detects idle than 3ms, FUSB220 will assert the "pw_save" to urge AP to enter "SUSPEND" mode. *2. The vaule of t susp_delay can be set by AP. Please refer to the idle_cnt register for details. *3. "go_suspend" is the internal signal of FUSB220, which is not visible to AP. However, AP can set it by writing 1 to GOSUSP of main control register. Then FUSB220 will clear it if it detects the RESUME / USB RESET signals. *4. At the end of resume asserted by host, the FUSB220 will assert "resume". *5. If host issues reset in the suspend mode, the FUSB220 will assert "u_usbrst" when it sees the SE0 state for at least 2.5s on USB. *6. When F/W sees the resume interrupt in offset 28H, it must clear it, then the resume will be de-asserted. one clk cycle width *1 host reset *5 *4 *2 unstable interval gated by PHY 2.5 gsmin. *3

*6

Figure 13-12. USBC Wakened Up by Host Resume / Reset USB OTG provides a suspend mode for power saving. The sequence for entering suspend mode is as follows: 1. 2. If there is no transition on D+/D- for more than 3 ms, USB OTG will assert suspend interrupt, to tell firmware it wants to enter suspend mode. Once firmware detects suspend interrupt, it decides whether or not to accept the suspend request from USB OTG. If firmware accepts the suspend request, it must finish the necessary operations,
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Technical Reference Manual e.g. reading some register of USB OTG, before setting the GOSUSP bit in the main_ctr register with offset 00 of USB OTG. Those operations are necessary, since the clock of USB OTG will be turned off after GOSUSP is set. 3. 4. 5. Firmware sets the GOSUSP bit in the register file of USB OTG.. Once GOSUSP is set, USB OTG will enter suspend mode and assert the suspend output, u_susp_n to transceiver. The clock input, u_clk, will then be turned off by transceiver. Finally, if USB OTG detects resume or USB reset signal, it will clear the GOSUSP bit. There are three events that can force USBC to leave suspend mode, in other words, to wake up. The first one is host resume, as figure 80 shows, which occurs when D+/D- toggles. The second is host reset, as shown in figure above, which occurs when USBC sees SE0 state on USB. The last is remote wake-up, shown in figure below, which takes place when AP asserts wake-up input. For remote wake-up, AP should keep wake-up asserted until USBC de-asserts pw_save. In other words, AP cannot de-assert wake-up before USBC de-asserts pw_save. The procedure of wake-up is: 1. 2. 3. 4. Host sets the Device_Remote_Wakeup feature to USBC Under suspend mode, either host resume or remote wake-up from AP will trigger the wake-up process and USBC will be waked up first. Once USBC is wakened up, it will de-assert suspend output to PHY, and PHY will turn on 30 MHz clock output after USBC de-asserts suspend output. The clock output of PHY is unstable within a short time interval after suspended transceiver is wakened up. The unstable interval is about 2 ms for USB2.0 transceiver

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u_clk
PHY turns off u_clk

pw_save (FUSB220) go_suspend tsusp_delay u_susp_n (FUSB220)

0 min unstable interval gated by PHY

at least 20ms

wakeup
*1

10ms *2

D+ DD+ D-

FUSB220 operates in HS mode before enteingr SUSPEND mode

FUSB220 operates in FS mode

*1. FUSB220 detects 3ms idle on USB in HS mode, then reverses to FS mode! *2. FUSB220 drives device-initialed resume-K state for about 10ms, then host detects the K state, and drives host-resumeK to downstream port!

13.5. 13.5.1.

Figure 13-13. USBC Wakened Up by AP Programming Model Summary of the USBC Registers

The following table shows the register provided by the USBC. Four groups are included. Please note that some register groups are not accessible while the PHY_SUSP (Address = 0xC4) is set to 1. Reading from these register will yield unexpected data. Table 13-1. Summary of the USBC Registers Address range Size(Bytes) Description 9h000 ~ 9h07F 128 Host controller register space. Accessible in PHY_SUSP mode 9h080 ~ 9h0BF 64 OTG controller register space Not accessible in PHY_SUSP mode 9h0C0 ~ 9h0FF 64 Global register space Not accessible in PHY_SUSP mode 9h100 ~ 9h1FF 256 Device controller register space Not accessible in PHY_SUSP mode

Name HC registers OTG registers Global registers Device registers

13.5.2. General Registers and Function

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Technical Reference Manual 13.5.2.1. 13.5.2.2. Host Controller Registers (Address = 000h ~ 07Fh) HC Capability Register (Address = 000h) Table 13-2. HC Capability Register Bit Name Type Default value Description 31:16 HCIVERSION RO 16h0100 Host controller interface version number . This is a two-byte register containing a BCD encoding of the EHCI revision number supported by host controller 15:8 RO 8h0 Reserved 7:0 CAPLENGTH RO 8h10 Capability register length This register is used as an add-on offset register base to locate the beginning of the operational register space. 13.5.2.3. HCSPARAMS HC Structural Parameters (Address = 004h) Table 13-3. HC Structure Parameters Bit Name Type Default value Description 31:4 RO 28b0 Reserved 3:0 N_PORTS RO 4h1 Number of ports This field specifies the number of physical downstream ports implemented on the host controller. 13.5.2.4. HCCPARAMS HC Capability Parameters (Address = 008h) Table 13-4. HC capability Parameters Bit Name Type Default value Description 31:3 RO 29b0 Reserved 2 ASYN_SCH_PARK_CAP RO 1b1 Asynchronous schedule park capability The host controller supports the park feature for high-speed queue heads in the asynchronous schedule. This feature can be disabled or enabled and set to a specific level by using Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. 1 PROG_FR_LIST_FLAG RO 1b1 Programmable frame list flag When this bit is set to 1b, the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. This requirement ensures that the frame list is always physically contiguous. 0 RO 1b0 Reserved 13.5.2.5. USBCMD HC USB Command Register (Address = 010h)

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Technical Reference Manual Table 13-5. HC USB Command Register Type Default value Description Reserved RO 8b0 Interrupt threshold control. This field is used by R/W 8,h08 the system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below: Value Maximum Interrupt Interval for High Speed 00 h Reserved 01h 1 microframes 02h 2 microframes 04h 4 microframes 08h 8 microframes (default, equal to 1 ms) 10h 16 microframes (2 ms) 20h 32 microframes (4 ms) 40h 64 microframes 98ms) Note: At full speed, these registers are reserved. Reserved RO 4b0 Asynchronous schedule park mode enable R/W 1b1 Software uses this bit to enable or disable the park mode. When this bit is set to 1, the park mode is enabled. Reserved RO 1b0 Asynchronous schedule park mode count R/W 2b11 This field contains the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the asynchronous schedule. Reserved RO 1b0 R/W 1b0 Interrupt on asynchronous advance doorbell This bit is used as a doorbell by the software to instruct the host controller to issue an interrupt the next time it advances the asynchronous schedule Asynchronous schedule enable This bit controls whether the host controller skips the asynchronous schedule processing. 0: Do not process Asynchronous Schedule 1: Use the ASYNCLISTADDR register to access the asynchronous Periodic schedule enable This bit controls whether the host controller skips the periodic schedule processing. 0: Do not process periodic schedule 1: Use the PERIODICKISTBASE register to access the periodic schedule

Bit 31:24 23:16

Name INT_THRC

15:12 11

ASYN_PK_EN

10 9:8

ASYN_PK_CNT

7 6

INT_OAAD

ASCH_EN

R/W

1b0

PSCH_EN

R/W

1b0

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Technical Reference Manual Frame list size This field specifies the size of the frame list. 00: 1024 elements (4096 bytes, default value) 01: 512 elements (2048 bytes) 10: 256 elements (1024 bytes) 11: Reserved Host controller reset 1 HC-RESET R/W 1b0 This control bit is used by the software to reset the host controller. Run/Stop 0 RS R/W 1b0 When set to a 1b, the host controller proceeds with execution of the schedule. 0: Stop 1: Run 13.5.2.6. USBSTS HC USB Status Register (Address = 014h) Table 13-6. HC USB Status Register Bit Name Type Default value Description 31:16 RO 16b0 Reserved 15 ASCH_STS RO 1b0 Asynchronous schedule status This bit reports the actual status of the asynchronous schedule 14 PSCH_STS RO 1b0 Periodic schedule status This bit reports the actual status of the periodic schedule. 13 Reclamation RO 1b0 This is a read-only status bit, which is used to detect an empty asynchronous schedule 12 HCHalted RO 1b1 Host controller halted This bit is 0 whenever the run/stop bit is 1. The host controller sets this bit to 1 after it has stopped executing as a result of the run/stop bit being set to 0. 11-6 RO 6b0 Reserved 5 INT_OAA R/WC 1b0 Interrupt on async advance. This status bit indicates the assertion of the interrupt on async advance doorbell 6 INT_OAAD R/W 1b0 Interrupt on asynchronous advance doorbell This bit is used as a doorbell by the software to instruct the host controller to issue an interrupt the next time it advances the asynchronous schedule 5 ASCH_EN R/W 1b0 Asynchronous schedule enable This bit controls whether the host controller skips the asynchronous schedule processing. 0: Do not process Asynchronous Schedule 1: Use the ASYNCLISTADDR register to access the asynchronous 4 H_SYSERR R/WC 1b0 Host system error The host controller sets this bit to 1 when a 3-2 FRL-SIZE R/W 2b00
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Technical Reference Manual serious error occurs during host system access involving the host controller module. Frame list rollover The host controller sets this bit to 1 when the frame list index rolls over from its maximum value to zero Port change detect The host controller sets this bit to 1 when any port has a change bit transition from 0 to 1. And, this bit is loaded with the OR of all of the PORTSC change bits. USB error interrupt The host controller sets this bit to 1 when completion of a USB transaction results in an error USB interrupt The host controller sets this bit to 1 upon completion of an USB transaction.

FRL_ROL

R/WC

1,B0

PO_CHG_DET

R/WC

1b0

USBERR_INT

R/WC

1b0

USB_INT

R/WC

1b0

13.5.2.7. Bit 31:6 5

USBINTR HC USB Interrupt Enable Register (Address = 018h) Table 13-7. HC USB Interrupt Enable Register Name Type Default value Description RO 26b0 Reserved INT_OAA_EN R/W 1b0 Interrupt on async advance enable When this bit is 1, and the interrupt on async advance bit in the USBSTS register is 1 also, the host controller will issue an interrupt at the next interrupt threshold. H_SYSERR_EN R/W 1b0 Host system error enable When this bit is 1, and the host system error status bit in the USBSTS register is 1 also, the host controller will issue an interrupt.. FRL_ROL_EN R/W 1b0 Frame list rollover enable When this bit is 1, and the frame list rollover bit in the USBSTS register is 1 also, the host controller will issue an interrupt. FRL_ROL R/W 1b 0 Port change interrupt enable When this bit is 1, and the port change detect bit in the USBSTS register is 1 also, the host controller will issue an interrupt. USBERR_INT_E R/W 1b0 USB error interrupt enable N When this bit is 1, and the USBERRINT bit in the USBSTS register is 1 also, the host controller will issue an interrupt at the next interrupt threshold. USB_INT_EN R/W 1b0 USB interrupt enable When this bit is 1, and the USBINT bit in the USBSTS register is 1 also, the host controller will issue an interrupt at the next interrupt
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Technical Reference Manual threshold. 13.5.2.8. Bit 31:14 13:0 FRINDEX HC Frame Index Register (Address = 01Ch) Table 13-8. HC Frame Index Register Name Type Default value Description RO 18b0 Reserved FRINDEX R/W 14b0 Frame index This register is used by the host controller to index the frame into the periodic frame list. It updates every 125 s. This register cannot be written unless the host controller is in the halted state.. PERIODICLISTBASE HC Periodic Frame List Base Address Register (Address = 024h) Table 13-9. HC Periodic Frame List base Address Register Name Type Default value Description PERI_BASADR R/W Undefined Periodic frame list base address This 32-bit register contains the beginning address of the periodic frame list in the system memory. These bits correspond to memory address signals[31:12]. RO 12b0 Reserved ASYNCLISTADDR HC Current Asynchronous List Address Register (Address = 028h) Table 13-10. HC Current Asynchronous List Address Register Name Type Default value Description Async_ladr R/W Undefined Current asynchronous list address This 32-bit register contains the address of the next asynchronous queue head to be executed. These bits correspond to memory address signals[31:5]. RO 5b0 Reserved PORTSC HC Port Status and Control Register (Address = 030h) Table 13-11. HC Port Status and Control Register Name Type Default value Description RO 11b0 Reserved HC_TST_PKDONE R/W 1b0 Data transfer is done for the test packet in the host port test control firmware It has completely sent the whole test patterns to FIFO for a PHY test packet mode by writing 1 to this bit. PORT_TEST R/W 4b0000 Port test control When this field is zero, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in the test mode and the specific test mode is indicated by a
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13.5.2.9.

Bit 31-12

11-0

13.5.2.10.

Bit 31:5

4:0 13.5.2.11. Bit 31:21 20

19:16

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Technical Reference Manual specific value. The encoding of the test mode bits are (0110 ~1111 bits are reserved) as follows. Bits Test mode 0000b Test mode is not enabled 0001b Test J_STATE 0010b Test K-STATE 0011b Test SE0_NAK 0100b Test Packet 0101b Test FORCE_ENABLE Please note that when this bit is set to 0100b (Test Packet), the test packet must be filled into FIFO by DMA first, then set HC_TST_PKDONE to 1. Reserved Line status These bits reflect the current logical levels of the D+ and D- signal lines. Reserved Port reset 0 = port is not in reset 1 = port is in reset The port enable bit and suspend bit of this register define the port states as follows: Bits[Port Enable, Suspend] Port State 0x Disable 10 Enable 11 Suspend When software writes 1 to this bit, the bus reset sequence as defined in the USB spec. is started. Software writes 0 to this bit to terminate the bus reset sequence. Software must keep this bit at 1 long enough to ensure reset sequence. Note: Before setting this bit, RUN/STOP bit should be set to 0. When in the suspend state, downstream propagation of data is blocked on this port, except for port reset. In the suspend state, the port is sensitive to resume detection. A write of 0 to this bit is ignored by the host controller. The host controller will unconditionally set this bit to 0 when: Software sets the force port resume bit to 0 (from 1) Software sets the port reset bit to 1 (from 0) Note: Before setting this bit, the RUN/STOP bit should be set to 0. Force port resume
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15:12 11:10 9 8

LINE_STS PO_RESET

RO RO RO R/W

4b0 2bxx 1b0 1b0

PO-SUSP

R/W

1b0

6
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F_PO_RESM

R/W

1b0

Technical Reference Manual 0 = No resume detected/driven on port 1 = Resume detected/driven on port Software sets this bit to 1 to resume signaling. The host controller sets this bit to 1 if a J-to-K transition is detected while the port is in the suspend state. When this bit transits to 1 because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to 1. Reserved Port enable/disable change 0 = No change 1 = Port enabled/disabled status has changed. Port enable/disable 0 = Disable 1 = Enable Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing 1 to this field. Connect status change 0 = No change 1 = Change current connect status Indicate a change has occurred in the current connect ion status of the port. Current connect status 0 = No device is present. 1 = Device is present on the port. This value reflects the current state of the port, and may not correspond directly to the event that caused the connect status changed bit to be set. When TST_FORCEEN is set to 1, this signal is the output of u_hdiscon.

5-4 3 2

PO_EN_CHG PO_EN

RO R/WC R/W

2b0 1b0 1b0

CONN_CHG

R/WC

1b0

CONN_STS

RO

1b0

13.5.2.12. Bit 31:7 6

5-4

Miscellaneous Register (Address = 040h) Table 13-12. Miscellaneous Register Name Type Default value Description RO 25b0 Reserved HostPhy_Suspend R/W 1b0 Host transceiver suspend mode Active high Put the transceiver into the suspend mode that draws the minimal power from power supplies. This bit is used in the host mode only. In addition, this bit is in the system clock domain instead of the UCLK clock domain. EOF2_Time R/W 2b0 EOF 2 timing points Controls EOF2 timing point before next SOF High-Speed EOF2 Time: 00b 2 clocks (30 MHz) 01b 4 clocks (30 MHz)
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Technical Reference Manual 10b 8 clocks (30 MHz) 11b 16 clocks (30 MHz) Full-Speed EOF2 Time: 00b 20 clocks (30 MHz) 01b 40 clocks (30 MHz) 10b 80 clocks (30 MHz) 11b 160 clocks (30 MHz) Low-Speed EOF2 Time: 00b 40 clocks (30 MHz) 01b 80 clocks (30 MHz) 10b 160 clocks (30 MHz) 11b 320clocks (30 MHz) EOF 1 timing points Controls EOF2 timing point before next SOF High-Speed EOF1 Time: 00b 540 clocks (30 MHz) 01b 360 clocks (30 MHz) 10b 180 clocks (30 MHz) 11b 720 clocks (30 MHz) Full-Speed EOF1 Time: 00b 1600 clocks (30 MHz) 01b 1400 clocks (30 MHz) 10b 1200 clocks (30 MHz) 11b 2100 clocks (30 MHz) Low-Speed EOF1 Time: 00b 3750 clocks (30 MHz) 01b 3500 clocks (30 MHz) 10b 3250 clocks (30 MHz) 11b 4200 clocks (30 MHz) Asynchronous Schedule Sleep Timer Controls the Asynchronous Schedule Sleep Timer 00b 5 s 01b 10 s 10b 15 s 11b 20 s

3-2

EOF1_Time

R/W

2b0

1-0

ASYN_SCH_SLPT

R/W

2b01

13.5.3. On-The-Go Controller Register (Address = 080h ~ 0BFh) Table 13-13. OTG Control/Status Register (Address = 080h) Bit 31:2 4 2322 Name HOST_SPD_TYP Type RO RO Default value 8b0 2b00 Description Reserved, and read as zeros. Host speed type Indicate speed type when the OTG device functioned as host 2b10: HS 2b00: FS 2b01: LS 2b11: Reserved Current ID
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ID

RO

Technical Reference Manual Record the current ID of the FOTG200 0: A-device 1: B-device Current role Record the current role of the FOTG200 0: Host 1: Device A-device Vbus valid This bit shows if the voltage on the Vbus is above the A-device Vbus valid threshold. A-device session valid This bit shows if the voltage on the Vbus is above the A-device session valid threshold. B-device session valid This bit indicates if the voltage on the Vbus is above the B-device session valid threshold. B-device session end This bit shows if the voltage on the Vbus is below the B-device session end threshold. Reserved for internal testing only. These bits should remain as zeros. Select a timer to filter out noise of HDISCON from UTMI+ 0: Approximated to 135 s 1: Approximated to 270 s Select a timer to filter out noise of Vbus_VLD from UTMI+ 0: Approximated to 135 s 1: Approximated to 472 s Select a timer to filter out noise of ID from UTMI+ 0: Approximated to 3 ms 1: Approximated to 4 ms SRP response type This bit determines the SRP type to which the A-device should respond. 0: A-device responds to Vbus pulsing 1: A-device responds to data-line pulsing Device SRP detection enable This bit determines if the A-device should detect SRP from B-device. 0: Disable SRP detection 1: Enable SRP detection indicates to A-device that the HNP function of B-device had been enabled. This bit should be set and cleared by software. 0: No effect
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20

CROLE

RO

19 18 17 16

VBUS_VLD A-SESS_VLD B_SESS_ VLD B_SESS_ END

RO RO RO RO

0 0 0 1

15:1 2 11

HDISCON_ FLT_SEL VBUS_FLT_SEL

R/W R/W

4b0 0

10

R/W

ID_FLT_SEL

R/W

1b0

A_SRP_RESP_TY P

R/W

A_SRP_ DET_EN

R/W

A_SET_B_HNP_E N

R/W

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Technical Reference Manual 1: Enable HNP feature of B-device This bit is valid while the current role is Adevice. This bit will be cleared to 0 only after A-device issues USB reset. A-device bus drop This bit determines if the A-device wants to power down the Vbus. Writing this bit to 1 will clear BUS_REQ of A-device. A-device bus request This bit determines if A-device should take control of the bus. 0: Stops driving Vbus and bus traffic 1: Drives Vbus and generates bus traffic Reserved, and read as zeros. B-device discharges Vbus This bit is used to determine if discharging Vbus is required after Vbus pulsing during SRP. 0: Vbus will not be discharged after Vbus pulsing. 1: Vbus will be discharged for 50 ms after Vbus pulsing. Inform B-device that it has been enabled to perform HNP This bit can be cleared only after B-device is reset by host. 0: Disable HNP 1: Enable HNP Device bus request This bit determines if the B-device should take control of the bus. After SRP pulsing is finished, this bit is automatically cleared by hardware. 0: Enable B-device to stop driving Vbus and generating bus traffic 1: Enable B-device requests to take control of bus

A_BUS_ DROP

R/W

A_BUS_REQ

R/W`

3 2`

B_DSCHRG_VBU S

RO R/W

0 0

B_HNP_EN

R/W

B_BUS_REQ

R/W

13.5.3.1.

OTG Interrupt Status Register (Address = 084h)

This register defines the interrupt status of the USBC. The interrupt status is not masked by interrupt enable. That is, if the corresponding events happen, the corresponding status bit is set to 1 even if the corresponding interrupt enable bit is 0. Bit 31:13 12 Name APLGRMV Table 13-14. OTG Interrupt Status Register Type Default value Description RO 0 Reserved, and read as zeros R/WC 0 Mini-A plug remove This bit is set to 1 once the mini-A plug is
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Technical Reference Manual removed. Writing 1 clears this bit and writing 0 takes no effect. Mini-B plug remove This bit is set to 1 once the mini-B plug is removed. Writing 1 clears this bit and writing 0 takes no effect. Over current detection This bit is set to 1 when Vbus does not reach VBUS_VLD within the expected time. Writing 1 clears this bit and writing 0 takes no effect. This bit is valid only when the current role is Adevice. ID change This bit is set to 1 when the current ID of the FOTG200 changes either from A-device to Bdevice or from B-device to A-device. Writing 1 clears this bit and writing 0 takes no effect Role change This bit is set to 1 when the current role of FOTG200 changes from host to peripheral or from peripheral to host. Writing 1 clears this bit Reserved, and read as zero VBus below B_SESS_END This bit is set to 1 when Vbus is below the B_SESS_END. Writing 1 clears this bit and writing 0 takes no effect. A-device Vbus error This bit is set to 1 when the OTG state machine moves to VBUS_ERROR state. Writing 1 clears this bit and writing 0 takes no effect. A-device detects SRP from B-device: This bit is set to 1 when the A-device detects SRP from B-device. Writing 1 clears this bit and writing a 0 takes no effect. Select a timer to filter out noise of HDISCON from UTMI+ 0: Approximated to 135 s 1: Approximated to 270 s Reserved, and read as zeros B-device SRP done This bit is set to 1 after the B-device has completed SRP signaling. Writing 1 clears this bit and writing a 0 takes no effect.

11

BPLGRMV

R/WC

10

OVC

R/WC

IDCHG

R/WC

RLCHG

R/WC

7 6

B_SESS_ END

RO R/WC

0 1b0

A_VBUS_ERR

R/WC

A_SRP_DET

R/WC

3-1 0

B_SRP_DN

RO R/WC

0 0

13.5.3.2.

OTG Interrupt Enable Register (Address = 088h)

This register defines the interrupt enable of interrupt events. This register will not mask the interrupt status.

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Technical Reference Manual It only masks the interrupt generation. Table 13-15. OTG Interrupt Enable Register Description Type Default value Reserved, and read as zeros RO 0 R/W R/W R/W R/W R/W RO R/W R/W R/W RO R/W 0 0 0 0 0 0 0 0 0 0 0 Enable APLGRMV interrupt Enable BPLGRMV interrupt Enable OVC interrupt Enable IDCHG interrupt Enable RLCHG interrupt Reserved, and read as zero Enable B_SESS_END interrupt Enable A_VBUS_ERR interrupt Enable A_SRP_DET interrupt Reserved, and read as zeros Enable B_SRP_DN interrupt

Bit 31:13 12 11 10 9 8 7 6 5 4 3-1 0

Name APLGRMV_EN BPLGRMV_EN OVC_EN IDCHG_EN RLCHG_EN -

B_SESS_ END_EN A_VBUS_ERR_EN A_SRP_DET_EN B_SRP_DN-EN

13.5.4. Global Controller Register (Address = 0C0h ~ 0FFh) 13.5.4.1. HC/OTG/DEV Interrupt Status Register (Address = 0C0h) Table 13-16. HC/OTG/DEV Interrupt Status Register Bit Name Type Default value Description 31:3 RO 29b0 Reserved, and read as zeros 2 HC_INT R/WC 1b0 HC interrupt This bit is set to 1 when an interrupt is issued from the host controller block. 1 OTG_INT R/WC 1b0 OTG interrupt This bit is set to 1 when an interrupt is issued from the OTG controller block. 0 DEV_INT R/WC 1b0 Device interrupt This bit is set to 1 when an interrupt is issued from the device controller block. 13.5.4.2. Bit 31:4 3 Mask of HC/OTG/DEV Interrupt (Address = 0C4h) Table 13-17. Mask of HC/OTG/DEV Interrupt Name Type Default value Description Reserved INT_POLARITY R/W 1b0 Control the polarity of the system interrupt signal sys_int_n 0: Active Low (default) 1: Active High MHC_INT R/W 1b0 Mask the interrupt bits of the HC interrupt 0: Enable the corresponding interrupt
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Technical Reference Manual 1: Disable the corresponding interrupt Mask the interrupt bits of the OTG interrupt 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt Mask the interrupt bits of the Device interrupt 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt

1 0

MOTG_INT MDEV_INT

R/W R/W

1b0 1b0

13.5.5. Device Controller Registers (Address = 100h ~ 1FFh) 13.5.5.1. Main Control Register (Address = 100h) Table 13-18. Main Control Register Bit Name Type Default value Description 31:10 Reserved 9 FORCE_FS R/W 1b0 Force the device to full-speed Setting this bit to 1 will disable the high-speed negotiation when reset from the USB host starts, thus forces the USB OTG to negotiate in full-speed when in the device mode. If this bit is cleared to zero, the USB OTG should resume a high-speed negotiation when reset from USB host starts. Please note that the user can only modify this bit while the un-plug bit is set. Otherwise it will cause the unexpected results. 8 R Reserved and read as 0 7 RISC51_INF R/W 1b0 RISC51 interface enable 0: CPU uses 32-bit interface. 1: CPU uses RISC51 interface 6 HS-EN RO 1b0 High speed status 0: Device is in full speed mode. 1: Device is in high speed mode. 5 CHIP_EN R/W 1b0 Chip enable Writing 1 enables write cycle of FIFO controller. (Please do not write 0 while in normal operation mode) 4 SFRST R/W 1b0 Device software reset Writing 1 sets a software-initiated reset to the USB OTG device. This bit cannot be set when the USB OTG is in suspend mode, because the u_clk is stopped. Setting this bit has the following effects: pw_save output will be de-asserted Chirp sequence will be terminated Command FIFO will be cleared Frame Number Register and SOF Timer Mask Register will be cleared Please note that the data FIFO status will not be cleared. (Software reset is self-cleared.) 3 GOSUSP R/W 1b0 Go suspend Writing 1 will activate the suspend mode of the
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Technical Reference Manual PHY. Global interrupt enable Writing 1 enables all interrupts. The individual interrupts can be masked by setting the corresponding bits in the interrupt mask register (index 11H ~ 17H). Half speed enable 0: FIFO controller asserts the ACK to DMA continuously 1: FIFO controller asserts the ACK to DMA once every two clock cycles This bit is set to 1 while doing FPGA implementation. Capability of remote wakeup 1 indicates that the USB OTG has the capability of being wakened up by wakeup signal.

GLINT_EN

R/W

1b0

HALF_SPEED

R/W

1b0

CAP_RMWAKUP

R/W

1b0

13.5.5.2.

Device Address Register (Address = 104h) Table 13-19. Device address register

Bit 31:8 7

Name AFT_CONF

Type R/W

Default value 1b0 1b0(U)

6-0

DEVADR

R/W

7b0 7b0(U)

Description Reserved After set configuration A 1 indicates that the device has successfully executed a SET_CONFIGURATION command. The USB OTG device will not response to any non-control transfer before this bit is set Device address Records the latest USB device address for each SET_ADDRESS.

13.5.5.3. Bit 31:7 6 5

Test Register (Address = 108h) Table 13-20. Test Register Name Type Default value Description Reserved DISGENSOF R/W 1b0 Disable generation of SOF Always use SOF issued by the host instead of the self-generated SOF TST_MOD R/W 1b0 Test mode A 1 turns the test_mode on. When this bit is set to 1, the FOTG200 will enter the test mode. In the normal mode, the FOTG200 uses a counter for 10 ms USB reset detection. The count is usually a large number. In the test mode, the FOTG200 will use a smaller counter for a USB reset detection to save the test cycle on the test machine.

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Technical Reference Manual 4 3 2 TST_DISTOG TST_DISCRC TST_CLREA R/W R/W R/WC 1b0 1b0 1b0 Disable toggle sequence 1 disables the toggle sequence Disable CRC When setting this bit as 1, the FOTG200 will not append the CRC for upstream packets. Clear external side address Writing 1 then 0 clears the external side address for the loop back test. (This bit is selfclear) Loop back test for control endpoint 1 indicates the loop back test for control transfers. Clear FIFO Writing 1 will clear all FIFO counters and the location counters of the PAM (this bit is selfclear).

1 0

TST_LPCX TST_CLRFF

R/W R/W

1b0 1b0

13.5.5.4. Bit 31:14 13-11 10-0

SOF Frame Number Register (Address = 10Ch) Table 13-21. SOF Frame Number Register Name Type Default value Description Reserved USOFN RO 3b0 SOF micro frame number bits[2:0] 3b0(U) Record the micro frame number for the high speed SOFN RO 11b0 SOF frame number bits[10:0] 11b0(S) Record the frame number for the high speed and full speed SOF Mask Timer Register (Address = 110h) Table 13-22. SOF Mask Time Register Name Type Default value Description Reserved SOFTM R/W 16h44C SOF mask timer 16h44C(S) Time since the last SOF in the 30 MHz clock bit PHY Test Mode Selector Register (Address = 114h) Table 13-23. PHY test mode register Name Type Default value Description Reserved TST_PKT R/W 1b0 Test mode for packet Upon writing 1 to this bit, the USB OTG repetitively sends the packet defined in the UTMI specification to the transceiver. After the set_feature command shows the test mode and index Test_Packet have been decoded, this bit will be asserted. TST_SE0NAK R/W 1b0 Upon writing 1, the D+/D- lines are set to the HS, quiescent state. The device only responds to a valid HS IN token and always responds to
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Technical Reference Manual the IN token with NAK. Upon writing 1, the D+/D- is set to the highspeed K state. Upon writing 1, the D+/D- is set to the highspeed J state. With UNPLUG set to logic 1, the device controller will set PHY in the non-driving mode, to emulate the detachment of a device even if it is really plugged. The USB host will not detect plugging of a device. Such an event is called soft-detachment. After a hardware reset, the UNPLUG will be logic 1 and therefore the device is softdetached. To let USB host detect the attachment of a device, the PHY must drive D+ and D- in the manner defined in the USB specification. To let the PHY drive D+ and D-, the AP should clear UNPLUG after the hardware reset. If the AP does not clear the UNPLUG bit, the device will be always softdetached and the USB host will never detect the attachment of the device.

2 1 0

TST_KSTA TST_JSTA UNPLUG

R/W R/W R/W

1b0 1b0 1b1 1b0(U)

13.5.5.7. Bit 31:6 5

Vendor-Specific I/O Control Register (Address = 118h) Table 13-24. Vendor-specific I/O control register Name Type Default value Description Reserved VCTLOAD_N R/W 1b1 Vendor-specific test mode control load This bit controls the active low output u_vctload_n to PHY. 1 in this bit makes u_vctload_n output 1. When this bit is cleared, u_vctload_n outputs 0. Vendor-specific test mode control The programmed value is delivered to PHY via the output u_vctl.

4-0

VCTL

R/W

5b0

13.5.5.8. Bit 31:8 5

7-0

CX Configuration and Status Register (Address = 11Ch) Table 13-25. CX Configuration and status register Name Type Default value Description Reserved VCTLOAD_N R/W 1b1 Vendor-specific test mode control load This bit controls the active low output u_vctload_n to PHY. 1 in this bit makes u_vctload_n output 1. When this bit is cleared, u_vctload_n outputs 0. VSTA RO Depend on Vendor-specific test mode status reset value of PHY
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Technical Reference Manual 13.5.5.9. Bit 31 30-24 23-12 11-8 7-6 5 4 3 Configuration and FIFO Empty Status Register (Address = 120h) Table 13-26. Configuration and FIFO Status Register Name Type Default value Description Reserved CX_FNT RO 7b0 CX FIFO Byte Count Reserved F_EMP RO 4b1111 FIFO is empty. These bits are for FWs review if a FIFO is fully empty. Reserved CX_EMP RO 1b1 CX FIFO is empty. 1: the endpoint 0 FIFO is empty. CX_FUL RO 1b0 CX FIFO is full. 1: the endpoint 0 FIFO is full. CX_CLR R/W 1b0 Clear CX FIFO data Writing 1 clears the data in Endpoint 0 FIFO. Please note that for endpoint 0, all the data in the FIFO will be cleared no matter whether the previous SETUP or IN or OUT transaction has been completed or not (this bit is self-clear). CX_STL R/W 1b0 Stall CX 1b0(U) Writing 1 to this bit can stall endpoint 0. The stall status will be cleared by the next setup transaction. This bit is cleared automatically when transaction for endpoint 0 is finished. Upon detection of a bus reset, the firmware should clear this bit. (Note: While setting this bit, CX_DONE must be set in the same write operation) TST_PKDONE R/W 1b0 Data transfer is done for test packet. Firmware has completely sent the whole test patterns to the endpoint 0 FIFO for a PHY test by writing 1 to this bit. This bit is cleared by a hardware reset. CX-DONE R/W 1b0 Data transfer is done for CX. 1b0(U) Firmware has finished the whole packet transaction for endpoint 0 by writing 1 to this bit. This bit is cleared by a hardware reset. This bit is cleared by an internal signal p_endcx or p_comfail. Idle Counter Register (Address = 124h) Table 13-27. Idle counter register Name Type Default value Description Reserved IDLE_CNT R/W 3b0 Control the timing delay from the time indicated in the GOSUSP bit of main control register to the time the device entered suspend mode. The

13.5.5.10. Bit 31-3 2-0

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Technical Reference Manual delay is denoted as tsusp_delay below. 000: tsusp_delay = 0 ms 001: tsusp_delay = 1 ms 010: tsusp_delay = 2 ms 011: tsusp_delay = 3 ms 100: tsusp_delay = 4 ms 101: tsusp_delay = 5 ms 110: tsusp_delay = 6 ms 111: tsusp_delay = 7 ms Note: USB 2.0 specification defines TSUSP to mandate that the device should enter a suspend mode no later than 10 ms after the D+/Dreaches continuous idle state. The firmware programmer should be cautious in programming the value of tsusp_delay. 13.5.5.11. Bit 31-3 2 1 0 Mask of Interrupt Group Register (Address = 130h) Table 13-28. Mask of interrupt group register Name Type Default value Description Reserved MINT_G2 R/W 1b0 Mask of source group 2 interrupt 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt MINT_G1 R/W 1b0 Mask of source group 1 interrupt 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt MINT_GO R/W 1b0 Mask of source group 0 interrupt 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt

13.5.5.12. Mask of Interrupt Source Group 0 Register (Address = 134h) Mask endpoint 0 setup data received interrupt bit 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt Bit 31-6 5 Table 13-29. Mask of interrupt source group 0 register Name Type Default value Description Reserved MCX_COMABORT R/W 1b0 Mask interrupt of control transfer command _INT abort 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt MCX_COMFAIL_IN R/W 1b0 Mask interrupt of host emits extra IN or OUT T data interrupt bit 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt MCX_COMEND R/W 1b0 Mask the host end of command (entering status stage) interrupt bit

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Technical Reference Manual 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt Mask the interrupt bits of endpoint 0 for OUT 0: Enable the corresponding interrupt 1: Disable the corresponding interrupt Mask the interrupt bits of endpoint 0 for IN Mask endpoint 0 setup data received interrupt bit

2 1 0

MCX_OUT_INT MCX_IN_INT MCX_SETUP_INT

R/W R/W R/W

1b0 1b0 1b0

13.5.5.13. Bit 31:20 19 18 17 16 15:8 7 6 5 4 3 2 1 0

Mask of Interrupt Source Group 1 Register (Address = 138h) Table 13-30. Mask of interrupt source group 1 register Name Type Default value Description Reserved MF3_IN_INT R/W 1b1 Mask the IN interrupt bits of FIFO 3 MF2_IN_INT R/W 1b1 Mask the IN interrupt bits of FIFO 2 MF1_IN_INT R/W 1b1 Mask the IN interrupt bits of FIFO 1 MF0_IN_INT R/W 1b1 Mask the IN interrupt bits of FIFO 0 Reserved MF3_SPK_INT R/W 1b1 Mask the short packet interrupt of FIFO 3 MF3_OUT_INT R/W 1b1 Mask the OUT interrupt of FIFO 3 MF2_SPK_INT R/W 1b1 Mask the short packet interrupt of FIFO 2 MF2_OUT_INT R/W 1b1 Mask the OUT interrupt of FIFO 2 MF1_SPK_INT R/W 1b1 Mask the short packet interrupt of FIFO 1 MF1_OUT_INT R/W 1b1 Mask the OUT interrupt of FIFO 1 MF0_SPK_INT R/W 1b1 Mask the short packet interrupt of FIFO 0 MF0_OUT_INT R/W 1b1 Mask the OUT interrupt of FIFO 0

13.5.5.14. Bit 31:11 10 9 8 7 6 5 6 5 4 3 2 1 0

Mask of Interrupt Source Group 2 Register (Address = 13Ch) Table 13-31. Mask of interrupt source group 2 register Name Type Default value Description Reserved MDev_Wakeup_by R/W 1b0 Mask Dev_Wakeup_byVBUS Interrupt VBUS MDev_Idle R/W 1b0 Mask Dev_Idle Interrupt MDMA_ERROR R/W 1b0 Mask DMA error interrupt MDMA_CMPLT R/W 1b0 Mask DMA completion interrupt MRX0BYTE_INT R/W 1b0 Mask received zero-length data packet interrupt MTX0BYTE_INT R/W 1b0 Mask transferred zero-length data packet interrupt MF3_OUT_INT R/W 1b1 Mask the OUT interrupt of FIFO 3 MF2_SPK_INT R/W 1b1 Mask the short packet interrupt of FIFO 2 MSEQ_ABORT_IN R/W 1b0 Mask ISO sequential abort interrupt T MSEQ_ERR_INT R/W 1b0 Mask ISO sequential error interrupt MRESM_INT R/W 1b0 Mask resume interrupt MSUSP_INT R/W 1b0 Mask suspend interrupt MUSBRST_INT R/W 1b0 Mask USB reset interrupt Interrupt Group Register (Address = 140h)
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Technical Reference Manual Table 13-32. Interrupt group register Type Default value Description Reserved RO 1b0 Indicate some interrupts occurred in Group 2 RO 1b0 Indicate some interrupts occurred in Group 1 RO 1b0 Indicate some interrupts occurred in Group 0

Bit 31:3 2 1 0

Name INT_G2 INT_G1 INT_G0

13.5.5.16. Bit 31:6 5

4 3 2 1

Interrupt Source Group 0 Register (Address = 144h) Table 13-33. Interrupt source group 0 register Name Type Default value Description Reserved bits CX_COMABT_ R/W 1b0 Indicate a command abort event occurred. For INT interrupts recorded in this source register, command abort interrupt gets the highest priority. For a command abort interrupt, the AP should only clear the CX_COMABT_INT bit. All other operations are unnecessary and should be avoided. In general, the command abort interrupt will be accompanied by CX_SETUP_INT. The AP should first service the command abort interrupt to clear CX_COMABT_INT, because CXF FIFO is frozen for AP access when CX_COMABT_INT remains at one. To get the 8-byte for SETUP to command abort, AP should clear CX_COMABT_INT first. CX_COMFAIL_INT RO 1b0 Indicate the control transfer is abnormally terminated CX_COMEND_INT RO 1b0 Indicate the control transfer has entered status stage CX_OUT_INT RO 1b0 Indicate the control transfer contains valid data for control-write transfers CX_IN_INT RO 1b0 Indicate that firmware should write data for control-read transfer to control transfer FIFO. For control reads with length less than or equal to 64 bytes, this bit will never be asserted. The firmware will decode the 8-byte data sent in SETUP stage of control transfer. The firmware should write the first payload of data into control transfer FIFO if the 8-byte indicates control-read transfer without the assertion of this bit. This bit will be asserted only when the length of controlread transfer is greater than 64 bytes and USB host has successfully received the data of previous packet. For example, for a 65-byte control-read transfer, the firmware should automatically write first 64 bytes after it decodes 8-byte of the setup data. The firmware will be interrupted to write the 65th byte when the USB
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Technical Reference Manual host acknowledges the first 64 bytes. This bit will remain asserted until firmware starts to read data from control transfer FIFO of device.

CX_SETUP_INT

RO

1b0

13.5.5.17. Bit 31:20 19 18 17 16 15:8 7 6 5 4 3 2 1 0

Interrupt Source Group 1 Register (Address = 148h) Table 13-34. Interrupt source group 1 register Name Type Default value Description Reserved F3_IN_INT RO 1b0 1: FIFO 3 is ready to be written. F2_IN_INT RO 1b0 1: FIFO 2 is ready to be written. F1_IN_INT RO 1b0 1: FIFO 1 is ready to be written. F0_IN_INT RO 1b0 1: FIFO 0 is ready to be written. Reserved Reserved bits F3_SPK_INT RO 1b0 This bit becomes 1 when short packet data is received in FIFO 3. F3_OUT_INT RO 1b0 This bit becomes 1 when FIFO 3 is ready to be read. F2_SPK_INT RO 1b0 This bit becomes 1 when short packet data is received in FIFO 2. F2_OUT_INT RO 1b0 This bit becomes 1 when FIFO 2 is ready to be read. F1_SPK_INT RO 1b0 This bit becomes 1 when short packet data is received in FIFO 1. F1_OUT_INT RO 1b0 This bit becomes 1 when FIFO 1 is ready to be read. F0_SPK_INT RO 1b0 This bit becomes 1 when short packet data is received in FIFO 0. F0_OUT_INT RO 1b0 This bit becomes 1 when FIFO 0 is ready to be read.

13.5.5.18. Bit 31:11 10 9

Interrupt Source Group 2 Register (Address = 14Ch Table 13-35. Interrupt source group 2 register Name Type Default value Description Reserved Dev_Wakeup_ RO 1;b0 Device wakeup by Vbus byVBUS When the device is in idle state and the VBUSVALID signal is high, this bit is set to 1b1. Dev_Idle RO 1b0 Device is in idle state. There are two conditions under which this bit is active: 1. A-device and B-device state machine are both in the idle state, 2. the SessEnd signal is high. DMA_ERROR R/W 1b0 DMA error interrupt DMA operation cannot be finished normally, and an error signal is received. When the CPU initiates DMA to fill up or read out the FIFO of the device, and the DMA controller gets an error response from the system bus, this bit will be
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Technical Reference Manual set. This bit can only be cleared by the firmware. This bit is not affected by a USB bus reset. DMA completion interrupt DMA operation has finished normally. When the CPU initiates the DMA to fill up or read out the FIFO of the device, this bit will be set after mission completion. This bit can only be cleared by the firmware. This bit is not affected by a USB bus reset. Received zero-length data packet interrupt Device received zero-length data packet from the USB host. When the device receives 0length data packet from the USB host, this bit will be set. The firmware may further check register 150H to determine which endpoint receives zero-length data packet from the USB host. When the interrupt occurs, the device will NAK the next OUT transaction to the same endpoint until the corresponding bit (in 150h) is cleared by the firmware. This bit is not affected by a USB bus reset. Transferred zero-length data packet interrupt: The device returned a zero-length data packet to the USB host. This bit will be set under the following two cases: When the USB host issues an IN transaction to an isochronous endpoint, while the device is not ready to return the data, the device will transfer a zero-length data packet to the USB host. In such case, this bit will be set. When TX0BYTE_IEPx bit is set, after the data of the endpoint in FIFO is transferred, the FOTG200 will return a zero-length data packet to the next IN transaction to the same endpoint. The firmware may further check register 154H to determine which endpoint returns a zerolength data packet to the USB host. After the AP serviced the interrupt request, this bit must be cleared by the firmware. This bit is not affected by a USB bus reset. ISO sequential abort interrupt High bandwidth isochronous sequential abort When a device detects an incomplete DATA PID sequence during a micro frame, this bit will be set. For example, if a device detects an MDATA followed by an SOF, this is taken as sequential abort. The firmware should further
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DMA_CMPLT

R/W

1b0

RX0BYTE_INT

R/W

1b0

TX0BYTE_INT

R/W

1b0

ISO_SEQ_ABORT _INT

R/W

1b0

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Technical Reference Manual check register 154h to determine which endpoint receives an isochronous sequential abort. After AP serviced the interrupt request, this bit must be cleared by the firmware. This bit is not affected by a USB bus reset. ISO sequential error interrupt High bandwidth isochronous sequential abort When a device detects an incomplete DATA PID sequence during a micro frame, this bit will be set. For example, if a device detects an MDATA followed by an SOF, this is taken as sequential abort. The firmware should further check register 154h to determine which endpoint receives an isochronous sequential abort. After AP serviced the interrupt request, this bit must be cleared by the firmware. This bit is not affected by a USB bus reset. Resume interrupt Resume-state-change interrupt bit When the device detects a resume event from host, this bit will be set. After the AP services the interrupt request, this bit must be cleared by the firmware. When a USB bus reset occurs, it will also be cleared Suspend interrupt Suspend-state-change interrupt bit When the USB bus remains in an idle state for over 3 ms, this bit will be set. This bit must be cleared before the firmware sets the bit GOSUSP of the register 0C0H. This bit will also be cleared when a USB bus reset or resume occurs USB reset interrupt Bus reset interrupt bit When device detects USB bus reset from host, this bit will be set. When AP services the interrupt request, this bit must be cleared by the firmware.

ISO_SEQ_ERR_IN T

R/W

1b0

RESM_INT

R/W

1b0

SUSP_INT

R/W

1b0 1b0(U)

USBRST_INT

R/W

1b0 1b1(U)

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Receive Zero-Length Data Packet Register (Address = 150h) Table 13-36. Receive zero-length data packet register Name Type Default value Description Reserved RX0BYTE_EP8 R/W 1b0 Endpoint 8 receives a zero-length data packet. RX0BYTE_EP7 R/W 1b0 Endpoint 7 receives a zero-length data packet. RX0BYTE_EP6 R/W 1b0 Endpoint 6 receives a zero-length data packet. RX0BYTE_EP5 R/W 1b0 Endpoint 5 receives a zero-length data packet. RX0BYTE_EP4 R/W 1b0 Endpoint 4 receives a zero-length data packet. RX0BYTE_EP3 R/W 1b0 Endpoint 3 receives a zero-length data packet
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Technical Reference Manual 1 0 RX0BYTE_EP2 RX0BYTE_EP1 R/W R/W 1b0 1b0 Endpoint 2 receives a zero-length data packet. Endpoint 1 receives a zero-length data packet.

13.5.5.20. Bit 31:8 7 6 5 4 3 2 1 0

Transfer Zero-length Data Packet Register (Address = 154h) Table 13-37. Transfer zero-length data packet register Name Type Default value Description Reserved TX0BYTE_EP8 R/W 1b0 Endpoint 8 transfers zero-length data packet. TX0BYTE_EP7 R/W 1b0 Endpoint 7 transfers zero-length data packet. TX0BYTE_EP6 R/W 1b0 Endpoint 6 transfers zero-length data packet. TX0BYTE_EP5 R/W 1b0 Endpoint 5 transfers zero-length data packet. TX0BYTE_EP4 R/W 1b0 Endpoint 4 transfers zero-length data packet. TX0BYTE_EP3 R/W 1b0 Endpoint 3 transfers zero-length data packet. TX0BYTE_EP2 R/W 1b0 Endpoint 2 transfers zero-length data packet. TX0BYTE_EP1 R/W 1b0 Endpoint 1 transfers zero-length data packet. Isochronous Sequential Error/Abort Register (Address = 158h) Table 13-38. Isochronous sequential error/abort register Name Type Default value Description Reserved ISO_SEQ_ERR_EP8 R/W 1b0 Endpoint 8 encounters an isochronous sequential error. ISO_SEQ_ERR_EP7 R/W 1b0 Endpoint 7 encounters an isochronous sequential error. ISO_SEQ_ERR_EP6 R/W 1b0 Endpoint 6 encounters an isochronous sequential error. ISO_SEQ_ERR_EP5 R/W 1b0 Endpoint 5 encounters an isochronous sequential error. ISO_SEQ_ERR_EP4 R/W 1b0 Endpoint 4 encounters an isochronous sequential error. ISO_SEQ_ERR_EP3 R/W 1b0 Endpoint 3 encounters an isochronous sequential error. ISO_SEQ_ERR_EP2 R/W 1b0 Endpoint 2 encounters an isochronous sequential error. ISO_SEQ_ERR_EP1 R/W 1b0 Endpoint 1 encounters an isochronous sequential error. Reserved ISO_ABT_ERR_EP8 R/W 1b0 Endpoint 8 encounters an isochronous sequential abort. ISO_ABT_ERR_EP7 R/W 1b0 Endpoint 7 encounters an isochronous sequential abort. ISO_ABT_ERR_EP6 R/W 1b0 Endpoint 6 encounters an isochronous sequential abort. ISO_ABT_ERR_EP5 R/W 1b0 Endpoint 5 encounters an isochronous sequential abort. ISO_ABT_ERR_EP4 R/W 1b0 Endpoint 4 encounters an isochronous sequential abort. ISO_ABT_ERR_EP3 R/W 1b0 Endpoint 3 encounters an isochronous
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Technical Reference Manual sequential abort.h Endpoint 2 encounters an isochronous sequential abort. Endpoint 1 encounters an isochronous sequential abort.

1 0

ISO_ABT_ERR_EP2 ISO_ABT_ERR_EP1

R/W R/W

1b0 1b0

13.5.6. In Endpoint x MaxPacket Size Register (One per Endpoint, x = 1 ~ 8) (Address = 160 + 4(x-1)h) Table 13-39. In endpoint x maxpacket size register Name Type Default value Description Reserved TX0BYTE_IEPx R/W 1b0 Transfer a zero-length data packet from Endpoint x to USB Host . This bit should be set after the last packet of a transaction is sent to FIFO. After all data of the endpoint in FIFO is transferred, the device will return a zerolength data packet to the next IN transaction at the same endpoint. The AP should not send the next packet to the same endpoint until the TX0BYTE_INT for the same endpoint occurred. This bit is cleared by hardware automatically when a TX0BYTE_INT occurred. TX_NUM_HBW_IEPx R/W 2b0 Transaction number for high bandwidth Endpoint xTX_NUM_HBW[1:0] (Only valid for Isochronous transfer) 0 0, 0 1: Indicate endpoint x is not in high bandwidth 1 0: Two transactions per micro frame 1 1: Three transactions per micro frame RSTG_IEPx R/W 1b0 Reset toggle sequence for IN Endpoint x Firmware resets the toggle bit of the indexed endpoint x by writing 1 to this bit. This bit should be cleared by firmware. STL_IEPx R/W 1b0 Stall IN Endpoint x 1b0(U) The indexed endpoint x can be stalled by writing 1 to this bit. The stalled status of the indexed endpoint x can be cleared by writing 0 to this bit. Before setting of this bit, one should check FIFO empty register (0x120) and make sure that related FIFO is empty. MAXPS_IEPx R/W 11h200 Max packet size of IN Endpoint x The maximum packet size of endpoint x, capable of sending or receiving data

Bit 31:16 15

14:13

12

11

10:0

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Technical Reference Manual smaller than or equal to this size. Note: This size must not exceed the FIFO size. 13.5.7. OUT Endpoint x MaxPacketSize Register (One per Endpoint, x = 1 ~ 8) (Address = 180 + 4(x-1)h) Table 13-40. Out endpoint x maxpacketsize register Name Type Default value Description Reserved RSTG_OEPx R/W 1b0 Reset toggle sequence for OUT Endpoint x Firmware that resets the toggle bit of the indexed endpoint x by writing 1 to this bit. This bit should also be cleared by firmware. STL_OEPx R/W 1b0 Stall OUT Endpoint x Writing 1 to STL_OEP will stall endpoint x. The stalled status of the indexed endpoint x can be cleared by writing 0 to this bit. MAXPS_OEPx R/W 11h200 Max packet size of OUT Endpoint x The maximum packet size of endpoint x means sending or receiving data smaller than or equal to this size.

Bit 31:13 12

11

10:0

13.5.8. Endpoint 1 ~ 4 Map Register (Address = 1A0h) Table 13-41. Endpoint 1~4 map register Bit Name Type Default value Description 31:30 Reserved 29:28 FNO_OEP4 R/W 2b11 FIFO number for OUT Endpoint 4 Record the physical FIFO number for logical OUT endpoint 4 27:26 Reserved 25:24 FNO_IEP4 R/W 2b11 FIFO number for IN Endpoint 4 Records the physical FIFO number for logical IN endpoint 4 23:22 Reserved 21:20 FNO_OEP3 R/W 2b11 FIFO Number for OUT Endpoint 3 Record the physical FIFO number for logical OUT endpoint 3 19:18 Reserved 17:16 FNO_IEP3 R/W 2b11 FIFO number for IN Endpoint 3 Record the physical FIFO number for logical IN endpoint 3 15:14 Reserved 13:12 FNO_OEP2 R/W 2b11 FIFO number for OUT Endpoint 2 Record the physical FIFO number for logical OUT endpoint 2 11:10 Reserved 9:8 FNO_IEP2 R/W 2b11 FIFO number for IN Endpoint 2
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Technical Reference Manual Records the physical FIFO number for logical IN endpoint 2 Reserved FIFO number for OUT Endpoint 1 Records the physical FIFO number for logical OUT endpoint 1 Reserved FIFO number for IN Endpoint 1 Records the physical FIFO number for logical IN endpoint 1

7:6 5:4 3:2 1:0

FNO_OEP1 FNO_IEP1

R/W R/W

2b11 2b11

13.5.9. Endpoint 5 ~ 8 Map Register (Address = 1A4h) Table 13-42. Endpoint 5~8 map register Bit Name Type Default value Description 31:30 Reserved 29:28 FNO_OEP8 R/W 2b11 FIFO number for OUT Endpoint 8 Record the physical FIFO number for logical OUT Endpoint 8 27:26 Reserved 25:24 FNO_IEP8 R/W 2b11 FIFO number for IN Endpoint 8 Record the physical FIFO number for logical IN Endpoint 8 23:22 Reserved 21:20 FNO_OEP7 R/W 2b11 FIFO number for OUT Endpoint 7 Record the physical FIFO number for logical OUT Endpoint 7 19:18 Reserved 17:16 FNO_IEP7 R/W 2b11 FIFO number for IN Endpoint 7 Record the physical FIFO number for logical IN Endpoint 7 15:14 Reserved 13:12 FNO_OEP6 R/W 2b11 FIFO number for OUT Endpoint 6 Record the physical FIFO number for logical OUT Endpoint 6 11:10 Reserved 9:8 FNO_IEP6 R/W 2b11 FIFO number for IN Endpoint 6 Record the physical FIFO number for logical IN Endpoint 6 7:6 Reserved 5:4 FNO_OEP5 R/W 2b11 FIFO number for OUT Endpoint 5 Record the physical FIFO number for logical OUT Endpoint 5 3:2 Reserved 1:0 FNO_IEP5 R/W 2b11 FIFO number for IN Endpoint 5 Record the physical FIFO number for logical IN Endpoint 5 13.5.10. FIFO Map Register (Address = 1A8h)

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Technical Reference Manual Table 13-43. FIFO map register Type Default value Description Reserved R/W 2b0 FIFO 3 direction Data transfer direction 2b00: Out 2b01: In 2b10: Bi-directional 2b11: Not allowed R/W 4b1111 Endpoint number for FIFO 3 Record the physical endpoint number for physical FIFO 3 Reserved R/W 2b0 FIFO 2 direction Data transfer direction 2b00: Out 2b01: In 2b10: Bi-directional 2b11: Not allowed R/W 4b1111 Endpoint number for FIFO 2: Records the physical endpoint number for physical FIFO 2 Reserved R/W 2b0 FIFO 1 Direction Data transfer direction 2b00: Out 2b01: In 2b10: Bi-directional 2b11: Not allowed R/W 4b1111 Endpoint number for FIFO 1 Record the physical endpoint number for physical FIFO 1 Reserved R/W 2b0 FIFO 0 direction Data transfer direction 2b00: Out 2b01: In 2b10: Bi-directional 2b11: Not allowed R/W 4b1111 Endpoint number for FIFO 0 Record the physical endpoint number for physical FIFO 0

Bit 31:30 29:28

Name Dir_FIFO3

27:24 23:22 21:20

EPNO_FIFO3 Dir_FIFO2

19:16 15:14 13:12

EPNO_FIFO2 Dir_FIFO1

11:8 7:6 5:4

EPNO_FIFO1 Dir_FIFO0

3:0

EPNO_FIFO0

13.5.11. Bit 31:30 29

FIFO Configuration (Address = 1ACH) Table 13-44. FIFO configuration Name Type Default value Description Reserved EN_F3 R/W 1b0 Enable FIFO 3

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Technical Reference Manual 1: FIFO 3 is enabled Block size of FIFO 3 BLKSIZE_F3 = 0: For transferring packets whose maximum packet size is smaller than or equal to 512 bytes. BLKSIZE_F3 = 1: For transferring packets whose maximum packet size is smaller than or equal to 1024 bytes and greater than 512 bytes. Block number of FIFO 3 BLKNUM_F3 = 00: Single block BLKNUM_F3 = 01: Double blocks BLKNUM_F3 = 10: Triple blocks BLKNUM_F3 = 11: Reserved Transfer type of FIFO 3 Indicates the transfer type used for a FIFO 3 transfer TYP_F3 = 00: Reserved TYP_F3 = 01: Isochronous type TYP_F3 = 10: Bulk type TYP_F3 = 11: Interrupt type Reserved Enable FIFO 2 1: FIFO 2 is enabled. Block size of FIFO 2 BLKSIZE_F2 = 0: For transferring packets whose maximum packet size is smaller than or equal to 512 bytes. BLKSIZE_F2 = 1: For transferring packets whose maximum packet size is smaller than or equal to 1024 bytes and greater than 512 bytes. Block number of FIFO 2 BLKNUM_F2 = 00: Single block BLKNUM_F2 = 01: Double blocks BLKNUM_F2 = 10: Triple blocks BLKNUM_F2 = 11: Reserved Transfer type of FIFO 2 Indicate the transfer type used for a FIFO 2 transfer TYP_F2 = 00: Reserved TYP_F2 = 01: Isochronous type TYP_F2 = 10: Bulk type TYP_F2 = 11: Interrupt type Reserved Enable FIFO 1 1: FIFO 1 is enabled. Block size of FIFO 1 BLKSIZE_F1 = 0: For transferring packets
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BLKSZ_F3

R/W

1b0

27:26

BLKNO_F3

R/W

2b0

25:24

BLK_TYP_F3

R/W

2b0

23:22 21 20

EN_F2 BLKSZ_F2

R/W R/W

1b0 1b0

19:18

BLKNO_F2

R/W

2b0

17:16

BLK_TYP_F2

R/W

2b0

15:14 13 12

EN_F1 BLKSZ_F1

R/W R/W

1b0 1b0

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Technical Reference Manual whose maximum packet size is smaller than or equal to 512 bytes. BLKSIZE_F1 = 1: For transferring packets whose maximum packet size is smaller than or equal to 1024 bytes and greater than 512 bytes. Block number of FIFO 1 BLKNUM_F1 = 00: Single block BLKNUM_F1 = 01: Double blocks BLKNUM_F1 = 10: Triple blocks BLKNUM_F1 = 11: Reserved Transfer type of FIFO 1 Indicate the transfer type used for a FIFO 1 transfer TYP_F1 = 00: Reserved TYP_F1 = 01: Isochronous type TYP_F1 = 10: Bulk type TYP_F1 = 11: Interrupt type Reserved Enable FIFO 0 1: FIFO 0 is enabled. Block size of FIFO 0 BLKSIZE_F0 = 0: For transferring packets whose maximum packet size is smaller than or equal to 512 bytes. BLKSIZE_F0 = 1: For transferring packets whose maximum packet size is smaller than or equal to 1024 bytes and greater than 512 bytes. Block number of FIFO 0 BLKNUM_F0 = 00: Single block BLKNUM_F0 = 01: Double blocks BLKNUM_F0 = 10: Triple blocks BLKNUM_F0 = 11: Reserved Transfer type of FIFO 0: Indicate the transfer type used for a FIFO 0 transfer TYP_F0 = 00: Reserved TYP_F0 = 01: Isochronous type TYP_F0 = 10: Bulk type TYP_F0 = 11: Interrupt type

11:10

BLKNO_F1

R/W

2b0

9:8

BLK_TYP_F1

R/W

2b0

7:6 5 4

EN_F0 BLKSZ_F0

R/W R/W

1b0 1b0

3:2

BLKNO_F0

R/W

2b0

1:0

BLK_TYP_F0

R/W

2b0

13.5.12.

Bit 31:13

FIFO x Instruction and Byte Count Register (One per FIFO, x = 0 ~ 3) (Address = 1B0 + 4xh) Table 13-45. FIFO x instruction and byte count register Name Type Default value Description Reserved

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Technical Reference Manual 12 FFRST R/W 1b0 FIFO x reset The FIFO can be reset by firmware through setting this bit. This bit is cleared automatically. Reserved Out FIFO x byte count: BC_Fx[10:0] indicates the byte number of data stored in the FIFO for OUT Epx.

11 10:0

BC_Fx

RO

11b0

13.5.13. Bit 31:5 4 3 2 1 0

DMA Target FIFO Number Register (Address = 1C0h) Table 13-46. DMA target FIFO number register Name Type Default value Description Reserved ACC_CXF R/W 1b0 Accessing control transfer FIFO When this bit is set to 1, the DMA target FIFO is the control transfer FIFO. ACC_F3 R/W 1b0 Accessing FIFO3 When this bit is set to 1, the DMA target FIFO is FIFO 3. ACC_F2 R/W 1b0 Accessing FIFO2 When this bit is set to 1, the DMA target FIFO is FIFO 2. ACC_F1 R/W 1b0 Accessing FIFO1 When this bit is set to 1, the DMA target FIFO is FIFO 1. ACC_F0 R/W 1b0 Accessing FIFO0 When this bit is set to 1, the DMA target FIFO is FIFO 0. DMA Controller Parameter Setting 1 Register (Address = 1C8h) Table 13-47. DMA controller parameter setting 1 register Name Type Default value Description DevPhy_Suspend R/W 1b0 Device transceiver suspend mode Active high Put the transceiver into the suspend mode that draws minimal power from power supplies. This bit is used in the device mode only. In addition, this bit is in the system clock domain instead of the UCLK clock domain. Reserved DMA_LEN R/W 17h00000 DMA length The total bytes DMA controller will move. The unit is in byte. The maximum length could be 128 kB-1 and must not be configured to 0. While handling control transfer, maximum length must not exceed 64 bytes.
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Technical Reference Manual 7:6 BurMod4ReqDMA R/W 2h0 Burst Size of side-band DMA request Please note this signal is hardware configurable, if not configured, it wont exist. And this is for Faradays DMA application only. The burst size coding: 2'b00: Burst Size = 1 2'b01: Burst Size = 4 2'b10: Burst Size = 8 2'b11: Reserved Enable bit of side-band signal for Request DMA Please note this signal is hardware configurable, if not configured, it wont exist. And this is for Faradays DMA application only. 1'b0: Disable the function of side-band DMA 1b1: Enable the function of side-band DMA Clear FIFO When DMA_ABORT This bit is set to 1 when combined with DMA_ABORT bits to clear the contents in FIFO after DMA abort completion. If the users need to abort the DMA and then clear the contents in FIFO, they must set this bit to 1 together with DMA_ABORT. The contents in FIFO will not be cleared if this bit is cleared to 0 while DMA_ABORT bit set. Please note that all data, not just the current FIFO number, in FIFO will be cleared. DMA abort Force DMA abort during DMA active. This bit is set to 1 to stop the DMA data movement and will be cleared when DMA is stopped. Please note this bit is only valid in device mode. Please note that the DMA_START and DMA_ABORT cannot be set simultaneously. Doing so will result in unexpected outcomes. Setting this bit to 1 while the DMA_START is 0 takes no effect. DMA I/O to I/O Force DMA controller not to toggle address. This bit is set when the DMA is not targeting system memory but I/O device. If this bit is set to 1, the
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Technical Reference Manual DMA_LEN must be the integer multiple of DWORD (4 bytes), and the DMA_MADDR must align with DWORD (4 bytes) boundary. DMA type The transfer type of data moving 0 : FIFO to Memory 1 : Memory to FIFO DMA start Inform the DMA controller to initiate a DMA transfer. This bit is set to start the transfer and cleared when DMA operation is completed. Please note that this bit cannot be cleared by software; it will be cleared by hardware in case of either DMA completion or DMA error. Please note that DMA_LEN must be configured before DMA_START is set.

DMA_TYPE

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DMA_START

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13.5.15. Bit 31:0

DMA Controller Parameter Setting 2 Register (Address = 1CCh) Table 13-48. DMA controller parameter setting 2 register Name Type Default value Description DMA_MADDR R/W 32h0000 DMA memory address Starting address of memory to request a DMA transfer DMA Controller Parameter Setting 3 Register (Address = 1D0h) Table 13-49. DMA controller parameter setting 3 register Name Type Default value Description SETUP_CMD_RPORT RO Undefined Control transfer setup command read port CPU reads an 8-byte setup command from this port instead of programming DMA to move data. The user should note that the CPU must read a word each time as it reads this port (a half-word or byte read is not allowed). Before reading this port, the DMA target FIFO (1c0h) must be set to the control transfer FIFO even though DMA is not used to move this data. Each time the CPU reads this port, the internal FIFO pointer will increase. Should the pointer increases erroneously, users must not set the target FIFO to the control transfer FIFO while using the ICE to scan all ports DMA Controller Status Register (Address = 1D4h)

13.5.16. Bit 31:0

13.5.17.

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Technical Reference Manual Table 13-50. Type RO DMA controller status register Default value Description Reserved Undefined Remaining length when DMA_ABORT This register shows the remaining length when DMA is aborted. This value is only valid when the DMA abortion is complete.

Bit 31:17 16:0

Name DMA_REMLEN

13.6.

USB OTG PHY

The USB OTG PHY is a Universal Serial Bus (USB) On-the-Go transceiver equipped with a wide spectrum of host and peripheral functions in full compliance with the USB specification version 2.0. It is a complete PHY for USB 2.0 integration in Host, Device and Dual-Role Device applications, which enables connecting USB peripherals to any USB-ready product at ease and enjoys accelerated data flow rate leading to optimal performance in applications spanning a wide variety of consumer markets. It includes the following features USB Implementers Forum certified UTMI+ level 3 compliant Backward compatible to USB 1.1legacy protocol Supports USB 2.0 BIST mode Generates clock from off-chip 30 MHz/12 MHz crystal oscillator or external 12 MHz clock source USB 2.0 integration in Host, Device and Dual-Role Device applications Integrated Phase-Locked Loop (PLL) oscillator DP / DM line supports 5 V tolerance Self-calibrated termination resistance

The figure below illustrates the simplified block diagram

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Figure 13-14. Block Diagram of USB OTG PHY 13.6.1. PLL and Clock Control These blocks generate appropriate internal clocks for USB PHY and CLK output signals. An external 12 MHz crystal must be connected to the XSCI to provide a reference clock to these blocks. All data transfer signals are synchronized with the CLK output. After the negation of SuspendM, the CLK signal generated by the USB PHY block will: Produce the first CLK transition no later than 1.5 ms Have a signal frequency error of less than 500 PPM, and a duty-cycle accuracy of 50 % 10 %.

When there is another clock source from another on-chip PLL, you may leave out the off-chip crystal via using the 12 MHz/30 MHz output clock from this on-chip PLL. 13.6.2. Receive Logic This block includes logic for the following operations: 1. Deserializing received data recovered by the HS or FS receiver. Bit destuffing, NRZI decoding, SYNC field and EOP field detection and stripping. Providing 16- / 8-bit parallel data to the UTMI interface. RXActive, RXValid and RXValid are sampled at the CLKs rising edge.

The receive logic behavior is as follows.

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Technical Reference Manual 2. 3. 4. 5. 6. The receiver looks for SYNC. The USB PHY asserts RXActive when SYNC is detected, and then strips the SYNC field. After RXActive is asserted, RXValid will be asserted if data is valid on the data outputs. Otherwise, RXValid will be negated. This negation occurs when 8 / 16 stuffed bits have been accumulated. For 30 MHz mode, RXValidH will also be asserted when high byte data is valid. Otherwise, RXValidH will be negated. This negation happens only at last byte of a received packet. If a bitstuffing error is detected, the receive logic will assert RXError, negate both RXActive and RXValid, and look for the next SYNC field. The possible sources of receive errors include. 1. 2. 3. Bitstuffing error detected during FS receive operation Elasticity buffer overrun or underrun found Alignment error: EOP is not on a byte boundary for HS mode

Figure below shows the timing relationship among the received data (DP/DM), RXActive, RXValid and DataOut signals in 8-bit mode

Figure 13-15. HS Receive Timing Diagram for 8-Bit Data Figure below shows how RXValid is used to skip invalid data bytes in the DataOut output stream.

Figure 13-16. HS Receive with Data Under-Runs due to Removing Stuffed Bits from Data Stream Figure below shows how RXActive, RXValid and RXError behave when an error occurs.

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Figure 13-17. HS RXError Timing Diagram DC Characteristics Figures below show the timing relationship among RXActive, DataOut, RXValid, RXValidH, and the received data (DP/DM) signals in 16-bit mode, for odd-byte and even-byte conditions, respectively.

Figure 13-18. HS Receive Timing Diagram for 16-Bit Data, Odd Byte Count

Figure 13-19. HS Receive Timing Diagram for 16-Bit Data, Even Byte Count
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Technical Reference Manual Figure below shows the timing relationship among RXActive, RXValid and DataOut signals in FS/LS mode. RXValid will be asserted for one CLK per byte time.

Figure 13-20. FS/LS Receiver Operation 13.6.3. Transmit Logic This block accepts 16- / 8-bit parallel data from the parallel application bus interface and serializes it for transmission over the USB 2.0 interface. The module also includes logic for bitstuffing, NRZI encoding, and SYNC and EOP field generation. The transmit logic behavior is as follows: 1. 2. 3. 4. 5. 6. The controller asserts TXValid to begin a transmission. The controller negates TXValid to end a transmission. After asserting TXValid, the controller assumes that the transmission has started when it detects the assertion of TXReady. The controller assumes the FZOTG230HA0A has consumed a data byte when both TXReady and TXValid are asserted. The controller must have valid data asserted on the DataIn input bus coincidently with the assertion of TXValid. TXReady is asserted later on. TXValid and TXReady are sampled at the CLKs rising edge. Figure below shows the timing relationship among TXValid, transmit data (DP/DM), TXReady and DataIn signals in 8-bit mode.

Figure 13-21. HS Transmit Timing Diagram for 8-Bit Data

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Technical Reference Manual Figure below shows how TXReady behaves when accumulating eight stuffing bits in the input data stream.

Figure 13-22. HS Transmit with Data Under-Runs Due to Pending Stuffed Bits to Data Stream The next two following figures show the timing relationship among TXReady, DataIn, TXValid, TXValidH and the transmit data (DP/DM) signals in 16-bit mode, for odd-byte and even-byte conditions, respectively.

Figure 13-23. HS Transmit Timing Diagram for 16-Bit Data, Odd Byte Count

Figure 13-24. HS Transmit Timing Diagram for 16-Bit Data, Even Byte Count HS Transmit Timing Diagram for 16-Bit Data, Even Byte Count

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Figure 13-25. FS/LS Transmitter Operation Diagram 13.6.4. Modes There are four operation modes available: Normal operation (0) Mode 0 allows the transceiver to operate with normal USB data encoding and decoding. Non-driving (1) Mode 1 allows the transceiver logic to support a soft disconnect feature, which tri-states both the HS and FS transmitters and removes any termination from the USB. In this mode, the device appears to an upstream port to be disconnected from the bus. Disable bitstuffing and NRZI encoding (2) Mode 2 disables bitstuffing and NRZI encoding logic. The 1s loaded from the DataIn bus become Js on the DP/DM lines, and 0s become Ks. The SYNC and EOP patterns are disabled so that Chirp can be generated on the USB. Normal operation without automatic generation of SYNC and EOP (3) NRZI encoding is always enabled, while bitstuffing depends on the values of TxBitstuffEnable and TxBitstuffEnableH. This is valid only when XcvrSelect is set to 00b. The behavior of the transceiver is undefined if OpMode is set to 11b and XcvrSelect is not equal to 00b. 13.6.5. Speed Selection The XcvrSelect [1:0] and TermSelect signals determine whether the device is in LS, HS, FS or Chirp mode and enable the associated transceiver and termination. XcvrSelect controls a number of transceiver related elements, for instance: It selects the receiver (source for the Mux block) in the receive path: 00b for HS receive path, 01b for FS receive path and 10b or 11b for LS receive path. It serves as a gating term for enabling the HS, FS or LS Transmit Driver. It switches internal UTMI clocks to shared logic.

13.6.6. UTMI+ level 2 To handle LS traffic, a host controller requires some more extensions:
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Technical Reference Manual The host controller must be able to transmit packets at LS. The host controller must be able to send LS keep-alive packets on a LS bus. A LS keep-alive packet is equal to a LS EOP. The UTMI+ level 2 covers all USB 2.0 traffic described in the USB specification except for the case, included in the next level, where a host sends a LS packet to a LS USB device that is connected through a FS hub (Pre-PID handling). 13.6.7. LS Keep-Alive Generation Figure below illustrates the SIE sets TXValid with XcvrSelect in the LS transceiver mode to enable TxData 0xA5 on the 8 LSBs. The transceiver will decode this assertion and determine that it needs to send a LS keep-alive packet on the USB bus.

Figure 13-26. LS Keep-Alive Generation Diagram 13.6.8. UTMI+ level 3 This is a further enhancement of level 2. In level 2, the host controller part of the USB On-The-Go DRD can only communicate with a LS device directly connected to the host if a parallel interface is used. With level 3, it will be feasible to handle LS traffic that is sent from the host to the LS device via a FS hub. An additional functionality for level 3 is that the host part can generate preamble packets. Table below shows the settings of XcvrSelect [1:0] and TermSelect signals for the selection of speed mode. Speed Mode High speed Full speed
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Table 13-51. XcvrSelect and Termselect XcvrSelect [1:0] TermSelect 0 0 1 or 3 1

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13.6.9. Line State The Line State signals are used by the SIE to detect the signals for Reset, Speed signaling, Packet timing, and the transitions from one behavior to another. To minimize unwanted transitions to the SIE during normal operations, the Line State is internally synchronized with the CLK. This does not apply, however, when the CLK is not usable. Where the CLK is not usable, the Line State signals will not be synchronized, but driven with combinational logic directly from the DP and DM signal lines instead. The USB OTG multiplexes between combinational and synchronous Line State outputs, depending on whether the CLK is usable. Table 12-52 shows the Line State and transfer mode settings. Transfer Mode XcvrSelect [1:0] TermSelect Line State [1:0] Table 13-52. Line State and Transfer Mode Selection (3) Low Speed Full Speed High Speed 2 1 or 3 0 1 1 0 SE0 0 0 0 J 1 1 1 K 2 2 1 SE1 Invalid Invalid Invalid Chirp 0 1 0 1 2 Invalid

(2) [3]

The values in this table are indicated in hexadecimal format. The values in this table are indicated in hexadecimal format. Electrical Specifications HS Inter-Packet Delay for a Receive Followed by a Transmit

13.6.10. 13.6.10.1.

Table 13-53. HS Inter-Packet Delay for a Receive Followed by a Transmit

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Technical Reference Manual Generally, the CLK described in this section is based on 60 MHz (8-bit mode). The RX end delay for the USB OTG is in the 40 - 63 bits. The RX end delay is the time between the end of the EOP and the CLK edge that the SIE detects the negated RXActive. The TX start delay is the time between the CLK edge that the USB OTG detects asserted TXValid, and the assertion of the SYNC on the USB bus. The SIE decision time is the delay between the detection by SIE of the RXActive and the detection by the USB OTG of the assertion of TXValid. The sum of RX end delay, TX start delay and SIE decision time must not exceed 192 bits. The maximum TX start delay for the USB OTG is 16 bits. The RX end delay for the USB OTG is 40-63 bits (8-bit mode) or 64-81 bits (16-bit mode). Important: SIE decision time must not exceed 113 bit times (15 CLKs for 8-bit mode) or 95 bit times (5 CLKs for 16-bit mode). 13.6.10.2. HS Inter-Packet Delay for a Transmit Followed by a Receive

Figure 13-27. HS Inter-Packet Delay for a Transmit Followed by a Receive The RX start delay for the USB OTG is in the range of 40-63 bits. The TX end delay for the USB OTG is in the range of 24-40 bits. SIE prep. time is the delay between the negation of TXValid and the detection of the assertion of RXActive. Assuming the best case, where TX end delay is 24-bit, inter-packet gap is 8 bits, and RX start delay is 40 bit times, the SIE prep. time will be as short as 72 bits (9 CLKs for 8-bit mode or 5 CLKs for 16-bit mode). Assuming the worst case, where TX end delay is 40-bit, inter-packet gap is 192 bits, and RX start delay is
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Technical Reference Manual 63 bit times, then the SIE prep. time will be up to 295 bits (36 CLKs for 8-bit mode or 18 CLKs for 16-bit mode). 13.6.10.3. FS/LS Inter-Packet Delay for a Receive Followed by a Transmit

Figure 13-28. FS/LS Inter-Packet Delay for a Receive Followed by a Transmit To time the inter-packet delay, the SIE must utilize Line State to determine the EOP transition from SE 0 to the J-state. For FS mode, SIE decision time must be in the range of 7-19 CLKs to ensure that FS inter-packet gap of 6.5 bit times is met. For LS mode, SIE decision time must be in the range of 7-243 CLKs to ensure that LS inter-packet gap of 6.5 bit times is met. 13.6.10.4. FS/LS Inter-Packet Delay for a Transmit Followed by a Receive

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Figure 13-29. FS/LS Inter-Packet Delay for a Transmit Followed by a Receive Line State EOP delay: 2-3 CLKs Line State SYNC delay: 2-3 CLKs The USB specification declares that, for 60 MHz clock, a device must not timeout before 16 bit times (80 CLKs) and shall timeout after 18 bit times (90 CLKs). For FS mode, if the inter-packet delay exceeds 89 CLKs, a timeout error will occur. In more detail, 89 - 2 (minimum Line State EOP delay) + 3 (maximum Line State SYNC delay) = 90. 13.6.10.5. Timing Constraints

Figure 13-30. Timing Constraint Diagram

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Technical Reference Manual 1. 16-bit mode Tcsu = control signal setup time = 4 ns min. Tdsu = data setup time = 2 ns min. Tch = Tdh = signal hold time = 2 ns min. Tcco = Tdco = signal clock to out time = 11 ns max., 2 ns min. 2. 8-bit mode Tcsu = control signal setup time = 4 ns min. Tdsu = data setup time = 2 ns min. Tch = Tdh = signal hold time = 2 ns min. Tcco = Tdco = signal clock to out time = 11 ns max., 2 ns min.

Figure 13-31. Full Speed Timing Diagram 13.7. Application The figure below illustrates the basic interface for USB-OTG

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Figure 13-32. USB- OTG Interface

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14. MediaCodec
14.1. Overview The MediaCodec is an AHB based codec capable of accelerating multimedia image and video related applications such as MPEG4 and JPEG. This codec includes some hardware engines to accelerate the computation intensive tasks such as motion estimation, DCT/IDCT, quantization, inverse quantization, and motion compensation. The MediaCodec is controlled by CPU via the AHB slave interface. By initializing the control registers of the codec, the motion estimation calculation task for an entire 16 by 16 or 8 by 8 block can be done automatically without further CPU intervention. The DCT/IDCT, quantization/inverse quantization, AC/DC prediction, zigzag scan and VLC/VLD calculation tasks can also be done automatically for a macro-block by MediaCodec. Thus CPU can be released from the timing critical tasks in video encoding. In order to improve decoded output quality, a deblocking post-filter is included, which can improve subjective and objective qualities especially when the quantization step size is large. It supports the following features: Compliant with MPEG-4 (ISO/IEC 14496-2) simple profile L0 ~ L3 standards Resolutions of Sub QCIF, QCIF, CIF, VGA, 4CIF, and D1 @ 30 fps with a step of 16 Compliant with JPEG (ISO/IEC 10918-1) base-line standard Hardware engines for motion estimation/motion compensation, DCT/IDCT, quantization/inverse quantization, AC/DC prediction, and variable length coding/decoding Local memory controller controls local memory shared by DMA master and other mediacodecs blocks DMA controller controls data transfers between system memory and local memory Automatic power down mechanism Motion estimation search range: -16 ~ +15.5 (optionally -32 ~ +31.5) with half-pixel accuracy Supports 4MV and unrestricted MV Rate control o Constant bit rate and variable bit rate control Encoder supports resynchronization marker and header extension code Decoder supports resynchronization marker, header extension code, data partition and RVLC Error resilient tools o o

Short video header (H.263 baseline) H.263/MPEG/JPEG quantization methods JPEG o 4 user-defined Huffman tables (2AC and 2DC)
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Technical Reference Manual o o o o 4 programmable quantization tables Interleave and non-interleave scans YUV 4:4:4, 4:2:2 and 4:2:0 formats Image size up to 64k 64k

Full-duplex operation (e.g. video phone and video conference) by software switching encoding and task decoding on the same hardware Deblocking post-filter to enhance decoded output quality (optional) Embedded RISC to minimize the host CPU loading Performance o Supports MPEG4 simple profile encoding up to D1 @ 30 fps with codec clock speed under 72 MHz

The figure below illustrates the simplified block diagram of Mediacodec

Figure 14-1. Block Diagram of Mediacodec 14.1.1. AHB Interface The MediaCodec consists of an AHB master interface and an AHB slave interface. The AHB master interface is used to access the video data from the outside memory to the local memory. The AHB slave interface is used to program the control registers of the MediaCodec and DMA controller. 14.1.2. DMA The DMA controller performs the task of transferring data between the system memory and the local memory of the MediaCodec. The main function of the DMA controller is to move and translate data to a suitable format for processing by other hardware engines. 14.1.3. Motion Estimation The Motion Estimation (ME) unit can do motion estimation for the entire search window based on a fast
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Technical Reference Manual search algorithm. By reading commands in local memory, the motion estimation for a macroblock can be completed automatically. 14.1.4. DCT/IDCT The DCT/IDCT unit is responsible for discrete cosine transform and inverse discrete cosine transform. The IDCT unit uses the same hardware resources as the DCT unit. The IDCT results are compliant with IEEE 1180-1990 specification. DCT results are passed to the Quantization unit during the encoding phase and IDCT results are passed to the MC unit at the decoding phase. 14.1.5. Quantization/Inverse Quantization The Quantization/Inverse Quantization unit supports H.263/MPEG/JPEG quantization methods. Quantization results are passed to the AC/DC prediction unit at the encoding phase and inverse quantization results are passed to the IDCT unit during the decoding phase. 14.1.6. AC/DC Prediction The AC/DC prediction unit supports MPEG-4 AC/DC prediction method and JPEG DC prediction method. AC/DC prediction results are passed to the Zigzag Scan unit during the encoding phase and inverse AC/DC prediction results are passed to the Inverse Quantization unit at the decoding phase. 14.1.7. Zigzag Scan The Zigzag Scan unit supports all MPEG-4 scan methods and JPEG zigzag method. Zigzag results of (run, level) pairs are passed to the VLC unit during the encoding phase and inverse zigzag results are passed to the AC/DC Prediction unit at the decoding phase. 14.1.8. Variable Length Coding/Decoding The Variable Length Coding/Decoding (VLC/VLD) unit supports MPEG4 fixed variable length codes and JPEG user-defined Huffman codes. VLC results are final compressed bitstreams during the encoding phase and VLD results are passed to the Zigzag unit at the decoding phase. 14.1.9. Motion Compensation The Motion Compensation (MC) unit is an engine responsible for the motion compensation task. At the encoding phase, it subtracts the interpolated block from the current block and sends the residual block to the DCT. During the decoding phase, it adds the interpolated block to the IDCT output block to get the reconstructed block. 14.1.10. Local Memory Controller The local memory controller arbitrates the local memory access requests from the CPU, DMA, and the media codec engines. A multi-bank memory architecture is used for the local memory to improve the

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Technical Reference Manual memory bandwidth. CPU has the highest access priority, followed by the DMA and then the codec. The local memory controller supports the following addressing modes for the codec operation: Transfer of a linear block or 2D block from the local memory to the codec. Transfer of CODEC output to a linear or 2D block in the local memory. Circular buffer addressing mode to transfer a 2D block to ME unit. Non-Circular Address Generation for Transferring a 2D Block

14.1.10.1.

Figure below shows an example to generate the address for an 8x8 block inside a 16x16 macroblock. The data are accessed row by row in the sequence: word 0, word 1, , word 15. Each word is assumed to contain 4 pixels. The address is generated in the sequence: A, A+1, A+4, A+5, , A+29. In this example, the corresponding Block Start Address Register must be set to A, the corresponding field in ME Address Increment Register must be set to 3, which is the address increment from word 1 to word 2, and the block type in ME Control Register must be set to indicate 8x8 block if this block is used by ME.

Figure 14-2. Non-Circular Address Generation for an 8x8 Block 14.1.10.2. Circular Address Generation for Transferring a 2D Block

The circular addressing mode is used to transfer a 2D reference block to the ME unit. Table below shows an example of a search window inside the frame buffer on system memory, where the motion vector range is assumed inside the pixel range [-16, 15.5]. Assume the top left corner of the current macroblock is at the position (16,16) in the frame buffer and the search window data are transferred to local memory for use by the ME unit. When processing the next macroblock, the search window is shifted to the right by 16 pixels, which include the dark-grey region and light-gray region in the figure. To save the memory bandwidth, only

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Technical Reference Manual the light-gray region need be transferred to the local memory, since the dark-grey region has been transferred already. However, this will need circular addressing mode as explained below.

Figure 14-3. Search Window inside Frame Buffer on System Memory Figure below shows the situations inside the local memory when the search windows are transferred to the local memory from system memory for current macroblock and next macroblock respectively. As shown in the above figure, the reference block of the current macroblock can be accessed like a non-circular 2D transfer. However, for the reference block of the next macroblock, the addresses are wrapped back to the start of each row. The byte address of each pixel in the reference block can be obtained by the following formula: RADD + (x + (MVX >>1) + HOFFSET) % SWIDTH + y SWIDTH Where (x, y) is the coordinate of a pixel inside the reference block with (0,0) for the top left corner. RADD is the address register to store the start address in local memory for the row that is the first row of the reference block. MVX is the horizontal motion vector in half-pixel unit. HOFFSET is the offset added for horizontal position in the local memory, which represents reference block horizontal position in the local memory when MVX is 0. For Figure (a), HOFFSET is set to 16, and for Figure (b), it is set to 32. Its value should not exceed SWIDTH, the search window width in pixels, which is set to 48 in the below figure

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14.1.10.3.

Figure 14-4. Search Window Inside Local Memory for Current Macroblock (a) and Next Macroblock (b) Data Transfer Parameters

A data transfer can be described by the following parameters. Direction o o AHB to local memory Local memory to AHB

Source base address Source data dimension o o Sequential read 2D block read, if 2D block read is assigned, the width of the transfer block and the width of the read frame should be specified first.

Destination base address Destination data dimension o o Sequential write 2D block write, if 2D block write is assigned, the width of the transfer block and the width of the write frame should be specified first.

Length Control o o Chain transfer control Interrupt trigger Dimension Translation

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14.1.10.4.
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Technical Reference Manual There are four types of dimension translation supported by the DMA controller. Sequential-to-Sequential (SS) Both source data and destination data are arranged in the sequential address sequence. The source address, destination address and data length should be specified in the SS type of transfer.

Figure 14-5. Sequential-to-Sequential Transfer Sequential-to-2D (S2D) The source data are arranged in the sequential address sequence and the destination data are arranged in the 2D address sequence. The source address, destination address, destination data block width, destination frame width and data length should be specified in the S2D type of transfer.

Figure 14-6. 2D-to-Sequential Transfer 2D-to-2D (2D2D) Both source data and destination data are arranged in the 2D address sequence. The source address, source data block width, source frame width, destination address, destination data block width, destination frame width and data length should be specified in the 2D2D type of transfer.

Figure 14-7. 2D-to-2D Transfer

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Technical Reference Manual xD-to-3D (xD3D) The destination data are arranged in the 3D address sequence. The transfer type of destination should be set to 3D transfer. The 2D block width is 4 and 2D block offset is 33. The second block width is 2 and the second block offset is -30.

Figure 14-8. xD-to-3D Transfer xD-to-4D (xD4D) The destination data are arranged in the 4D address sequence. The transfer type of destination should be set to 4D transfer. The 2D block width is 4 and 2D block offset is 33. The second block width is 2 and the second block offset is -30. The third block width is 4 and the third block offset is 6.

14.1.10.5.

Figure 14-9. xD-to-4D Transfer Chain Transfer Function

The chain transfer function allows the DMA controller to load the commands from the memory. A block of memory should be reserved for storing the pre-defined transfer sequence. Once the chain transfer function is activated, the DMA controller will load a block of data from the memory to set the DMA controller register

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Technical Reference Manual set according to the address in the link list pointer register. A bit in the control register is used to define the DMA controller to load the next command set from the memory when the current command is done.

Figure 14-10. Chain Transfer Function 14.1.10.6. DMA Interrupts There are two types of interrupt triggered by the DMA controller. Transfer complete interrupt. The DMA controller will trigger an interrupt to inform the system when a transfer command has been completed. Bus error interrupt. The DMA controller will trigger an interrupt to inform the system when an AHB bus error is received by the DMA controller. 14.1.10.7. YUV2RGB Data format Transfer

The YUV2RGB Data format Transfer unit performs the task of transferring decoded output image from separated YUV to interleave CbYCrY or 16/24 bits RGB. During the decoding phase, it catches the MC reconstructed block and produce image of the selected format. 14.1.10.8. Deblocking Post-filter

The Deblocking post-filter unit is designed according to a simplified method similar to MPEG4 (ISO/IEC 14496-2) F.3 definition. If deblocking function is enabled by hardware configuration or by software programming, it will catch the MC reconstructed block in local memory bank1 and do filtering, then output to local memory bank 5. And YUV2RGB unit can successively transfer data in bank 5 to get final output image. 14.2.

Modes of Operation

Mediacodec provides four operation modes:

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Technical Reference Manual MPEG4 encode MPEG4 decode JPEG encode JPEG decode Programming

14.3.

The MediaCodec has a number of local memory blocks for internal use and a number of registers to control the operations of various function units. The local memory block address mapping is shown in the following table. Symbol Program Data Bank0 Bank1 Bank2/3 Bank4 Bank5 Table 14-1. Offset 0x00000 0x08000 0x10000 0x14000 0x18000 0x17C00 0x1A000 MPEG4 Encoder/Decoder Local Memory Mapping Size Access Description 4 R/W Used by the internal RISC 4 R/W Used by the internal RISC 8 R/W Calculation buffer 1.5 R/W Current block buffer/Interpolation buffer 4.6 R/W Reference block buffer 0.8 R/W Quantization table buffer 9 R/W Deblocking buffer

The MPEG4/JPEG codec control registers are separately described in the following tables Table 14-2. MPEG-4 Encoder/Decoder Control Registers and Local Memory Symbol Offset Size Access Description MECTL 0x20000 11 R/W ME control register MECR 0x20008 7 R/W ME coefficient register MIN_SAD 0x2000C 16 R Minimum SAD register CMDADDR 0x20010 16 R/W ME command queue start address register MECADDR 0x20014 16 R/W ME current block start address register HOFFSET 0x20018 8 R/W Horizontal offset to reference block address MCCTL 0x2001C 25 R/W MC control register MCCADDR 0x20020 16 R/W MC current block start address register MEIADDR 0x20024 16 R/W ME interpolation block start address register CPSTS 0x20028 23 R Coprocessor status register QCR0 0x2002C 32 R/W Quantization coefficient register 0 DZAR/QAR 0x20038 32 R/W De-zigzag scan buffer address register Quantization block address register CKR 0x2003C 3 R/W Coprocessor clock control register ACDCPAR 0x20040 16 R/W AC/DC predictor buffer address register VADR 0x20044 19 R/W VLC/VLD local data address register CURDEV 0x20048 16 R ME current block deviation register BITDATA 0x2004C 32 R/W Bit-stream access data port BITLEN 0x20050 6 R/W Bit-stream access length/auto-buffer local memory pointer

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Technical Reference Manual MBIDX MCIADDR VLDCTL VOP0 VOP1 MVD0/SCODE MVD1/RSMRK TOADR VLDSTS ASADR INNER_CPUCTL VOP_SIZE PMVADDR DTOFMT INNER_MASK EXT_MASK INT_FLAG INT_STS 0x20054 0x20058 0x2005C 0x20060 0x20064 0x20068 0x2006C 0x20070 0x20074 0x20078 0x2007C 0x20080 0x20084 0x20088 0x20090 0x20094 0x20098 0x2009C 12 16 6 32 32 32 32 16 32 30 5 32 16 8 32 32 32 32 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WC R MB index for data partition decoding MC interpolation and result block start address register VLD control register VOP parameter 0 VOP parameter 1 Differential motion vector register 0/Start code Differential motion vector register 1/Re-sync marker VLD table output address VLD status register Auto-buffering system data address Inner CPU control register VOP size register Prediction motion vector buffer start address register Image output format select register Enable bit for the inner CPU interrupt Enable bit for the external CPU interrupt Interrupt flag, read for flag (after mask), write 1 clear Interrupt status, read for status (before mask), read only

Symbol MCUBR MCCTL MCCADDR CPSTS MCUTIR PYDCR PUVDCR DZAR/QAR Reserved VADR BADR BALR MCIADDR VLDCTL VLDLUTR VLASTWORD VLDSTS ABADR JPGSeqCtl
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Table 14-3. Offset Size 0x20008 4 0x2001C 17 0x20020 16 0x20028 14 0x2002C 32 0x20030 16 0x20034 32 0x20038 32 0x2003C 0x20044 0x2004C 0x20050 0x20058 0x2005C 0x20068 0x2006C 0x20074 0x20078 0x200A0 3 16 32 6 16 6 32 32 32 30 2

JPEG Encoder/Decoder Registers Access Description R/W Minimum coded unit block number register R/W MC control register R/W MC current block start address register R Coprocessor status register R/W Minimum coded unit table index register R/W JPEG previous Y dc value register R/W JPEG previous UV dc value register R/W De-zigzag scan buffer address register Quantization block address register R/W Reserved R/W VLC data output address register R/W Bit-stream access data register R/W Bit-stream access length register R/W MC interpolation and result block start address register R/W VLD control register R/W VLD look up table register R VLC output last word R/W VLD status register R/W Auto-buffer system data address R/W JPEG sequence control register
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Technical Reference Manual JPGFrmInfo1 JPGFrmInfo2 JPGFrmInfo3 0x200A4 0x200A8 0x200AC 26 16 32 R/W R/W R JPEG MCU row/column number JPEG restart interval JPEG-encoded bitstream length (unit: byte)

14.3.1. ME Control Register (MECTL, Offset ==0x20000) Bit 31-9 8 7 Symbol Reserved Bank5_initPos Set_MB_xy Table 14-4. ME Control Register Offset Description Initiate the local memory bank-5 toggle position. Set this bit to fit the software pipeline request between the I-frame and the P-frame. Disable the MB counter. Set the MB position, and set the mb_x and mb_y value for error concealment, which must come from the VOP_SIZE register. This bit is auto-cleared. Disable the MB counter Sets this bit to 1 to disable macroblock counter. Skip PXI command for decoding. Sets this bit to 1 to skip PXI command for decoding. Start VOP layer Sets this bit to 1 to start the VOP layer processing. This bit is autocleared. Video packet start Sets this bit to 1 when a new video packet is started. This bit is autocleared. Rounding control. The rounding_control bit is used in pixel interpolation as defined by the MPEG-4 standard. Interpolation block size. The block size for interpolation command in decoding mode. If PXI_1MV=1, the block size is 16 x 16; otherwise, the block size is 8x8. ME start. Starts ME operation when ME_GO is set to 1. This bit is auto-cleared.

6 5 4 3 2 1 0

MBCNT_DIS SKIP_PXI VOP_START VPKT_START RND PXI_1MV ME_GO

14.3.2. ME Coefficient Register (MECR, Offset == 0x20008) Table 14-5. 31 7 ME coefficient 0 Coefficient 0 is used for ME. 14.3.3. Minimum SAD Result Register (MIN_SAD, Offset == 0x2000C) Table 14-6. 31 16 Bit 15-0 Minimum SAD result Minimum SAD Result Register 15 0 MIN_SAD MECR 60 MECOEFF0

Bit 6-0

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Technical Reference Manual The MIN_SAD records the minimum SAD of searched result. The MIN_SAD is automatically set to its maximum value (0xffff) at the start of ME_GO. 14.3.4. ME Command Queue Start Address Register (CMDADDR, Offset == 0x20010) Table 14-7. ME Command Queue Start Address Register 31 16 15 0 CMDADD Bit 15-0 Command queue start address The command queues start address in local memory. The command queue size must not exceed 128 words and the start address must be 128-word aligned, i.e. CMDADD [8:0] is ignored. 14.3.5. ME Current and Result Block Start Address Register (MECADDR, Offset == 0x20014) Table 14-8. MECADDR 15 0 MECADD 31 16 ME current and result block start address i.e. MECADD [1:0] is ignored. 14.3.6. Horizontal Offset Register (HOFFSET, Offset == 0x20018) Table 14-9. HOFFSET 31 16 Bit 7-0 Horizontal offset must be a multiple of 16, i.e. HOFFSET [3:0] is ignored. HOFFSET should be set to 0 in decoding mode. 14.3.7. MC Control Register (MCCTL, Offset == 0x2001C) Bit 31-25 24 23 22-21 Symbol Reserved Encode mode Frame_bottom Frame_top Frame_left Table 14-10. MCCTL Description Encoding mode for one frame 1: Set to 1 means the current frame is in the encoding process. 0: Set to 0 means the current frame is in the decoding process. DT macroblock location. Indicates the current macroblock location in the whole frame. Deblocking macroblock location. Indicates the current macroblock location in the whole frame 11: upperleft most MB in the whole frame 10: upper most row in the whole frame
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Bit 15-0

The ME current and result block start address in bytes. The address must be 32-bit aligned,

15 0 HOFFSET

These bits indicate the address offset to compute the reference block address for ME. HOFFSET

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Technical Reference Manual 01: left most column in the whole frame 00: others Whole frame deblocking function enable. Indicates that deblocking post-filter would be active or inactive in the whole frame. Deblocking filter start. Starts deblocking filter when Deblk_GO is set to 1. This bit is autocleared. YUV to RGB transfer enable. Indicates that output format transfer would be active or inactive in the whole frame. YUV to RGB transfer start. Starts YUV to RGB transfer operation when DT_GO is set to 1. This bit is auto-cleared. Motion vector zero indication register. Indicates that the current motion vector is zero. Intra frame When the current frame is an intra frame, INTRA_FRAME is set to 1; otherwise, INTRA_FRAME is set to 0. Short video header enable Uses short video header mode. Please note, if this bit is set, both MPEG4 quantization mode and 1mv mode must be set, also. ie. The bit[3] must set to 1 and bit[8:6] must not set to 2. AC/DC prediction parameter The AC/DC_PARM register is used to indicate the attribute of the neighbors of current macro-block for the AC/DC prediction process. Setting this register to one will force the predictors of the corresponding neighbor to be the default predictors, {1024, 0, 0, 0, 0, 0, 0, 0}. [13]: Diagonal macroblock [12]: Top macroblock [11]: Left macroblock Start decode MC Starts decode MC operation when DMC_GO is set to 1. This bit is autocleared. JPEG mode When operating JPEG, the JPGM register is set to 1. MPEG4 mode The MP4M register indicates the mode of current macroblock: 0: inter 2: 4mv 3: intra Others: Reserved Decoding cycle of one macroblock start Start decoding cycle of one macroblock operation when DEC_GO is set to 1. This bit is auto-cleared. AC/DC predictor buffer remap Controls the AC/DC predictor buffer remapping. MPEG4 quantization function If this bit is set to 0, H.263 quantization function is used. If this bit is set to 1, MPEG4 quantization function is used AC prediction disable
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20 19 18 17 16 15 14

Deblk_EN Deblk_GO DT_EN DT_GO MVZ INTRA_FRAME SVH

13-11

ACDC_PARM

10 9 8-6

DMC_GO JPGM MP4M

5 4 3 2
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DEC_GO REMAP MP4Q DIS_ACP

Technical Reference Manual Disables the AC prediction function. Intra block When the current block is an intra block, INTRA is set to 1; otherwise INTRA is set to 0. In JPEG mode, this bit is also set to 1. MC start Starts MC operation when MC_GO is set to 1. This bit is auto-cleared.

1 0

INTRA MC_GO

14.3.8. MC Interpolation Block Start Address Register (MEIADDR, Offset == 0x20024) Table 14-11. MEIADDR 31 16 15 0 MEIADD Bit 15-0 ME interpolation result block start address The pixel interpolation result block start address in bytes for ME. The address must be 32-bit aligned; i.e., MEIADD[1:0] is ignored. 14.3.9. Coprocessor Status Register (CPSTS, Offset ==0x20028) Table 14-12. CPSTS Bit Symbol Description 31-28 Reserved 27 JPG_VLD_ error JPG_VLD_error This bit will be set to 1 when the JPEG decoder decodes the error bitstream or restarts the marker error. JPG_sys_buff_empty This bit will be set to 1 if the JPEG decoder finds the decoded bitstream buffer is empty. System bitstream buffer full in the JPEG mode This bit is set to 1 when the bitstream buffer in the system memory is full in the JPEG mode. JPEG 0xFFD7 restart marker is inserted. This bit is set to 1 when the JPEG 0xFFD7 restart marker is inserted. JPEG frame done. This bit is set to 1 when one frame encoding/decoding is completed in the JPEG mode. ME CMD type. These bits indicate the running ME CMD type, which is the reference for software to prepare next MB ME command. Whole frame ME block number. These bits indicate the running ME block number, which is the reference for software to prepare next MB ME command. ME copy done. This bit is set to 1 when ME copies current MB to memory bank0 has finished. This bit is auto-cleared when ME_GO is set in the MECTL register.
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26

JPG_sys_ buff_empty JPG_sys_buff_full

25

24 23

JPG_FFD7_marker JPG_FRM_ DONE

22-20

ME_CMD

19-18

BK_NUM

17

ME_CP_DONE

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Technical Reference Manual 16 ME_CP_DONE Deblocking finish. This bit is set to 1 when deblocking filtering has finished. It is autocleared when Deblk_GO is set in the MCCTL register. MPEG VLC finish. This bit is set to 1 when VLC has finished in MPEG mode. This bit is auto-cleared when MC_GO is set in MCCTL register of MPEG mode. YUV to RGB transfer finish. This bit is set to 1 when YUV to RGB transfer has finished. It is autocleared when DT_GO is set in the MCCTL register Y0 block quantization non-zero result. Indicates that the Y0 block has at least one non-zero result. Y1 block quantization non-zero result Indicates that the Y1 block has at least one non-zero result. Y2 block quantization non-zero result Indicates that the Y2 block has at least one non-zero result. Y3 block quantization non-zero result indicates that the Y3 block has at least one non-zero result. U block quantization non-zero result Indicates that the U block has at least one non-zero result. V block quantization non-zero result Indicates that the V block has at least one non-zero result. ME_INTRA ME intra mode After ME searched result and mode decision command, this bit is set to 1 if intra mode is used; otherwise, this bit is set to 0. This bit is cleared to 0 at the start of ME_GO. ME block size After ME searched result this bit is set to 1 if the block size of the motion vectors is determined to be 16 x 16 (1MV mode); otherwise, this bit is set to 0 for block size 8x8 (4MV mode). JPEG VLC finish This bit is set to 1 when VLC has finished in JPEG mode. This bit is auto-cleared when MC_GO is set in MCCTL register of JPEG mode. AC prediction result This bit indicates whether the AC prediction is taken or not taken. PMV command finish for decoding This bit is set to 1 when all PMV commands have finished in decoding mode. This bit is auto-cleared when ME_GO is set in MECTL register MV buffer select Selects valid MV buffer after ME_done in decoding mode. 0 selects MV buffer 0 and 1 selects MV buffer 1. MC finish This bit is set to 1 when MC has finished. This bit is autocleared when MC_GO is set in the MCCTL register.
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VLC_done

14

DT_done

13 12 11 10 9 8 7

QNZ

ME_BSIZE

VLC_DONE

4 3

ACPR PMV_DONE

2 1

MVBUF MC_DONE

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Technical Reference Manual 0 14.3.10. ME_DONE ME finish This bit is set to 1 when ME has finished. This bit is autocleared when ME_GO is set in the MECTL register.

Quantization Coefficient Register 0 (QCR0, Offset == 0x2002C) Table 14-13. QCR0 31 25 24 18 17 6 QCOEFF2 QCOEFF1 Reserved Bit 31-25 Quantization coefficient 2 level can be 1 ~ 31. Bit 24-18 Bit 5-0 Quantization coefficient 1

50 QCOEFF0

Coefficient 2 is the quantization level used for deblocking function. The value of quantization

Coefficient 1 is the quantization level. The value of quantization level can be 1 ~ 31. Quantization coefficient 0 Coefficient 0 is the cbp value. 14.3.11. De-Zigzag Scan Buffer Address/Quantization Block Address Register (DZAR/QAR, Offset == 0x20038) Table 14-14. DZAR/QAR 31 16 DZAR Bit 31-16 De-zigzag scan output buffer address The de-zigzag scan output buffer address in bytes. The address must be 1 kB aligned, i.e. DZAR [9:0] is ignored. Bit 15-0 Quantization block start address 0 The quantization block start address in bytes. The address must be 1 kB aligned, i.e. QAR[9:0] is ignored. 14.3.12. ACDC Predictor Buffer Address Register (ACDCPBAR, Offset == 0x20040) Table 14-15. ACDCPBAR 31 16 15 10 ACDCPBAR ACDC predictor buffer start address The AC/DC predictor buffer start address in bytes. The address must be 512 byte aligned, i.e. ACDCPA[8:0] is ignored. 14.3.13. VLC/VLD Data Address Register (VADR, Offset == 0x20044) Table 14-16. VADR
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15 10 QAR

Bit 15-0

Technical Reference Manual 31 16 15 8 ABADR VLC/VLD auto-buffering data address 75 -

Bit 15-8

The ABADR indicates the memory allocation for the DMA auto-buffering function. In encoding process, the DMA will move data out to the system memory automatically. In decoding process, the DMA will move data from the system memory automatically. The ABADR only indicates the allocation in 256-byte boundary. Bit 4-0: VLC/VLD last-bit register. The last-bit register indicates the position that the VLC starts to pack the data or the VLD starts to decode the data. The last-bit should be 0 ~ 31. 14.3.14. ME Current Block Deviation Register (CURDEV, Offset == 0x20048) Table 14-17. CURDEV 15 0 CURDEV Bit 15-0 Current block deviation The current block deviation is defined by the following equation: MEAN=, CURDEV= 211/)(NCNiNjij====NiNjijMEANC11, where N=16 for ME_BSIZE=1 and N=8 for ME_BSIZE=0, and Cij is the pixel value of the current block. The ME engine calculates the current block deviation in parallel with SAD command and there must be at least two SAD commands to calculate the current block deviation. The CURDEV result is valid when ME_done is 1. 14.3.15. Bit-Stream Access Data Register (BADR, Offset == 0x2004C) Table 14-18. BADR 31 0 BADR Bit 31-0 Bit-stream access data port The data port is used to access the bit-stream under auto-buffering mechanism. In encoding process, the write operation will pack the number of bits into the bit-stream. The packed data should be aligned to the LSB in the data port. In decoding process, the read operation to the data port will check out the number of bits from the bit-stream. The read data will be aligned to the MSB in the data port. The number is indicated in the BITLEN register. 14.3.16. Bit-Stream Access Length Register/Auto-buffering Local Memory Pointer (BALR/ABLP, Offset == 0x20050) Table 14-19. BALR Read function
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Technical Reference Manual 31 8 72 10 0 BALR 0 Bit 7-2: Auto-buffering local memory access pointer The register indicates the read/write pointer to the local memory while the auto-buffering function is active under encoding/decoding process. Write function 31 5 40 BALR Bit 4-0: Bit-stream access length register The register indicates the number of bits operated in the bitstream access data register. The last-bit should be 0 ~ 31. 14.3.17. MC Interpolation and Result Block Start Address Register (MCIADDR, Offset == 0x20058) Table 14-20. MCIADDR 31 16 15 0 MCIADD Bit 15-0: MC interpolation and result block start address The pixel interpolation block start address in bytes for MC. It also used to store MC result. The address must be 32-bit aligned, i.e. MCIADD[1:0] is ignored. 14.3.18. VLD Control Register (VLDCTL, Offset == 0x2005C) 4 ABF_start 3-0 CMD

Bit 6

Table 14-21. VLDCTL 31-7 6 5 ABF_endian ABF_stop Swap auto-buffer data byte order in a word 0 1 No swap Swap

Bit 5 Bit 4

Stop VLC/VLD auto-buffer function Start VLC/VLD auto-buffer function. Before starting the auto-buffer function, the related registers in DMA controller should be set correctly.

Bit 3-0 VLD command 0000 0001 0010 0011 1000 1001 MPEG4 normal decoding MPEG4 searches re-sync marker before stop. MPEG4 searches re-sync marker before decoding. MPEG4 searches re-sync marker and decoding in reverse direction. JPEG normal decoding JPEG searches re-sync marker before decoding.

Others Reserved

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Technical Reference Manual 14.3.19. 31-24 Bit 23-20 Bit 19-16 Bit 15-8 Bit 3-0 14.3.20. Bits 31-28 27-24 23-16 15-12 11-2 1 0 14.3.21. VOP Parameter 0 Register (VOP0, Offset == 0x20060) 23-20 fcode_forward fcode_forward Quant scale VOP coding type VOP Parameter 1 Register (VOP1, Offset == 0x20064) Table 14-23. VOP1 Symbol Description length of start code header Length of start code header n: length=8 * n, (0 < n < 5) length of re-sync marker Length of re-sync marker n: length=16 + n length of vop_time_increment code Length of vop_time_increment code plus 2 n: length=n- 2 length of macroblock_number code Length of macroblock_number code Reserved RVLC Using RVLC DP Data partition mode enable Differential Motion Vector 0/Start Code Register (MVD0/SCODE, Offset == 0x20068) Table 14-24. MVD0/SCODE Encoding mode 31 24 23 16 MVDY1 MVDX1 Bit 31-24: Block 1 vertical differential motion vector Bit 23-16: Block 1 horizontal differential motion vector Bit 15-8: Block 0 vertical differential motion vector Bit 7-0: Block 0 horizontal differential motion vect Decoding Mode 31 0 SCODE Start code The VLD can search the start code pattern in the bit-stream automatically using the SCODE register and start code length in the VOP1 register to specify the search pattern. The data in the SCODE register will be used from the MSB. 14.3.22. Differential Motion Vector 1/Re-sync Marker Register (MVD1/RSMRK, Offset == 0x2006C) 15 8 MVDY0 70 MVDX0 Table 14-22. VOPO 19-16 15-8 intra_dc_vlc_thr quant 7-4 3-0 vop_type

Intra DC VLC threshold

Bit 31-0

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Technical Reference Manual Table 14-25. MVD1/RSMRK Encoding mode 31 24 MVDY3 Encoding Mode: Bit 31-24 Bit 23-16 Bit 15-8 Bit 7-0 Block 3 vertical differential motion vector, also used as vertical differential motion vector for the macroblock in 1MV mode. Block 3 horizontal differential motion vector, also used as horizontal differential motion vector for the macroblock in 1MV mode. Block 2 vertical differential motion vector Block 2 horizontal differential motion vector 31 0 RSMRK Bit 31-0 Re-sync marker The VLD can search the re-sync maker in the bit-stream automatically, using the RSMRK register and re-sync marker length in the VOP1 register to specify the search pattern. The data in the RSMRK register will be used from the MSB. 14.3.23. VLD Table Output Address (TOADR, Offset == 0x20070) Table 14-26. TOADR 31 16 VLD table output address shown below. Video Packet Header Word0 31 25 Word1 31 16 vop_time_increment Word2 31 19 18 16 15 11 10 8 72 10 15 8 70 modulo_time_base 24 Extension 23 21 20 16 Quant 15 0 mb_number 15 0 TOADR 23 16 MVDX3 15 8 MVDY2 70 MVDX2

Decoding mode

Bit 15-0

The VLD will output the macroblock information to the local memory. The data format is

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Technical Reference Manual Normal I-VOP Word0 31 29 Dequant Normal P-VOP Word0 31 29 Dequant Word1 31 24 MVD1_X[7:0] Word2 31 28 MVD2_Y[3:0] Word3 31 20 MVD3_Y Data Partition I-VOP Intra Block Word0 31 29 Dequant Word1 31 16 Y1_DC Word2 31 16 Y3_DC Word3 31 16 V_DC Data Partition P-VOP Intra Block
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Intra_dc_vlc_thr

Vop_coding_type

28 24 Cbp[5:1]

23 Cbp[0]

22 5 -

4 intra_DC

3 ac_pred_flag

20 Mbtype

28 24 Cbp[5:1]

23 Cbp[0]

22 6 -

5 Not coded

43 -

20 Mbtype

23 12 MVD0_Y

11 0 MVD0_X

27 16 MVD2_X

15 4 MVD1_Y

30 MVD1_X[11:8]

19 8 MVD3_X

70 MVD2_Y[11:4]

28 24 Cbp[5:1]

23 Cbp[0]

22 5 -

4 intra_DC

3 ac_pred_flag

20 Mbtype

15 0 Y0_DC

15 0 Y2_DC

15 0 U_DC

Technical Reference Manual Word0 31 29 Dequant Word1 31 16 Y1_DC Word2 31 16 Y3_DC Word3 31 16 V_DC Data Partition P-VOP Inter Block Word0 31 29 Dequant Word1 31 24 MVD1_X[7:0] Word2 31 24 MVD2_Y[3:0] Word3 31 20 MVD3_Y 14.3.24. 19 8 MVD3_X 70 MVD2_Y[11:4] 27 16 MVD2_X 15 4 MVD1_Y 30 MVD1_X[11:8] 23 12 MVD0_Y 11 0 MVD0_X 28 24 Cbp[5:1] 23 Cbp[0] 22 6 5 Not coded 43 20 Mbtype 31 29 Dequant 15 0 U_DC 15 0 Y2_DC 15 0 Y0_DC 28 24 Cbp[5:1] 23 Cbp[0] 22 6 5 Not coded 4 intra_DC 3 ac_pred_flag 20 Mbtype

VLD Status Register (VLDSTS, Offset == 0x20074) Table 14-27. VLDSTS 31 16 Number of macro-block 10 ABclean Error code 0 1 No error Decode mode error
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15 12 Error Code 9 ABF_wait 84 Reserved 30 Flag

11 ABrdy Bit 31-16 Bit 15-12

Used to indicate the number of macroblock in current partition

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Technical Reference Manual 2 3 4 5 6 7-13 14 Bit 11 Bit 10 Bit 9 Bit 2 Bit 1 Bit 0 14.3.25. Decode cbpy error Decode MVD error Decode DC error Decode AC error Un-supported vop type Reserved Re-sync search timeout 15: Unknown error

Auto-buffer ready for access Auto-buffer clean for access pointer Auto-buffer wait for bit-stream fill Start code detected Re-sync marker detected VLD_done Auto-Buffer System Data Address (ABADR, Offset == 0x20078) Table 14-28. ABADR

Read function 31 2 ABADR Bit 31-2 1 0

Auto-buffer current address Indicates the current address of auto-buffering function. The address will be word aligned.

Write function 31 2 ABADR Bit 31-2 Bit 1 Bit 0 14.3.26. 19 Reset CPU 1 ABF_dir 0 ABF_write

Auto-buffer start address Indicates the start address for auto-buffering function. The address should be word aligned. Set the VLD auto-buffer read direction 0: Look-ahead data pre-fetch 1: Look-backward data pre-fetch Buffering direction 0: Read operation for VLD 1: Write operation for VLC Inner CPU Control Register (INNER_CPUCTL, Offset == 0x2007C) 18 Start CPU Table 14-29. Inner_CPUCTL 17 16 Stop CPU Software interrupt to inner CPU 15-0 Reserved

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Technical Reference Manual 31-24 Reserved Bit 23 23 22-21 20 Inner CPU idle Reserved Software interrupt to external CPU Read 1: The internal CPU is idle now. Read 0: The internal CPU is running. Write: No effect Bit 20 Write 1: Set an interrupt to external CPU Write 0: No effect (this bit can only be cleared by INT_FLAG[31]) Read: Status of software interrupt for external CPU Bit 19 Bit 18 Bit 17 Bit 16 Reset internal CPU Setting this bit to 1 will reset the internal CPU. This bit is auto cleared. Start internal CPU Setting this bit to 1 will start the internal CPU. This bit is auto cleared. Stop internal CPU Setting this bit to 1 will stop the internal CPU. This bit is auto cleared. Write 1: Set an interrupt to inner CPU Write 0: No effect (this bit can only be cleared by INT_FLAG[30]) Read: Status of software interrupt for inner CPU 14.3.27. VOP Size Register (VOP_SIZE, Offset == 0x20080) 32 28 Bit 27-16 Bit 11- 0 Table 14-30. VOP_SIZE 27 16 15 12 VOP_WIDTH 11 0 VOP_HEIGHT

VOP width. The VOP width in pixel unit, and must be a multiple of 16. The VOP width must be in the range from 32 up to 2032. VOP height. The VOP height in pixel unit, and must be a multiple of 16. The VOP height must be in the range from 32 up to 2032.

14.3.28.

Prediction MV Buffer Start Address Register (PMVADDR, Offset == 0x20084) Table 14-31. PMVADDR 31 16 Prediction MV buffer start address 15 0 PMVADD

Bit 15 0

The prediction MV buffer start address in bytes for ME. The address must be 1024-byte aligned, i.e. PMVADD[9:0] is ignored. 14.3.29. Image Output Format Select Register (DTOFMT, Offset == 0x20088)

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Technical Reference Manual Table 14-32. DTOFMT 75 42 Deblk_THR2 Deblk_THR1

31 8 Bit 1 0

10 DTOFMT

Image output format 0: CbYCrY 31~24 Y 23~16 Cr 14~10 B 23~16 B 9~5 G 15~8 G 10~5 G 15~8 Y 4~0 R 7~0 R 4~0 R 7~0 Cb

1 15 0

RGB 16bpp

2 RGB 24bpp 31~24 0 3 RGB 16bpp 15~11 B

Bit 4 2 Bit 7 5 14.3.30.

The threshold value 1 for the deblocking filter. The threshold value 1 for the deblocking filter. Inner CPU Interrupt Mask Register (INNER_MASK, Offset == 0x20090)

Table 14-33. INNER_MASK 7 6 5 4 3 2 1 0 Mask0 of Mask0 of Mask0 of Mask0 of Mask0 of Mask0 of Mask0 of Mask0 of DMA_done VLD_done VLC_done DT_done PMV_done PXI_done MC_done ME_done 15-10 9 8 Reserved Mask0 of JPG_frm_done Mask0 of deblk_done 31-26 25 24 Reserved Mask1 of JPG_frm_done Mask1 of deblk_done Bits 25-16 Mask of the interrupt for the internal CPU wakeup 1: Enable the related condition to the internal CPU 0: Mask the related condition to the internal CPU Bits 9-0 Mask of the interrupt for the internal CPU interrupt 1: Enable the related condition to the internal CPU 0: Mask the related condition to the internal CPU 14.3.31. 7 Mask2 of
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External CPU Interrupt Mask Register (EXT_MASK, Offset == 0x20094) 6 Mask2 of 5 Mask2 of Table 14-34. EXT_MASK 4 3 2 Mask2 of Mask2 of Mask2 of
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Technical Reference Manual DMA_done VLD_done VLC_done DT_done PMV_done PXI_done 31-14 13 12 11 10 9 Reserved Mask of Mask of Mask of Mask of Mask2 of JPG_VLD_ JPG_sys_ JPG_sys_b JPG_FFD7 JPG_frm_d error buff_empty uff_full _ Marker one Bits 13-0 Mask of the interrupt for the external CPU interrupt 1: Enable the related condition to the external CPU 0: Mask the related condition to the external CPU 14.3.32. Bit 31 Interrupt Flag (after masked) Register (INT_FLAG, Offset == 0x20098) Symbol
Flag of ext interrupt

MC_done ME_done 8 31-14 Mask2 of Reserved deblk_done

30

Flag of inner interrupt

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15-10 9 8 7 6 5 4 3 2 1
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Flag of JPG_VLD_error Flag of JPG_sys_buff_empty Flag of JPG_sys_ buff_full Flag of JPG_FFD7_MARKER Flag2 of JPG_FRM_DONE Flag2 of deblk_done Flag2 of DMA_done Flag2 of VLD_done Flag2 of VLC_done Flag2 of DT_done Flag2 of PMV_done Flag2 of PXI_done Flag2 of MC_done Flag2 of ME_done

Table 14-35. INT_FLAG Description Read: Flag status of the interrupt (set by the software in INNER_CPUCTL[20]) for the external CPU Write 1: Clear this flag Write 0: No effect Read: Flag status of the interrupt (set by the software in INNER_CPUCTL[16]) for the internal CPU Write 1: Clear this flag Write 0: No effect Read: Flag status (after masked by EXT_MASK[13:0]) of the interrupt for the external CPU interrupt Write 1: Clear the corresponding bit of the interrupt Write 0: No effect

Reserved
Flag0 of JPG_FRM_DONE Flag0 of deblk_done Flag0 of DMA_done Flag0 of VLD_done Flag0 of VLC_done Flag0 of DT_done Flag0 of PMV_done Flag0 of PXI_done Flag0 of MC_done

Read: Flag status (after masked by INNER_MASK[8:0]) of the interrupt for the internal CPU interrupt Write 1: Clear the corresponding bit of the interrupt. Write 0: No effect Note that the effect of write 1 command to INT_FLAG[9:0] and to INT_FLAG[25:16] are the same; i.e. both write 1 to INT_FLAG[0] and to INT_FLAG[16] will clear the ME_done interrupt flag (status).

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Technical Reference Manual 0 14.3.33. Bit 31 30 29-28 27 26 25 24 23 22-9 8 7 6 5 4 3 2 1 0 14.3.34.

Flag0 of ME_done

Interrupt Status (before masked) Register (INT_STS, Offset == 0x2009C) Symbol Status of ext interrupt Status of inner interrupt Reserved Status of JPG_VLD_ error Status of JPG_sys_ buff_empty Status of JPG_sys_buff_full Status of JPG_FFD7_ MARKER Status of JPG_FRM_DONE Reserved Status of deblk_done Status of DMA_done Status of VLD_done Status of VLC_done Status of DT_done Status of PMV_done Status of PXI_done Status of MC_done Flag0 of ME_done Table 14-36. INT_STS Description Read: Status of the interrupt (set by the software in INNER_CPUCTL[31]) for the external CPU Write: No effect Read: Status of the interrupt (set by the software in INNER_CPUCTL[30]) for the internal CPU Write: No effect Read: Status (before being masked) of the external CPU interrupt Write: No effect

Status (before being masked) of the internal/external CPU interrupt Write: No effect

Minimum Coded Unit Block Number Register (MCUBR, Offset == 0x20008) Table 14-37. MCUBR 31 4 30 MCUBLKN Number of blocks per MCU The number of blocks in MCU will be defined by the Hi and Vi , which are defined at the header of JPEG files. Total block number is equal to or less than ten, which can be calculated by where N101=sNjjjVHs is the total components in image, which is usually equal to one or three.

Bit 3-0

14.3.35.

Minimum Coded Unit Table Index Register (MCUTIR, Offset == 0x2002C)

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Technical Reference Manual Table 14-38. MCUTIR 31 20 TBIDX Bit 31-20 Bits 23-20 Bits 27-24 Bits 31-28 Table index of JPEG mode Table index in component one Table index in component two Table index in component three 19 0 COMP

In the table index of each component, the lower two bits (ex. bits 21-20) indicate the quantization table index, and bits 23-22 indicate the AC, DC Huffman table index respectively. C2_ha C2_hd C2_q C2_q C1_ha C1_hd C1_q 31 30 29 28 27 26 25 Bit 19-0 Component index of each block per MCU Bits 1-0 Bits 3-2 Bits 17-4 Bits 19-18 14.3.36. Component index in block number one Component index in block number two . Component index in block number ten JPEG Previous Y DC Value Register (PYDCR, Offset == 0x20030) Table 14-39. PYDCR 31 16 15 0 PYDC Bit 15-0: Previous DC value of component Y in the JPEG mode At the start of an image PYDC=0, after the restart marker, the value in this register will be reset. 14.3.37. JPEG Previous UV DC Value Register (PUVDCR, Offset == 0x20034) Table 14-40. PUVDCR 31 16 15 0 PUDC PVDC Previous DC value of component U in the JPEG mode At the start of an image PUDC=0, after the restart marker, the value in this register will be reset. Bit 15-0 Previous DC value of component V in JPEG mode At the start of an image PVDC=0, after the restart marker, the value in this register will be reset. 14.3.38. 31 15
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C1_q 24

C0_ha 23

C0_hd 22

C0_q 21

C0_q 20

Bit 31-16

VLD Look Up Table Register (VLDLUTR, Offset == 0x20068) 14 12 LUTAC1 11 Table 14-41. VLDLUTR 10 8 7 64 LUTDC1 LUTAC0
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Technical Reference Manual The VLD look up table register for jpeg mode. Bit 14-12 Bit 10-8 Bit 6-4 Bit 2-0 14.3.39. Initial length of data to look up codeword in DC table 0. Initial length of data to look up codeword in AC table 0. Initial length of data to look up codeword in DC table 1. Initial length of data to look up codeword in AC table 1. VLC Last Word Register (VLASTWORD, Offset == 0x2006C)

Table 14-42. VLASTWORD 31 0 Last-word Bit 31-0: VLC last-word register for jpeg mode. The last-word register indicates the last un-finished word in the bit-stream. Put the last-word into the register before starting VLC process. Get the last-word after VLC process if the CPU needs to pack the other information behind the current result. The VLC will pack the data from MSB to LSB. 14.3.40. JPEG Sequencer Control register (JPGSeqCtl, Offset == 0x200A0)

Table 14-43. JPGSeqClt 31-4 3 2 1 0 Flush_bits FFD7_int_en Start JPEG sequencer Stop JPEG sequencer Bit 3 Flush_bits Setting this bit to 1 will flush out the bitstream from the JPEG encoder local memory to system memory. This bit is auto-cleared. Bit 2 Insert FFD7 interrupt enable In the JPEG encode mode, if the user sets this bit to 1, the hardware will send an interrupt to the system CPU whenever it inserts an FFD7 restart marker. Bit 1 Bit 0 Start the JPEG sequencer. Setting this bit to 1 will start the JPEG sequencer. This bit is autocleared. Stop the JPEG sequencer In the JPEG encode mode, set this bit to terminate the encoding procedure. This bit is auto-cleared. 14.3.41. 31-29 Bits 28-26 JPEG Frame Information Register 1 (JPGFrmInfo1, Offset == 0x200A4) Table 14-44. JPGFrmInfo1 28-26 25 13 YUV_format MCUrows_minus1 YUV_format 0: YUV420 1: YUV422 2: YUV211
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Technical Reference Manual 3: YUV333 4: YUV222 5: YUV111 Note: In the YUV333 mode, the JPEG encoder only supports a frame of which the image width is the multiple of 24 pixels. Bits 25-13 Bits 12-0 MCUrows_minus1 Plus 1 specifies the total numbers of the MCU rows in the current encoded frame in the JPEG encode mode. MCUcols_minus1 Plus 1 specifies the total numbers of the MCU columns in the current encoded frame in the JPEG encode mode. 14.3.42. JPEG Frame Information Register 2 (JPGFrmInfo2, Offset == 0x200A8) Table 14-45. JPGFrmInfo2 31 16 Reserved Restart_interval 15 0 restart_interval

Bit 15-0

This register indicates the restart interval of the current encoded frame in the JPEG encode mode. 14.3.43. JPEG Frame Information Register 3 (JPGFrmInfo3, Offset == 0x200AC) Table 14-46. JPGFrmInfo3 31 0 bitslen Bits 31-0: bitslen This register indicates the bitstream length in units of bytes in the JPEG encode mode. 14.4. ME Command Definitions

14.4.1. ME Buffer Structure The ME buffer in local memory consists of MV buffer which stores MV values for 4MV mode and 1MV mode, MVD buffer which stores differential motion vectors, previous SAD command buffer which stores up to 4 different previous SAD commands, and command buffer which is filled by CPU. The ME buffer size is up to 128 words and the start address CMDADDR must be 128-word aligned. The following figure shows ME buffer structures. Note that the ME commands must be put from address CMDADDR+64 in encoding mode and from address CMDADDR+52 in decoding mode. The PMV buffer which stores MV values of block 2/3 of previous row is stored in a separate local memory space. The PMV buffer size is up to 256 words which support horizontal frame size up to 2048 pixels. The PMV buffer start address must be 256-word aligned. The search MV for encoding mode is stored in MV0

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Technical Reference Manual and MV1 buffers alternately for each MB. The calculated MV for decoding mode is stored in MVD and MVuv buffer (a subset of MV buffer). ME Buffer in Encoding Mode

Figure 14-11. ME Buffer in encoding mode ME Buffer in Decoding Mode

Figure 14-12. MV Buffer Definition

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ME Buffer in decoding mode

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Technical Reference Manual Encoding mode 31- 26 Bit 25-19 25 - 19 MVX 18 - 12 MVY 11 - 0 RADD

Horizontal motion vector The search result horizontal motion vector in the encoding mode Bit 18-12 Vertical motion vector The search result vertical motion vector in the encoding mode Bit 11-0 Reference block start address This field is updated automatically by ME hardware. Decoding Mode 31 - 16 15 - 0 MVX MVY Horizontal motion vector The horizontal motion vector for PXI command in the decoding mode Vertical motion vector The vertical motion vector for PXI command in the decoding mode

Bit 31-16 Bit 15-0

MVD Buffer Definition 31 - 16 15 - 0 MVDX MVDY Horizontal differential motion vector/horizontal motion vector The horizontal differential motion vector in the encoding mode The calculated horizontal motion vector in the decoding mode Vertical differential motion vector/vertical motion vector The vertical differential motion vector in the encoding mode The calculated vertical motion vector in the decoding mode

Bit 31-16 Bit 15-0

Prediction MV Buffer Definition: 31 - 16 MVX Bit 31-16 15 - 0 MVY

Horizontal prediction motion vector The horizontal prediction motion vector in the decoding mode Bit 15-0 Vertical prediction motion vector The vertical prediction motion vector in the decoding mode Table below lists all supported ME commands and their descriptions. Table 14-47. ME Commands Symbol CMD[2:0] Description PMVX 000 Set horizontal prediction vector command PMVY 001 Set vertical prediction vector command SAD 010 Perform SAD calculation based on a given motion vector DIA 011 Perform diamond search repeatedly to find the best motion vector REF 100 Perform half-pixel refinement based on previous found best motion vector by diamond search MOD 101 Intra/inter mode decision command
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Technical Reference Manual PXI 110 Perform pixel interpolation of the reference block and output the interpolated result block to local memory 28 26 25 BSIZE 24 - 23 BK_NUM 22 - 0 -

Set Prediction Vector Commands 31- 29 000/001 Bit 31-29 Bit 25 Bit 24-23 31- 29 010 Bit 31-29 Bit 28

Command type These bits should be 0 for setting horizontal prediction vector, and 1 for setting vertical prediction vector. Block size 0 for 4MV mode, and 1 for 1MV mode. This is used in encoding mode only. It should be 0 in decoding mode. Block number Current block number, which should be 0 when BSIZE=1. 28 last Command type These bits should be 0x2 for SAD command. Last SAD command This bit should be set to 1 for the last SAD command in a sequence of SAD commands; otherwise, it should be set to 0. 27 MPMV 26 SRC 25 - 19 MVX 18 - 12 MVY 11 - 0 RADD

SAD command

Bit 27

Use Median Predictor This bit is set to 1 if the vector for SAD command is from the median prediction vector calculated in previous PMV command.

Bit 26

SAD vector source This bit specifies the source for the motion vector MVX, MVY, and reference start address RADD. If it is 0 then use the fields defined in this command; otherwise, the source is from MV buffer. This bit is meaningful only when MPMV bit is 0.

Bit 25-19

Horizontal motion vector/Index to motion vector If the SRC bit is 0 then this field is used as horizontal motion vector; otherwise, it is used as an index to the MV buffer to get the motion vector and reference start address.

Bit 18-12 Bit 11-0

Vertical motion vector This field is unused if SRC=1. Reference block start address The start address of the first row of the reference block in words. This field is unused if SRC=1.

Diamond Command

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Technical Reference Manual 31- 29 011 Bit 31-29 Bit 24 28 - 25 Command type These bits should be 0x3 for diamond command. Diamond size Select big or small diamond for diamond search. dsize=0 selects small diamond and dsize=1 selects big diamond. Bit 23-16 Bit 15-0 Maximum diamond search iterations These bits set the maximum diamond search iterations. Threshold for minimum SAD These bits set the SAD threshold to stop diamond search. When the minimum SAD result in the current diamond search is less than or equal to MinSADth the diamond search is stopped. Half-Pel-Refine Command 31- 29 100 Bit 31-29 Command type Bit 28 Bit 27-16 4MV mode enable This bit should be set to 1 if 4MV mode is used. 1MV/4MV threshold Threshold used for 1MV/4MV mode decision. If SAD for 4MV result SAD for 1MV result SAD8th then choose 1MV mode else choose 4MV mode. Bit 15-0 Threshold for minimum SAD These bits set the SAD threshold to skip Half-Pel-Refine search. When the minimum SAD result in the previous search commands is less than or equal to MinSADth, the Half-PelRefine search is skipped. Intra/Inter Mode Decision Command 31- 29 101 Bit 31-29 Bit 28 Command type These bits should be 0x5 for intra/inter mode decision command. Enable mode decision command This bit is set to 1 to enable intra/inter mode decision. 28 MODEN 27 - 16 15 - 0 intraSADth 28 4MV 27 - 16 SAD8th 15 - 0 MinSADth 24 dsize 23 - 16 maxloop 15 - 0 MinSADth

These bits should be 0x4 for Half-Pel-Refine command.

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Technical Reference Manual Bit 15-0 Threshold for intra/inter mode When SAD result intraSADth > CURDEV then choose intra mode else choose inter mode. Pixel Interpolation Command Encoding mode: 31 - 29 110 Bit 31-29 Bit 28 Bit 27 28 last Command type These bits should be 0x6 for pixel interpolation command. Last command This bit is set to 1 for the last pixel interpolation command. Component type Chroma=0 selects luminance (Y) component for pixel interpolation. Chroma=1 selects chrominance (Cb or Cr) component for pixel interpolation Bit 11-0 Reference block start address The start address of the first row of the reference block in words (4-pixel) when the vertical motion vector is zero. These bits are used only when Chroma=1. Decoding mode 31 - 29 110 22 BUF_NUM Bit 28 Bit 27 Last command This bit is set to 1 for the last pixel interpolation command. Component type Chroma=0 selects luminance (Y) component for pixel interpolation. Chroma=1 selects chrominance (Cb or Cr) component for pixel interpolation. Bit 24-23 Bit 22 Bit 11-0 Block number Current block number, which should be 0 when Chroma=1. Buffer number PXI command buffer number. Reference block start address The start address of the reference block in words (4-pixel) ME Command Sequence Example Table below gives an example of ME command sequence in encoding mode and Table 4-6 gives an example of ME command sequence in decoding mode. 28 last 27 Chroma 21 -12 26 - 25 11:0 RADD 24-23 BK_NUM 27 Chroma 26 - 12 11 - 0 RADD

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Technical Reference Manual Table 14-48. ME Command Sequence Example in Encoding Mode Command Note PMVX command, BSIZE=1 For 1MV mode: The MV result is stored in MV buffer [3], and the PMVY command, BSIZE=1 MVD result is stored in MVD buffer [3]. SAD command SAD command Diamond command Refine command PMVX command, BSIZE=0, BK_NUM=0 For 4MV block 0: MV result is stored in MV buffer [0], and MVD result PMVY command, BSIZE=0, BK_NUM=0 is stored in MVD buffer [0]. SAD command SAD command Diamond command Refine command PMVX command, BSIZE=0, BK_NUM=1 For 4MV block 1: MV result is stored in MV buffer [1], and MVD result PMVY command, BSIZE=0, BK_NUM=1 is stored in MVD buffer [1]. SAD command SAD command Diamond command Refine command PMVX command, BSIZE=0, BK_NUM=2 For 4MV block 2: The MV result is stored in MV buffer [2], and the PMVY command, BSIZE=0, BK_NUM=2 MVD result is stored in MVD buffer [2]. SAD command SAD command Diamond command Refine command PMVX command, BSIZE=0, BK_NUM=3 For 4MV block 3: Decide the 1MV/4MV mode, and MV result will be PMVY command, BSIZE=0, BK_NUM=3 stored to MV buffer [3] and MVD result stored in SAD command MVD buffer [3] if 4MV mode is used. SAD command Diamond command Refine command Mode decision command Decide intra/inter mode (optional) PXI command for Y These commands will be skipped if the mode PXI command for U PXI command for V, last = 1 Table 14-49. ME Command Sequence Example in Decoding Mode Command Note PMVX command, BK_NUM=0 Calculate predictor and MV for block 0 or for all blocks in the 1MV mode Skips following PMV commands if 1MV mode is used.
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Technical Reference Manual PMVY command, BK_NUM=0 PMVX command, BK_NUM=1 PMVY command, BK_NUM=1 PMVX command, BK_NUM=2 PMVY command, BK_NUM=2 PMVX command, BK_NUM=3 PMVY command, BK_NUM=3 PXI command for Y, BK_NUM=0 MV result will be stored to MVD buffer [0] (BSIZE = 0) or MVD buffer [3] (BSIZE = 1). Calculate predictor and MV for block 1 These commands will be skipped in the 1MV mode Calculate predictor and MV for block 2 These commands will be skipped in the 1MV mode. Calculate predictor and MV for block 3 These commands will be skipped in the 1MV mode. Performs pixel interpolation for all luminance blocks if BSIZE = 1 or for block 0 if BSIZE = 0. Skip following PXI command for Y if BSIZE = 1. Skip all PXI commands if SKIP_PXI = 1. Performs pixel interpolation for block 1. Performs pixel interpolation for block 2. Performs pixel interpolation for block 3.

PXI command for Y, BK_NUM=1 PXI command for Y, BK_NUM=2 PXI command for Y, BK_NUM=3 PXI command for U PXI command for V 14.4.2. DMA Control Registers

There is an AHB slave interface connected to the DMA control registers. These control registers define the behavior of the DMA controller. The host processor can access these registers through the AHB system bus. Symbol SMaddr LMaddr BlkWidth Control CCA Status Reserved GRPC GRPS ABF_ctrl THRESHOLD AUTOINT Sys_buf_size MCUYrow_offset MCUUrow_offset Offset 0x20400 0x20404 0x20408 0x2040C 0x20410 0x20414 0x20418 0x2041C 0x20420 0x20424 0x20428 0x2042C 0x20430 0x20434 0x20438 Table 14-50. DMA Control Registers Size Access Description 30 R/W System memory base address (word aligned) 14 R/W Local memory base address (word aligned) 32 R/W Block width information 32 R/W Control register and transfer length register (word) 30 R/W Chain command address (four-word aligned) 4 R/W Status register Reserved 32 R/W Group execution control 32 R/W Group sync control 2 R/W Auto-buffer control 12 R/W DMA threshold value 1 R/W Auto send interrupt even last cmd is skip/disable 26 R/W The bitstream buffer size in the system memory in units of 64 bytes 29 R/W The start address offset between two MCU Y component of each neighboring MCU row 29 R/W The start address offset between two MCU U component of each neighboring MCU
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Technical Reference Manual row MCUVrow_offset 0x2043C 29 R/W The start address offset between two MCU V component of each neighboring MCU row

14.4.3. DMA System Memory Base Address Register (Offset == 0x20400) Table 14-51. DMA System Memory Base Address Register 31 - 3 2-0 System Memory Base Address Increment Index Bit 31-3 Bit 2-0 System memory base address (should be 8 byte aligned). Increment Index. The index is used to specify an offset. The system memory base address will be automatically increased by the offset after the transfer command has been executed. Only the commands in the internal memory support the auto-increment function. Index: Increment amount In the JPEG mode only: 0: No change 1: +8 bytes 2: +16 bytes 3: +24 bytes 4: +32 bytes 5: +48 bytes 6: +64 bytes 7: +128 bytes In other cases: 0: No change 1: +16 bytes 2: +32 bytes 3: +48 bytes 4: +64 bytes 5: +128 bytes 6: +256 bytes 7: +512 bytes 14.4.4. DMA Local Memory Base Address Register/Block Width Register, Offset == 0x20404) Table 14-52. DMA Local Memory Base Address /Block Width Register
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Technical Reference Manual 31 - 28 3rd Block Width Bit 31-28 Bit 27-20 Bit 19-16 Bit 15-2 Bit 1-0 15 - 2 Local Memory Base Address Third block width of the 4D block addressing mode Second block offset of the 3D block addressing mode Second block width of the 3D block addressing mode Local memory base address (Unit: 8 byte) Increment Index The index is used to specify an offset. The local memory base address will be automatically increased by the offset after the transfer command has been executed. Only the commands in the internal memory support the auto-increment function. Index: Increment amount 0: No change 1: +16 bytes 2: +32 bytes 3: +64 bytes In the JPEG encode mode, the users should fill the local memory base address with 0xA000. 14.4.5. DMA Block Width Register (Offset == 0x20408) 31 - 24 Local Memory Line Offset (word) Bit 31-24 Bit 23-20 Bit 19-6 Table 14-53. DMA Block Width Register 23 - 20 19 - 6 Local Memory Block System Memory Line Width (word) Offset (word) 5-0 System Memory Block Width (2-words) 27 - 20 2nd Block Offset 19 - 16 2nd Block Width 1-0 Increment Index

Local memory data line offset The data line offset is the frame width minus block width. Local memory block width Indicates the width of a 2D block in word System memory data line offset The data line offset is the frame width minus block width. The offset is a 14-bit signed integer and the range is from -8192 to 8191, ie. if negative value is wanted, user can fill 2complement value to this field. The unit is word.

Bit 5-0:

System memory block width Indicates the width of a 2D block. The unit is 8-byte.

14.4.6. DMA Control and Length Register (Offset == 0x2040C) 15 - 12 ID 23 22 Enable Reserved 31 - 28 3rd Block Offset Bit 31-28 Bit 27
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Table 14-54. DMA Control and Length Register 11 - 0 Transfer Length 21 20 19 18 Chain Dir LType SType 27 26 Reset TDmask

17 Enable 25 BEINT

16 Reserved 24 TDINT

Third block offset of the 4D block addressing mode Reset

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Technical Reference Manual Resets Whole FTMCP100 circuits controller. Setting this bit high will reset the DMA controller. This bit is self-cleared after a few HCLK period (since both CPCLK and HCLK domain circuits will be reset). Bit 26 Bit 25 Bit 24 Bit 23 Transfer done flag mask Masks the transfer done flag in chain transfer operation. Bus error interrupt enable Enables the bus error interrupt Transfer done interrupt enable Enables the transfer done interrupt Enable Setting this bit high will enable the DMA controller to start data transfer. This bit will be cleared by the DMA controller if the data transfer is completed. Clearing this bit will enable the DMA controller to discard the current data transfer. If the host sets this bit high after clearing this bit, the data transfer will re-start from the first data word. Bit 21 Enable chain transfer Enables the DMA controller to load the next command from the system memory indicated by CCA register. Bit 20 Transfer direction 0: Data transfer from the system memory to the local memory 1: Data transfer from the local memory to the system memory Bit 19-18 Local memory data type 00: Sequential data 01: 2D data block 10: 3D data block 11: 4D data block Bit 17-16 System memory data type 00: Sequential data 01: 2D data block 1x: Reserved Bit 15-12 Bit 11-0 Command ID Indicates the ID number of current command Transfer length Specifies the length of data to be transferred in word. The maximum transfer length is 4095 words (16380 bytes).

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Technical Reference Manual 14.4.7. DMA Chain Command Address Register (Offset == 0x20410) 31 - 4 CCA Bit 31-4 Table 14-55. DMA Chain Command Address Register 3-0 Reserved Chain command address. Indicates the address of the next command for the DMA controller. Each command set is 4 words long. The sequence of command set should be arranged sequentially in the Local memory. The chain command address register will increase by 4 words after the current command set is loaded. 14.4.8. DMA Status Register (Offset == 0x20414) 31 - 7 Reserved Bit 2 Bit 1 Table 14-56. DMA Status Register 6 5 4 3 Reserved Reserved Reserved Reserved Auto-buffer ready Auto-buffer is ready for read or write. Bus error flag This bit will be set if a bus transfer error occurs in the AHB bus. User need to write 0 if want to clear this bit. Bit 0 Transfer done flag This bit will be set if a data transfer operation is completed. This bit will be cleared after the enable bit in the control register is set. 14.4.9. DMA Group Control Register (Offset == 0x2041C) Table 14-57. DMA Group Control Register
31-30 GP15 29 - 28 GP14 27 -26 GP13 25 - 24 GP12 23 - 22 GP11 21 - 20 GP10 19 - 18 GP9 17 - 16 GP8 15 - 14 GP7 13 - 12 GP6 11 - 10 GP5 9-8 GP4 7-6 GP3 5-4 GP2 3-2 GP1 1-0 GP0

2 ABF_rdy

1 BEfg

0 TDfg

GPx

Specify the execution type of each group of command 0: Normal execution 1: Skip this transfer but auto-increment function is still work 2: Disable this command 3: Sync to specified condition.

14.4.10.

DMA Group Sync Register (Offset == 0x20420) Table 14-58. DMA Group Sync Register

31-30 GP15

29 - 28 GP14

27 -26 GP13

25 - 24 GP12

23 - 22 GP11

21 - 20 GP10

19 - 18 GP9

17 - 16 GP8

15 - 14 GP7

13 - 12 GP6

11 - 10 GP5

9-8 GP4

7-6 GP3

5-4 GP2

3-2 GP1

1-0 GP0

GPx: Specify the source to synchronization

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Technical Reference Manual 0: Sync to VLD_done 1: Sync to DT_done 2: Sync to MC_done 3: When MCCTL[20], Deblk_EN = 0: Sync to VLC_done When MCCTL[20], Deblk_EN = 1: Sync to Deblking_done 14.4.11. DMA Auto-buffer Control Register (Offset == 0x20424) 11 - 0 ABF_cnt

Table 14-59. DMA Auto-buffer Control Register 31 30 29 - 12 ABF_cnt_en ABF_last Reserved Bit 31 Enables the auto-buffer bit-stream length counter Bit 30 Denotes the end of bit-stream after the counter decreased to zero.

If the last bit is set and the counter is decreased to zero, the VLD module will return to idle and raise an error flag with bit-stream end. Bit 11:0 Auto-buffer available bit-stream length counter The value of the counter means the available bit-stream length in times of 64 byte. If the available bit-stream length is 1024 byte in the system memory, the counter should be set to 16. Each time the DMA module read a 64-byte block from the system memory, the counter will be decreased one until the counter becomes zero. If the counter becomes zero, the decoder will wait the host controller to reset this counter and a flag in the VLD status register will be set to inform the host controller. 14.4.12. DMA Threshold Value Register (Offset== 0x20428)

Table 14-60. DMA Threshold Value Register 31 - 12 11 - 8 7-4 3-0 Reserved Write threshold Reserved Read threshold Bit 11:8 DMA will write data to AHB bus if FIFO counter is larger than write threshold value. Bit 3:0 DMA will start read data from AHB bus if FIFO counter is smaller than or equal to read threshold value. 14.4.13. DMA Auto Interrupt Register (Offset: 0x2042c) Table 14-61. DMA Auto Interrupt Register 31 - 1 Reserved 0 a) 0 autoint

DMA will send interrupt mcp_int when each valid cmd (not skip/disable) done with bit24 and Bit26 of DMA Control Reg of that command is properly set.

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Technical Reference Manual b) DMA will set bit0 of DMA Status Reg to 1 (and will be cleared at next command) when each valid cmd (not skip/disable) done with the bit26 of DMA Control Reg of that command is properly set. c) 1 a) The last command of command chain must be a valid (not skip/disable) command. DMA will send interrupt mcp_int when all command chain done (last command can be skip/disable) if the bit24 and bit26 of DMA Control Reg of last command is set properly. b) DMA will set bit0 of DMA Status Reg to 1 (and will be cleared at next command) when each valid cmd (not skip/disable) or last not valid command done with bit26 of DMA Control Reg of that command is properly set. c) The last command of command chain can be a skip/disable command, but at most one mcp_int pulse will be sent during command chain. 14.4.14. System Bitstream Buffer Size (Offset ==0x20430) Table 14-62. System Bitstream Buffer Size 31 6 sys_buf_size Bit 31-6 sys_buf_size This register indicates the bitstream buffer size in the system memory. (It should be 64 byte align. i.e. the bits [5:0] will be ignored). This register should be updated whenever the system CPU allocate a new buffer for the JPEG encoder. 14.4.15. JPEG Frame Information Register 4 (JPGFrmInfo4, Offset == 0x20434) Table 14-63. JPEG Frame Information Register 4 31 2 2 0 MCUYrow_offset -Bit 31-3 MCUYrow_offset The address offset between the Y component start address of the last MCU in one MCU row and the Y component start address of the 1st MCU in the next MCU row (It should be 8 byte align, i.e. the bits [2:0] will be ignored) 14.4.16. JPEG Frame Information Register 5 (JPGFrmInfo5, Offset == 0x20438) Table 14-64. JPEG Frame Information Register 5 31 3 2-0 MCUUrow_offset -50 --

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Technical Reference Manual Bit 31-3 MCUUrow_offset The address offset between the U component start address of the last MCU in one MCU row and the U component start address of the 1st MCU in the next MCU row (It should be 8 byte align, i.e. the bits [2:0] will be ignored). 14.4.17. JPEG Frame Information Register 6 (JPGFrmInfo6, Offset == 0x2043C) Table 14-65. JPEG Frame Information Register 6 31 3 2-0 MCUVrow_offset -MCUVrow_offset The address offset between the V component start address of the last MCU in one MCU row and the V component start address of the 1st MCU in the next MCU row (It should be 8 byte align, i.e. the bits [2:0] will be ignored).

Bit 31-3:

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15. Video Capture

15.1.

General Description

The video capture is in charge of capturing video data from ITU-R BT.656 or SONY 16-bit YUV interface. It provides de-interlace function to reduce video artifact for interlace video. Noise reduction can remove unwanted noise and preserve fine details and edges. With size down ability, user can size down image to the resolution needed individually for preview or record path. Color OSD function at record path can help user to paste any characters at captured video. Window clipping function can clip the region of interest from image before or after size down. One loop-back path provides to read image through AHB slave for the purpose of any possible application. It supports the following features: Three 8/10-bit video input ports Maximum input capture resolution up to 1920 x 1080 Video input format o o o ITU-R BT 656 8/16-bit input interface ITU-R BT.1120 16/20-bit input interface YCbCr 4:2:2 8/16-bit with H/V reference control signal interface RGB 888 RGB 565 YCbCr 4:4:4 YCbCr 4:2:2 YCbCr 4:2:0

Output image format o o o o o

Edge-based line average de-interlacer Noise reduction Maximum 128 fonts with 12 x 18 size in a window for the color OSD at the record path Individual image size down with independent integer horizontal and vertical ratios at preview and record path Individual frame skip function at preview and record path VBI (vertical blanking interval) data extraction Input/Output Image crop Add the color border at the output Image Output formats o RGB 888/RGB 565

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Technical Reference Manual o o o YCbCr 4: 4: 4 YCbCr 4: 2: 2 YCbCr 4: 2: 0

Raster and macro block order output sequence Maximum 2-frame ring buffer control Loop-back path to read image data from memory to do the post-image processing

The below figure illustrates the simplified block digram of the video capture block

Line Buffer

Line Buffer

FIFO

Denoise CAP0_DATA CAP1_DATA CAP2_DATA Video Port DeInterlace

Source/ Target Window Clip

Size Down

Preview DMA

AHB Master1

Preview

Color Space Conversion

OSD

Record DMA

AHB Master0

Recording

Line Buffer

VSI Extraction

Font RAM

FIFO

AHB Slave

Figure 15-1. Video Capture Block 15.2. Video Port This block is used to receive video data from various type of video interfaces. It can be Y/C mix in one 8/10-bit separated or Y/C separated in two 8/10-bit data. H/V synchronous timing can be as time code embedded in video stream or be referred to H/V reference input signals. 15.2.1. ITU-R BT. 656 Table 15-1. D7 1 0 0 1 D6 1 0 0 F U-R BT. 656 EAV and SAV Sequence 8-bit Data D5 D4 D3 D2 1 1 1 1 0 0 0 0 0 0 0 0 V H P3 P2

Preamble Status

D1 1 0 0 P1

D0 1 0 0 P0

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Figure 15-2. Vertical Interval of ITU-BT.656 Only the SAV and EAV sequences are used to recover the video timing. Dont make any assumption about the number of clock cycles per line or horizontal blanking interval. 15.2.2. ITU-R BT. 656 like D7 1 0 0 1 1 1 1 1 D6 1 0 0 F 0 0 0 0 D5 1 0 0 V 1 1 0 0 8-bit Data D4 D3 1 1 0 0 0 0 H P3 0 1 1 0 0 0 1 1 D2 1 0 0 P2 0 1 0 1 D1 1 0 0 P1 1 1 0 0 D0 1 0 0 P0 1 0 0 1

Preamble Status word Vertical start (VS) Vertical start (VE) Horizontal start (HS) Horizontal start (HE)

Vertical Active

Horizontal Active X_CAP _ DATA VS SAV HS Cb SAV Y Cr Y HE EAV HS Cb SAV Y Cr Y HE EAV VE EAV

Figure 15-3. Timing of ITU-R BT. 656 like Note: No EAV/SAV code for horizontal line during vertical blank 15.2.3. 8-/16-bit H/V Reference Control Interface

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Figure 15-4. Vertical timing of 8-bit H/V Reference Control

Figure 15-5. Horizontal Timing of 8-bit H/V Reference Control The sequence of Cb and Cr can be swapped. The active polarity of vcap_hsync and vcap_vsync can be set to high or low. 15.2.4. 8-/16-bit H/V Sync Control Interface

Figure 15-6. Vertical Timing of 16-bit H/V Sync. Control

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Figure 15-7. Horizontal Timing of 16-bit H/V Sync. Control The sequence of Cb and Cr can be swapped. The active polarity of vcap_hsync and vcap_vsync can be set to high or low. 15.3. De-interlacer

This block is used to perform the conversion from interlaced field to progressive frame. Even or Odd row in the original image will be removed and interpolated by the neighboring existing raw. An edge-based line average method used in the block can find the best interpolation points to generate progressive frame to reduce video artifact from interlaced field. 15.4. De-noise

This block is used to remove undesired salt and pepper noise. Controllable threshold can help user to choose to preserve more image details or reduce more image noise by different conditions. 15.5. Size-down

This block is used to size-down the image with independent integer horizontal and vertical ratio down to 1/127. The ratio of size down can be independent on two video capture paths. Line buffers are needed for the size-down algorithm to provide high quality size-down image

Figure 15-8. Independent Preview and Record Path Size-down

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Technical Reference Manual 15.6. OSD This block is used to paste any characters to video capture data on one record path. Four windows with different attribute can be defined. 64 fonts with size of 12 x 18 are programmable and max. 128 fonts can be shown on the display window. Adjustable font size, font space, font color, and transparency attribute are provided for variety applications. 15.7. 15.8. Color Space Conversion Window Clip

This block is used to do color space conversion between YCbCr and RGB domain. This block is used to clip the region of interest from image before or after size down. Color border with controllable width can be appended to clipping window. 15.9. VBI Extraction This block is used to extract Vertical Blanking Interval (VBI) data into specified memory location 15.10. DMA This block is used to send video data with any color format into any memory location by scan-line or macro block order. FIFO depth is configurable depending on the available bandwidth on the system. 15.11. Video Data Output Format The format of video capture data output to memory can be RGB888, RGB565, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0. The sequence can be raster order (RGB888/RGB565/YCbCr 4:4:4/YCbCr 4:2:2) or macro block order (YCbCr 4:2:2/YCbCr 4:2:0). The number of the memory block can be one single block (RGB888/RGB565/YCbCr 4:4:4/YCbCr 4:2:2 with raster order), 2 split memory block (YCbCr 4:2:2/YCbCr 4:2:0 with macro block order), and 3 separated memory block (YCbCr 4:2:2/YCbCr 4:2:0). 15.11.1. RGB888 0x0 B0G0R0 B1 R0G0B0 R1 0x0 B0G0R0 B1G1R1 R0G0B0 R1G1B1 0x0 Cb0Y0Cr0 Cb1 Cr0Y0Cb0 Cr1 0x4 G1R1B2 G2 G1B1R2 G2 0x4 B2G2R2 B3G3R3 R2G2B2 R3G3B3 0x4 Y1Cr1Cb2 Y2 Y1Cb1Cr2 Y2 0x8 R2B3G3 R3 B2R3G3 B3 0x8 B4G4R4 B5G5R5 R4G4B4 R5G5B5 0x8 Cr2Cb3Y3 Cr3 Cb2Cr3Y3 Cb3

Offset Data Data (BR Swap) 15.11.2. RGB565 Offset Data Data (BR Swap) 15.11.3. YCbCr 4:4:4 Offset Data Data (BR Swap) 15.11.4. YCbCr 4:2:2

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Technical Reference Manual Offset Data Data (BR Swap) 15.11.5. 0x0 Cb0Y0Cr0 Y1 Cr0Y0Cb0 Y1 0x4 Cb2Y2Cr2 Y3 Cr2Y2Cb2 Y3 0x8 Cb4Y4CR4 Y5 Cr4Y4Cb4 Y5

Macro Block Order Sequence

Figure 15-9. Macro Block Order in One Image 15.11.6. Macro Block 16 x 16
(y , x)
( 0 , 0) (0 , 0) (1 , 0) (2 , 0) (3 , 0) (4 , 0) (5 , 0) (6 , 0) (7 , 0) (8 , 0) (9 , 0) ( 10 , 0 ) ( 11 , 0) ( 12 , 0) (13 , 0 ) ( 14 , 0) ( 15 , 0) (0 , 1) (0 , 2) (0 , 3 ) ( 0 , 4) (0 , 5 ) ( 0 , 6) ( 0 , 7 ) ( 0 , 8) ( 0 , 9) ( 0 , 10 ) (0 , 11 ) (0 , 12 ) (0 , 13 ) (0 , 14 ) ( 0 , 15 )

Figure 15-10. Pixel Output Order in One 16 x 16 Macro Block

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MacroBlock Y axis

Macro Block 16 x 16

Technical Reference Manual 15.11.7. Macro Block 8 x 8

( y , x) (0,0) (0,1) (0,2) (0,3) (0,4) (0,5) (0,6) (0,7) (0,0) (1,0) (2,0) (3,0) (4,0) (5,0) (6,0) (7,0) Macro Block 8 x 8

Figure 15-11. Pixel Output Order in One 8 x 8 Macro Block 15.11.8. Macro Block 4 x 4
( y , x)
( 0 , 0) (0 , 0 ) (1 , 0 ) (2 , 0 ) (3 , 0 ) (4 , 0 ) (5 , 0 ) (6 , 0 ) (7 , 0 ) (8 , 0 ) (9 , 0 ) ( 10 , 0 ) ( 11 , 0) ( 12 , 0) (13 , 0) ( 14 , 0) ( 15 , 0) (0 , 1) (0 , 2 ) (0 , 3) ( 0 , 4 ) (0 , 5 ) ( 0 , 6) ( 0 , 7 ) ( 0 , 8 ) ( 0 , 9) ( 0 , 10 ) (0 , 11 ) (0 , 12 ) (0 , 13 ) (0 , 14 ) ( 0 , 15 )

Macro Block 4 x 4

Figure 15-12. Pixel Output Order in One 4 x 4 Macro Block

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Technical Reference Manual 15.11.9. Two-split Memory Block

Figure 15-13. YCbCr 4:2:0 Macro Block Order in Two-split Memory Block 15.12. Programming Model 15.12.1. Summary of Video Capture Block Registers

This section describes all control and status registers in the video capture block. Table 15-2. Offset 0x0000 0x0004 0x0008 0x0010 0x0014 0x0018 0x001c 0x0020 0x0024 0x0028 0x002c 0x0030 0x034 0x0038 0x003c 0x0040 0x0044
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Video Capture Control Registers Description Basic function enable and trigge control Update register Clock control Output target image width and height at preview path Top-left corner of output crop window at preview path Output crop image width and height at preview path Output target image width and height at record path Top-left corner of output crop window at record path Output crop image width and height at record path Border size Border color Data output format Frame skip and block control Source interface related control
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Symbol VCAPEN VCAPUPD CAPCLK PVSIZE0 PVSIZE1 PVSZIE2 Reserved RCSIZE0 RCSIZE1 RCSZIE2 Reserved BORDER_SIZE BORDER_COLOR DFORMAT Reserved FMRATE SRCIF

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Technical Reference Manual 0x0048~ 0x004f 0x0050 0x0054 0x0058 0x005c 0x0060 0x0064 0x0068 0x006c 0x01d0 0x01d4 0x01d8~ 0x01df 0x01e0 0x01e4 0x01e8~ 0x01ff 0x0200 0x0204 0x0208 0x020c 0x0210 0x0214 0x0218 0x021c 0x0220 0x0224 0x0228~ 0x022f 0x0230 0x0234 0x0238~ 0x023f 0x0240 0x0244 0x0248~ 0x024f
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Reserved SRCSIZE0 PVSIZE3 PVSIZE4 Reserved SRCSIZE1 RCSIZE3 RCSIZE4 Reserved DICTRL0 DICTRL1 Reserved DNCTRL0 DNCTRL0 Reserved PDMA0 RDMA0 MEMSRC0 MEMSRC1 MEMSRC2 Reserved PDMA1 RDMA1 PMDDEST0 PMDDEST1 Reserved PMDDEST2 PMDDEST3 Reserved PMDDEST4 PMDDEST5 Reserved

R/W R/W R/W R/W R/W R/W Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -

Source image width and height Top-left corner of source active window at preview path Source active window at preview path Horizontal and vertical pixel active point of source image Top-left corner of active window at record path Source active window width and height at record path De-interlacer control Horizontal blanking control De-noise control 0 De-noise control 1 Preview path DMA length and sequence control Record path DMA length and sequence control Memory source format control for loopback path Memory source image start address for loopback path Memory source image size for loopback path Pitch of destination window for preview path Pitch of destination window for record path Destination frame buffer 0 Y start address at preview path Destination frame buffer 1 Y start address at preview path Destination frame buffer 0 Cb start address at preview path Destination frame buffer 1 Cb start address at preview path Destination frame buffer 0 Cr start address at preview path Destination frame buffer 1 Cr start address at preview path -

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Technical Reference Manual 0x0250 0x0254 0x0258~ 0x025f 0x0260 0x0264 0x0268~ 0x026f 0x0270 0x0274 0x0278~ 0x028f 0x290 0x294 0x298~ 0x29f 0x2a0 0x2a4 0x2a8~ 0x2af 0x0300 0x0304 0x0308 0x030c 0x0310 0x0314 0x0318 0x031c 0x0320 0x0324 0x0328 0x032c 0x0330 0x0334 0x0338 0x033c 0x0340 0x0344 0x0348 0x034c RMDEST0 RMDEST1 Reserved RMDEST2 RMDEST3 Reserved RMDEST4 RMDEST5 Reserved VBICTRL0 VBICTRL1 Reserved VBICTRL2 VBICTRL3 Reserved OSDFONT OSDDISP OSDREAD OSDEN OSDPAT0 OSDPAT1 OSDPAT2 OSDPAT3 OSDPAT4 OSDPAT5 OSDPAT6 Reserved OSDCOR0 OSDWSZ0 OSDSSZ0 OSDFSZ0 OSDCOL1 OSDWSZ1 OSDSSZ1 OSDFSZ1 R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Destination frame buffer 0 Y start address at record path Destination frame buffer 1 Y start address at record path Destination frame buffer 0 Cb start address at record path Destination frame buffer 1 Cb start address at record path Destination frame buffer 0 Cr start address at record path Destination frame buffer 1 Cr start address at record path VBI frame number 0 VBI frame number 1 VBI start line VBI start line OSD font RAM address and data port OSD display RAM address and data port OSD front RAM and display RAM data read port OSD window 0~ window 3 enable OSD palette color 0 OSD palette color 1 OSD palette color 2 OSD palette color 3 OSD palette color 4 OSD palette color 5 OSD palette color 6 OSD font color window 0 OSD window 0 width/height OSD window 0 start point OSD font size window 0 OSD font color of window 1 OSD window 1 width/height OSD window 1 start point OSD font size window 1

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Technical Reference Manual 0x0350 0x0354 0x0358 0x035c 0x0360 0x0364 0x0368 0x036c 0x0370~ 0x03df 0x03e0 0x03e4 15.12.2. Bit 31 OSDCOL2 OSDWSZ2 OSDSSZ2 OSDFSZ2 OSDCOL3 OSDWSZ3 OSDSSZ3 OSDFSZ3 Reserved INTSTS INTMASK R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OSD font color of window 2 OSD window 2 width/height OSD window 2 start point OSD font size window 2 OSD font color of window 3 OSD window 3 width/height OSD window 3 start point OSD font size window 3 Video capture status register Interrupt mask register

Capture Control Register (Offset= 0x0000) Name CAPTURE_EN Table 15-3. Type R/W Capture Control Register Description Enable image data capture 0 Disable the image data capture 1 Enable the image data capture Single frame capture mode (Sync register) 0 Continue the frame capture mode 1 Single frame capture mode Photo album capture mode enable (Sync register) 0 Disable the photo album mode 1 Enable the photo album mode One frame capture fire for single frame capture mode (Auto clear) 1 Fire one frame capture Post-image processing fire. (Auto clear) 1 Fire post-image processing Enable De-interlace (DI) function at the record path 0 Disable DI at the record path 1 Enable DI at the record path Enable De-interlace (DI) function at the preview path 0 Disable DI at the preview path 1 Enable DI at the preview path Enable DI ELA function 0 Disable. DI will duplicate even or odd line 1 Enable
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30 29

Reserved FM_SINGLE

R/W

28

ALBUM_EN

R/W

27-26 25

Reserved ONE_CAP_EN

R/W

24 23

PIMG_EN RC_DI_EN

R/W R/W

22

PV_DI_EN

R/W

21 20

Reserved DI_ELA_EN

R/W

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Technical Reference Manual 19-18 17 Reserved DN_EN R/W Enable De-Noise (DN) function (Sync register) 0 Disable DN 1 Enable DN Enable the error correction of CCIR 656 SAV/EAV code 0 Disable error correction 1 Enable error correction Enable dither function for DT module 0 Disable dither 1 Enable dither -

16

VP_EC_EN

R/W

15-9 8

Reserved DITHER_EN

R/W

7-0 15.12.3. Bit 31-17 16

Reserved

VCAPUPD Register (Offset = 0x0004) Table 15-4. VAPUPD Register Name Reserved INT_SYNC_CLR Type Description Clear interrupt source at every vertical start automatically. 0 User clear 1 Clear automatically R/W Force CU to do calculation (Auto clear) 0 CU does calculation in the vertical blank interval 1 Force CU to do calculation. Force all of the sync register to do update (Auto clear) Dont update sync register. All of the sync register will be updated immediately Trigger all of the sync register. (Auto clear) 0 Sync register retain original value. 1 All of the sync register will be updated at time of the last v_end.

15-5 4

Reserved FORCE_CU

3-2 1

Reserved FORCE_UPDATE

R/W

SYNC_REG_UPDATE

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Table 15-5. 15.12.4. Bit 31-29 28 27-13 12

Timing Diagram of sync_reg_update

CAPCLK Register (Offset = 0x0008) Table 15-6. Clock Control Register Name Reserved SW_RST Reserved ASST_CLK_SEL Type R/W R/W Description Software reset (Auto clear) 1 Set 1 to do reset Select external assistant clock 0 Main clock comes form PCLK 1 Main clock comes from external assistant clock, vcap_iclk Invert the input video pixel clock 0 Disable 1 Enable -

11-5 4

Resereved VP_CLK_INV

R/W

3-0 15.12.5. Bit 31-27 26-16 15-11 10-0

Reserved

PVSIZE0 Register (Offset = 0x0010) Table 15-7. PVSIZE0 Register Name Type Description Reserved PV_TARGET_HEIGHT Reserved PV_TARGET_WIDTH R/W R/W Output target image height for preview path (Sync register) Output target image width in the multiple of 4 for preview path (Sync register)

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VP_SRC_WIDTH

swc_x, swc_y

swc_ width
Target_width

Active Window

Size Down

Target Image

Figure 15-14. Relationship between Source Image and Target Image 15.12.6. Bit 31-27 26-16 15-11 10-0 15.12.7. Bit 31-27 26-16 15-11 10-0 15.12.8. Bit 31-27 26-16 15-11 10-0 15.12.9. Bit
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PVSIZE1 (Offset = 0x0014) Table 15-8. Name Type Reserved PV_CROP_Y R/W Reserved PV_CROP_X R/W

PVSIZE1 Register Description Y-coordinate of top-left corner for output crop window for preview path (Sync. register) X-coordinate of top-left corner for output crop window for preview path (Syn.c register)

PVSIZE2 Register (Offset = 0x0018) Table 15-9. PVSIZE2 Register Name Type Description Reserved PV_CROP_HEIGHT R/W Output crop image height in the multiple of 2 for preview path (Sync. register) Reserved PV_CROP_WIDTH R/W Output crop image width in the multiple of 4 for preview path (Sync. register) RCSIZE0 Register (Offset = 0x0020) Table 15-10. RCSIZE0 Register Name Type Description Reserved RC_TARGET_HEIGHT R/W Output target image height for record path (Sync. register) Reserved RC_TARGET_WIDTH R/W Output target image width in the multiple of 4 for record path (Sync. register) RCSIZE1 Register (Offset = 0x024) Table 15-11. RCSIZE1 Register Name Type Description
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Technical Reference Manual 31-27 26-16 15-11 10-0 15.12.10. Bit 31-27 26-16 15-11 10-0 15.12.11. Bit 31-16 15-12 Reserved RC_CROP_Y Reserved R/W R/W Y-coordinate of top-left corner for output crop window for the record path X-coordinate of top-left corner for output crop window for the record path

RC_CROP_X

RCSIZE2 Register (Offset = 0x0028) Table 15-12. RCSIZE2 Register Name Type Description Reserved RC_CROP_HEIGHT R/W Output crop image height in the multiple of 2 for the record path Reserved RC_CROP_WIDTH R/W Output crop image width in the multiple of 4 for the record path BORDER_SIZE Register (Offset = 0x0030) Table 15-13. BORDER_SIZE Register Name Type Description Reserved RC_BD_HEIGHT R/W Border height for record path 00 No border at the top and bottom side 001~111 Border height = (register value x 2) lines at the both top and bottom sides. RC_BD_WIDTH R/W Border width for record path 00 No border at the left and right side 001~111 Border width = (register value x 2) pixels at both the left and right sides PV_BD_HEIGHT R/W Border height for preview path (Sync register) 00 No border at the top and bottom side 001~111 Border height = (register valuex 2) lines at both the top and bottom sides PV_BD_WIDTH R/W Border width for preview path (Sync register) 00 No border at the left and right side 001~ 111 Border width = (register value x 2) pixels at both the left and right sides

11-8

7-4

3-0

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Target Image Width

Target Image Height

Crop Width ( crop _x,crop _y )

Crop Height

Crop Window

Border Height

Border Width

Figure 15-15. Relationship between Border Width/Height and Crop Window 15.12.12. Bit 31-27 26-21 20-16 15-11 4-0 15.12.13. Bit 31-14 13 BORDER_COLOR Register (Offset = 0x0034) Table 15-14. BORDER_COLOR Register Name RC_BD_R_COLOR RC_BD_G_COLOR RC_BD_B_COLOR PV_BD_R_COLOR PV_BD_B_COLOR Type R/W R/W R/W R/W R/W Description R/Cr bit[7:3] Border color at the record path G/Y bit[7:2] Border color at the record path B/Cb bit[7:3] Border color at the record path R/Cr bit[7:3] Border color at the preview path B/Cb bit[7:3] Border color at the preview path

12

11-8

DESTFORMAT Register (Offset = 0x0038) Table 15-15. DESTFORMAT Register Name Type Description Reserved RC_DEST_YC_SWA R/W Destination CbCr/Y or BR/G sequences swap for P record path. This bit is ineffective if DMA write YCbCr data into two or three separated memory blocks 0 Sequence of CbCr is ahead of Y (Cb Y Cr or Cr Y Cb) 1 Sequence of Y is ahead of CbCr (Y Cb Cr or Y Cr Cb) RC_DEST_RB_SWA R/W Destination R/B or Cr/Cb sequence swap for record P path. This bit is ineffective if DMA write YCb/Cr data into two ir three separated memory blocks. 0 Sequence of Cr is ahead of Cb 1 Sequence of Cb is ahead of Cr RC_DEST_FORMAT R/W Data output format for record path x000 RGB 888 x001 RGB 565

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Technical Reference Manual x010 ~ x011: Reserved x100 YCbCr 4:4:4 x101 YCbCr 4:2:2 x110 YCbCr 4:2:0 mode 0 x111 YCbCr 4:2:0 mode 1 0xxx YCbCr 256 level 1xxx YCbCr 240 level.
YCbCr 4 : 2 : 0 Mode 0 Active Line Number 1

Y sample Calculated Cb, Cr sample

YCbCr 4 : 2 : 0 Mode 1 Active Line Number 1

Y sample Calculated Cb, Cr sample

7-6 5

Reserved PV_DEST_YC_SWA P

R/W

Destination CbCr/Y or BR/G sequences swap for preview path. This bit is ineffective if DMA write YCbCr data into three separated memories. 0 Sequence of CbCr is ahead of Y (Cb Y Cr or Cr
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Technical Reference Manual Y Cb) 1 Sequence of y is ahead of CbCr (Y Cb Cr or Y Cr Cb) Destination R/B or Cr/Cb sequences swap for preview path. This bit is ineffective if DMA write YCbCr data into three separated memories. 0 Sequence of Cr is ahead of Cb ->CrCb. 1 Sequence of Cb is ahead of Cr ->CbCr. Data output format for preview path. x000 RGB 888 x001 RGB 565 x010 ~ x011: Reserved x100 YCbCr 4:4:4 x101 YCbCr 4:2:2 x110 YCbCr 4:2:0 mode 0 x111 YCbCr 4:2:0 mode 1 0xxx YCbCr 256 level 1xxx YCbCr 240 level

PV_DEST_RB_SWA P

R/W

3-0

PV_DEST_FORMAT

15.12.14. Bit 31-24 23

22-20

19

18-16

FMRATE Register (Offset = 0x0040) Table 15-16. FMRATE Register Name Type Description Reserved RC_SWC_FC_EN R/W Odd/even sequence check according to the setting of VP_Field_Seq to gurantee the pass of oen even/odd field pair at the record path. 0 Disbale the check of odd/even field sequence 1 Enable the check of odd/even field sequence RC_FM_RATE R/W Number of image frame to be skipped after deinterlace at the record path (Sync register) 000 Dont skip any frame. 001 1/2 frame rate 010 1/3 frame rate 011 1/4 frame rate 100 1/5 frame rate 101 1/6 frame rate 110 1/10 frame rate 111 Block all data PV-SWC_FC_EN R/W Odd/even sequence check according to the setting of VP_FIELD_SEQ to gurantee the pass of one odd/even field pair at the preview path. 0: Disbale the check of odd/even field sequence 1: Enable the check of odd/even field sequence PV_FM_RATE 18-16 PV_FM_RATE R/W Number of image frame to be skipped after de-interlace at the preview path (Sync register) 000 Dont skip any frame. 001 1/2 frame rate
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Technical Reference Manual 010 011 100 101 110 111 15-10 9 Reserved SWC_CENTER_XY R/W 1/3 frame rate 1/4 frame rate 1/5 frame rate 1/6 frame rate 1/10 frame rate Block all data

VP_RANGE

R/W

RC_SWC_SRC_SEL

R/W

PV_SWC_SRC_SEL

R/W

5-4 3 2 1-0

Reserved IM_SRC_SEL Reserved VP_SRC_SEL

R/W

Force source active window to locate at center of image. Dont care the start point of reg_swc_x and reg_swc_y. (Sync register) 0 Disable 1 Enable Data range of input video 0 16 <= Y <= 235 16 <= Cb/Cr <= 240 1 1 <= Y/Cb/Cr <= 254 Select source video data form other IP by local video interface for record path 0: Source from public video port 1: Source from local video interface Select source video data form other IP by local video interface for preview path 0 Source from public video port 1 Source from local video interface Global source image selection. (Sync register) 0 Source image is from the external image/video 1 Source image is from the memory. Video port source selection 00 Select video port from data input 0 01 Select video port from data input 1 10 Select video port from data input 2 11 Reserved SRCIF Register Description Swap Cb, Cr input sequence Define CCIR 656 as progressive or interleave mode 0 Interleave mode 1 Progressive mode Different CCIR 656 mode 00 Standard CCIR 656 01 Reserved 10 Reserved
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15.12.15. Bit 31:29 28 27-20 19 18 17-16

SRCIF Register (Offset = 0x0044) Table 15-17. Name Type Reserved YUV16_CBCR_SWAP R/W Reserved ITU656_PROG R/W Reserved ITU656_MODE

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Technical Reference Manual 11 Reserved Active polarity of video port horizontal sync/valid control 0 Video port horizontal control timing active low 1 Video port horizontal control timing active high Active polarity of video port vertical sync/valid control 0 Video port vertical control timing active low 1 Video port vertical control timing active high The definition of video port horizontal sync/valid control 0 Video port horizontal control timing is treated as data valid signal 1 Video port horizontal control timing is sync. signal The definition of video port vertical sync/valid control 0 Video port vertical control timing is treated as data valid signal 1 Video port vertical control timing is sync. signal H/V sync. Embedded in or separated from video stream 0 Sync. Signals are separated from video data 1 Sync. Signals are embedded in video data Video port interface format 00 CCIR-656 format 01 Reserved 10 SONY 16-bit YUV format 11 General 16-bit YCbCr format Odd/Even sequence 0 Odd field first 1 Even field first Different field skip method 00 Dont care the even/odd field. 01 Count the even and odd fields 10 Pass the odd field only 11 Pass the even field only Number of image field to be skipped before deinterlace. (Sync register) 000 Dont skip any field. 001 1/2 field rate 010 1/3 field rate 011 1/4 field rate 100 1/5 field rate 101 1/6 field rate 110 1/10 field rate 111 1/15 field rate

15

VP_H_REF_PL

R/W

14 13

VP_V_REF_PL VP_H_REF_DEF

R/W R/W

12

VP_V_REF_DEF

R/W

11

VP_H_REF_EMB

R/W

10 9-8

Reserved VP_IF_FORMAT

7 6 5-4

VP_FILED_SEQ Reserved FIELD_SKIP_MODE -

3 2-0

Reserved FIELD_RATE

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Technical Reference Manual 15.12.16. Bit 31-27 26-16 15:11 10-0 15.12.17. Bit 31-26 26-16 15-10 10-0 SRCSIZE0 Register (Offset = 0x0050) Table 15-18. SRCSIZE0 Register Name Type Description Reserved VP_SRC_HEIGHT R/W Image source height. (Sync. register) Reserved VP_SRC_WIDTH R/W Image source width. (Sync. register) PVSIZE3 Register (Offset = 0x0054) Table 15-19. PVSIZE3 Register Name Type Description Reserved PV_SWC_Y R/W Y-coordinate of top-left corner for source active window at preview path. In the multiple of 2. (Sync. register) Reserved PV_SWC_X R/W X-coordinate of top-left corner for source active window at preview path. In the multiple of 2. (Sync. register) PVSIZE4 Register (Offset = 0x0058) Table 15-20. PVSIZE4 Register Name Type Description Reserved PV_SWC_HEIGHT R/W Image source active window height at preview path. In the multiple of 2. (Sync. register)) Reserved PV_SWC_WIDTH R/W Image source active window width at preview path. In the multiple of 4. (Sync. register) SRCSIZE1 Register (Offset = 0x0060) Table 15-21. SRCSIZE1 Register Name Type Description Reserved VP_SRC_Y R/W Vertical pixel capture start point of source image Reserved VP_SRC_X R/W Horizontal pixel capture start point of source image

15.12.18. Bit 31-27 26-16 15-11 10-0 15.12.19. Bit 31-27 26-16 15-11 10-0

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Figure 15-16. VPSRC_X and VP_SRC_Y 15.12.20. Bit 31-27 26-16 15-11 10-0 RCSIZE3 Register (Offset = 0x0064) Table 15-22. RCSIZE3 Register Name Type Description Reserved RC_SWC_Y R/W Y-coordinate of top-left corner for source active window at record path. In the multiple of 2. (Sync. register) Reserved RC_SWC_X R/W X-coordinate of top-left corner for source active window at record path. In the multiple of 2. (Sync. register) RCSIZE4 Register (Offset = 0x0068) Table 15-23. RCSIZE4 Register Name Type Description Reserved RC_SWC_HEIGHT R/W Image source active window height at the record path. In the multiple of 2. (Sync. register) Reserved RC_SWC_WIDTH R/W Image source active window width at the record path. In the multiple of 4. (Sync. register
VP_SRC_WIDTH

15.12.21. Bit 31-27 26-16 15-11 10-0

swc _ x, swc_y VP_SRC_HEIGHT

swc_width

swc_height

Active Window

Figure 15-17. Source Active Window 15.12.22. DICTRL0 Register (Offset = 0x01D0)

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Technical Reference Manual Table 15-24. Type R/W R/W R/W DICTRL0 Register Description High threshold for ELA value calculation Low threshold for ELA value calculation High/Low threshold are used to correct the result of the interpolation Weighted judgment threshold Used to determine the pixel interpolation direction

Bit 31-24 23-16 15-3 2-0 15.12.23. Bit 31-8 7-0 15.12.24. Bit 31-10 9-8

Name DI_ELA_H_TH DI_ELA_L_TH Reserved DI_WEIGHT_TH

DICTRL1 Register (Offset = 0x01D4) Table 15-25. DICTRL1 Register Name Type Description Reserved DI_H_BLANK_PIX R/W Horizontal blank interval between intra and odd/even line DNCTRL0 Register (Offset = 0x01E0) Table 15-26. DNCTRL0 Register Name Type Description Reserved DN_CWMF_SEL R/W De-noise Center Weighted Median Filter Selection 00: Standard Median Filter 01: Center Weighted Median Filter with weight = 3 10: Center Weighted Median Filter with weight = 5 11: Reserved Reserved DN_ACWMF_EN R/W De-noise Adaptive Center Weighted Median Filter Enable Reserved DNCTRL1 Register (Offset = 0x01E4) Table 15-27. DNCTRL1 Register Name Type Description Reserved DN_ACWMF_TH R/W De-noise Adaptive Center Weighted Median Filter Threshold DNCTRL2 Register (Offset = 0x01EC) Table 15-28. DNCTRL2 Register Name Type Description Reserved DN_WIN_PAD R/W De-noise sliding window padding value 00 Padding Zero 01 Padding 255 10 Padding symmetric 11 Reserved Reserved 444 5/5/2010 Version 2.1

7-2 1 0 15.12.25. Bit 31-8 7-0 15.12.26. Bit 31-10 9-8

7-2
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Technical Reference Manual 1-0 DN_HBLANK_LEN R/W De-noise horizontal blank length 00 One line length 01 Half line length 10 Quarter line length 11 Eighth line length

15.12.27. Bit 31-27 26-24 23-21 20

19-17 16 15-14 13-12

11-10 9-8

7-6

5-4

3-2

PDMA0 Register (Offset = 0x0200) Table 15-29. PDMA0 Register Name Type Description Reserved PV_HRESP_DLY R/W AHB retry/Split delay clock = 8+ reg_hresp_dly For preview path Reserved PDMA_FC_EN R/W Control DMA to write even/odd field to the related even/odd field memory location for preview path 0 Dont distinguish the even/odd field 1 Enable the DMA the even/odd field sorting Reserved PDMA_MST_EN R/W Multi-start address enable for preview DMA write 0 Enable frame numbers 0 start address 1 Enable frame numbers 0, 1 start address Reserved PDMA_ORDER R/W YCbCr 4:2:2/4:2:0 data organization in three memory buffers for preview path 00 Sequential order 01 4 x 4 macro block order 10 8 x 8 macro block order 11 16 x 16 macro block order Reserved PDMA_SPLIT YCbCr data arrangement in memory. 00 Reserved 01 Write three color components into three different memory buffers. 10 Write Y into one memory buffer and Cb/Cr into another memory buffer. Please refer to the record DMA segment for more details. PDMA_CHROMA_ Cb,Cr burst write length WLEN 00 1 data package for one burst 01 2 data package for one burst 10 4 data package for one burst 11 8 data package for one burst PDMA_LUMA_WLEN R/W Y burst write length 00 4 data package for one burst 01 8 data package for one burst 10 12 data package for one burst 11 16 data package for one burst PDMA_RLEN DMA read burst length at preview path 00 8 data package for one burst
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Technical Reference Manual 01 16 data package for one burst 10 ~ 11: Reserved DMA write burst length at preview path 00 8 data package for one burst 01 16 data package for one burst 10 ~ 11: Reserved

1-0

PDMA_WLEN

15.12.28. Bit 31-27 26-24 23-21 20

19 18-17 16 15-14 13-12

11-10 9-8

7-6

5-4

RDMA0 Register (Offset = 0x0204) Table 15-30. RDMA0 Register Name Type Description Reserved RC_HRESP_DLY R/W AHB retry/split delay clock = 8+ reg_ahb_hresp_dly For record path Reserved RDMA_FC_EN R/W Control DMA to write even/old field to the related even/odd field memory location for record path 0 Dont distinguish the even/odd field 1 Enable the DMA the even/off field sorting RDMA_VBI_EN R/W VBI capture enable/disable 0 Disable VBI capture 1 Enable VBI capture Reserved RDMA_MST_EN R/W Multi-start address enable for record DMA write 0 Enable frame numbers 0 start address 1 Enable frame numbers 0, 1 start address Reserved RDMA_ORDER R/W YCbCr 4:2:2/4:2:0 data organization in three memory buffers for record path 00 Sequential order 01 4 x 4 macro block order 10 8 x 8 macro block order 11 16 x 16 macro block order Reserved RDMA_SPLIT R/W YCbCr data arrangement in memory. 00 Reserved 01 Write three color components into three different memory buffers. 10 Write Y into one memory buffer and Cb/Cr into another memory buffer. Please refer to the record DMA segment for more details. RDMA_CHROMA_WLEN R/W Cb,Cr burst write length 00 1 data package for one burst 01 2 data package for one burst 10 4 data package for one burst 11 8 data package for one burst RDMA_LUMA_WLEN Y burst write length R/W 00 4 data package for one burst 01 8 data package for one burst
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Technical Reference Manual 10 12 data package for one burst 11 16 data package for one burst DMA write burst length at the record path 00 8 data package for one burst 01 16 data package for one burst 10 ~ 11: Reserved

3-2 1-0

Reserved RDMA_WLEN

R/W

15.12.29. Bit 31-29 28 27-19 18-16 15-5 4

3 2-0

MEMSRC0 Register (Offset == 0x0208) Table 15-31. MEMSRC0 Register Name Type Description Reserved MEM_SRC_FIELD R/W Odd or even field for current memory source image. 0 Odd field 1 Even field Reserved MEM_SRC_HBLANK R/W MEM_SRC_HBLANK R/W Pixel number of horizontal line blank for memory source image Reserved MEM_SRC_RB_SWAP Memory source image R/B or Cb/Cr swap. Only for RGB565 or YCbCr 4:2:2 format 0 Sequence of R/Cr is ahead of B/Cb. 1 Sequence of B/Cb is ahead of R/Cr. Reserved MEM_SRC_FORMAT R/W Memory source image color format 000 RGB888 001 RGB565 010 ~ 011 Reserved 100 YCbCr 4:4:4 101 YCbCr 4:2:2 110 ~ 111 Reserved MEMSRC1 Register (Offset = 0x020C) Table 15-32. MEMSRC1 Register Name Type Description Reserved MEM_SRC_ST R/W Memory source image start address DWORD alignment MEMSRC2 Register (Offset = 0x0210) Table 15-33. MEMSRC2 Register Name Type Description Reserved MEM_SRC_HEIGHT R/W Memory source image height Reserved MEM_SRC_WIDTH Memory source image width PDMA1 Register (Offset = 0x0218)

15.12.30. Bit 31-30 29-0 15.12.31. Bit 31-27 26-16 15-11 10-0 15.12.32.

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Technical Reference Manual Table 15-34. Type R/W PDMA1 Register Description Pitch of sub-window for preview DMA

Bit 31-11 10-0 15.12.33. Bit 31-11 10-0

Name Reserved PV_SUB_WIN_PIT

RDMA1 Register (Offset = 0x021C) Table 15-35. RDMA1 Register Name Type Description Reserved RC_SUB_WIN_PIT R/W Pitch of sub-window for record DM
800 Source active window at preview path (PV) 1200 800 Source active window at record path (RC) Memory 1200 800 800

1600

Sensor

PV RC PV_SUB _WIN_PIT RC_SUB _WIN_PIT = 1600 = 1600 1200

ALBUM _EN = 1 to open the user-defined pitch

Figure 15-18. Pitch of Sub-Window of Preview and Record Path 15.12.34. Bit 31-30 29-0 15.12.35. Bit 31-30 29-0 15.12.36. Bit 31-30 29-0 15.12.37.
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PMDEST0 Register (Offset = 0x0220) Table 15-36. PMDEST0 Register Name Type Description Reserved PMEM_DEST_YST 0 R/W Destination Y frame numbers 0 start address for preview DMA. DWORD alignment PMDEST1 Register (Offset = 0x0224) Table 15-37. PMDEST1 Register Name Type Description Reserved PMEM_DEST_YST1 R/W Destination frame buffer 1 Y start address for preview path. DWORD alignment PMDEST2 Register (Offset = 0x0230) Table 15-38. PMDEST2 Register Name Type Description Reserved PMEM_DEST_CBST0 R/W Destination frame buffer 0 Cb start address for preview. DWORD alignment PMDEST3 Register (Offset = 0x0234)
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Technical Reference Manual Table 15-39. PMDEST3 Register Name Type Description Reserved PMEM_DEST_CBST1 R/W Destination frame buffer 1 Cb start address for preview path. DWORD alignment PMDEST4 Register (Offset = 0x0240) Table 15-40. PMDEST4 Register Name Type Description Reserved PMEM_DEST_CRST0 R/W Destination frame buffer 0 Cr start address for preview path. DWORD alignment PMDEST5 Register (Offset = 0x0244) Table 15-41. PMDEST5 Register Name Type Description Reserved PMEM_DEST_CRST1 R/W Destination frame buffer 1 Cr start address for preview path.DWORD alignment
reg_ pdma_dest_ yst0 Frame0 reg_ pdma_ dest_ cbst0 reg_ pdma_ dest_ crst0 reg_ pdma_ dest_yst1 Y reg_ pdma_ dest_ cbst1 Frame1 reg_ pdma_ dest_ crst1 Cb Cr Y Cb Cr

Bit 31-30 29-0 15.12.38. Bit 31-30 29-0 15.12.39. Bit 31-30 29-0

Figure 15-19. Start Address of Destination Frame Buffer 15.12.40. Bit 31-30 29-0 15.12.41. Bit 31-30 29-0 RMDEST0 Register (Offset = 0x0250) Table 15-42. RMDEST0 Register Name Type Description Reserved RMEM_DEST_YST0 R/W Destination frame buffer 0 Y start address for record path. DWORD alignment RMDEST1 Register (Offset = 0x0254) Table 15-43. RMDEST1 Register Name Type Description Reserved RMEM_DEST_YST1 R/W Destination frame numbers 1 Y start address for record path. DWORD alignment.

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Technical Reference Manual 15.12.42. Bit 31-30 29-0 15.12.43. Bit 31-30 29-0 15.12.44. Bit 31-21 20-0 15.12.45. Bit 31-30 20-0 15.12.46. Bit 31-30 20-0 15.12.47. Bit 31-30 20-0 15.12.48. Bit 31-30 20-16 RMDEST2 Register (Offset = 0x0260) Table 15-44. RMDEST2 Register Name Type Description Reserved RMEM_DEST_CBST0 R/W Destination frame buffer 0 Cb start address for record path. DWORD alignment RMDEST3 Register (Offset = 0x264) Table 15-45. RMDEST3 Register Name Type Description Reserved RMEM_DEST_CBST1 R/W Destination frame buffer 1 Cb start address for record path.DWORD alignment RMDEST4 Register (Offset = 0x0270) Table 15-46. RMDEST4 Register Name Type Description Reserved RMEM_DEST_CRST0 R/W Destination frame buffer 0 Cr start address for record R/W path. DWORD alignment RMDEST5 Register (Offset = 0x0274) Table 15-47. RMDEST5 Register Name Type Description Reserved RMEM_DEST_CRST1 R/W Destination frame buffer 1 CR start address for record path. DWORD alignment VBICTRL0 Register (Offset = 0x0290) Table 15-48. VBICTRL0 Register Name Type Description Reserved RMEM_DEST_VBI_ST0 R/W VBI frame numbers 0 start address for record DMA. DWORD alignment VBICTRL1 Register (Offset = 0x0294) Table 15-49. VBICTRL1 Register Name Type Description Reserved RMEM_DEST_VBI_ST1 R/W VBI frame numbers 1 start address for record DMA. DWORD alignment VBICTRL2 Register (Offset = 0x02A0) Table 15-50. VBICTRl2 Register Name Type Description Reserved VBI_Y R/W VBI start R/W VBI_Y R/W VBI start line line
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Technical Reference Manual 15-10 10-0 15.12.49. Bit 31-21 20-16 15-11 10-0 15.12.50. Bit 31 28-29 28-16 15-12 11-0 15.12.51. Bit 31 30-22 21-16 15-9 7-0 Reserved VBI_X

VBI start pixel

VBICTRL3 Register (Offset = 0x02B0) Table 15-51. VBICTRL3 Register Name Type Description Reserved VBI_HEIGHT R/W Total VBI lines to be captured for each field Reserved VBI_WIDTH R/W Total VBI pixels to be captured for each line In the multiple of 4. OSDFONT Register (Offset = 0x0300) Table 15-52. OSDFONT Register Name Type Description FONT_RAM_READ R/W OSD font memory read/write setting, default write Reserved FONT_RAM_ADDR R/W OSD font address Reserved FONT_RAM_DATA R/W OSD font data OSDDISP Register (Offset = 0x0304) Table 15-53. OSDDISP Register Name DISP_RAM_READ Reserved DISP_RAM_ADDR Reserved DISP_RAM_DATA Type R/W R/W R/W Description Display ram read/write, default write Display RAM address MSB[7], set 1 to select RAM

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Window display start address register and window dimension

osd_win 0_dispaddr osd_win 0_ width osd_ win 0_height 0x 0003 0x 0002 0x 0002

Display RAM
Address 0x0000 0x 0001 0x 0002 0x 0003 0x 0004 0x 0005 0x 0006 0x 0007 Data (Font index) 0x01 0x00 0x01 0x01 0x00 0x80 0x81 Index transfer to font address

Window 0 display character number = osd_win0 _ width *osd_win0_height = 2 *2 = 4

0x001F

[6:0] x 18

0x08FF MSB = 1 select to RAM 0x0000 0x0001 0x0002 Font RAM Font 0 Line 0 Font 0 Line 1 Font 0 Line 2 . . .

0x0011 0x0012 0x0013

Font 0 Line 17 Font 1 Line 0 Font 1 Line 2 . . .

Font 64 Line 17 0x047F

Figure 15-20. OSD Font RAM and Display RAM 15.12.52. Bit 31 30 29-20 19-12 11-0 15.12.53. Bit 31-17 16 15-4 3 2 1 0 15.12.54. OSDREAD Register (Offset = 0x0308) Table 15-54. OSDREAD Register Name Type Description DISP_RAM_BUSY R Display RAM busy FONT_RAM_BUSY R R Font memory busy Reserved DISP_RAM_DATAOUT R R Display RAM read data out FONT_RAM_DATAOUT R Font memory read data out OSDEN Register (Offset = 0x030C) Table 15-55. OSDEN Register Name Type Description Reserved OSD_EDGE_SMTH_EN R/W Edge smooth enable function 0: Disable 1: Enable Reserved OSD_WIN3_EN R/W Window 3 enable (Sync. register) OSD_WIN2_EN R/W Window 2 enable (Sync. register) OSD_WIN1_EN R/W Window 1 enable (Sync. register) OSD_WIN0_EN R/W Window 0 enable (Sync. register) OSDPAT0 Register (Offset = 0x0310)

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Technical Reference Manual Table 15-56. OSDPAT0 Register Type Description R/W R/W R/W Palette color 0 Y Palette color 0 Cb Palette color 0 Cr

Bit 31-22 21-16 15-13 12-8 7-5 4-0 15.12.55. Bit 31-22 21-16 15-13 12-8 7-5 4-0 15.12.56. Bit 31-22 21-16 15-13 12-8 7-5 4-0 15.12.57. Bit 31-22 21-16 15-13 12-8 7-5 4-0 15.12.58. Bit 31-22 21-16 15-13 12-8 7-5 4-0
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Name Reserved OSD_PAL0_Y Reserved OSD_PAL0_CB Reserved OSD_PAL0_CR

OSDPAT1 Register (Offset = 0x0314) Table 15-57. OSDPAT1 Register Name Type Description Reserved OSD_PAL1_Y R/W Palette color 1 Y Reserved OSD_PAL1_CB R/W Palette color 1 Cb Reserved OSD_PAL1_CR R/W Palette color 1 Cr OSDPAT2 Register (Offset = 0x0318) Table 15-58. OSDPAT2 Register Name Type Description Reserved OSD_PAL2_Y R/W Palette color 2 Y Reserved OSD_PAL2_Y R/W Palette color 2 Y Reserved OSD_PAL2_CR R/W Palette color 2 Cr OSDPAT3 Register (Offset = 0x031C) Table 15-59. OSDPAT3 Register Name Type Description Reserved OSD_PAL3_Y R/W Palette color 3 Y Reserved OSD_PAL3_CB R/W Palette color 3 Cb Reserved OSD_PAL3_CR R/W Palette color 3 C OSDPAT4 Register (Offset = 0x0320) Table 15-60. OSDPAT4 Register Name Type Description Reserved OSD_PAL4_Y R/W Palette color 4 Y Reserved OSD_PAL4_CB R/W Palette color 4 Cb Reserved OSD_PAL4_CR R/W Palette color 4 Cr
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Technical Reference Manual 15.12.59. Bit 31-22 21-16 15-13 12-8 7-5 4-0 15.12.60. Bit 31-22 21-16 15-13 12-8 7-5 4-0 15.12.61. Bit 31-10 9-8 OSDPAT5 Register (Offset = 0x0324) Table 15-61. OSDPAT5 Register Name Type Description Reserved OSD_PAL5_Y R/W Palette color 5 Y Reserved OSD_PAL5_Y R/W Palette color 5 Y Reserved OSD_PAL5_CR R/W Palette color 5 Cr OSDPAT6 Register (Offset = 0x0328) Table 15-62. OSDPAT6 Register Name Type Description Reserved OSD_PAL6_Y R/W Palette color 6 Y Reserved OSD_PAL6_CB R/W Palette color 6 Cb Reserved OSD_PAL6_CR R/W Palette color 6 C OSDCOR0 Register (Offset = 0x0330) Table 15-63. OSDCOR0 Register Name Type Description Reserved OSD_WIN0_TRAN R/W Window Font backward color Transparency level 00: 0% (Normal) 01: 50% 10: 75% 11: 100% Reserved OSD_WIN0_BWCOLOR R/W Window font backward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3 100: Palette color No.4 101: Palette color No.5 110: Palette color No.6 111: Inverse background color Reserved OSD_WIN0_FWCOLOR R/W Window font forward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3 100: Palette color No.4 101: Palette color No.5
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Technical Reference Manual 110: Palette color No.6 111: Inverse background color 15.12.62. Bit 31-23 22-16 15 14-8 7 6-0 15.12.63. Bit 31-26 25-16 15-11 10-0 15.12.64. Bit 31-26 27-24 23-20 19-16 7-4 3-0 15.12.65. Bit 31-10 9-8 OSDWSZ0 Register (Offset = 0x0334) Table 15-64. OSDWSZ0 Register Name Type Description Reserved OSD_WIN0_DISPADDR R/W Window0 character display start address (Sync register) Reserved OSD_WIN0_HEIGHT R/W Window 0 dimension height (Sync register) 1 ~ 63 Reserved OSD_WIN0_WIDTH R/W Window 0 dimension width (Sync register) 1 ~ 63 OSDSSZ0 Register (Offset = 0x0338) Table 15-65. OSDSSZ0 Register Name Type Description Reserved OSD_WIN0_POS_Y R/W Window 0 start point Y (Sync register). Max. 1023 Reserved OSD_WIN0_POS_X R/W Window 0 start point X (Sync register). Max. 1280 OSDFSZ0 Register (Offset = 0x033C) Table 15-66. OSDFSZ0 Register Name Type Description Reserved OSD_WIN0_FSPACE_ROW R/W Window 0 font row space (Sync. register) Reserved OSD_WIN0_FSPACE_COL R/W Window 0 font column space (Sync. register) Reserved OSD_WIN0_FONT_W R R/W Window 0 font width 7 ~ 12 (Sync. register) OSDCOR1 Register (Offset = 0x0340) Table 15-67. OSDCOR1 Register Name Type Description Reserved OSD_WIN1_TRAN R/W Window font backward color Transparency level 00: 0% (Normal) 01: 50% 10: 75% 11: 100% Reserved OSD_WIN1_BWCOLOR R/W Window font backward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3

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Technical Reference Manual 100: Palette color No.4 101: Palette color No.5 110: Palette color No.6 111: Inverse background color Window font forward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3 100: Palette color No.4 101: Palette color No.5 110: Palette color No.6 111: Inverse background color

3 2-0

Reserved OSD_WIN1_FWCOLOR

R/W

15.12.66. Bit 31-23 22-16 15 14-8 7 2-0 15.12.67. Bit 31-26 25-16 15-11 10-0 15.12.68. Bit 31-28 27-24 23-20 19-16 15-13 12-8 7-4 3-0 15.12.69.

OSDWSZ1 Register (Offset = 0x0344) Table 15-68. OSDWSZ1 Register Name Type Description Reserved OSD_WIN1_DISPADDR R/W Window 0 character display start address (Sync. register) Reserved OSD_WIN1_HEIGHT R/W Window 0 dimension height (Sync. register) 1 ~ 63 Reserved OSD_WIN1_WIDTH R/W Window 0 dimension width (Sync. register) 1 ~ 63

OSDSSZ1 Register (Offset = 0x0348) Table 15-69. OSDSSZ1 Register Name Type Description Reserved OSD_WIN1_POS_Y R/W Window 1 start point Y (Sync. register). Max. 1023 Reserved OSD_WIN1_POS_X R/W Window 1 start point X (Sync. register). Max. 1280 OSDFSZ1 Register (Offset = 0x034C) Table 15-70. OSDFSZ1 Register Name Type Description Reserved OSD_WIN1_FSPACE_ROW R/W Window 1 font row space (Sync. register) Reserved OSD_WIN1_FSPACE_COL R/W Window 1 font column space (Sync. register) Reserved OSD_WIN1_FONT_H R/W Window 1 font height 7 ~ 12 (Sync. register) Reserved OSD_WIN1_FONT_W R/W Window 1 font width 7 ~ 12 (Sync. register) OSDCOR2 Register (Offset = 0x0350)

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Technical Reference Manual Table 15-71. OSDCOR2 Register Name Type Description Reserved OSD_WIN2_TRAN R/W Window Font backward color Transparency level 00: 0% (Normal) 01: 50% 10: 75% 11: 100% Reserved OSD_WIN2_BWCOLOR R/W Window font backward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3 100: Palette color No.4 101: Palette color No.5 110: Palette color No.6 111: Inverse background color Reserved OSD_WIN2_FWCOLOR R/W Window font forward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3 100: Palette color No.4 101: Palette color No.5 110: Palette color No.6 111: Inverse background color OSDWSZ2 Register (Offset = 0x0354) Table 15-72. OSDWSZ2 Register Name Type Description Reserved OSD_WIN2_DISPADDR R/W Window 0 character display start address (Sync. register) Reserved OSD_WIN2_HEIGHT R/W Window 0 dimension height (Sync. register)1 ~ 63 Reserved OSD_WIN2_WIDTH R/W Window 0 dimension width (Sync. register) 1 ~ 63 OSDSSZ2 Register (Offset = 0x0358) Table 15-73. OSDSSZ2 Register Name Type Description Reserved OSD_WIN2_POS_Y R/W Window 2 start point Y (Sync. register) Max. 1023 Reserved OSD_WIN2_POS_X R/W Window 2 start point X (Sync. register)Max. 1280

Bit 31-10 9-8

7 6-4

3 2-0

15.12.70. Bit 31-23 22-16 15 14-8 7 2-0 15.12.71. Bit 31-26 25-16 15-11 10-0

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Technical Reference Manual 15.12.72. Bit 31-26 25-24 23-18 19-16 15-13 12-8 7-4 3-0 15.12.73. Bit 31-10 9-8 OSDFSZ2 Register (Offset = 0x035C) Table 15-74. OSDFSZ2 Register Name Type Description Reserved OSD_WIN2_FSPACE_ROW R/W Window 2 font row space (Sync. register) Reserved OSD_WIN2_FSPACE_COL R/W Window 2 font column space (Sync. register) Reserved OSD_WIN2_FONT_H R/W Window 2 font height 7 ~ 12 (Sync. register) Reserved OSD_WIN2_FONT_W R/W Window 2 font width 7 ~ 12 (Sync. register) OSDCOR3 Register (Offset = 0x0360) Table 15-75. OSDCOr3 Register Name Type Description Reserved OSD_WIN3_TRAN R/W Window font backward color Transparency level 00: 0% (Normal) 01: 50% 10: 75% 11: 100% Reserved OSD_WIN3_BWCOLOR R/W Window font backward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3 100: Palette color No.4 101: Palette color No.5 110: Palette color No.6 111: Inverse background color Reserved OSD_WIN3_FWCOLOR R/W Window font forward color index 000: Palette color No.0 001: Palette color No.1 010: Palette color No.2 011: Palette color No.3 100: Palette color No.4 101: Palette color No.5 110: Palette color No.6 111: Inverse background color OSDWSZ3 Register (Offset = 0x0364) Table 15-76. OSDWSZ3 Register Name Type Description Reserved OSD_WIN3_DISPADDR R/W Window 0 character display start address
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Technical Reference Manual (Sync.register) 15 14-8 7 6-0 15.12.75. Bit 31-26 25-16 15-11 10-0 15.12.76. Bit 31-28 27-24 23-20 19-16 15-13 12-8 7-4 3-0 15.12.77. Bit 31-29 28 27-26 25 24 23-13 12 11-10 9 8 7-0 15.12.78. Reserved OSD_WIN3_HEIGHT Reserved OSD_WIN3_WIDTH R/W R/W Window 0 dimension height (Sync. register)1 ~ 63 Window 0 dimension width (Sync. register)1~ 63

OSDSSZ3 Register (Offset = 0x0368) Table 15-77. OSDSSZ3 Register Name Type Description Reserved OSD_WIN3_POS_Y R/W Window 3 start point Y (Sync. register) Max. 1023 Reserved OSD_WIN3_POS_X R/W Window 3 start point X (Sync. register)Max. 1280 OSDFSZ3 Register (Offset = 0x036C) Table 15-78. OSDFSZ3 Register Name Type Description Reserved OSD_WIN3_FSPACE_ROW R/W Window 3 font row space (Sync. register) Reserved OSD_WIN3_FSPACE_COL R/W Window 3 font column space (Sync. register) Reserved OSD_WIN3_FONT_H R/W Window 3 font height 7 ~ 12 (Sync. Register) Reserved OSD_WIN3_FONT_W R/W Window 3 font width 7 ~ 12 (Sync. register) INTSTS Register (Offset = 0x03E0) Table 15-79. INTSTS Register Name Type Description Reserved RDMA_OVF_ERR R/W RDMA write overflow error Reserved RC_AHB_ERR R/W AMBA AHB receives error response at the record path RC_AHB_IDLE R/W AMBA AHB transmits one frame then return to idle state at the record path Reserved PDMA_OVF_ERR R/W PDMA write overflow error Reserved PV_AHB_ERR R/W AMBA AHB receives error response at the preview path PV_AHB_IDLE R/W AMBA AHB transmits one frame then return to idle state at the preview path Reserved INTMASK Register (Offset = 0x03E4) Table 15-80. INTMASK Register

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Technical Reference Manual Bit 31-25 24 23-9 8 7-0 15.12.79. Bit 31-30 29-24 Name Reserved RC_AHB_IDLE_MASK Reserved PV_AHB_IDLE_MASK RC_AHB_IDLE Type R/W R/W R/W Description Mask interrupt from rc_ahb_idle 0: Retain original rc_ahb_idle interrupt source 1: Mask rc_ahb_idle interrupt source Mask interrupt from pv_ahb_idle 0: Retain original pv_ahb_idle interrupt source 1: Mask pv_ahb_idle interrupt source AMBA AHB transmits one frame then return to idle state at the record path

23-22 21-16

15-14 13-8

TEST_MODE0 Register (Offset = 0x03F0) Table 15-81. TEST_PAT0 Register Name Type Description Reserved 29-24 R/W Type of test pattern inserted before SWC for RC_SWC_TEST_PAT record path xxxxx0: Disable test pattern xxxxx1: Enable test pattern xxxx0x: Cr = 0 xxxx1x: Cr = 255 xxx0xx: Y = 0 xxx1xx: Y = 255 xx0xxx: Cb = 0 xx1xxx: Cb = 255 00xxxx: All pure color 01xxxx: Coordinate RGB 10xxxx: Vertical color bar 11xxxx: Horizontal color bar Reserved PV_SWC_TEST_PAT R/W Type of test pattern inserted before SWC for preview path xxxxx0: Disable test pattern xxxxx1: Enable test pattern xxxx0x: Cr = 0 xxxx1x: Cr = 255 xxx0xx: Y = 0 xxx1xx: Y = 255 xx0xxx: Cb = 0 xx1xxx: Cb = 255 00xxxx: All pure color 01xxxx: Coordinate RGB 10xxxx: Vertical color bar 11xxxx: Horizontal color bar Reserved 13-8 DRV_TEST_PAT Type of test pattern inserted before DRV xxxxx0: Disable test pattern xxxxx1: Enable test pattern
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Technical Reference Manual xxxx0x: R = 0 xxxx1x: R = 255 xxx0xx: G = 0 xxx1xx: G = 255 xx0xxx: B = 0 xx1xxx: B = 255 00xxxx: All pure color 01xxxx: Coordinate RGB 10xxxx: Vertical color bar -

7-0

Reserved

18.6.2.79 TEST_MODE1 Register (Offset = 0x03F4) Table 15-82. TEST_PAT1 Register Bit Name Type Description 31-30 Reserved 29-24 29-24 RC_DT_TEST_PAT R/W Type of test pattern inserted before DT at record path xxxxx0: Disable test pattern xxxxx1: Enable test pattern xxxx0x: R = 0 xxxx1x: R = 255 xxx0xx: G = 0 xxx1xx: G = 255 xx0xxx: B = 0 xx1xxx: B = 255 00xxxx: All pure color 01xxxx: Coordinate RGB 10xxxx: Vertical color bar 11xxxx: Horizontal color bar 23-22 Reserved 21-16 21-16 PV_DT_TEST_PAT R/W Type of test pattern inserted before DT at preview path xxxxx0: Disable test pattern xxxxx1: Enable test pattern xxxx0x: R = 0 xxxx1x: R = 255 xxx0xx: G = 0 xxx1xx: G = 255 xx0xxx: B = 0 xx1xxx: B = 255 00xxxx: All pure color 01xxxx: Coordinate RGB 10xxxx: Vertical color bar 11xxxx: Horizontal color bar 15-14 Reserved 13-8 RC_SD_TEST_PAT R/W Type of test pattern inserted before SD at record path xxxxx0: Disable test pattern

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Technical Reference Manual xxxxx1: Enable test pattern xxxx0x: R = 0 xxxx1x: R = 255 xxx0xx: G = 0 xxx1xx: G = 255 xx0xxx: B = 0 xx1xxx: B = 255 00xxxx: All pure color 01xxxx: Coordinate RGB 10xxxx: Vertical color bar 11xxxx: Horizontal color bar 7-6 5-0 Reserved PV_SD_TEST_PAT Type of test pattern inserted before SD at preview path xxxxx0: Disable test pattern xxxxx1: Enable test pattern xxxx0x: R = 0 xxxx1x: R = 255 xxx0xx: G = 0 xxx1xx: G = 255 xx0xxx: B = 0 xx1xxx: B = 255 00xxxx: All pure color 01xxxx: Coordinate RGB 10xxxx: Vertical color bar 11xxxx: Horizontal color bar

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16. AHB to APB Bridge (APB Bridge)

16.1. General Description The APB bridge converts the transaction between the APB bus and the AHB bus. The bridge is fully compliant with the AMBA specification v 2.0. The APB bridge is the only bus master on the APB bus and it also serves as a slave on the AHB bus. The bridge provides latching of all address, data and control signals, as well as a second level of decoding to generate slave select signals for the APB peripherals. It supports the following features: Up to 133 MHz for high-speed AHB bus Up to 66 MHz for low-speed APB bus Compliant with AHB 2.0 Specification Up to 32 sets of APB devices

The figure below illustrates the simplified block diagram of the APB-t0-AHB bridge

Figure 16-1. Block Diagram of AHB to APB Bridge The APB bridge consists of a control register, an AHB-to-APB slave, an AHB master, an APB master, an arbiter, and a DA. The following sections contain detailed descriptions of each block. 16.2. Control Register

The main function of this block is to control the APB Bridge. The APB bridge supports up to twenty-three
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Technical Reference Manual APB devices. To program registers of the bridge, set the base address and space size of all devices. 16.3. Programming Model

16.3.1. Summary of the APB Bridge Registers Table 16-1. Summary of APB Bridge Registers Offset Type Description Reset Value +0x04 R/W APB Slave 1 Base / Size Register 0x18D0 0000 +0x08 R/W APB Slave 2 Base / Size Register 0x18B0 0000 +0x0C R/W APB Slave 3 Base / Size Register 0x1820 0000 +0x10 R/W APB Slave 4 Base / Size Register 0x1830 0000 +0x14 R/W APB Slave 5 Base / Size Register 0x18E0 0000 +0x18 R/W APB Slave 6 Base / Size Register 0x1940 0000 +0x20 R/W APB Slave 8 Base / Size Register 0x1810 0000 +0x24 R/W APB Slave 9 Base / Size Register 0x1960 0000 +0x28 R/W APB Slave 10 Base / Size Register 0x1960 0000 +0x2C R/W APB Slave 11 Base / Size Register 0x1890 0000 +0x30 R/W APB Slave 12 Base / Size Register +0x34 +0x38 +0x3C +0x40 +0x44 +0x48 +0x4C +0x50 +0x54 +0x58 +0x5C +0x60 +0xC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W APB Slave 13 Base / Size Register APB Slave 14 Base / Size Register APB Slave 15 Base / Size Register APB Slave 16 Base / Size Register APB Slave 17 Base / Size Register APB Slave 18 Base / Size Register APB Slave 19 Base / Size Register APB Slave 20 Base / Size Register APB Slave 21 Base / Size Register APB Slave 22 Base / Size Register APB Slave 23 Base / Size Register APB Slave 24 Base / Size Register Revision register 0x18F0 0000 0x1900 0000 0x1800 0000 0x1840 0000 0x1850 0000 0x1860 0000 0x1870 0000 0x1880 0000 0x18A0 0000 0x1910 0000 0x1930 0000 -

Assignment CFC SSP UART1 UART2 SDC I2S/I2C/SPI UART3 Reserved Resreved UART4 Reserved Reserved GPIOB GPIOC PMU TIMER WDT RTC GPIOA PINTC I2C PWM JEMCore-II

16.3.2. Register Descriptions The following sections describe the APB Bridge registers in detail 16.3.2.1. APB Slave n Base / Size Register (Offset == 0x04 ~ 0x5C)

The base/size registers for all the slaves have the same format and the same definition of the bit fields. Bit 31-30 29-20 19-16 Name -Base Size Table 16-2. APB Slave n Base/Size Register Type Description -Reserved R/W Base Address [29:20] Size of Address Space R/W 0000: 1M. It has been configured for 1 MBytes
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Technical Reference Manual Bit Name Type Description 0001: 2M 0010: 4M 0011: 8M 0100: 16M 0101: 32M 0110: 64M 0111: 128M 1000: 256M 1001-1111: Reserved. Reserved

15-0

--

--

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17.
17.1.

Peripheral Interrupt Controller (PINTC)

General Description

The peripheral interrupt controller provides both Fast Interrupt Request (FIQ) and Standard Interrupt Request (IRQ) modes to the JEMCore. This PINT takes all up to 31 standard interrupt sources and up to 31 fast interrupt sources and generates two interrupt request outputs respectively. The interrupt requests are fed directly to the JEMCore interrupt controller, whereby the interrupt requests will processed based on the defined interrupt priority. The FIQ output is connected with JEMCore NMI, while the IRQ output is passed to the JEMCore interrupt 10 respectively. It supports the following features: Up to thirty-two (32) fast interrupt (FIQ) inputs Up to thirty-two (32) standard interrupt (IRQ) inputs Interrupts can be routed to either IRQ or FIQ Both edge and level triggered interrupt source with positive and negative directions D-bounce circuit for interrupt input sources Independently enable or disable any interrupt source

Figure below shows the block diagram of the interrupt controller.

PCLK PRSTn pwrite pe nable psel paddr

APB Controller

APB

int_irqn
pwdata/prdata

Config Registers int_fiqn

Microprocessor

io_irqin io_fiqin

Interrupt Detect Block

Figure 17-1. INTC Block Diagram 17.2. APB All registers can be read / written via APB bus protocol.

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Technical Reference Manual 17.3. Configuration Register Block

This register is used to generate the IRQ and FIQ signal fed to microprocessor. 17.4. Interrupt Detect Block

The interrupt detect block is used to detect the incoming interrupt signal bus with the following two methods: Edge triggered with positive or negative edge. Level triggered with active high or low. 17.5. Interrupt Routing Table

The interrupt source assignment of the IRQ is shown in the Table 416. The IRQ output is connected with the JEMCore interrupt 10. Some interrupt requests also fed directly to the JEMCore interrupt 11~31. The interrupt handlings for these direct interrupt requested is faster since they dont have to query the PINTC. IRQ 31 30 29 Device Video capture Video capture Video capture Table 17-1. Interrupt Routing Table for IRQs Name Condition Description dma_ov_intr Active high Video capture pdma_ov rdma_ov_intr Active high Video capture rdma_ov vcap_fd_int Active high Video capture interrupt Media codec interrupt request as follows: DMA transfer done Active high Motion estimation done mcp_intr Motion compensation done Pixel interpolation done Predict motion vector done tmr_intr0 Active high General Purpose Timer/counter 0 interrupt request Active high Indicates the occurrence of interrupts. usb_int0 User must read interrupt register to check the cause of interrupt event. Ethernet interrupt request. mac_int Active high User must read the Interrupt Status Register to find out which interrupt occurs. DMA interrupt signal. rshint Active high Indicate that the total cycles of the DMA transfer are finished irda_intr2 Active high This interrupt request signal is only used in FIR mode. UART4 interrupt request goes high whenever any one of the following conditions: Receiver Error Flag irda_intr1 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status Active high Interrupt request for combining dmaint_tc and dmaint dmaint_err lc_intr Active high LCD global interrupt request
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Mediacodec

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Timer/counter0 USB 2.0 OTG Ethernet MAC APB Bridge IrDA/UART4

22

IrDA/UART4

21 20

DMA LCD

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Technical Reference Manual IRQ 19 18 17 16 15 14 13 12 Device TIMER1 RTC RTC WDT TIMER2 TIMER1 GPIOA RTC Condition Description Active high Timer 1 interrupt request Active high RTC once-per-second auto alarm The RTC second, minute and hour counter registers rtc_alarm Active high all match with the alarm second, minute and hour registers. wd_intr Active high Watch Dog Timer system interrupt request tm3_intr Active high Timer/counter 2 interrupt request tm2_intr Active high Timer/counter 1 interrupt request Active high It indicates that a valid match has occurred between gpioa_intr any of the interrupts associated with GPIOA Indicates the occurrence of interrupts. rtc_intr Active high The application should read the interrupt register to check the cause of the interrupt event UART2 interrupt request goes high whenever any one of the following interrupt conditions Receiver Error Flag uartintr2 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status UART1 interrupt request goes high whenever any one of the following interrupt conditions Receiver Error Flag uartintr1 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status UART3 interrupt request goes high whenever any one of the following interrupt conditions Receiver Error Flag uartintr3 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status Active high It indicates that a valid match has occurred between Gpioc_intr any of the interrupts associated with GPIOC Active high It indicates that a valid match has occurred between Gpiob_intr any of the interrupts associated with GPIOB I2C/AC97/SPI interrupt request. ssp_intr Active high Users can read SSP status register to identify the exact conditions SD controller interrupt request. sdc_intr Active high Users can read status register to identify the exact conditions AES interrupt request. aes_des_intr Active high Users can read interrupt status register to identify the exact interrupt conditions I2C interrupt request. isi2c Active high Users can read I2C status register to identify the exact conditions ssp_intr SSP interrupt.
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GPIOC GPIOB I2S/AC97/SPI SDC AES I2C SSP

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Technical Reference Manual Condition Description Active high Users can read interrupt status register to identify the exact interrupt conditions. CFC interrupt request. 1 CFC cfc_int_r Active high Users can read CFC host status register to identify the exact conditions. 0 AHB Framewx_intr Active high The interrupt source assignment of the FRQ is shown in the Table 416. The FRQ output is connected with the JEMCore NMI. Some interrupt requests also fed directly to the JEMCore interrupt 11~31. The interrupt handlings for these direct interrupt requests are faster since they dont need to query the PINTC, in order to identify the interrupt source. FRQ 31 30 29 Table 17-2. Interrupt Routing Table for FRQs Device Name Condition Description Video capture dma_ov_intr Active high Video capture pdma_ov Video capture rdma_ov_intr Active high Video capture rdma_ov Video capture vcap_fd_int Active high Video capture interrupt Media codec interrupt request as follows: DMA transfer done Active high Motion estimation done Mediacodec mcp_intr Motion compensation done Pixel interpolation done Predict motion vector done Timer/counter0 tmr_intr0 Active high General Purpose Timer/counter 0 interrupt request Active high Indicates the occurrence of interrupts. USB 2.0 OTG usb_int0 User must read interrupt register to check the cause of interrupt event. Ethernet interrupt request. Ethernet MAC mac_int Active high User must read the Interrupt Status Register to find out which interrupt occurs. DMA interrupt signal. APB Bridge rshint Active high Indicate that the total cycles of the DMA transfer are finished IrDA/UART4 irda_intr2 Active high This interrupt request signal is only used in FIR mode. UART4 interrupt request goes high whenever any one of the following conditions: Receiver Error Flag IrDA/UART4 irda_intr1 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status Active high Interrupt request for combining dmaint_tc and DMA dmaint dmaint_err LCD lc_intr Active high LCD global interrupt request TIMER1 tm1_intr Active high Timer 1 interrupt request RTC rtc_sec Active high RTC once-per-second auto alarm The RTC second, minute and hour counter registers all RTC rtc_alarm Active high match with the alarm second, minute and hour
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Technical Reference Manual FRQ 16 15 14 13 12 Device WDT TIMER2 TIMER1 GPIOA RTC Name Condition Description registers. wd_intr Active high Watch Dog Timer system interrupt request tm3_intr Active high Timer/counter 2 interrupt request tm2_intr Active high Timer/counter 1 interrupt request Active high It indicates that a valid match has occurred between gpioa_intr any of the interrupts associated with GPIOA Indicates the occurrence of interrupts. rtc_intr Active high The application should read the interrupt register to check the cause of the interrupt event UART2 interrupt request goes high whenever any one of the following interrupt conditions Receiver Error Flag uartintr2 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status UART1 interrupt request goes high whenever any one of the following interrupt conditions Receiver Error Flag uartintr1 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status UART3 interrupt request goes high whenever any one of the following interrupt conditions Receiver Error Flag uartintr3 Active high Received Data Available: timeout (FIFO Mode only) Transmitter Holding Register Empty Modem Status Active high It indicates that a valid match has occurred between Gpioc_intr any of the interrupts associated with GPIOC Active high It indicates that a valid match has occurred between Gpiob_intr any of the interrupts associated with GPIOB I2C/AC97/SPI interrupt request. ssp_intr Active high Users can read SSP status register to identify the exact conditions SD controller interrupt request. sdc_intr Active high Users can read status register to identify the exact conditions AES interrupt request. aes_des_intr Active high Users can read interrupt status register to identify the exact interrupt conditions I2C interrupt request. isi2c Active high Users can read I2C status register to identify the exact conditions SSP interrupt. ssp_intr Active high Users can read interrupt status register to identify the exact interrupt conditions. CFC interrupt request. cfc_int_r Active high Users can read CFC host status register to identify the
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Technical Reference Manual FRQ 0 17.6. Device AHB Name Condition Description exact conditions. Framewx_intr Active high

Programming Model

17.6.1. Summary of Interrupt Controller Registers The Interrupt Controller registers are shown as follows: Address (Offset) +0x00 +0x04 +0x08 +0x0c +0x10 +0x14 +0x18 ~ +0x1c +0x20 +0x24 +0x28 +0x2c +0x30 +0x34 +0x38~+0x3c +0x50 +0x54 +0x58 +0x5C Table 17-3. Summary of Interrupt Controller Registers Type Description RO IRQ Source register R/W IRQ Mask register WO IRQ Interrupt Clear Register R/W IRQ Trig Mode Register R/W IRQ Trig Level Register RO IRQ Status Register Reserved RO FIQ Source Register R/W FIQ Mask Register WO FIQ Interrupt Clear Register R/W FIQ Trig Mode Register R/W FIQ Trig Level Register RO FIQ Status Register Reserved RO Revision Register RO Feature Register for Input Number RO Feature Register for IRQ De-bounce Location RO Feature Register for FIQ De-bounce Location Reset Value 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -

17.6.2.

Register Descriptions 17.6.2.1. IRQ Source Register (Offset == 0x00) The value of the IRQ source register records the status of the input source. The source register is asserted (1b1) when the source interrupt is activate. Bit 31-0 Name irqsrcreg Table 17-4. The IRQ Source Register Type Description RO IRQ inputs

17.6.2.2. IRQ Mask Register (Offset == 0x04) The mask register is used to mask the interrupt source. The interrupt source will be ignored when the corresponding bit of the mask register is set to zero. Bit 31-0 Name irqmask Table 17-5. The IRQ Mask Register Type Description IRQ mask R/W 0: Mask the interrupt source
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Technical Reference Manual 1: Unmask the interrupt source 17.6.2.3. IRQ Interrupt Clear Register (Offset == 0x08) The interrupt clear register is used to clear the corresponding interrupt source register. The register takes action only when the input interrupt sources are edge triggered. Bit 31-0 Name irqclear Table 17-6. The IRQ Interrupt Clear Register Type Description Clear interrupt. This clear bit will only work on edge triggered interrupt WO sources and will reset to 0 automatically after the interrupt status is cleared.

17.6.2.4. IRQ Trig Mode Register (Offset == 0x0C) The trig mode register is used to indicate the type of interrupt source. Table 17-7. The IRQ Trig Mode Register Bit Name Type Description 0: Level trigger 31-0 irqtrigmode R/W 1: Edge trigger 17.6.2.5. IRQ Trig Level Register (Offset == 0x10) The IRQ trig level register indicates whether the source interrupt signal is high active or low active. Table 17-8. The IRQ Trig Level Register Bit Name Type Description 0: High active when level triggered or rising edge triggerred 31-0 irqtriglevel R/W 1: Low active when level triggered or falling edge triggered 17.6.2.6. IRQ Status Register (Offset == 0x14) The IRQ status register records the current interrupt source status after masking. Bit 31-0 Name irqstatus Table 17-9. The IRQ Status Register Type Description IRQ status after masking R/W 0: No interrupt 1: Interrupt activated

17.6.2.7. FIQ Source Register (Offset == 0x20) The value of the FIQ source register records the status of the input source. The source register is asserted (1b1) when the source interrupt is activated. Bit 31-0 Name fiqsrcreg Table 17-10. The FIQ Source Register Type Description RO FIQ inputs

17.6.2.8. FIQ Mask Register (Offset == 0x24) The mask register is used to mask the interrupt source. The interrupt source will be ignored when the corresponding bit of the mask register is set to zero.

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Technical Reference Manual Table 17-11. The FIQ Mask Register Type Description FIQ mask R/W 0: Mask the interrupt source 1: Unmask the interrupt source

Bit 31-0

Name fiqmask

17.6.2.9. FIQ Interrupt Clear Register (Offset == 0x28) The interrupt clear register is used to clear the corresponding interrupt source register. The register takes action only when the input interrupt sources are edge triggered. Table 17-12. The FIQ Interrupt Clear Register Bit Name Type Description Clear interrupt. This clear bit will only work on edge triggered interrupt 31-0 fiqclear WO sources and will reset to 0 automatically after the interrupt status is cleared. 17.6.2.10. FIQ Trig Mode Register (Offset == 0x2C) The trig mode register is used to indicate the type of interrupt source. Bit 31-0 Name fiqtrigmode Table 17-13. The FIQ Trig Mode Register Type Description 0: Level trigger R/W 1: Edge trigger

17.6.2.11.

FIQ Trig Level Register (Offset == 0x30)

The FIQ trig level register indicates whether the source interrupt signal is high active or low active. Table 17-14. The FIQ Trig Level Register Bit 31-0 Name fiqtriglevel Type R/W Description 0: High active when level triggered or rising edge triggered 1: Low active when level triggered or falling edge triggered

17.6.2.12. FIQ Status Register (Offset == 0x34) The FIQ status register records the current interrupt source status after masking. Table 17-15 shows the bit assignment of FIQ status register. Bit 31-0 Name fiqstatus Table 17-15. The FIQ Status Register Type Description FIQ status after masking R/W 0: No interrupt 1: Interrupt activated

17.6.2.13. Bit 31-24

Revision Register (Offset == 0x50) Table 17-16. Revision Register Name Type Description Reserved
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Technical Reference Manual 23-0 intcrevision RO Record INTC revision

17.6.2.14. Bit 31-16 15-8 7-0

Feature Register for Input Number (Offset == 0x54) Table 17-17. Feature Register for Input Number Name Type Description Reserved irq_number RO Record supported IRQ pin number of INTC fiq_number RO Record supported FIQ pin number of INTC Feature Register for IRQ De-bounce Location (Offset == 0x58) Table 17-18. Feature Register for IRQ De-bounce Location Name Type Description irq debounce RO Record IRQ interrupt source with de-bounce indication Feature Register for FIQ De-bounce Location (Offset == 0x5C) Table 17-19. Feature Register for FIQ De-bounce Location Name Type Description Fiq debounce RO Record FIQ interrupt source with de-bounce indication

17.6.2.15. Bit 31-0

17.6.2.16. Bit 31-0

17.6.3. Programming Sequence Before you turn on the interrupt controller, you should fill the correct register setting about the input interrupt source of trig mode and trig level, and then turn on the interrupt controller mask enable bit. The programming sequence includes setting the clear register, filling the trigmode and triglevel, and then turning the mask bit on (by setting the corresponding bit to 1). This way, the interrupt controller will work normally. You can read the status register and source register to check the current interrupt status.

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18. General Purpose Input / Output (GPIO)

18.1. General Description aJ-200 includes three GPIO ports, which provide ninety-six programmable GPIO pins. Each GPIO can be programmed as an input or output, or as an interrupt input. The GPIO supports rising edge / falling edge, both-edge, and high level / low level interrupt sense types and pull-up and pull-down capability. It supports the following features: Three 32-bit ports. Each port provides 32 independent input, output and output enable buses for bidirectional I/O pins Each port can separately trigger the GPIO interrupt Each port interrupt generation can be triggered by rising edge, falling edge, both edges, or high and low level Each input port can be pulled high or pulled low Programmable sampling rate for all I/O ports Output data bit can be set or cleared separately All ports are set to input mode at hardware reset

Figure below shows the block diagram of the GPIO.

GPIOA
AMBA APB Interface Register Block In/Out Control Data Register
PinDir[31:0]

gpio_en[31:0]

IO MUX

GPIOA_out[31:0] GPIOA_in[31:0]

GpioDataOut[31:0]

GpioDataIn[31:0]

Interrupt Control
BCLK

Interrupt Detection Logic Bounce Clock Logic Pull High or Down & Detect Logic

GPIOA_intr GPIOA_mis[31:0]

Bounce Control Pull Control

GPIOA_pulldown[31:0] GPIOA_pullup[31:0]

GPIOB_out[31:0] GPIOB_in[31:0] GPIOB_intr GPIOB_mis[31:0] GPIOB_pullup[31:0] GPIOB_pulldown[31:0] GPIOC_in[31:0] GPIOC_out[31:0] GPIOC_intr GPIOC_mis[31:0] GPIOC_pullup[31:0] GPIOC_pulldown[31:0]

GPIOB

GPIOC

Figure 18-1. GPIO Block Diagram

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Technical Reference Manual The GPIO supports data input / output, data bit set / clear, variable interrupt detection, pull function and bounce clock. 18.2. Programming Model

18.2.1. Summary of General Purpose I/O Registers Table below shows the offset, type, width, reset value and name of each GPIO programming registers. Table 18-1. Summary of General Purpose I/O Registers Offset Type Width Reset Name Description 0x9870 0000 Base address of GPIOA +0x00 R/W 32 0x0 GpioDataOut GPIOA data output register +0x04 R 32 0x0 GpioDataIn GPIOA data input register GPIOA direction register +0x08 R/W 32 0x0 PinDir 0 Input 1 Output +0x0C Reserved GPIOA data bit set register. When writing to this register, the +0x10 W 32 0x0 GpioDataSet corresponding bits in data register are set to one, while the other bits are unchanged. GPIOA data bit clear register. When writing to this register, the +0x14 W 32 0x0 GpioDataClear corresponding bits in data register are cleared to zero, while the other bits are unchanged GPIOA pull enable register +0x18 R/W 32 0x0 PinPullEnable 0 Pin is not pulled 1 Pin is pulled GPIOA pull high pull low register +0x1C R/W 32 0x0 PinPullType 0 Pin is pulled low 1 Pin is pulled high GPIOA interrupt enable register +0x20 R/W 32 0x0 IntrEnable 0 Pin interrupt is disabled 1 Pin interrupt is enabled GPIOA interrupt raw status register +0x24 R 32 0x0 IntrRawState 0 Interrupt is not detected 1 Interrupt is detected GPIOA interrupt masked status register +0x28 R 32 0x0 IntrMaskedState 0 Interrupt is not detected or masked 1 Interrupt is detected and not masked GPIOA interrupt mask register +0x2C R/W 32 0x0 IntrMask 0 Mask is disabled 1 Mask is enabled GPIOA interrupt clear +0x30 W 32 0x0 IntrClear 0 No effect 1 Clear interrupt +0x34 R/W 32 0x0 IntrTrigger GPIOA interrupt trigger method register

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Technical Reference Manual Offset Type Width Reset Description 0 Edge trigger 1 Level trigger GPIOA interrupt edge trigger by both IntrBoth 0 Single edge 1 Both edges GPIOA interrupt trigger by rising or falling edge 0 Rising edge IntrRiseNeg 1 Falling edge GPIOA interrupt trigger by high or low level 0 High level 1 Low level GPIOA pre-scale clock enable. When enabled, PCLK will be divided by BouncePreScale clocks. It is used to extend BounceEnable the clock cycle of detecting interrupt. 0 Disable 1 Enable GPIOA pre-scale. It is used to adjust different PCLK frequencies. The allowed range is 0x1 ~ BouncePreScale 0xFFFF. If BouncePreScale is zero, and Bounce is enabled, this pin cannot detect any interrupt. Reserved GPIOB data output register GPIOB data input register GPIOB direction register 0 Input 1 Output Reserved GPIOB data bit set register. When writing to this register, the corresponding bits in data register are set to one, while the other bits are unchanged. GPIOB data bit clear register. When writing to this register, the corresponding bits in data register are cleared to zero, while the other bits are unchanged GPIOB pull enable register 0 Pin is not pulled 1 Pin is pulled GPIOB pull high pull low register 0 Pin is pulled low 1 Pin is pulled high
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Name

+0x38

R/W

32

0x0

+0x3C

R/W

32

0x0

+0x40

R/W

32

0x0

+0x44

R/W

24

0x7D0

+0x48 +0x4C 0x98F0 0000 +0x00 +0x04 +0x08 +0x0C +0x10

Base Address of GPIOB R/W 32 0x0 GpioDataOut R 32 0x0 GpioDataIn R/W 32 0x0 PinDir

32

0x0

GpioDataSet

+0x14

32

0x0

GpioDataClear

+0x18 +0x1C

R/W R/W

32 32

0x0 0x0

PinPullEnable PinPullType

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Technical Reference Manual Offset +0x20 +0x24 +0x28 +0x2C +0x30 +0x34 +0x38 Type R/W R R R/W W R/W R/W Width 32 32 32 32 32 32 32 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description GPIOB interrupt enable register IntrEnable 0 Pin interrupt is disabled 1 Pin interrupt is enabled GPIOB interrupt raw status register IntrRawState 0 Interrupt is not detected 1 Interrupt is detected GPIOB interrupt masked status register IntrMaskedState 0 Interrupt is not detected or masked 1 Interrupt is detected and not masked GPIOB interrupt mask register IntrMask 0 Mask is disabled 1 Mask is enabled GPIOB interrupt clear IntrClear 0 No effect 1 Clear interrupt GPIOB interrupt trigger method register IntrTrigger 0 Edge trigger 1 Level trigger GPIOB interrupt edge trigger by both IntrBoth 0 Single edge 1 Both edges GPIOB interrupt trigger by rising or falling edge 0 Rising edge IntrRiseNeg 1 Falling edge GPIOB interrupt trigger by high or low level 0 High level 1 Low level GPIOB pre-scale clock enable. When enabled, PCLK will be divided by BouncePreScale clocks. It is used to extend BounceEnable the clock cycle of detecting interrupt. 0 Disable 1 Enable GPIOB pre-scale. It is used to adjust different PCLK frequencies. The allowed range is 0x1 ~ BouncePreScale 0xFFFF. If BouncePreScale is zero, and Bounce is enabled, this pin cannot detect any interrupt. Reserved GPIOC data output register GPIOC data input register GPIOC direction register 0 Input 1 Output
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+0x3C

R/W

32

0x0

+0x40

R/W

32

0x0

+0x44

R/W

24

0x7D0

+0x48 +0x4C 0x9900 0000 +0x00 +0x04 +0x08

Base address of GPIOC R/W 32 0x0 GpioDataOut R 32 0x0 GpioDataIn R/W 32 0x0 PinDir

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Technical Reference Manual Offset +0x0C +0x10 Type Width Reset Description Reserved GPIOC data bit set register. When writing to this register, the GpioDataSet corresponding bits in data register are set to one, while the other bits are unchanged. GPIOC data bit clear register. When writing to this register, the GpioDataClear corresponding bits in data register are cleared to zero, while the other bits are unchanged GPIOC pull enable register PinPullEnable 0 Pin is not pulled 1 Pin is pulled GPIOC pull high pull low register PinPullType 0 Pin is pulled low 1 Pin is pulled high GPIOC interrupt enable register IntrEnable 0 Pin interrupt is disabled 1 Pin interrupt is enabled GPIOC interrupt raw status register IntrRawState 0 Interrupt is not detected 1 Interrupt is detected GPIOC interrupt masked status register IntrMaskedState 0 Interrupt is not detected or masked 1 Interrupt is detected and not masked GPIOC interrupt mask register IntrMask 0 Mask is disabled 1 Mask is enabled GPIOC interrupt clear IntrClear 0 No effect 1 Clear interrupt GPIOC interrupt trigger method register IntrTrigger 0 Edge trigger 1 Level trigger GPIOC interrupt edge trigger by both IntrBoth 0 Single edge 1 Both edges GPIOC interrupt trigger by rising or falling edge 0 Rising edge IntrRiseNeg 1 Falling edge GPIOC interrupt trigger by high or low level 0 High level 1 Low level GPIOC pre-scale clock enable. When enabled, PCLK will be divided by BounceEnable BouncePreScale clocks. It is used to extend the clock cycle of detecting interrupt.
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Name

32

0x0

+0x14

32

0x0

+0x18 +0x1C +0x20 +0x24 +0x28 +0x2C +0x30 +0x34 +0x38

R/W R/W R/W R R R/W W R/W R/W

32 32 32 32 32 32 32 32 32

0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

+0x3C

R/W

32

0x0

+0x40

R/W

32

0x0

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Technical Reference Manual Offset Type Width Reset Description 0 Disable 1 Enable GPIOC pre-scale. It is used to adjust different PCLK frequencies. The allowed range is 0x1 ~ BouncePreScale 0xFFFF. If BouncePreScale is zero, and Bounce is enabled, this pin cannot detect any interrupt. Name

+0x44

R/W

24

0x7D0

18.2.2. Register Descriptions The following sections describe the GPIO registers in detail. 18.2.2.1. GpioDataOut (Offset == 0x00)

The GpioDataOut register is the GPIO data out register. When the PinDir indicates the pin is in output mode, the GpioDataOut content is connected to gpio_out. When the PinDir indicates the pin is in input mode, the GpioDataOut can hold the data. Bit 31-0 18.2.2.2. Name GpioDataOut Table 18-2. GPIO DataOut Register Type Comment Read / Write None

GpioDataIn (Offset == 0x04)

The GpioDataIn register is the GPIO data in register. When the PinDir indicates the pin is in input mode, the GpioDataIn will latch the value of gpio_in at PCLK rising edge. When the PinDir indicates the pin is in output mode, the GpioDataIn register is a dont care register. Table 18-3. Bit 31-0 Name GpioDataIn Type Read GPIO DataIn Register Comment None

18.2.2.3.

PinDir (Offset == 0x08)

The PinDir register controls the gpio_en. When the PinDir indicates the pin is in output mode, the related gpio_en is set to one. Otherwise, the related gpio_en is set to zero. Table 18-4. Bit 31-0 Name PinDir Type Read / Write GpioDataSet (Offset == 0x10) Pin Direction Register Comment None

18.2.2.4.

GpioDataSet is one-bit operation logic. When writing to this address, if some bits of GpioDataSet are one, the related bits of GpioDataOut will be set. For example, if GpioDataOut[7:0] = 0x23 and pwdata[7:0] from APB is 0x47 in a write operation to GpioDataSet address, the result of GpioDataOut[7:0] will be 0x67.

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Technical Reference Manual Table 18-5. Type Write GPIO Data Bit Set Register Comment None

Bit 31-0

Name GpioDataSet

18.2.2.5.

GpioDataClear (Offset == 0x14)

GpioDataClear is one-bit operation logic. When writing to this address, if some bits of GpioDataClear are one, the related bits of GpioDataOut will be cleared. For example, if GpioDataOut[7:0] = 0x23 and pwdata[7:0] from APB is 0x47 in a write operation to GpioDataClear address, the result of GpioDataOut[7:0] will be 0x20. Bit 31-0 Name GpioDataClear Table 18-6. Type Write GPIO Data Bit Clear Register Comment None

18.2.2.6.

PinPullEnable (Offset == 0x18)

The PinPullEnable register controls the gpio_pullup and gpio_pulldown. If the PinPullEnable indicates the pin is disabled pull, the gpio_pullup and gpio_pulldown are masked to zero. Bit 31-0 18.2.2.7. Name PinPullEnable Table 18-7. Type Read / Write Pin Pull Enable Register Comment None

PinPullType (Offset == 0x1C)

PinPullType controls the gpio_pullup and gpio_pulldown. If PinPullEnable is enabled and PinPullType is set to zero, the gpio_pullup will be set to zero, and the gpio_pulldown will be set to one. Bit 31-0 Name PinPullType Table 18-8. Pin Pull Type Register Type Comment Read / Write None Table 18-9. Pull Truth Table PinPullType gpio_pullup X 0 0 0 1 1

PinPullEnable 0 1 1 18.2.2.8.

gpio_pulldown 0 1 0

IntrEnable (Offset == 0x20)

The IntrEnable register controls the enabling or disabling interrupt detection logic. It is a mask of interrupt detection logic. While the pin direction is input and interrupt detection is enabled, the pin can accept interrupt from pad. The sense state is stored in the IntrMaskedState register (masked by IntrEnable). Before turning on the IntrEnable, the programmer can clear the masked state by writing one to the IntrClear to ensure the initial state.

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Technical Reference Manual Table 18-10. Interrupt Enable Register Name Type Comment Gpio Interrupt Detection Enable Read / Write None IntrRawState (Offset == 0x24)

Bit 31-0

18.2.2.9.

The IntrRawState register is the raw results of interrupt detection. If the IntrEnable is enabled, the IntrRawState register reflects the interrupt detection status. The programmer can poll this register to detect an interrupt. Bit 31-0 Table 18-11. Interrupt Raw State Register Name Type Comment Interrupt Detection Raw State Read None IntrMaskedState (Offset == 0x28)

18.2.2.10.

The IntrMaskedState register is the masked result of the interrupt detection. The IntrMaskedState register is controlled by the IntrEnable, IntrRawState and IntrMask registers. Bit 31-0 Table 18-12. Interrupt Masked State Register Name Type Comment Interrupt Detection Masked State Read None IntrMask (Offset == 0x2C)

18.2.2.11.

The IntrMask register is the mask register of the interrupt detection. It masks the IntrRawState register. For example, if IntrEnable[0] = 1, IntrRawState[0] = 1 and IntrMask[0] = 1, then IntrMaskedState[0] will never be changed to 1. Bit 31-0 Name Interrupt Mask Table 18-13. Interrupt Mask Register Type Comment Read / Write None

18.2.2.12.

IntrClear (Offset == 0x30)

The IntrClear is one-bit operation logic. If some bits of the pwdata are set in a write operation to the IntrClear address, the related bit of IntrMaskedState will be cleared. Bit 31-0 Name Interrupt Clear Table 18-14. Interrupt Clear Type Comment Read None

18.2.2.13.

IntrTrigger (Offset == 0x34)

The IntrTrigger register indicates the interrupt trigger method for each pin. If the IntrTrigger is zero, interrupt is edge triggered; otherwise, interrupt is level triggered.
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Technical Reference Manual Table 18-15. Interrupt Trigger Method Register Name Type Comment Interrupt Detection Trigger Method Read / Write Require INTR option. IntrBoth (Offset == 0x38)

Bit 31-0

18.2.2.14.

The IntrBoth register indicates whether the edge trigger is done by both-edge or single edge. If the IntrTrigger indicates edge trigger and IntrBoth is zero, interrupt edge trigger is done by single edge. If the IntrTrigger indicates edge trigger and the IntrBoth is one, interrupt edge trigger is done by both edges. Bit 31-0 Table 18-16. Interrupt Both Edge Trigger Register Name Type Comment Interrupt Both Edge Trigger Read / Write None IntrRiseNeg (Offset == 0x3C)

18.2.2.15.

The IntrRiseNeg register indicates whether the edge trigger is done by rising edge or falling edge. If the IntrTrigger is edge trigger, the IntrBoth is single edge and IntrRiseNeg is 0, interrupt edge trigger is done by rising edge. If the IntrTrigger is edge trigger, the IntrBoth is single edge and IntrRiseNeg is 1, interrupt edge trigger is done by falling edge. Bit 31-0 Table 18-17. Interrupt Rise or Neg Edge Trigger Register Name Type Comment Interrupt Rise or Neg Edge Trigger Read / Write None BounceEnable (Offset == 0x40)

18.2.2.16.

The BounceEnable register controls the bounce function. If the BounceEnable indicates on, interrupt detection is sampled by extended clock. The extended number is controlled by the BouncePreScale register. Bit 31-0 Name Bounce Enable Table 18-18. Bounce Enable Register Type Comment Read / Write None

18.2.2.17.

BouncePreScale (Offset == 0x44)

The BouncePreScale register is an auto reload register dedicated for the bounce timer. It can extend PCLK to the BouncePreScale cycles. This can be used to adjust interrupt sample clock period in different machines. The reset value is 0x7D0, which means that if APB clock frequency is 66 MHz, then the debounce clock will be divided to 33 KHz frequency. The programmer can adjust this register to fit different systems.

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Technical Reference Manual Table 18-19. Bounce Clock Pre-scale Register Name Type Comment Bounce Pre-Scale Read / Write None Timing

Bit 23-0 18.3.

18.3.1. Write to GpioDataOut Register

PADDR PWRITE PSEL PENABLE PWDATA GpioDataOut
GpioData Address

DATA1 DATA1

Figure 18-2. Write to GpioDataOut Register 18.3.2. Positive Edge Trigger

PCLK IntrTrigger[0] PinDir[0] gpio_en[0] gpio_in[0] IntrRawState[0] IntrMaskedState[0] gpio_intr

Figure 18-3. Positive Edge Trigger 18.3.3. Level High Trigger

PCLK IntrTrigger[0] PinDir[0] gpio_en[0] gpio_in[0] IntrRawState[0] IntrMaskedState[0] gpio_intr

Figure 18-4. Level High Trigger 18.4. Programming Sequence

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Technical Reference Manual The GPIO is default set to input data. So, the programmer can read the GpioDataIn register after reset directly. If the GPIO is used to output data, the programmer should set the PinDir to one, so that the GpioDataOut register can be sent to pad. If the GPIO is used to detect an interrupt, the programmer needs to set the PinDir and detection type first. The PinDir needs to be set to zero to indicate the pin is input. The detection types include rising edge, falling edge, both-edge, high level and low level. Please see the IntrTrigger, IntrBoth and IntrRiseNeg register descriptions for the details. The following steps constitute the GPIO programming sequence: 1. 2. 3. Set PinDir. Set IntrTrigger, IntrBoth and IntrRiseNeg. Enable IntrEnable.

In some cases, the interrupt detection may need the de-bounce function, for example, when the GPIO is used to control keypad or switch. The following steps are required to activate the de-bounce function: 1. 2. 3. 4. 5. Set PinDir. Set IntrTrigger, IntrBoth and IntrRiseNeg. Set BouncePreScale. Enable BounceEnable. Enable IntrEnable.

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Technical Reference Manual

19. Pulse Width Modulators (PWMs)

19.1. Overview The aJ-200 contains three enhanced pulse width modulator channels. Each channel provides two PWM outputs, and is controlled by its own set of registers. This allows up to eight PWM outputs using potentially four different PWM frequencies. The PWM channels use the PCLK signal as the primary timing source. It supports the following features: 45 MHZ input frequency (PCLK) 10-bit prescaler 16-bit counter Enhanced period control through 10-bit clock prescaler and 16-bit period counter Dead-band generation with independent rising and falling time control A trip condition can be forced either low or high

Figure below shows the simplified block diagram of PWMs

PCLK

PWM Channel0

PWMA0 PWMB0

PWM Channel1 APB APB Slave PWM Channel2

PWMA1 PWMB1

PWMA2 PWMB2

Figure 19-1. Block Diagram of PWMs The PWM block consists of an APB slave interface, and four PWM channels 19.1.1. APB Slave The APB slave module provides AMBA/APB interface so that the processor can access the control registers of each PWM modules via APB slave module. This interface is complaint with AMBA 2.0 specification.
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Technical Reference Manual 19.1.2. PWM Channels Each channel composes of two PWM outputs. It consists of a 10-bit prescaler, 16-bit counter, six comparators, and a set of control registers. This allows all channels to operate independently. The figure below shows more details on PWM channels:

Figure 19-2. Block Diagram of PWMs 19.1.3. Counters and Comparators Each channel contains its own 10-bit pre-scale counter and a 16-bit counter that are used to adjust the period waveform of the output signals at different frequencies. The 10-bit counter is used to set the scale of the PCLK clock. The 16-bit counter is used to define the period of the waveform. In addition, two comparators are used to specify the output rising-edge and falling-edge count value, whereby the values are specified in the Edge registers respectively. 19.1.4. Control Registers PWM contains a common Master PWM Control register and each PWM channel contains a set of it own registers to allow four channels to operate independently 19.1.4.1. Master PWM Control

The master PWM control logic provides common control over the operation of all four PWM channels. The register configuration allows single bus transactions to update the operation of all four PWM channels (ex: disable all counters, drive all outputs low, etc.).

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Technical Reference Manual 19.1.4.2. PWM Waveform Control Registers

For each channel, there is a PWM period control register (PERIOD) and two edge control registers (EDGE). The EDGE registers contains the rising and falling time values of the two PWM signals so that these count values may be updated with a single register write. The detail information for each register is illustrated in the next chapter. 19.1.4.3. PWM Current Count Register

This registers indicate the current values of the Prescaler and PWM counter of each channel. It may be read and written at any time. Generally the counters are not directly written to via software. However, the ability to directly write to the registers may facilitate specific timing needs or testing. 19.1.4.4. Master Output Mode (MOM

The Master Output Mode register sets operating mode of all PWM outputs. Each PWM output may be set high, low, or based on the PWM signal. In addition, PWM channel 3 provides a chopping function which may be used with PWM channels 0-2. The chopping function allows a high frequency carrier signal to be modulated by the PWM signal. With all output control located in a single register all PWM outputs may be modified with a single register write. 19.2. Programming Model

19.2.1. Summary of PWM Registers Table 19-1. Summary of PWM Control Register Offset Type Description +0x00 R/W Master enable and clear register +0x04 R/W Master ouput mode register (MOM) +0x10 R/W PWM0 waveform control register +0x14 R/W PWM0 edge count register A +0x18 R/W PWM0B edge count register B +0x1C R/W PWM0 current counter register +0x20 R/W PWM1 waveform control register +0x24 R/W PWM1 edge count register A +0x28 R/W PWM1 edge count register B +0x2C R/W PWM1 current counter register +0x30 R/W PWM2 waveform control register +0x34 R/W PWM2 edge count register A +0x38 R/W PWM2 edge count register B +0x3C R/W PWM2 current counter register 19.2.2. Register Descriptions 19.2.2.1. Master Enable and Clear Control (MECC)

Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000

The Master Enable and Clear Control register provides control over the counting operation of the four PWM channels. The format of the register is shown below.
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Technical Reference Manual Table 19-2. Master Enable and Clear Control Register (Offset==0x00) Bit Name Type Description 31-11 Reserved 10 CLR2 W Load channel 2 prescaler and counter with 0x0000 9 CLR1 W Load channel 1 prescaler and counter with 0x0000 8 CLR0 W Load channel 0 prescaler and counter with 0x0000 7-6 Reserved This bit is used to control the operation of counter 5 CNTEN2 R/W 0 Disabled 1 Enabled This bit is used to control the counting operation of prescaler 2 4 PSCLEN2 R/W 0 Disabled 1 Enabled This bit is used to control the operation of counter 1 3 CNTEN1 R/W 0 Disabled 1 Enabled This bit is used to control the counting operation of prescaler 1 2 PSCLEN1 R/W 0 Disabled 1 Enabled This bit is used to control the operation of counter 0 1 CNTEN0 R/W 0 Disabled 1 Enabled This bit is used to control the counting operation of prescaler 0 0 PSCLEN0 R/W 0 Disabled 1 Enabled 19.2.2.2. Master Output Mode Register (MOM) The Master Output Mode register sets operating mode of all PWM outputs. Bit 31-22 21 20 19 18 17 16 15:12 11:10 Name Reserved CHPENB2 CHPENA2 CHPENB1 CHPENA1 CHPENB0 CHPENA0 Reserved OMDB2 Table 19-3. Type R/W R/W R/W R/W R/W R/W R/W Master Output Mode Register (Offset==0x04) Description Enable chopping of PWMB2 Enable chopping of PWMA2 Enable chopping of PWMB1 Enable chopping of PWMA1 Enable chopping of PWMB0 Enable chopping of PWMA0 Channel 2B output mode: 00 Force a low level 01 PWMB2 10 Negated PWMB2 11 Force a high level Channel 2A output mode: 00 Force a low level 01 PWMA2 10 Negated PWMA2

9:8

OMDA2

R/W

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Technical Reference Manual 11 Force a high level Channel 1B output mode: 00 Force a low level 01 PWMB1 10 Negated PWMB1 11 Force a high level Channel 1A output mode: 00 Force a low level 01 PWMA1 10 Negated PWMA1 11 Force a high level Channel 0B output mode 00 Force a low level 01 PWMB0 10 Negated PWMB0 11 Force a high level Channel 0A output mode 00 Force a low level 01 PWMA0 10 Negated PWMA0 11 Force a high level

7:6

OMDB1

R/W

5:4

OMDA1

R/W

3:2

OMDB0

R/W

1:0

OMDA0

R/W

19.2.2.3. channel 0. Bit 31-26 25:16 15:0

PWM0 Waveform Control Register

This register is used control period of PWM0. It specifies the prescaler and the period values for the

Table 19-4. PWM0 Waveform Control Register (Offset==0x10) Name Type Description Reserved Specifies the prescaler divider value for channel 0. The prescaler PSCLPRD0 R/W output frequency is set by PCLKfreq/(PSCLPRD0+1). A minmum value of 1 is required. Specifies the period of the PWM output for channel 0. The PWM base PWMPRD0 R/W frequency is defined by PSCLRfreq/(PWMPRD0+1) PWM0 Edge Count Register A

19.2.2.4.

The register is used to specify the high and low time of the PWM0 output signal A. Bit 32:16 15:0 Table 19-5. PWM0 Edge Count Register A (Offset==0x14) Name Type Description Specifies the maximum count value with the PWM0A ouput is high. The PWM0A output will only be high if the PWM count value is less FALLCNT0A R/W than FALLCNT0A. Note: if FALLCNT0A must be greater than RISECNT0A in order for the PWM0A output to go high. RISECNT0A R/W Specifies the initial minimum count where the PWM0A output remains

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Technical Reference Manual low. The PWM0A output will go high when the PWM counter is greater than or equal to RISECNT0A and less than FALLCNT0A. 19.2.2.5. PWM0 Edge Count Register B

The register is used to specify the high and low time of the PWM0 output signal B. Bit 32:16 Name Table 19-6. Type R/W PWM0 Edge Count Register B (Offset==0x18) Description Specifies the maximum count value with the PWM0B ouput is high. The PWM0B output will only be high if the PWM count value is less than FALLCNT0B. Note: if FALLCNT0B must be greater than RISECNT0B in order for the PWM0B output to go high. Specifies the initial minimum count where the PWM0B output remains low. The PWM0B output will go high when the PWM counter is greater than or equal to RISECNT0B and less than FALLCNT0B.

FALLCNT0B

15:0

RISECNT0B

R/W

19.2.2.6.

PWM0 Current Count Register

This register indicates the current values of the Prescaler and PWM counter of the channel 0. Bit 31-26 25:16 15:0 Table 19-7. Name Type Reserved PSCLCNT0 R/W PWMCNT0 R/W PWM0 Current Count Register (Offset==0x1C) Description The prescaler current count value PWM current count value

19.2.2.7. PWM1 Waveform Control Register This register is used control period of PWM1 channel. It specifies the prescaler and period values for the channel 1. Bit 31-26 25:16 15:0 Table 19-8. PWM1 Waveform Control Register (Offset==0x20) Name Type Description Reserved Specifies the prescaler divider value for channel 1. The prescaler PSCLPRD1 R/W output frequency is set by PCLKfreq/(PSCLPRD1+1). A minmum value of 1 is required. Specifies the period of the PWM output for channel 1. The PWM base PWMPRD1 R/W frequency is defined by PSCLRfreq/(PWMPRD1+1)

19.2.2.8. PWM1 Edge Count Register A The register is used to specify the high and low time of the PWM1 output signal A Bit 32:16 Name Table 19-9. Type R/W PWM1 Edge Count Register A (Offset==0x24) Description Specifies the maximum count value with the PWM1A ouput is high. The PWM1A output will only be high if the PWM count value is less than FALLCNT1A.

FALLCNT1A

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Technical Reference Manual Note: if FALLCNT1A must be greater than RISECNT1A in order for the PWM1A output to go high. Specifies the initial minimum count where the PWM1A output remains low. The PWM1A output will go high when the PWM counter is greater than or equal to RISECNT1A and less than FALLCNT1A.

15:0

RISECNT1A

R/W

19.2.2.9. PWM1 Edge Count Register B The register is used to specify the high and low time of the PWM1 output signal B Bit 32:16 Table 19-10. PWM1 Edge Count Register B (Offset==0x28) Name Type Description Specifies the maximum count value with the PWM1B ouput is high. The PWM1B output will only be high if the PWM count value is less FALLCNT1B R/W than FALLCNT1B. Note: if FALLCNT1B must be greater than RISECNT1B in order for the PWM1B output to go high. Specifies the initial minimum count where the PWM1B output remains RISECNT1B R/W low. The PWM1B output will go high when the PWM counter is greater than or equal to RISECNT1B and less than FALLCNT1B. PWM1 Current Count Register

15:0

19.2.2.10.

This register indicates the current values of the Prescaler and PWM counter of the channel 1. Bit 31-26 25:16 15:0 Table 19-11. Name Type Reserved PSCLCNT1 R/W PWMCNT1 R/W PWM1 Current Count Register (Offset==0x2C) Description The prescaler current count value PWM current count value

19.2.2.11. channel 2. Bit 31-26 25:16 15:0

PWM2 Waveform Control Register

This register is used control period of PWM1 channel. It specifies the prescaler and period values for the

Table 19-12. PWM2 Waveform Control Register (Offset==0x30) Name Type Description Reserved Specifies the prescaler divider value for channel 2. The prescaler PSCLPRD2 R/W output frequency is set by PCLKfreq/(PSCLPRD2+1). A minmum value of 1 is required. Specifies the period of the PWM output for channel 2. The PWM base PWMPRD2 R/W frequency is defined by PSCLRfreq/(PWMPRD2+1) PWM2 Edge Count Register A

19.2.2.12.

The register is used to specify the high and low time of the PWM2 output signal A Bit 32:16 Table 19-13. PM2 Edge Count Register A (Offset==0x34) Name Type Description Specifies the maximum count value with the PWM2A ouput is high. FALLCNT2A R/W The PWM2A output will only be high if the PWM count value is less
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Technical Reference Manual than FALLCNT2A. Note: if FALLCNT2A must be greater than RISECNT2A in order for the PWM2A output to go high. Specifies the initial minimum count where the PWM2A output remains low. The PWM2A output will go high when the PWM counter is greater than or equal to RISECNT2A and less than FALLCNT2A.

15:0

RISECNT2A

R/W

19.2.2.13.

PWM2 Edge Count Register B

The register is used to specify the high and low time of the PWM2 output signal B Bit 32:16 Table 19-14. PWM2 Edge Count Register B (Offset==0x38) Name Type Description Specifies the maximum count value with the PWM2B ouput is high. The PWM2B output will only be high if the PWM count value is less FALLCNT2B R/W than FALLCNT2B. Note: if FALLCNT2B must be greater than RISECNT2B in order for the PWM2B output to go high. Specifies the initial minimum count where the PWM2B output remains RISECNT2B R/W low. The PWM2B output will go high when the PWM counter is greater than or equal to RISECNT2B and less than FALLCNT2B. PWM2 Current Count Register

15:0

19.2.2.14.

This register indicates the current values of the Prescaler and PWM counter of the channel 2. Bit 31-26 25:16 15:0 19.3. Table 19-15. Name Type Reserved PSCLCNT2 R/W PWMCNT2 R/W PWM2 Current Count Register (Offset==0x3C) Description The prescaler current count value PWM current count value

Pulse Width Modulator Output Signal Examples

The following figures illustrates the basic pulse width waveform and chopping waveform respectively

Figure 19-3. Basic Pulse Width Waveform

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PWM0,1,2A Disabled Chop PWM0,1,2B Disabled Chop chopCLK (PWM3) PWM0,1,2A Enabled Chop PWM0,1,2B Enabled Chop

Figure 19-4. Basic Chop Pulse Width Waveform

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20.
20.1.
2

I2C Bus Interface Controller

General Descriptions

The I C is a two-wire bidirectional serial bus that provides a simple and efficient method of data exchange while minimizing the interconnection between devices. The I2C bus interface controller allows the host processor to serve as a master or slave residing on the I2C bus. Data are transmitted to and received from the I2C bus via a buffered interface. It supports the following features: Input clock of 66 MHz(PCLK) Stand, and fast modes through programming the clock divided register 7-bit, 10-bit and general call addressing modes Glitch suppression throughout the de-bounce circuits Programmable slave address Master-transmit, Master-receive, Slave-transmit and Slave-receive modes Slave mode general call address detection Multi-master mode

Figure below shows the block diagram of Faradays I2C bus interface controller.

Figure 20-1. Block Diagram of I2C Controller The main building blocks of the I2C bus interface controller include Register Files, Control Logic, SCLout Generator, and De-bounce Circuit. The following sections contain detailed descriptions of each block.

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Technical Reference Manual 20.2. Register Files

The Register Files, which contain Control Register, Slave Address Register, Clock Divider, Status, Data, Setup / Hold Time & Glitch Suppression and Bus Monitor Registers, are read / write or read-only or read / clear from the host processor throughout the APB 2.0 bus protocol. 20.3. bus. 20.4. SCLout Generator Control Logic

The control logic, which detects the SCLin and SDAin residing on the I2C bus, decides the status on the

The SCLout generator, which accepts the APB bus clock (PCLK) and divides the value in the clock divider register, multiplies 2 to generate the SCLout on the I2C bus. 20.5. De-Bounce Circuit

The de-bounce circuit is used as glitch suppression logic. Glitches are suppressed according to GSR * internal bus clock period, where GSR is bits 10 ~ 12 of the register TGSR at offset 0x14. 20.6. Programming Model

20.6.1. Summary of I2C Controller Registers The following registers are associated with the I2C Bus Interface Controller. They are all allocated within the peripheral memory-mapped address of the host processor. Address (Offset) +0x00 +0x04 +0x08 +0x0C +0x10 +0x14 +0x18 Table 20-1. Summary of I2C Controller Register Type Description R/W I2C Control Register (CR) RO/RC I2C Status Register (SR) R/W I2C Clock Divided Register (CDR) R/W I2C Data Register (DR) R/W I2C Slave Address Register (SAR) I2C Setup / Hold Time & Glitch Suppression Setting R/W Register (TGSR) RO I2C Bus Monitor Register (BMR) Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x00000_0401 0x00000_0003

20.6.2. Register Descriptions The following sections describe details of the I2C controller register. 20.6.2.1. I2C Control Register (offset == 0x00) The host processor uses the Control Register (CR) to control the I2C interface controller to transmit and receive data from I2C bus. Table 20-2.
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Technical Reference Manual Bit 31-18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20.6.2.2. Name Test_bit SD_LOW SCL_LOW STARTI_EN ALI_EN SAMI_EN STOPI_EN BERRI_EN DRI_EN DTI_EN TB_EN ACK / NACK STOP START GC_EN SCL_EN I2C_EN I2C_RST Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Special test mode, which must be set to 0. If set, the SDAout will be tied to 0. For special case, it is suggested to set this bit to 0. If set, the SCLout will be tied to 0. For special case, it suggested to set thisbit to 0. If set, this bit enables I2C controller to interrupt the host processor when I2C controller detects a Start condition happening on the I2C bus. If set, this bit enables I2C controller to interrupt the host processor when I2C controller loses arbitration in master mode. If set, this bit enables I2C controller to interrupt the host processor when I2C controller detects a slave address which matches the SAR register or a general call address (when GC_EB is set). If set, this bit enables I2C controller to interrupt the host processor when I2C controller detects a stop condition happening on the I2C bus in slave mode. If set, this bit enables I2C controller to interrupt the host processor when I2C controller detects non-ACK responses from slave device after one byte of data has been sent in master mode. If set, this bit enables I2C controller to interrupt the host processor when I2C controller DR register has received one data byte from the I2C bus. If set, this bit enables I2C controller to interrupt the host processor when I2C controller DR register has transmitted one data byte onto the I2C bus. When Transfer Byte Enable (TB_EN) is set, I2C controller is ready to receive or transmit one byte. Otherwise, I2C controller will insert wait state by pulling SCLout low on I2C bus. The acknowledge signal is sent by I2C controller when I2C controller is in master-receive or slave-receive mode, 0: ACK, 1: NACK. I2C controller initiates a stop condition after transferring the next data byte on the I2C bus when I2C is in master mode. I2C controller initiates a start condition when I2C bus is idle, or initiates a repeated start condition after transferring the next data byte on the I2C bus in master mode. Enables I2C controller to respond to a general call message as a slave. Enables I2C controller clock output for master mode operation. Enables the I2C bus interface controller. Resets the I2C controller. This bit will automatically be cleared after two PCLK clocks.

I2C Status Register (Offset == 0x04)

The I2C interrupts are signaled through the pin I2C_INT. The I2C_INT is set when the interrupt enable bit is set in the control register (CR), and the interrupt condition meets, which means that the corresponding status register will be set. When the I2C controller interrupt is asserted, software reads the SR bits to check the status of the I2C controller. The SR is also used to clear interrupts signaled by reading the status

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Technical Reference Manual register, including: Bit 31-12 11 10 9 8 7 6 5 4 3 2 1 0 20.6.2.3. DR receive data completely DR transmit data completely Slave address detected Bus error detected Stop condition detected Arbitration loss detected Name START AL GC SAM STOP BERR DR DT BB I2CB ACK RW Type RC RC RC RC RC RC RC RC RO RO RO RO Table 20-3. I2C Status Register Description Reserved Set when I2C controller detects a Start condition on the I2C bus. Set when I2C controller loses arbitration when operating in master mode. Set when I2C controller receives a slave address which matches the general call address, when I2C controller operates in slave mode. Set when I2C controller receives a slave address which matches the address in the slave register (SAR) when I2C controller operates in slave mode. Set when I2C controller detects a stop condition on the I2C bus when I2C controller operates in slave mode. Set when I2C controller detects non-ACK responses from the slave device after one byte of data has been transmitted when I2C controller operates in master mode. Set when the data register (DR) has received one new data byte from the I2C bus. Set when the data register (DR) has transmitted one data byte onto the I2C bus. Set when the I2C bus is busy, but the I2C controller is not involved in the transaction. Set when the I2C controller is busy, i.e. during the time period between the first START and STOP. Set when the I2C controller receives or sends non-acknowledges. Set when the I2C controller serves in a master-receive or slavetransmit mode.

I2C Clock Divider Register (Offset == 0x08)

The I2C clock divider register (CDR) defines the divider value used to generate the I2C SCL clock. This register is used with an internal 10-bit counter. When the SCL enable bit in the control register is set, this counter decreases from the programmable value to zero, and then reloads the programmable value and decreases again. Each time the counter reaches zero, the SCL line transaction starts from high to low or vice versa, depending on the current state. This register can be programmed to select the transfer speed

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Technical Reference Manual needed on the I2C bus. Bit 31-10 9-0 Name COUNT Table 20-4. I2C Clock Divider Register Type Description Reserved The counter value is used to generate an I2C clock (SCLout) from the internal bus clock PCLK. The relation between PCLK and I2C bus R/W clock (SCLout) is: SCLout = PCLK / 2 * (COUNT GSR + 1).

20.6.2.4.

I2C Data Register (Offset == 0x0C)

The host processor to transmit and receive data from the I2C bus uses the I2C Data register (DR). The DR is accessed by the host processor on one hand and by the I2C controller shift register (SHR) on the other hand. Data coming into the I2C bus interface are received into the DR register after a full data byte has been received. Data going out of the I2C bus interface are written into the DR register by the host processor and sent to the serial bus. When the I2C controller is in transmission mode, the host processor writes data into the DR register over the APB bus. This occurs when a master transition is initiated or when a data transmit interrupt is signaled. Data are moved from the DR register to the SHR register when the Transfer Byte Enable (TB_EN) in the control register is set. The data transmit interrupt is signaled when one byte of data has been transferred on the I2C bus. If DR is not written by the host processor before the next byte package, the I2C controller inserts wait state until the host processor writes to the DR and sets the Transfer Byte Enable bit. When the I2C controller serves in a received mode, the processor reads DR register data over the APB bus, and this occurs when DR received interrupt is signaled. The I2C controller automatically inserts wait state until the DR has been read by the host processor, and the ACK / NACK control bit is written and the Transfer Byte bit is cleared. Users must set the Transfer Byte bit again for the next byte transfer on the I2C bus. Bit 31-8 7-0 Name DR Type R/W Table 20-5. I2C Data Register Description Reserved Buffer for I2C bus data transmission and reception

20.6.2.5.

I2C Slave Address Register (Offset == 0x10)

The I2C slave address register defines the I2C controller 10-bit slave address or 7-bit address to which the processor responds when I2C controller operates in slave mode. The host processor writes this register before enabling I2C operation. The register is fully programmable so it can be set to a value other than the fixed slave peripheral address that might exist in the system.

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Technical Reference Manual Table 20-6. I2C Slave Address Register Type Description R/W 10-bit addressing mode enable bit Reserved The most significant 3-bit address to which the I2C controller responds when I2C operates in 10-bit addressing slave mode (EN10 R/W =1). When EN10 = 0, the I2C controller ignores these 3 bits. The 7-bit address to which the I2C controller responds when the I2C operates in 7-bit addresssing slave mode (EN10 = 0) or the least R/W significant 7-bit address to which the I2C controller responds when the I2C operates in 10-bit addressing slave mode.

Bit 31 30-10 9-7

Name EN10 SAR

6-0

SAR

20.6.2.6.

I2C Set / Hold Time & Glitch Suppression Setting Register (Offset == 0x14)

The I2C Set / Hold Time & Glitch Suppression Setting Register (TGSR [9:0]) defines the values of PCLK clock cycles. After the SCL bus goes low, the data will be sent into the SDA bus when I2C controller serves as a transmitter, or the acknowledge will be sent into the SDA bus when I2C controller serves as a receiver. The I2C Set / Hold Time & Glitch Suppression Setting Register (TGSR [12:10]) defines the values of PCLK clock period that the I2C Bus Interface has built-in glitch suppression logic. Glitches are suppressed according to TGSR [12:10]* PCLK clock period. For example, with a 66 MHz (15ns period) PCLK clock, and TGSR [12:10] = 3b100, glitches of 60ns or less are suppressed. With a 40 MHz (25ns period) clock, and TGSR [12:10] = 2b010, glitches of 50ns or less would be suppressed. This is within the 50 ns glitch suppression specification. One limitation is: CDR > 3 + GSR + TSR. Bit 31-2 12-10 9-0 Table 20-7. I2C Set / Hold Time & Glitch Suppression Setting Register. Name Type Description Reserved These bits define the values of PCLK clock period that the I2C Bus GSR R/W Interface has built-in glitch suppression logic. Glitch is suppressed according to: GSR * PCLK clock period. These bits define the values of PCLK clock cycles after I2C SCL bus TSR R/W goes low, the data and acknowledge will drive into the I2C SDA bus.

20.6.2.7.

Figure 20-2. Relationship among TSR SCL, and SDA I2C Bus Monitor Register (Offset == 0x18)

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Technical Reference Manual Table 20-8. I2C Bus Monitor Register Type Description Reserved RO This bit continuously reflects the value of the SCLin pin. RO This bit continuously reflects the value of the SDAin pin.

Bit 31-2 1 0 20.7.

Name SCLin SDAin

Programming Sequence

20.7.1. Slave Mode Data Write Programming Sequence

1.
2. 3. 4. 5.

Write SAR: Set slave address. Write CR: Enable all interrupts and I2C enable, and disable SCL enable. Wait for slave address match interrupt Read SR: SAM (1), I2CB (1), RW (1), ACK (0). Write DR: Load data byte to DR for transfer. Write CR: Set Transfer Byte Enable. Wait for data transmit interrupt Read SR: DT (1), ACK (1 or 0), RW (1), STOP (1 or 0). If ACK or STOP is set, go to initial step. If ACK and STOP are not set, go to step 4 to load the second data byte.

Note: If STOP interrupt occurs, go to initial step. 20.7.2. Slave Mode Data Read Programming Sequence 1. 2. 3. 4. 5. 6. Write SAR: Set slave address. Write CR: Enable all interrupts and I2C enable, and disable SCL enable. Wait for slave address match interrupt Read SR: SAM (1), I2CB (1), RW (0), ACK (0). Write CR: Set Transfer Byte Enable or NACK (CR [6], if the last data byte is sent). Wait for data receive interrupt Read SR: DR (1), ACK (0 or 1), STOP (1 or 0). Read DR: To obtain data. If STOP is set, go to initial step. If STOP is not set, go to step 4 to obtain the next data. Note: If STOP interrupt occurs, go to initial step. 20.7.3. Master Mode Data Write Programming Sequence

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1. 2. 3. 4. 5.

Write CDR: Set clock count. Write DR: Target slave address and RW bit for slave. Write CR: Enable all interrupts, set SCL enable, set I2C enable, set START bit, clear STOP bit and set transfer byte enable. Wait for data transmit interrupt Read SR: DT(1), ACK(0), RW(0), AL(0). (a). If the master wants to stop after one byte of data has been transferred: Write DR: First data will be sent. Write CR: Clear START bit, set STOP bit, and set transfer byte bit. Go to initial step. (b). If the master wants to send second data byte transfer after the first data byte transfer: Write DR: First data will be sent. Write CR: Clear START bit, clear STOP bit, and set transfer byte bit. Go to step 5 or 6.

6.

If the master want to send data byte transfer on the same slave or other slave (i.e. restart): GO to step 2.

20.7.4. Master Mode Data Read Programming Guide 1. 2. 3. 4. 5. Write CDR: Set clock count. Write DR: Target slave address and RW bit for slave. Write CR: Enable all interrupts, set SCL enable, set I2C enable, set START bit, clear STOP bit, and set transfer byte enable. Wait for data transmit interrupt Read SR: DR (1), ACK (0), RW (1), AL (0). (a). If the master wants to stop after one byte of data has been received: Writ CR: Clear START bit, set STOP bit, set NACK bit, and set transfer byte enable. Wait for data receive interrupt Read SR: DR(1), ACK(1), RW(1). Read DR: To obtain data. Go to initial step. (b). If the master wants to receive second data byte transfer after the first data byte transfer: Write CR: Clear START bit, clear STOP bit, and set transfer byte bit. Wait for data receive interrupt Read SR:

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Technical Reference Manual DR(1), ACK(0) , RW(1). Read DR: To obtain data. Go to step 5 or 6. 6. If the master wants to receive data byte transfer on the same slave or other slave (i.e. restart): Go to step 2.

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21. Watch Dog Timer (WDT)

21.1. General Descriptions The WDT is used to prevent system from infinite looping if the software becomes trapped in deadlock. In normal operation, the user restarts the WDT at regular intervals before the counter counts down to zero. The WDT generates one or a combination of the following signals: reset, interrupt or external interrupt. It supports the following features:

While timeout, outputs are one or a combination of: System Reset / System Interrupt / External Interrupt 32-bit down counter Clock source selection Internal PCLK clock An external clock source of XIN/16 can be applied at the EXTCLK

Variable time-out period of reset Access protection via password and under the executive mode.

The figure below illustrates the simplified block diagram of WDT

EXTCLK PCLK PRSTn psel penable pwrite paddr pwdata prdata APB Interface Watch Dog Timer Counter Watch Dog Comparison wd_rst wd_intr wd_ext Watch Dog Timer Registers Control registers

Figure 21-1. Block Diagram of Watch Dog Timer When reset, WDT registers are set to the reset values. After the programmer turns on the WDT enable bit in the WDT control register, the WDT counter starts to decrease. If the WDT counter reaches zero, the WdStatus bit will be set to 1, indicating watchdog time-out. The status will be cleared by writing 1 to the WdClear bit. Once a time-out has occurred, the WDT will assert the wd_rst, wd_intr or wd_ext signal, depending on the state of the WdRst, WdIntr or WdExt bit in the WdCR register. The pulse width depends
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Technical Reference Manual on the setting value of the WdIntrCter register. To prevent unexpected watchdog reset, the programmer should write 0x5AB9 to the WdRestart register as the password to activate down counting. If the WdRestart register equals 0x5AB9, the value of the WdLoad register will be loaded into the WDT counter. The default reset value of the WdRestart register is zero. The WdRestart register automatically returns to zero after each write. The default value of the WdLoad is set to 0x3EF1480, the programmer can write this register to customize the operation of WDT reset. 21.2. Programming Model

21.2.1. Summary of WDT Registers Table below is a summary of the Watch Dog Timer programming registers. Offset Type +0x00 R +0x04 R/W Width 32 32 Table 21-1. Summary of WDT Registers Reset Value Name Config Description 0x3EF1480 WdCounter None Watch Dog Timer Counter Register Watch Dog Timer Counter Auto Reload Register 0x3EF1480 WdLoad None The auto reload register is default set to 0x3EF1480. Watch Dog Timer Counter Restart Register When writing 0x5AB9 to this register, 0x0000 WdRestart None Watch Dog Timer will automatically reload WdLoad to WDcounter and restart counting. 0x0 WdCR None Watch Dog Timer Control Register Watch Dog Timer Status This bit is set when the counter reaches zero. 0x0 WdStatus None 0: Watch Dog Timer does not reach zero 1: Watch Dog Timer reachs zero Watch Dog Timer Clear 0x0 WdClear None Writing one to this register will clear the WdStatus. Watch Dog Timer Interrupt Length This register controls the length of 0xFF WdIntrCter None wd_rst, wd_intr and wd_ext. The default value is 0xFF.

+0x08

16

+0x0C R/W

+0x10

+0x14

+0x18

R/W

21.2.2. Register Descriptions The following sections describe the WDT registers in greater detail. 21.2.2.1. WdCounter (Offset == 0x00)

The WdCounter contains the current counter value. When reset, the WdCounter register is set to

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Technical Reference Manual 0x3EF1480. After the programmer writes to WdRestart with 0x5AB9, the value of the WdLoad will be loaded into the WdCounter. The WdCounter starts to decrease once the WdEnable bit of the WdCR register is set. If the Watch Dog timer is disabled, the WdCounter will hold the value. If the WdClock bit of the WdCR register is set, the clock source is from an external clock and the WdCounter will decrease at EXTCLK frequency. This register is read-only. Table 21-2. Bit Name Type 32 WdCounter Read only 21.2.2.2. WdLoad (Offset == 0x04) WdCounter Register Comment None

The WdLoad contains a value which will be loaded into WdCounter. Upon reset or restart, the WdLoad value will be automatically loaded into the WdCounter register. The reset value of the WdLoad is 0x3EF1480. Bit 32 21.2.2.3. Name WdLoad Table 21-3. Type Read/Write WdLoad Register Comment None

WdRestart (Offset == 0x08)

The WdRestart is used to avoid unexpected counting. If the programmer writes 0x5AB9 to this register, the Watch Dog timer counter will load WdLoad into the WdCounter register and the WD will restart to decrease. After finishing write cycle, The WdRestart will automatically reset to zero. Table 21-4. WdRestart Register Bits Name Type Comment 16 WdRestart Write None 21.2.2.4. WdCR (Offset == 0x0C) The WdCR is Watch Dog timer control register. It defines enable, reset, interrupt, external enable and clock source bits. Bit 0 1 2 3 Name WdEnable WdRst WdIntr WdExt Table 21-5. WdCR Register Reset Comment Watch Dog Timer Enable Bit 0x0 0: Disable 1: Enable Watch Dog Timer System Reset Enable Bit 0x0 0: Disable 1: Enable Watch Dog Timer System Interrupt Enable Bit 0x0 0: Disable 1: Enable Watch Dog Timer External Signal Enable Bit 0x0 0: Disable
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WdStatus (Offset == 0x10)

The WdStatus register records if the Watch Dog Timer reaches zero or not. It is a read-only register. Bit 1 21.2.2.6. Name WdStatus Table 21-6. Type Read WdStatus Register Comment None

WdClear (Offset == 0x14)

When writing one to this register, the WdStatus will be cleared. Bit 1 21.2.2.7. Name WdClear Table 21-7. Type Write WdClear Register Comment None

WdIntrCter (Offset == 0x18)

The WdIntrCter register decides the asserting duration of wd_rst, wd_intr, and wd_ext signals. The default value is 0xFF. It means the default durations of wd_rst, wd_intr, and wd_ext assertion are 256 clock cycles. Bits 16 21.3. Name WdIntrCter Timing Table 21-8. WdIntrCter Register Type Comment Read / Write None

21.3.1. Write to WdLoad Register

PADDR PWRITE PSEL PENABLE PWDATA WdLoad
WdLoad Address

DATA1 DATA1

Figure 21-2. Write to WdLoad Register 21.4. Write to WdLoad Register

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PCLK counter W dLoad wd_intr W dClear

21.5.

0 0xAA

0xAA

0xA9

Figure 21-3. Watch Dog Timer Interrupt Programming Sequence

To enable the WDT, the programmer needs to set the WdLoad first. The WdLoad decides the period of Watch Dog Timer reset. The default value of the WdLoad is 0x3EF1480, which means that in a 66 MHz system, the period of Watch Dog Timer reset is one second. The programmer can change this. For example, setting WdLoad to 0xEC08CE00 makes the period of Watch Dog Timer reset 1 minute, which guarantees the system will be reset in one minute. This can be used to avoid system deadlock. The programmer also needs to write 0x5AB9 to the WdRestart for purpose of protection. Another consideration is clock source. The clock source PCLK cannot be gated when system sleeps, even if the WdCR[WdClock] bit is turned on. The Watch Dog Timer can be driven by external clock. The programmer just needs to write one to the WdCR[WdClock] bit. The relationship between EXTCLK and PCLK should follow the limitation: EXTCLK cycle time / PCLK cycle time > 1. If the system does not need the external clock, just keep WdCR[WdClock] bit in the default value. After setting the WdLoad, the WdRestart and the WdCR[WdClock] bits, the programmer can enable Watch Dog Timer by writing one to the WdCR[WdEnable] bit. After that, Watch Dog Timer will start to count down. The following steps are the summary steps: 1. 2. 3. 4. 5. Disable Watch Dog Timer. Set WdLoad register. Write 0x5AB9 to WdRestart register. Set WdCR[Clock] bit. Enable Watch Dog.

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22. Timer/Counters
22.1. Overview The aJ-200 includes three general purposed 24-bit timer/counters (GPTC). The GPTC can perform a wide range of timing functions. The Timer/counter function includes frequency measurement, event counting, interval measurement, delay timing, and pulse width modulation. The main features of the general purpose timer/counter are: Three 24-bit timer/counters 16-bit prescaler Internal chaining of timers Two pulse width modulation and wave-form modules Flexible interrupt generation

The timer/counters comprise a 16-bit prescalar and three 24bit general purpose timer/counter (T/C) blocks as shown in figure 151. Two clock sources are provided as timing sources for the prescalar block, the internal peripheral clock (PCLK) and an external clock (TCLK0). Selection of the prescalar clock source is via the PSMODE field of the input/output mode configuration register (GPTC_IOMR). The prescalar divides the selected input clock by PRL+1, where 0 PRL 16,777,215. The three timers may use the prescalar clock output or the external clock source. Flexible control timer/counter operation is provided via the timer inputs and internal signals. This flexibility includes a variety of means for timer/counter triggering, reloading, gating, and stopping.

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Internal Clock

16-bit Prescaler

PSCL_TO

TIOA0

GPTC0_INT GPTC0_TO

GPTC_INT

TIOB0

24-bit General Timer/Counter0

TCK0
GPTC1_INT GPTC1_TO GPTC1_PWM

TIOA1 I/O Select & Control

TIOB1 TCK1

24-bit General Timer/Counter& Waveform1

APB Bus Interface

Timer/ Counter Control Registers

GPTC2_INT GPTC2_TO GPTC2_PWM

TIOA2

TIOB2 TCK2

24-bit General Timer/Counter& Waveform2

Figure 22-1. Top Level Block Diagram of Timer/Counters 22.2. Timer Input/Output Block The I/O block is provides selection of the timer clocks, timer control, and timer outputs. The Input/Output mode configuration register (GPTC_IOMR) is used to control the I/O block. The active sense (high or low) of the I/O pins is controlled via the Input/Output polarity register (GPTC_IOPR). The individual timer clocks are selected with the timer clock input source field (TCKS) of the GPTC_IOMR. Each timer block may select the prescaler output or the external clock (TCK[2:0]) as the clock source. When the external clock source is used its sense may be inverted via the CLKPOL field of the GPTC_IOPR. In this case the timers will count on the falling edge of the clock input.
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Technical Reference Manual The aJ-200 provides two pins (TIOAx and TIOBx) for each timer/counter to be used as control inputs or timing waveform outputs. The function of these I/O pins is via the TxBOSEL and TxAOSEL fields in the I/O mode register (GPTC_IOMR). The pins may be configured as an input by setting the appropriate field to 00. A variety of internal timing sources may be used to drive the pins when configured as an output. For example TIOA1 may be driven with the output of timer 1, the output of timer 1 divided by 2 (square wave), or the output of the Pulse Width Modulator 1 (PWM1). The TIOAPOL and TIOBPOL fields of the GPTC_IOPR may be used to invert the sense of the I/O signals. The timer/counter block uses two control inputs, TC2 and TC1, to perform various control operations. The I/O block selects the source for these control signals via the source select fields (TxCS1 and TxCS2) fields in the GPTC_IOMR register. Options are available to control the timers via external signals or other internal timing sources. Internal source are provided to allow two or three of the timers to be chained together to make a larger timer (up to 72 bits).

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Figure 22-2. General Purpose Timer/Counter Block Diagram 22.3. General Purpose Timer/Counter Register Summary Table below lists the addresses and bit widths of all registers in the general purpose timer/counter block. All registers are set to 0 by reset.
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Technical Reference Manual Table 22-1. Timer/Counter Register Summary Offset Type Width Name Description +0x00 R/W 10 GPTC-GMR GPTC Global mode register +0x04 R/W 29 GPTC_IOPR GPTC Input/Output mode register +0x08 R/W 9 GPTTC_IOMR GPTC Input/Output polarity register +0x0C R/W 17 GPTC_GTR GPTC Global Trigger register +0x10 R/W 5 GPTC_ISR GPTC Interrupt Status register +0x14 R/W 16 GPTC_PRR GPTC Presecaler Reload Register Timer/Counter 0 Registers +0x18 R/W 20 GPTC0_MR GPTC0 Mode register +0x1C R/W 24 GPTC0_RLR GPTC0 Reload register +0x20 R/W 24 GPTC0_CTR GPTC0 Current Time register +0x24 R/W 24 GPTC0_SVR GPTC0 Sample Value register +0x28 R/W 7 GPTC0_STICR GPTC0 Status/Interrupt Clear register Timer/Counter 1 Registers +0x2C R/W 20 GPTC1_MR GPTC1 Mode register +0x30 R/W 24 GPTC1_RLR GPTC1 Reload register +0x34 R/W 24 GPTC1_CTR GPTC1 Current Time register +0x38 R/W 24 GPTC1_SVR GPTC1 Sample Value register +0x3C R/W 7 GPTC1_STICR GPTC1 Status/Interrupt Clear register Timer/Counter 2 Registers +0x40 R/W 20 GPTC2_MR GPTC2 Mode register +0x44 R/W 24 GPTC2_RLR GPTC2 Reload register +0x48 R/W 24 GPTC2_CTR GPTC2 Current Time register +0x4C R/W 24 GPTC2_SVR GPTC2 Sample Value register +0x50 R/W 7 GPTC2_STICR GPTC2 Status/Interrupt Clear register Waveform Module 1 Registers +0x54 R/W 5 WF1_MR WF1 Mode register +0x58 R/W 11 WF1_STR WF1 Status register +0x5C R/W 28 WF1_RDP WF1 FIFO Read port +0x60 R/W 24 WF1_WRP WF1 FIFO Write port +0x64 R/W 2 WF1_CP WF1 FIFO Clear port Waveform Module 2 Registers +0x68 R/W 5 WF2_MR WF2 Mode register +0x6C R/W 11 WF2_STR WF2 Status register +0x70 R/W 28 WF2_RDP WF2 FIFO Read port +0x74 R/W 24 WF2_WRP WF2 FIFO Write port +0x78 R/W 2 WF2_CP WF2 FIFO Clear port +0x7C R/W 5 WF2_MR WF2 Mode register

Notes

Write only Read only

Read only

Read only

Read only

Read only Write only Write only

Read only Write only Write only

22.3.1. Global Mode Register The global mode register (GPTC_GMR) contains enables for the three timer/counters, the prescaler, and the waveform modules. The grouping of the enables into a single register allows all timer/counters started and stopped simultaneously. The GPTC_GMR contains a master interrupt enable for each timer/counter and waveform blocks. Active and enabled interrupts for the blocks are reflected in the interrupt status register (GPTC_ISR). The timer/counter blocks have a variety of potential interrupt sources. The ability of
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Technical Reference Manual these sources to activate the interrupt for the block is controlled via the mode registers for the block (GPTCx_MR). The active and enabled interrupt conditions for a timer/counter are reflected in the status and interrupt clear register (GPTCx_STICR). The tester stop bit in the global mode register allows the timer/counter blocks to suspend operation while the CPU is halted via the test port. The debugger in software development environments may halt the CPU in the case of breakpoints or via a user generated command. Some users may prefer the timers stop while the CPU operation is suspended. Offset: 0x00 Bits 31:11 9:8 Table 22-2. Global Mode Register GPTC Global mode register Field Names Description Unused WF_IE Waveform module interrupt enables. The individual bits in the WF_IE field enable the ability of the waveform modules to activate the interrupt output of the GPTC block. A set bit, 1, in the WF_IE field enables the corresponding waveform module to generate an interrupt. A clear bit, 0, masks any potential interrupt. Enabled and active wave form interrupts are reflected in the interrupt status register. TC_IE Timer/Counter module interrupt enables. The individual bits in the TC_IE field enable the ability of the timer/counter modules to activate the interrupt output of the GPTC block. A set bit, 1, in the TC_IE field enables the corresponding timer/counter module to generate an interrupt. A clear bit, 0, masks any potential interrupt. Enabled and active timer/counter interrupts are reflected in the interrupt status register. The variety of interrupt conditions of each timer/counter block is controlled via the timer counter mode register (GPTCx_MR). Each timer/counter block status and interrupt clear register (GPTCx_STICR) reflects the active and enabled interrupt conditions. TSTRSTOP Tester stop enable The test enable controls the timer/counter operation while the CPU is halted via the test interface. The interface is typically connected to a software development environment (debugger). 0 Timer/counter and the waveform modules continue to run while CPU is halted 1 Suspend all timers when the CPU is halted. PSCEN Prescaler enable. 0 Count operation of the prescaler is disabled. 1 Count operation of the prescaler is enabled MTEN Master timer enables. The individual bits in the MTEN field control the counting operation of the timer/counter blocks. A clear bit, 0, in the MTEN field inhibits counting operation of the timer/counter. The clear bit also suspends operation of the trigger
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Technical Reference Manual and reload logic associated with the timer/counter. A set bit, 1, allows the timer/counter to operate as specified in the individual mode registers (GPTCx_MR). 22.3.2. Timer/Counter Input/Output Mode Register The timer/counter (T/C) input/output mode register is illustrated below. This register includes fields for selecting a variety of timing configurations. The register selects the clock sources of the timer blocks and the operation of the timer I/O ports (TIOA2..0 and TIOB2..0). Offset: 0x04 Bits 31:29 28:27 Table 22-3. Timer/Counter Input/Output Mode Register GPTC Input/Output mode register Field Names Description Unused T2BOSEL Timer 2 B output select 00 Input mode 01 Timer 2 output 10 Timer 2 output divide by 2 11 PWM 2 output T2AOSEL Timer 2 A output select 00 Input mode 01 Timer 2 output 10 Timer 2 output divide by 2 11 PWM 1 output T1BOSEL Timer 1 B output select 00 Input mode 01 Timer 1 output 10 Timer 1 output divide by 2 11 PWM 2 output T1AOSEL Timer 1 A output select 00 Input mode 01 Timer 1 output 10 Timer 1 output divide by 2 11 Timer 0 output T0BOSEL Timer 0 B output select 00 Input mode 01 Timer 0 output 10 Timer 0 output divide by 2 11 PWM 1 output T0AOSEL Timer 0 A output select 00 Input mode 01 Timer 0 output 10 Timer 0 output divide by 2 11 Timer 2 output T2CS2 Timer 2 control input 2 (also sample input for WF2) 00 TIOA2: input A for T/C 2 01 TIOB2: input B for T/C 2 10 Timer 0 output 11 Timer 1 output AND timer 0 output (for chaining all
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Technical Reference Manual three timers, 48 bits) Timer 2 control input 1 00 TIOA2: input A for T/C 2 01 TIOB2: input B for T/C 2 10 Timer 1 output 11 Timer 1 output AND timer 0 output (for chaining all three timers, 48 bits) Timer 1 control input 2 (also sample input for WF1) 00 TIOA1: input A for T/C 1 01 TIOB1: input B for T/C 1 10 Timer 0 output 11 Timer 2 output Timer 1 control input 1 00 TIOA1: input A for T/C 1 01 TIOB1: input B for T/C 1 10 Timer 0 output 11 Timer 2 output Timer 0 control input 2 00 TIOA0: input A for T/C 0 01 TIOB0: input B for T/C 0 10 Timer 1 output 11 Timer 2 output Timer 0 control input 1 00 TIOA0: input A for T/C 0 01 TIOB0: input B for T/C 0 10 Timer 1 output 11 Timer 2 output Timer Clock Select. Specifies the timer clock sources. A 0 in a bit position of the TCKS field selects the prescaler output as the clock source. A 1 in a bit position selects the external clock (TCKx) as the clock source. Prescaler Mode. Specifies the clock source of the prescaler. 00 Prescaler disabled 01 Internal peripheral clock (peripheral clock is 1/2 the frequency of the CPU clock) 1x External clock source (TCK0).

14:13

T2CS1

12:11

T1CS2

10:9

T1CS1

8:7

T0CS2

6:5

T0CS1

4:2

TCKS

1:0

PSMODE

22.3.3. Timer/Counter Input/Output Polarity Selection Register. The I/O polarity register allows the signal at the TCKx, TIOAx, and TIOBx pins to be inverted from the internal state. The ability to perform such inversions eliminates the need for external logic to perform such an inversion. The I/O polarity register is shown below. The polarity fields are three bits wide. Each bit corresponds to inversion control for the corresponding Timer/Counter (ex: TIOBPOL1 performs an inversion of the TIOB1 pin). Offset: 0x08 Bits Table 22-4. GPTC Input/Output polarity register GPTC Input/Output polarity register Field Names Description

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5:3

TIOAPOL

2:0

CLKPOL

TIOB polarity. Selects the active state of the timer I/O port B. TIOBPOL bit positions with a 0 value indicate the sense of the TIOB pin is inverted with respect to the internal state. A bit value of 1 indicates there is no inversion between the pin and the internal signal. TIOA polarity. Selects the active state of the timer I/O port A. TIOAPOL bit positions with a 0 value indicate the sense of the TIOA pin is inverted with respect to the internal state. A bit value of 1 indicates there is no inversion between the pin and the internal signal. Clock input polarity. Selects the active edge when the timer the TCKS field of the GPTC_IOMR register). CLKPOL bit positions falling edge clock while a 1 represents a rising edge clock.

22.3.4. Global Trigger Register The global trigger register provides software to initiate timer control operations. The register allows the timers to be started, stopped, reloaded, or sampled via the global trigger register. Grouping the control of all three timers and the prescaler allow the triggering functions to be completed simultaneously under software control. The timers may also be configured to do these same operations based on the timer control inputs. Offset: 0x0C Bits 31:15 14 13 Table 22-5. GPTC Global Trigger Register GPTC Global Trigger register Field Names Description Unused RLD_PSC Re-load Prescaler. A write of a 1 to the RLD_PSC bit will cause the prescaler timer to be reloaded with the prescaler reload value (GPTC_PRLR). STOP_PSC Stop prescaler. A write of a 1 to the STOP_PSC bit will clear the prescaler trigger register and suspend the counting operation of the prescaler (STRT_PSC must be 0). STRT_PSC Start prescaler. A write of a 1 to the STRT_PSC bit will set the prescaler trigger register and allow the prescaler to count (assuming the prescaler is enabled, PSCEN=1). SMPL_TC2 Sample timer/counter 2. A write of a 1 to the SMPL_TC2 bit will load the Timer/Counter 2 sample register with the current count. The sample command will also clear the reloads since last sample field (RSLS) of the sample register. RLD_TC2 Re-load timer/counter 2. A write of a 1 to the RLD_TC2 bit will cause the timer/counter 2 to be reloaded with the timer/counter reload value (TC2_RLR). STOP_TC2 Stop timer/counter 2. A write of a 1 to the STOP_TC2 bit will clear the timer/counter 2
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Technical Reference Manual trigger register and suspend the counting operation of timer/counter 2 (STRT_TC2 must be 0). Start timer/counter 2. A write of a 1 to the STRT_TC2 bit will set the timer/counter trigger register and allow the timer/counter to count (assuming the timer/counter is enabled). Sample timer/counter 1. A write of a 1 to the SMPL_TC1 bit will load the Timer/Counter 1 sample register with the current count. The sample command will also clear the reloads since last sample field (RSLS) of the sample register. Re-load timer/counter 1. A write of a 1 to the RLD_TC1 bit will cause the timer/counter 1 to be reloaded with the timer/counter reload value (TC1_RLR). Stop timer/counter 1. A write of a 1 to the STOP_TC1 bit will clear the timer/counter 1 trigger register and suspend the counting operation of timer/counter 1 (STRT_TC1 must be 0). Start timer/counter 1. A write of a 1 to the STRT_TC1 bit will set the timer/counter trigger register and allow the timer/counter to count (assuming the timer/counter is enabled). Sample timer/counter 0. A write of a 1 to the SMPL_TC0 bit will load the Timer/Counter 0 sample register with the current count. The sample command will also clear the reloads since last sample field (RSLS) of the sample register. Re-load timer/counter 0. A write of a 1 to the RLD_TC0 bit will cause the timer/counter 0 to be reloaded with the timer/counter reload value (GPTC0_RLR). Stop timer/counter 0. A write of a 1 to the STOP_TC0 bit will clear the timer/counter 0 trigger register and suspend the counting operation of timer/counter 0 (STRT_TC0 must be 0). Start timer/counter 0. A write of a 1 to the STRT_TC0 bit will set the timer/counter trigger register and allow the timer/counter to count (assuming the timer/counter is enabled).

STRT_TC2

SMPL_TC1

6 5

RLD_TC1 STOP_TC1

4 STRT_TC1 3 SMPL_TC0

2 1

RLD_TC0 STOP_TC0

STRT_TC0

22.3.5. Interrupt Status Register The interrupt status register indicates which of the timer/counter and waveform modules have a pending interrupt condition. The status register of the individual timer/counter blocks may be interrogated to determine the exact cause of the interrupt condition. Offset: 0x10 Bits 31:5
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Table 22-6. GPTC Interrupt Status Register GPTC Interrupt Status register Field Names Description Unused
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Technical Reference Manual 4 WF2_INT Waveform Module 2 interrupt. A set WF2_INT bit indicates the valid depth of the waveform FIFO has reached the desired interrupt condition. The interrupt condition is specified via the INTMD field of the waveform module mode register (WF2_MR). Waveform interrupts are enabled via the WF_IE field of the timer/counter global mode register (GPTC_GMR). Waveform Module 1 interrupt. A set WF1_INT bit indicates the valid depth of the waveform FIFO has reached the desired interrupt condition. The interrupt condition is specified via the INTMD field of the waveform module mode register (WF1_MR). Waveform interrupts are enabled via the WF_IE field of the timer/counter global mode register(GPTC_GMR). Timer/Counter 2 interrupt. A set TC2_INT bit indicates a timer/counter interrupt condition has occurred. The interrupt condition is specified via the TCLRIE, TSETIE, SMPLIE, RLDIE, and TOIE bits of the timer/counter mode register (GPTC2_MR). The exact cause of the timer/counter interrupt is reflected in the timer/counter status and interrupt clear register (GPTC2_STICR). Timer/counter interrupts are enabled via the TC_IE field of the timer/counter global mode register (GPTC_GMR) Timer/Counter 1 interrupt. A set TC1_INT bit indicates a timer/counter interrupt condition has occurred. The interrupt condition is specified via the TCLRIE, TSETIE, SMPLIE, RLDIE, and TOIE bits of the timer/counter mode register (GPTC1_MR). The exact cause of the timer/counter interrupt is reflected in the timer/counter status and interrupt clear register (GPTC1_STICR). Timer/counter interrupts are enabled via the TC_IE field of the timer/counter global mode register (GPTC_GMR). Timer/Counter 0 interrupt. A set TC0_INT bit indicates a timer/counter interrupt condition has occurred. The interrupt condition is specified via the TCLRIE, TSETIE, SMPLIE, RLDIE, and TOIE bits of the timer/counter mode register (GPTC0_MR). The exact cause of the timer/counter interrupt is reflected in the timer/counter status and interrupt clear register (GPTC0_STICR). Timer/counter interrupts are enabled via the TC_IE field of the timer/counter global mode register (GPTC_GMR).

WF1_INT

TC2_INT

TC1_INT

TC0_INT

22.3.6. Prescaler A 16-bit prescalar is provided to divide the input clock source to the desired resolution for the three general purpose timers. This allows the other timers to count at slower rates in order to minimize power consumption and extend the maximum range of the timers

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Figure 22-3. General Purpose Timer/Counter Prescaler The prescalar clock source is selected with the PSMODE field of the input/output mode configuration register (GPTC_IOMR). The prescalar reload register (GPTC_PRLR) is loaded with N-1 in order to divide the selected input clock by N. Offset: 0x14 Bits 31:16 15:0 Prescaler Reload Register Field Names Description Unused WF2_INT Prescaler Reload Value

The prescalar timer is loaded from the reload register. The timer counts down to 0x0000 and activates the prescalar clock output. On the following cycle the prescalar timer is reloaded with the value in the reload register. Enable control of the prescalar is provided with the PSCEN bit of the global mode register (GPTC_GMR). Triggering control is provided via the STRT_PSC and STOP_PSC bits in the timer/counter global trigger register (GPTC_GTR). An explicit start command is not needed to start the prescalar since the prescalar trigger register is set following reset. 22.4.

Timer/Counter Block

The aJ-200 includes three timer/counter modules that may be configured for a variety of timing and counting functions. The basic operation of the timer is illustrated in below figure. The timer is loaded from the reload register and counts down to a value of 0000. When the timer reaches 0x0000 the timer output is activated. On the following cycle the timer is loaded from the reload register, the time out interrupt is generated (TOINT), and the count down process begins anew. There are a number of alternate timer

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Technical Reference Manual operating modes that utilize the timer control inputs, TC1 and TC2. The source of the timer control inputs is specified via the input/output block. The next section discusses the registers of the timer/counter followed by additional information on the timer operation.

Figure 22-4. Timer/Counter Block Diagram

Figure 22-5. Basic Timer/Counter Waveform 22.4.1. Timer/Counter Registers This section describes the registers associated with a timer/counter block. There are three copies of these registers which corresponding to the three timer/counter blocks. 22.4.1.1. Timer/Counter Mode Register The timer/counter mode register specifies the operation of the control inputs (TC1 and TC2) and provides the timer and interrupt enables. The source of the timer control inputs is specified via the input/output block.

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Technical Reference Manual Table 22-7. Timer/Counter (x=0,1,2) Mode Register Timer/Counter (x=0,1,2) Mode Register Field Names Description Unused TCLRIE Trigger Clear Interrupt Enable. Enables the generation of an interrupt when the trigger register is cleared. TCLRIE set to 1 enables the interrupt and a value of 0 disables the interrupt. The interrupt status is reflected in the status and interrupt clear register (GPTCx_STICR). Trigger Set Interrupt Enable. Enables the generation of an interrupt when the trigger register is set. TSETIE set to 1 enables the interrupt and a value of 0 disables the interrupt. The interrupt status is reflected in the status and interrupt clear register (GPTCx_STICR). Sample Timer Interrupt Enable. Enables the generation of an interrupt when a sample condition occurs. SMPLIE set to 1 enables the interrupt and a value of 0 disables the interrupt. The interrupt status is reflected in the status and interrupt clear register (GPTCx_STICR) Reload Timer Interrupt Enable Enables the generation of an interrupt when a reload operation is requested. The normal reload following the timer/counter reaching a value of 0x0000 does not activate a reload interrupt. RLDIE set to 1 enables the interrupt and a value of 0 disables the interrupt. The interrupt status is reflected in the status and interrupt clear register (GPTCx_STICR) Time Out Interrupt Enable Enables the generation of an interrupt when the timer reaches a value of 0x0000. TOIE set to 1 enables the interrupt and a value of 0 disables the interrupt. The interrupt status is reflected in the status and interrupt clear register (GPTCx_STICR). Sample Polarity Specifies the edge (rising/falling) required on the timer control signal to perform the sample operation. The SMPLMD field selects the sample control signal (none, TC1, or TC2). 0 The timer is sampled on the falling edge of the selected timer control signal (TX). 1 The timer is sampled on the rising edge of the selected timer control signal (TX). Sample Mode Specifies the external event that causes the sample register to be loaded with the current timer value. The SMPLPOL bit is used to select which control signal edge is used to capture the sample. Software may also sample the timer via the global trigger register (GPTC_GTR). 0x No external sample. 10 Sample taken on the desired edge of TC1. 11 Sample taken on the desired edge of TC2.

Offset: 0x14 Bits 31:20 19

18

TSETIE

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SMPLIE

16

RLDIE

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TOIE

14

SMPLPOL

13:12

SMPLMD

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Technical Reference Manual 11 RLDPOL Reload Polarity Specifies the edge (rising/falling) required on the timer control signal to perform the timer reload operation. The RLDMD field selects the sample control signal (none, TC1, or TC2). 0 The timer is reloaded on the falling edge of the selected timer control signal (TX). 1 The timer is reloaded on the rising edge of the selected timer control signal (TX). Reload Mod Specifies the external event that causes the timer to be loaded from the reload register. The RLDPOL bit is used to select which control edge is used to trigger the reload operation. Software may also cause a reload operation via the global trigger register (GPTC_GTR). 0x No external reload. 10 Reload initiated by the desired edge of TC1. 11 Reload initiated by the desired edge of TC2. Stop Polarity Specifies the edge (rising/falling) required on the control signal to clear the trigger register. The STOPMD field selects the trigger clear signal (none, TC1, or TC2). 0 The trigger is cleared on the falling edge of the selected timer control signal (TX). 1 The trigger is cleared on the rising edge of the selected timer control signal (TX). Stop Mode Specifies the external event that clears the timers trigger register. Clearing the trigger register will suspend operation of the timer. The STOPPOL bit is used to select which control edge used to clear the trigger. Software may also clear the timer trigger register via the memory mapped global trigger register (GPTC_GTR). The STOPMD field does not affect timer operation if the start mode (STRT_MD) field specifies the trigger register is not used (STRT_MD=00). 0x No external stop. 10 Trigger cleared by the desired edge of TC1. 11 Trigger cleared by the desired edge of TC2. Start Polarity Specifies the edge (rising/falling) required on the control signal to set the trigger register. The STRTMD field selects the trigger set signal (none, TC1, or TC2). 0 The trigger is set on the falling edge of the selected timer control signal (TX). 1 The trigger is set on the rising edge of the selected timer control signal (TX). Start Mode Specifies the external event that sets the timers trigger register. Setting the trigger register will enable operation of the timer. The STRTPOL bit is used to select which control edge used to clear the
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Technical Reference Manual trigger. Software may also set the timer trigger register via the memory mapped global trigger register (GPTC_GTR). Setting the STRTMD field to 00 forces the trigger register set so that the timer enable is dependent on the TCEN field of the global mode register (GPTC_GMR) and the TMREN field in this register (GPTCx_MR) 00 Forces the timer trigger register (stop conditions have no effect) 01 No external trigger set, a stop condition will clear the trigger. 10 Trigger cleared by the desired edge of TC1. 11 Trigger cleared by the desired edge of TC2. External Enable Polarity Specifies the polarity required on the control signal to enable the timer. The TMREN field selects the external enable source (none, TC1, or TC2). 0 The timer is enabled when the selected timer control signal (TX) is low. 1 The timer is enabled when the selected timer control signal (TX) is high (assuming the other enable conditions are satisfied). Timer enable Specifies when the timer is enabled for counting. The enable is further qualified with corresponding master timer enable bit (MTEN) in the global mode register and the trigger register. The trigger register may be forced active by setting the STRTMD field to 00. The TMREN field is decoded as follows: 00 Timer disabled. 01 Enabled when the MTEN and trigger registers are set. 10 Enabled when TC1 is active (see XENPOL) and the MTEN and trigger registers are set. 11 Enabled when TC2 is active (see XENPOL) and the MTEN and trigger registers are set.

XENPOL

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TMREN

22.4.2. Reload Register The reload register value is transferred into the corresponding timer when a reload event occurs. A reload event can be triggered via software, an external pin, or when the timer reaches a 0x0000 value. The RLDMD field in the timer/counter mode register (GPTCx_MR) configures the reload events via the control inputs (TC1 or TC2). The RLDPOL field of the timer/counter mode register specifies the edge on the selected TX input to perform the reload operation. Software may also trigger a reload operation via the global trigger register (GPTC_GTR) Offset: 0x1C Bits 31:16 15:0 Table 22-8. Reload Register Timer/Counter (x=0,1,2) Reload Register (GPTCx_RLR) Field Names Description Unused TRV Timer Reload Value

22.4.3. Current Time Register

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Technical Reference Manual The current value of the timer may be read at anytime via the current time register (GPTCx_CT). In general operation the timer counts down to 0x0000 and is then reloaded with the GPTCx_RLR value. The timer may be written to at any time to change the count. Offset: 0x20 Bits 31:24 23:0 Table 22-9. Current Timer Register Timer/Counter (x=0,1,2) Reload Register (GPTCx_CTR) Field Names Description Unused CTV Current Timer Value

22.4.4. Sample Time Register The sample register for each timer/counter may be loaded under software control or with an external control signal. The SMPLMD field in the timer/counter mode register (GPTCx_MR) enables loading the register with the control inputs (TC1 or TC2). The SMPLPOL field of the timer/counter mode register specifies the polarity on the selected TX input to perform the sample. Software may also sample the timer via the global trigger register (GPTC_GTR) Offset: 0x24 Bits 31:26 25:24 Table 22-10. Timer/Counter (x=0,1,2) Reload Register (GPTCx_SVR) Timer/Counter (x=0,1,2) Reload Register (GPTCx_SVR) Field Names Description Unused RSLS Reloads Since Last Sample. Indicates how many times the timer/counter has been reloaded since the last sample was taken. This is useful when comparing the value in the sample register with the value in the current time register. 00 - No reloads 01 - 1 Reload 10 - 2 Reloads 11 - 3 or more reloads Snap shot. Contains the timer/counter value when the sample was taken.

23:0

SNAPSH

22.4.5. Status and Interrupt Clear Register The read only timer/counter status register and the write only timer/counter interrupt clear register are accessible using the same address. The status register for each timer/counter provides access to a number of status flags that reflect the operation of the corresponding timer/counter. Table 22-11. Timer/Counter (x=0,1,2) Reload Register (GPTCx_STICR) Status (read) Offset: 0x28 Timer/Counter (x=0,1,2) Reload Register (GPTCx_STICR) Status (read) Bits Field Names Description 31:7 Unused

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Technical Reference Manual 6 5 TMRRUN TRGR Timer Running. The timer running flag indicates all internal and external enable conditions have been satisfied to allow the timer to operate. Trigger. It indicates the current state of the trigger register. The trigger register may be used to enable the timer. The trigger register is set and cleared via the external control signals TC1/TC2 or under software control. Operation of the trigger register is controlled with the STRTMD, STOPMD, STRTPOL, and STOPPOL fields of the timer/counter mode register (GPTCx_MR) Trigger Clear Interrupt. The trigger clear interrupt status flag indicates a clear trigger condition has occurred. The trigger clear operation is configured via the STOPMD and STOPPOL fields of the timer/counter mode register. The trigger clear interrupt may be masked with the TCLRIE flag in the GPTCx_MR. Trigger Set Interrupt. The trigger set interrupt status flag indicates a set trigger condition has occurred. The trigger set operation is configured via the STRTMD and STRTPOL fields of the timer/counter mode register (GPTCx_MR). The trigger set interrupt may be masked with the TSETIE flag in the GPTCx_MR. Sample Timer/Counter Interrupt. The sample timer interrupt status flag indicates a sample of the current time has occurred. The sample operation is configured via the SMPLMD and SMPLPOL fields of the timer/counter mode register (GPTCx_MR). The sample interrupt may be masked with the SMPLIE flag in the GPTCx_MR. Reload Timer/Counter Interrupt. The reload timer interrupt status flag indicates a reload has occurred due to a timer control transition or a software request via the global trigger register. Timer reloads due to the current count reaching 0x0000 do not generate the reload interrupt. The reload operation is configured via the RLDMD and RLDPOL fields of the timer/counter mode register (GPTCx_MR). The sample interrupt may be masked with the RLDIE flag in the GPTCx_MR. Timer/Counter Time-out Interrupt. The Time out interrupt status flag indicates the Timer/ Counter has reached 0x0000. The time-out interrupt may be masked with the TOE flag in the T/C mode register

TCLRINT

TSETINT

SMPLINT

RLDINT

TOINT

Table 22-12. Timer/Counter (x=0,1,2) Reload Register (GPTCx_STICR) Interrupt Clear (Write) Offset: 0x28 Timer/Counter (x=0,1,2) Reload Register (GPTCx_STICR) Interrupt Clear (Write) Bits Field Names Description 31:7 6 5 4 Unused Unused Unused TCLRICLR

TSETICLR

Clear Trigger Clear Interrupt. A write to the interrupt clear port with this bit set will clear the TCLRINT flag in the timer/counter status register. A write with this bit clear has no effect on TCLRINT flag. Clear Trigger Set Interrupt. A write to the interrupt clear port with this bit set will clear the
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Technical Reference Manual TSETINT flag in the timer/counter status register. A write with this bit clear has no effect on TSETINT flag. Clear Sample T/C Interrupt. A write to the interrupt clear port with this bit set will clear the SMPLINT flag in the timer/counter status register. A write with this bit clear has no effect on SMPLINT flag. Clear Reload T/C Interrupt. A write to the interrupt clear port with this bit set will clear the RLDINT flag in the timer/counter status register. A write with this bit clear has no effect on RLDINT flag. Clear T/C Time-out Interrupt. A write to the interrupt clear port with this bit set will clear the TOINT flag in the timer/counter status register. A write with this bit clear has no effect on TOINT flag

SMPLICLR

RLDICLR

TOICLR

22.5.

Timer/Counter Operation

The following sections discuss several uses of the timer/counters and the necessary configurations to perform those functions. 22.5.1. Basic Cyclic Timing A basic cyclic timer with an external sample input and an active low cyclic output is illustrated in figure below. While this example illustrates timer/counter 0, similar operation is available with T/C 1 and T/C 2.

Figure 22-6. Cyclic Timer with External Sample and Pulse Output
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Technical Reference Manual Table 22-13. GPTC global mode register GPTC Global mode register (GPTC_GMR) Field Names Value Unused WF_IE -TC_IE --1 TSTRSTOP 1 PSCEN MTEN --1 Table 22-14. Timer/Counter I/O mode register Timer/Counter I/O Mode register (GPTC_IOPR) Field Names Value Unused T2BOSEL -T2AOSEL -T1BOSEL -T1AOSEL -T0BOSEL 01 T0AOSEL 00 T2CS2 -T2CS1 -T1CS2 -T1CS1 -T0CS2 -T0CS1 00 TCKS --0 PSMODE 01 Table 22-15. Timer/counter I/O polarity register Timer/Counter I/O Polarity Register (GPTC_IOMR) Field Names Description Unused TIOBPOL --0 TIOAPOL --1 CKPOL --Table 22-16. Timer/counter 0 mode register Timer/Counter 0 Mode Register (GPTC0_MR) Field Names Description Unused TCLRIE TSETIE SMPLIE 1 1 RLDIE TOIE 1 1
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Offset: 0x00 Bits 31:11 9:8 7:5 4 3 2:0

Offset: 0x04 Bits 31:29 28:27 26:25 24:23 22:21 20:19 18:17 16:15 14:13 12:11 10:9 8:7 6:5 4:2 1:0

Offset: 0x08 Bits 31:11 8:6 5:3 2:0

Offset: 0x18 Bits 31:20 19 18 17 16 15

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Technical Reference Manual 14 13:12 11 10:9 8 7:6 5 4:3 2 1:0 SMPLPOL 1 SMPLMD RDLDPOL RLDMD 00 STOPPOL STOPMD 00 STRTPOL STRTMD 00 XENPOL TMREN 01 1 10 00 00 00 01

Note: The - character in the above table indicates the value is not applicable to the example configuration. The timer global mode register (GPTC_GMR) enables operation of T/C 0 and the prescaler. The GPTC_GMR also enables the interrupt associated with T/C 0. The I/O configuration register (GPTC_IOMR) configures the prescaler to use the internal clock and configures T/C 0 to use the prescaler output. The GPTC_IOMR and I/O polarity register (GPTC_IOPR) configures TIOA0 as an input and TIOB0 as an output. TIOA0 is an active high input driving the TC1 control signal. TIOB0 is an active low output driven by the T/C output (TO0). The T/C 0 mode register (GPTC0_MR) configures the TC1 control input (connected to TIOA0) to cause a sample of the current time. This feature is useful for time stamping of external events. The SMPLIE interrupt is enabled so that an interrupt is generated when a sample is taken. The reload, trigger, and external enable options are disabled by the T/C mode register settings. The cyclic timer operation is illustrated in Figure 22-7. The T/C reload register value (N) is loaded into the T/C current count register. The timer output is activated as the timer counts from 0x0001 down to 0x0000. The output is deactivated on the next cycle and the time-out interrupt is generated. Figure 151 illustrates a sample taken when the current count is equal to 0x0001. Associated with the sample register is the reloads since last sample field (GPTC0_SVR). This field indicates the number of times the current time register (GPTC0_CTR) has been reloaded. This allows the T/C0 sample interrupt handler to determine the number of timer clock cycles that have elapsed since the sample was taken. The waveform module (Section 6.6, page 83) provides an alternate means of time stamping external signals. The waveform module places the time stamp values in a FIFO in order to minimize interrupt handling overhead.

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Figure 22-7. Waveform of Cyclic Timer with external sample and output 22.5.2. External Triggering External triggering (starting and stopping) of the timers is illustrated in figure 152 . The configuration information is shown in table 534. This configuration uses the external TCK0 external clock source for the timer. TIOA0 is used as the timer start trigger and TIOB0 is used as the timer stop trigger. The trigger conditions have been configured as active low. The reload, enable, and sample modes have been disabled. The T/C has been configured to generate an interrupt when the timer is started and stopped (in addition to the timer reload interrupt). While this example illustrates T/C 0, similar operation is available with T/C 1 and T/C 2.

Figure 22-8. External Timer Trigger Control

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Technical Reference Manual Table 22-17. T/C Configuration for external triggering GPTC Global mode register (GPTC_GMR) Field Names Value Unused WF_IE -TC_IE --1 TSTRSTOP 1 PSCEN MTEN --1 Table 22-18. Timer/counter I/O mode register Timer/Counter I/O Mode register (GPTC_IOPR) Field Names Value Unused T2BOSEL -T2AOSEL -T1BOSEL -T1AOSEL -T0BOSEL 00 T0AOSEL 00 T2CS2 -T2CS1 -T1CS2 -T1CS1 -T0CS2 01 T0CS1 00 TCKS --1 PSMODE -Table 22-19. Timer/counter I/O polarity register Timer/Counter I/O Polarity Register (GPTC_IOMR) Field Names Description Unused TIOBPOL --0 TIOAPOL --0 CKPOL --1 Table 22-20. Timer/counter 0 mode register Timer/Counter 0 Mode Register (GPTC0_MR) Field Names Description Unused TCLRIE 1 TSETIE 1 SMPLIE 1 RLDIE TOIE 1 1 SMPLPOL 1 SMPLMD 00 RDLDPOL 531 5/5/2010 Version 2.1

Offset: 0x00 Bits 31:11 9:8 7:5 4 3 2:0 Offset: 0x04 Bits 31:29 28:27 26:25 24:23 22:21 20:19 18:17 16:15 14:13 12:11 10:9 8:7 6:5 4:2 1:0 Offset: 0x08 Bits 31:11 8:6 5:3 2:0 Offset: 0x18 Bits 31:20 19 18 17 16 15 14 13:12 11
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Technical Reference Manual 10:9 8 7:6 5 4:3 2 1:0 RLDMD 00 STOPPOL STOPMD 00 STRTPOL STRTMD 00 XENPOL TMREN 01 00 1 11 1 10 01

Note: The - character in the above table indicates the value is not applicable to the example configuration. The timer global mode register (GPTC_GMR) enables operation of T/C 0 and enables the ability of T/C 0 to generate the interrupt. The I/O configuration register (GPTC_IOMR) configures the T/C 0 to use the external clock source (TCK0) and sets up the timer I/O pins (TIOA0 and TIOB0) as inputs. The I/O polarity register (GPTC_IOPR) configures the TIOA0 and TIOB0 as active low. The T/C 0 mode register (GPTC0_MR) configures the TC1 control input as the start trigger and the TC2 control input as the stop trigger (GPTC_IOMR connected TC1 to TIOA0 and TC2 to TIOB0). The GPTC_MR specifies the control signals to be rising edge generated triggers. However, the I/O polarity registers defined the TIOA0 and TIOB0 pins (to which TC1 and TC2 are connected) as active low. The I/O block performs the necessary inversion on the input pins. The two means of specifying polarity allows additional flexibility when the TC1/TC2 signals or the TIOB/TIOA pins are used for multiple functions within the timer/counter blocks. The use of external trigger signals is illustrated figure 22-9. The count down operation of the timer is suspended while the trigger register is clear. The active (falling) edge on TIOA0 sets the trigger register and the trigger set interrupt (TSETINT). On the next edge of the clock the counter will begin to count down. The count down operation continues until the active (falling) edge of TIOB0 clears the trigger register. The clearing of the trigger register will suspend the count down operation and activate the TCLRINT. The TSETINT and TCLRINT interrupts may be disabled if that functionality is not needed.

Figure 22-9. Waveform Illustrating External Timer Triggers

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Technical Reference Manual 22.6. Watchdog Operation

The aJ-200 timer/counter modules support watchdog functions that many embedded systems require. The timer/ counters may be configured to monitor an external signal for periodic activity. The periodic activity is required for the device to be considered healthy. An example of this is discussed in this section. The timers may also be used by a periodic health monitor thread running on the aJ-200. The health monitor thread would load the timer so that it does not reach a count of 0x0000. A timer configured as a single cycle timer may be used to implement this type of monitor. The scenario discussed here uses the aJ-200 to monitor the health of a second CPU. The configuration of this watchdog timer is depicted in figure 154. The timer I/O input (TIOA0) is connected to an output of the 2nd CPU. TIOA0 is configured to reload the timer on a rising edge of TIOA0. The 2nd CPU must periodically activate TIOA0 to prevent the counter from reaching a count of 0x0000. If the timer does reach 0x0000 the output (TIOB0) is activated to flag the unhealthy condition. The configuration information for this watchdog timer is shown in figure 22-21.

Offset: 0x00 Bits 31:11

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Figure 22-10. External Watchdog Timer Operation Table 22-21. Configuration for Watchdog Monitor of External Logic GPTC Global mode register (GPTC_GMR) Field Names Value Unused
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WF_IE -TC_IE --0 TSTRSTOP 1 PSCEN 1 MTEN --1 Table 22-22. Timer/counter I/O mode register Timer/Counter I/O Mode register (GPTC_IOPR) Field Names Value Unused T2BOSEL -T2AOSEL -T1BOSEL -T1AOSEL -T0BOSEL 01 T0AOSEL 00 T2CS2 -T2CS1 -T1CS2 -T1CS1 -T0CS2 -T0CS1 00 TCKS --0 PSMODE 01 Table 22-23. Timer/counter I/O polarity register Timer/Counter I/O Polarity Register (GPTC_IOMR) Field Names Description Unused TIOBPOL --0 TIOAPOL --1 CKPOL --Table 22-24. Timer/counter 0 mode register Timer/Counter 0 Mode Register (GPTC0_MR) Field Names Description Unused TCLRIE TSETIE SMPLIE 1 RLDIE 0 TOIE 1 0 SMPLPOL 1 SMPLMD 00 RDLDPOL 1 RLDMD 00 10 STOPPOL STOPMD 00 00 STRTPOL 534 5/5/2010 Version 2.1

Technical Reference Manual 4:3 2 1:0 Note The - character in the above table indicates the value is not applicable to the example configuration. The timer global mode register (GPTC_GMR) enables operation of T/C 0 and the prescaler. The I/O configuration register (GPTC_IOMR) configures the prescaler to use the internal clock and configures T/C 0 to use the prescaler output. The GPTC_IOMR and I/O polarity register (GPTC_IOPR) configures TIOA0 as an input and TIOB0 as an output. TIOA0 is an active high input driving the TC1 control signal. TIOB0 is an active low output driven by the T/C output (TO0). No aJ-200 interrupts are necessary for this application. The T/C 0 mode register (GPTC0_MR) configures the TC1 control input (connected to TIOA0) to generate a reload of the timer/counter. If the reload operation does not occur before the timer reaches a count of 0x0000 the timer output (connected to TIOB0) will be activated. The timer is reloaded once successfully avoiding a watchdog time-out. The timer is then allowed to expire which activates the timer output STRTMD 00 XENPOL TMREN 01 00 01

Figure 22-11. External Watchdog Timer Waveform 22.6.1. Single Cycle Operation The aJ-200 timer may be configured to count from an initial count down to 0x0000 and then stop operation. This type of operation is referred to as Single Cycle Operation. The configuration for single cycle operation is straight forward and does not make use of the various I/O configuration options for the timers. The configuration is shown in 545. In addition, the reload register (GPTC0_RLR) must have value of 0x0000. Single cycle timer operation is initiated by directly writing to the current count register (GPTC0_CCR). This is illustrated in figure 156. Offset: 0x00 Bits 31:11 9:8
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Table 22-25. Configuration Single Cycle Operation GPTC Global mode register (GPTC_GMR) Field Names Value Unused WF_IE -535 5/5/2010 Version 2.1

Technical Reference Manual 7:5 4 3 2:0 Offset: 0x18 Bits 31:20 19 18 17 16 15 14 13:12 11 10:9 8 7:6 5 4:3 2 1:0 TC_IE TSTRSTOP PSCEN MTEN --1 1 1 --1

Table 22-26. Timer/counter 0 mode register Timer/Counter 0 Mode Register (GPTC0_MR) Field Names Description Unused TCLRIE TSETIE SMPLIE 1 RLDIE TOIE 1 1 SMPLPOL 1 SMPLMD 00 RDLDPOL RLDMD 00 00 STOPPOL STOPMD 00 00 STRTPOL STRTMD 00 00 XENPOL TMREN 01 01

Figure 22-12. Single Cycle Waveform The previous section discussed how a timer/counter module could be used to implement a watchdog monitor where the monitor is triggered via an external signal (perhaps a 2nd CPU). The single cycle operation could be used to implement another type of watchdog. A health monitor thread running on the aJ-200 could periodically write to the current count register (GPTC0_CCR) such that it never reaches the 0x0000 count. If the count is reached the watchdog would time-out indicating the software system is not operating properly. This operation is illustrated in figure below.

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Figure 22-13. Single Cycle Counter Performing a Watchdog Function 22.6.2. Chaining Multiple Timers The timers may be chained together to create a larger timer (two T/C for 32 bits, three T/C for 72 bits). Figure 22-14 illustrates the timer configurations for a 72 bit timer and the necessary register settings are shown in Table 22-27. All timers are configured to use the prescalar output as the clock source. T/C 1 and TC 2 utilize the external enable feature of the T/C. The enable for T/C 1 is connected to the TO signal of T/C 0 such that it counts only when T/C 0 reaches 0x0000. The enable for T/C 2 is only active when both T/C 0 and T/C 1 are equal to 0x0000. The interrupt output from T/C 2 is used to detect the rollover interrupt. Offset: 0x00 Bits 31:11 9:8 7:5 4 3 2:0 Table 22-27. Configuration for Timer Chaining (48-bit) GPTC Global mode register (GPTC_GMR) Field Names Value Unused WF_IE -TC_IE 100 TSTRSTOP 1 PSCEN 1 MTEN 111 Table 22-28. Timer/counter I/O mode register Timer/Counter I/O Mode register (GPTC_IOPR) Field Names Value Unused T2BOSEL 00 T2AOSEL 00 T1BOSEL 00 T1AOSEL 00 T0BOSEL 00 T0AOSEL 00 T2CS2 -T2CS1 11 T1CS2 -T1CS1 10 T0CS2 -T0CS1 -TCKS 000 PSMODE 01

Offset: 0x04 Bits 31:29 28:27 26:25 24:23 22:21 20:19 18:17 16:15 14:13 12:11 10:9 8:7 6:5 4:2 1:0

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Technical Reference Manual Table 22-29. Timer/counter 0 mode register Timer/Counter 0 Mode Register (GPTC0_MR) Field Names Description Unused TCLRIE TSETIE SMPLIE 1 RLDIE TOIE 1 0 SMPLPOL 1 SMPLMD 00 RDLDPOL RLDMD 00 00 STOPPOL STOPMD 00 00 STRTPOL STRTMD 00 00 XENPOL TMREN 01 00 Table 22-30. Timer/counter 1 mode register Timer/Counter 1 Mode Register (GPTC1_MR) Field Names Description Unused TCLRIE TSETIE SMPLIE 1 RLDIE TOIE 1 0 SMPLPOL 1 SMPLMD 00 RDLDPOL RLDMD 00 00 STOPPOL STOPMD 00 00 STRTPOL STRTMD 00 00 XENPOL 1 TMREN 01 10 Table 22-31. Timer/counter 2 mode register Timer/Counter 2 Mode Register (GPTC2_MR) Field Names Description Unused TCLRIE TSETIE SMPLIE 1 -

Offset: 0x18 Bits 31:20 19 18 17 16 15 14 13:12 11 10:9 8 7:6 5 4:3 2 1:0 Offset: 0x18 Bits 31:20 19 18 17 16 15 14 13:12 11 10:9 8 7:6 5 4:3 2 1:0

Offset: 0x18 Bits 31:20 19 18 17

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Technical Reference Manual 16 15 14 13:12 11 10:9 8 7:6 5 4:3 2 1:0 RLDIE TOIE 1 SMPLPOL 1 SMPLMD RDLDPOL RLDMD 00 STOPPOL STOPMD 00 STRTPOL STRTMD 00 XENPOL TMREN 01 1 00 00 00 00 1 10

Figure 22-14. Timer Chaining Configuration (72 bits)

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Figure 22-15. Timer Chaining (48 bits) Waveform The aJ-200 contains two waveform modules capable of performing timing measurements or generating pulse width modulated outputs (PWM). One waveform module is associated with timer/counter 1 and the other is associated with timer/counter 2. 22.6.3. PWM Mode The PWM mode of operation is configured via the waveform operation field (WFOP) of the waveform mode register (WFx_MR). The PWM mode of operation is depicted in figure 22-16. The PWM generates a periodic with a varying duty cycle as depicted in figure below. The period is specified via the reload register of the T/C (GPTCx_RLR) and the duty cycle is controlled via the times stored in the FIFO. The FIFO is loaded via writes to the FIFO write port (WFx_WRP). The FIFO stores a maximum of 32 values. Depicted in Figure 167 is a PWM waveform with an N+1 period (GPTCx_RLR=N) and FIFO contents of a, b, c, d, and e. As can be seen the sample value specifies the number of cycles the output is in the low state. Therefore the duty cycle is:

Duty Cycle =

GPtCx_RLR +1 - FIFO Sample GPTCx_RLR +1

Note The output may be inverted via the I/O polarity register (GPTC_IOPR) if its desired to have the sample value reflect the amount of time the output is high.

Figure 22-16. Pulse width Modulation Mode

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Figure 22-17. PWM Waveform The interrupt mode field (INTMD) of the WFx_MR register also configures the interrupt operation of the FIFO levels for generation of the PWM interrupt. The interrupt condition is based on the amount of empty entries in the FIFO. The user may select from 25%, 50%, 75%, or 100% empty. As samples are being added to the FIFO the user may monitor the FIFO full flag in the status register (WFx_STR) in order to avoid overflowing the FIFO. Some applications may require the duty cycle to be constant for an extended period of time. This would generate a constant analog value on the output of a low pass filter connected to the PWM output. A single value may be written to the FIFO. The waveform will continue to have the duty cycle associated with this sample until a new value is written to the FIFO. 22.6.3.1. Sample Mode The sample mode of operation is configured via the waveform operation field (WFOP) of the waveform mode register (WFx_MR). The sample mode of operation is depicted in figure 22-18 The sample mode captures the timestamp associated with transitions of the sample input. This sample mode enables several timing measurement operations such as pulse width, duty cycle, and frequency. The timer control input (TC2) is used as the source of the sample signal. The timer I/O block provides several options for the source of the TC2 input. The TC2 source is specified via the I/O mode register (GPTC_IOMR) and the I/O polarity register (GPTC_IOPR). The sample module may be configured to time stamp the rising edge of the TC2 input (ex: frequency measurement) or either edge (ex: pulse width). In addition to the time stamp the FIFO captures the state of TC2, the number of times the T/C was reloaded between samples, and a FIFO overflow flag. The samples are retrieved via the FIFO read port (WFx_RDP). The FIFO overflow flag indicates a sample was taken

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Technical Reference Manual while the FIFO was full. If the FIFO is already full when a sample is taken the last element is overwritten resulting in a lost sample value. A non-zero value in the reloads since last sample field indicates the T/C has been reloaded since the previous sample was taken. As an example of the use of the reload register consider the following four samples retrieved from the FIFO. This waveform is recreated in figure 163. Sample X : 0x2_FFFF; reloads = 1, sample = 0, time = 0xFFFF (65,535) Sample X+1 : 0x1_1FFF; reloads = 0, sample = 1, time = 0x1FFF ( 8,191) Sample X+2 : 0x2_7FFF; reloads = 1, sample = 0, time = 0x7FFF (32,767) Sample X+3 : 0x7_EFFF; reloads = 2, sample = 1, time = 0xEFFF (61,439)

Figure 22-18. Sample Mode

Figure 22-19. Sampled Waveform 22.6.3.2. Register Description This section describes the registers associated with a waveform module. There are two copies of these registers which corresponding to the two waveform modules. Waveform Module Mode Register The waveform mode register selects PWM or Sample mode of operation and the desired interrupt mode. Offset: 0x54 Bits 31:5 4:3 Table 22-32. Waveform Module Waveform Module (x=1 or 2) Mode Register (WFx_MR) Field Names Description Unused INTMD INTMD Interrupt mode. Specifies the interrupt condition for the waveform module. Waveform module interrupts are visible in interrupt status register (GPTC_ISR) with enable control provided via the global mode register (GPTC_ISR) In sample mode (WFOP field is set to 10)
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Technical Reference Manual 00 - Interrupt on FIFO at least 25% full 01 - Interrupt on FIFO at least 50% full 10 - Interrupt on FIFO at least 75% full 11 - Interrupt on FIFO full In PWM mode (WFOP is set to 11) 00 - Interrupt on FIFO at least 25% empty 01 - Interrupt on FIFO at least 50% empty 10 - Interrupt on FIFO at least 75% empty 11 - Interrupt on FIFO empty SMPLMD Sample mode. This bit has no effect if WFOP is set to 1. It is decoded as follows: 0 - Sample occurs on rising edge of the control input. 1 - A sample occurs on either transition of the control input. WFOP Waveform operating mode. 0x - Disable waveform block (also resets FIFO) 10 - Waveform sampling mode 11 PWM mode

SMPLMD

1:0

WFOP

Waveform Status Register The waveform status register reflects the various flags associated with the FIFO contents. FIFO overflow and underflow error flags are captured in the status register. Once set, these flags remain set until they are cleared via the FIFO clear port (WFx_CP). Offset: 0x54 Bits 31:11 10 Table 22-33. Waveform Module (x=1 or 2) Mode Register (WFx_MR) Waveform Module (x=1 or 2) Mode Register (WFx_MR) Field Names Description Unused FIFOUNF FIFO Underflow (valid in PWM mode). The underflow error flag indicates the FIFO has underflowed at some point in the past. FIFO underflow occurs in PWM mode when the output deactivation samples have been exhausted. The underflow condition is cleared via the waveform clear port. FIFO underflow is only valid in the PWM mode of operation. FIFOVF FIFO Overflow (valid in sample mode). The overflow error flag indicates that the FIFO has overflowed at some point in the past. The FIFO overflow flag is cleared via the wave-form clear register. FIFO overflows may also be detected as samples are read from the FIFO via the overflow field (OVR) of the FIFO read port. The FIFO overflow is only valid in the sample mode of operation. INT Waveform module interrupt. The INT flag indicates the interrupt condition is pending. The interrupt condition is specified in the INTMD field of the mode register (WFx_MR; Section 6.6.3.1, page 85). FIFOTFQ Three Quarters Full Flag. The 3/4 full flag indicates at least 75% of the FIFO entries contain valid data. This is typically applicable to the sample mode of operation. FIFOHF FIFO Half Full Flag. The 1/2 full flag indicates at least 50% of the FIFO entries contain valid data.
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Technical Reference Manual This is typically applicable to the sample mode of operation. FIFO One Quarter Full Flag. The 1/4 full flag indicates at least 25% of the FIFO entries contain valid data. This is typically applicable to the sample mode of operation. FIFO Three Quarters Empty Flag. The 3/4 empty flag indicates at least 75% of the FIFO is available to receive additional data. This is typically applicable to the PWM mode of operation. FIFO Half Empty Flag. The 1/2 empty flag indicates at least 50% of the FIFO is available to receive additional data. This is typically applicable to the PWM mode of operation. FIFO One Quarter Empty Flag. The 1/4 empty flag indicates at least 25% of the FIFO is available to receive additional data. This is typically applicable to the PWM mode of operation. FIFO Full Flag. The FIFO full flag indicates the FIFO cannot receive additional samples. In PWM mode the FIFOFULL flag is used as the exit condition of adding additional samples to the FIFO. A full FIFO in sample mode generally indicates an error condition since it can no longer capture samples. FIFO Empty Flag. The FIFO empty flag indicates the FIFO can does not have any valid data. In sample mode the FIFOEMPTY flag is used as the exit condition when unloading the samples from the FIFO. An empty FIFO in PWM mode generally indicates an error condition since the PWM logic has exhausted all samples. The exception to this is when a no variation in the PWM duty cycle is required. The PWM duty cycle is specified with the last value written to the FIFO when the FIFO is emptied.

5 4 3 2 1

FIFOOQF FIFOTQE FIFOOHE FIFOOQE FIFOFULL

FIFOEMPTY

Waveform FIFO Read Port Samples collected in the sample mode of operation are unloaded from the via the FIFO read port. The read port contains the sample time stamp, the state of the pin that caused the sample, the number of timer reloads since the previous sample, and an overflow flag. Table 22-34. Waveform Module (x=1 or 2) Mode Register (WFx_RDP) Offset: 0x5C Waveform Module (x=1 or 2) Mode Register (WFx_RDP) Bits Field Names Description 31:20 Unused 19 OVR FIFO overflow. This flag indicates a sample was taken while the FIFO was full. This indicates that the timestamps associated with some samples was lost. Since some samples were lost, the RSLS field does not reflect the proper number of reloads since the preceding sample unloaded from the FIFO. 18:17 RSLS Reloads Since Last Sample. The RSLS field indicates the number of times the T/C has been reloaded since the last sample was taken. This is necessary to determine the time differential between samples around points where the timer reloads. For example: Sample X had a SMPLTIME value of 0x0003 and Sample X+1 has a sample time of 0xFFFE (assuming the GPTC_RLR=0xFFFF). A RSLS value of 1 indicates five cycles between samples while a RSLS
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Technical Reference Manual value of 2 indicates 65,571 cycles (65,536 + 5). 00 - No reloads since the previous sample 01 - One reload since the previous sample 10 - Two reloads since the previous sample 11 - Three or more reloads since the previous sample. Sample value. The SMPLVAL value indicates the state of the input pin when the sample was taken. The SMPLVAL is only meaningful when samples are collected on the rising and the falling edge of the input signal. This is selected via the SMPLMD field in the waveform mode register (WFx_MR; Section 6.6.3.1, page 85). Sample time. The sample field is the value of the T/C current count register when the transition on the sample input occurred.

16

SMPLVAL

15:0

SMPLTIME

Waveform FIFO Write Port The waveform FIFO write register is used to specify the deactivation time for the PWM output. The value of the sample configures the number of timer cycles the PWM output is low. Table 22-35. Waveform Module (x=1 or 2) Mode Register (WFx_WRP) Offset: 0x60 Waveform Module (x=1 or 2) Mode Register (WFx_WRP) Bits Field Names Description 31:16 Unused 15:0 Deactivation time Waveform FIFO Clear Port The waveform clear port (WFx_CP) is used to clear the FIFO overflow and underflow flags and place the FIFO in the empty state. The FIFO overflow flag is set when a full FIFO is written to and the FIFO underflow flag is set when an empty FIFO is read from. Once set, an error flag is only cleared via the WFx_CP. The error flags are visible via the waveform status register (WFx_STR) Offset: 0x64 Bits 31:2 1 0 Table 22-36. Waveform Module (x=1 or 2) Mode Register (WFx_CP) Waveform Module (x=1 or 2) Mode Register (WFx_CP) Field Names Description Unused ERR_CLR FIFO error clear flag. Writing to the clear port with the ERR_CLR field set will clear the FIFO overflow and underflow flags in the waveform status register (WFx_STR) FIFO_CLR FIFO clear. Writing to the clear port with the FIFO_CLR field set will place the waveform FIFO in the empty state.

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23. Real Time Clock (RTC)

23.1. General Descriptions The RTC provides a basic alarm function or long-time-based counter. Its powered by a li-ion battery when the system power is off. The RTC is set to be 1 Hz output and is utilized as a system timekeeper. The RTC also serves as an alarm that generates an interrupt signal or a wake up event when the RTC output clock increments to a preset time. All the registers in the RTC are reset by power-on reset only. The RTC accepts two clock sources: APB bus clock (PCLK) and 32.768 KHz clock (which is divided internally to generate 1Hz). When the system is in sleep mode, the PCLK clock can be gated while the RTC keeps on counting. This mechanism promises the lowest power consumption when the system is in sleep mode. It supports the following features: When the system is in sleep mode, PCLK can be gated to save power consumption Separated second, minute, hour and day counters to reduce power consumption and software complexity Programmable auto second, minute, or hour alarm The block diagram of RTC is shown in the figure below

Figure 23-1. Block Diagram of RTC

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Technical Reference Manual 23.2. APB Interface The APB interface accepts standard APB bus signals. It services read / write requirements from APB bus. When the psel is active, the APB interface decodes the paddr to select one register in the RTC. The pwrite signal indicates read or write. If the pwrite signal indicates write, the pwdata will be written to the selected register. If the pwrite signal indicates read, then the selected register will be read out in prdata. 23.3. RTC Alarm Registers

The RTC alarm registers include the AlarmSecond, the AlarmMinute and the AlarmHour registers. The legal range of the AlarmSecond and the AlarmMinute registers is 0 ~ 59, and the legal range of the AlarmHour register is 0 ~ 23. If either one of the AlarmSecond, AlarmMinute or AlarmHour values exceeds the legal range, the rtc_alarm interrupt will never be triggered. 23.4. RTC Control Registers

The RTC control registers control the RTC enable / disable, and the auto alarm function enable / disable. The default is RTC disable and auto alarm function disable. 23.5. RTC Record Register

The RTC record register only includes one RtcRecord register. When system is initialized, the user inputs the current time. The following expression can calculate the record value:
RtcDays*86400 + RtcHour*3600 + RtcMinute*60 + RtcSecond + RtcRecord = seconds of (Current time - Base time)

time. 23.6.

RtcHour, RtcMinute and RtcSecond are registers contained in RTC counter block. Base time is defined by programmer. For example, it can be defined at 2000/01/01/00:00:00. Current time is input by user when system is initialized.

After setting the record register, the software can always use the above expression to calculate the current

Sync Block

The RTC has two clock domains that may propagate a metastable value when crossing domain reading. Hence, the relationship between PCLK and CLK1HZ needs to follow the limitation: (CLK1HZ cycle time) / (PCLK cycle time) > 4 The following crossing reading situations need to be considered. Table 23-1. Crossing Clock Domain Signals RtcSecond, RtcMinute, RtcHour and RtcDay registers: The synchronization is made by sync block. CLK1HZ domain PCLK domain rtc_alarm, rtc_sec, rtc_min, rtc_hour and rtc_day interrupts: The synchronization is made by interrupt controller.

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Technical Reference Manual Alarm registers and control register: These registers are assumed to remain stable when RTC is working.

PCLK domain CLK1HZ domain

23.7. RTC Counter The RTC counter includes second, minute, hour and day counters. The second register increases by every second but rounds to zero when the value exceeds 59. Similarly, the minute register increases by every minute but rounds to zero when the value exceeds 59, the hour register increases by every hour but rounds to zero when the value exceeds 23. The day register increases by every day. When RTCRSTn is asserted, these counters are set to zero. These counters belong to the CLK1HZ clock domain and are read-only. 23.8. RTC Auto Alarm Logic The auto alarm logic can auto trigger an interrupt by each second, each minute, each hour or each day. For example, if the second auto alarm function is turned on, the RTC auto alarm logic will trigger an interrupt every second. This function is useful for implementing a clock. The programmer can enable the auto alarm function by writing a 1 to the RTC control register. 23.9. RTC Compare Logic The RTC compare logic is used to determine the rtc_alarm interrupt. This logic block includes second, minute and hour comparators. If the AlarmSecond register equals the RTC counters second value, the AlarmMinute register equals the RTC counters minute value and the AlarmHour register equals the RTC counters hour value, then rtc_alarm interrupt will be triggered. The programmer can enable this logic block by writing a 1 to RTC control register. 23.10. Frequency Divider Since the RTC counters belong to 1 Hz clock domain, the EXTCLK which is not 1 Hz clock must be divided into 1 Hz by the frequency divider. If the EXTCLK is already 1 Hz clock, the user can disable the frequency divider and the EXTCLK will pass to the RTC counters directly. 23.11. Programming Model

23.11.1.

Summary Of Real Time Clock Registers Table 23-2 shows the offset, type, width, reset value and name of each RTC programming register.
Table 23-2. Summary of RTC Registers

Offset 0x00 0x04 0x08 0x0C 0x10 0x14

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Type R R R R R/W R/W

Width 6 6 5 16 6 6

Reset 0x0 0x0 0x0 0x0 0x3F 0x3F

Name RtcSecond RtcMinute RtcHour RtcDays AlarmSecond AlarmMinute

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Description RTC second counter register RTC minute counter register RTC hour counter register RTC day counter register RTC second alarm register RTC minute alarm register
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Technical Reference Manual Offset 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R Width 5 32 5 6 6 5 16 5 32 32 Reset 0x1F 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Name AlarmHour RtcRecord RtcCR WRtcSecond WRtcMinute WRtcHour WRtcDays IntrState RtcDivide RtcRevision Description RTC hour alarm register RTC record register RTC control register RTC_CONTWR RTC_CONTWR RTC_CONTWR RTC_CONTWR None None RTC Revision Register

23.11.2. Register Descriptions The following sections describe the details of Faradays RTC registers. 23.11.2.1. RtcSecond (Offset == 0x00) The RtcSecond register is the RTC second counter register. When the RTCRSTn is asserted, the RtcSecond is set to zero. After the RTC is enabled, the RtcSecond value increases every second. When the RtcSecond value exceeds 59, the value is reset to zero. The RtcSecond range is 0 ~ 59. If the RTC is disabled, the RtcSecond will hold the value. Bit 5-0 Name RtcSecond Table 23-3. RtcSecond Register Type Reset Comment Read 0 None

23.11.2.2. RtcMinute (Offset == 0x04) The RtcMinute register is the RTC minute counter register. When RTCRSTn is asserted, the RtcMinute is set to zero. After the RTC is enabled, the RtcMinute value increases every minute. When the RtcMinute value exceeds 59, the value is reset to zero. The RtcMinute range is 0 ~ 59. If the RTC is disabled, the RtcMinute will hold the value. Bit 5-0 Name RtcMinute Table 23-4. RtcMinute Register Type Reset Comment Read 0 None

23.11.2.3. RtcHour (Offset == 0x08) The RtcHour register is the RTC hour counter register. When RTCRSTn is asserted, the RtcHour is set to zero. After RTC is enabled, the RtcHour value increases every hour. When the RtcHour value exceeds 23, the value is reset to zero. The RtcHour range is 0 ~ 23. If the RTC is disabled, the RtcHour will hold the value.

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Technical Reference Manual Table 23-5. RtcHour Register Type Reset Comment Read 0 None

Bit 4-0

Name RtcHour

23.11.2.4. RtcDay (Offset == 0x0C) The RtcDay register is the RTC day counter register. Before the RTC can be enabled, the programmer needs to input the current time and calculate the RtcRecord value. After the programmer has enabled the RTC, the RtcDay value will infinitely increase on a daily basis. This register will count the days from the enable time. The programmer can use this register to calculate the correct date when each system was wakened up. This register is read-only. Bit 15-0 Name RtcDay Table 23-6. RtcDay Register Type Reset Comment Read 0 None

23.11.2.5. AlarmSecond (Offset == 0x10) The AlarmSecond is the RTC second alarm register. If the programmer wants to trigger an rtc_alarm interrupt at 12:10:10, the AlarmSecond needs to be set to 0xA. If the AlarmSecond value exceeds 0x3B, the rtc_alarm will never be triggered. However, the RTC counter will keep on counting. Table 23-7. AlarmSecond Register Bit Name Type Reset Comment 5-0 AlarmSecond Read / Write 0x3F None 23.11.2.6. AlarmMinute (Offset == 0x14) The AlarmMinute is the RTC minute alarm register. If the programmer wants to trigger an rtc_alarm interrupt at 12:10:10, the AlarmMinute needs to be set to 0xA. If the AlarmMinute value exceeds 0x3B, the rtc_alarm will never be triggered. However, the RTC counter will keep on counting. Bit 5-0 Name AlarmMinute Table 23-8. AlarmMinute Register Type Reset Comment Read / Write 0x3F None

23.11.2.7. AlarmHour (Offset == 0x18) The AlarmHour is the RTC hour alarm register. If the programmer wants to trigger an rtc_alarm interrupt at 12:10:10, the AlarmHour needs to be set to 0xC. If the AlarmHour value exceeds 0x17, the rtc_alarm will never be triggered. However, the RTC counter will keep on counting. Bit 5-0 Name AlarmHour Table 23-9. AlarmHour Register Type Reset Comment Read / Write 0x1F None

23.11.2.8.
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RtcRecord (Offset == 0x1C)

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Technical Reference Manual The RTC record register is used to adjust the difference between current time and RTC counter time. The following expression can determine the RtcRecord value.
RtcDays*86400 + RtcHour*3600 + RtcMinute*60 + RtcSecond + RtcRecord = seconds of (Current time - Base time)

RtcHour, RtcMinute and RtcSecond are registers contained in RTC counter block. Base time is defined by programmer. For example, it can be defined at 2000/01/01/00:00:00. Current time is input by user when system is initialized.

The RtcDay, RtcHour, RtcMinute and RtcSecond registers are read-only. When the user inputs the current time, the RtcRecord register can be used to record the difference between the current time and the RTC counter time. Bit 31-0 Name RtcRecord Table 23-10. RtcRecord Register Type Reset Comment Read / Write 0x0 None

23.11.2.9. RtcCR (Offset == 0x20) The RtcCR is Faradays RTC control register. It controls the RTC enable / disable and auto alarm function enable / disable. Bit 0 of the RtcCR is the RTC enable bit. If it is disabled, the rtc_alarm is gated to zero, and the RTC counters will be held. This means that the power consumption approaches to zero when the RTC is disabled. Bit 1 of the RtcCR controls the once-per-second auto alarm function; if it is turned on, the rtc_sec interrupt will be triggered every second. Bit 2 of the RtcCR controls the once-per-minute auto alarm function; if it is turned on, the rtc_min interrupt will be triggered every minute. Bit 3 of the RtcCR controls the once-per-hour auto alarm function; if it is turned on, the rtc_hour interrupt will be triggered every hour. Bit 4 of the RtcCR controls the once-per-day auto alarm function; if it is turned on, the rtc_day interrupt will be triggered every day. The following table is a summary of the RtcCR bits and functions. Bit 0 Table 23-11. RTC Control Register Name Description RTC interrupt enable RTC enable 0: Disable 1: Enable RTC auto alarm per second When set on, the RTC rtc_sec interrupt is triggered every second. RTC interrupt per second 0: Disable 1: Enable RTC auto alarm per minute When set on, the RTC rtc_min interrupt is triggered every minute. RTC interrupt per minute 0: Disable 1: Enable

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Technical Reference Manual Bit 3 Name RTC interrupt per hour Description RTC auto alarm per hour When set on, the RTC rtc_hour interrupt is triggered every hour. 0: Disable 1: Enable RTC auto alarm per day When set on, the RTC rtc_day interrupt is triggered every day. 0: Disable 1: Enable RTC alarm interrupt When set on, the RTC rtc_alarm interrupt is issued if the RTC counters all match the RTC alarm registers. RTC counter load When set on, the counters can be reloaded. 0: Disable 1: Load

RTC interrupt per day

5 6

RTC alarm interrupt RTC Counter Load

23.11.2.10.

WRtcSecond

The WRtcSecond is the port to write RtcSecond counter. When CountLoad is set to 1, the value of WRtcSecond will be loaded to the RtcSecond counter. This register is effective when the user defines the RTC_CONTWR macro. Bit 5:0 Name WRtcSecond WRtcMinute Table 23-12 WRtcSecond Register Type Reset Comment Read/Write 0x0 None

23.11.2.11.

The WRtcMinute is the port to write the RtcMinute counter. When CountLoad is set to 1, the value of WRtcMinute will be loaded to the RtcMinute counter. This register is effective when the user defines the RTC_CONTWR macro. Bit 5:0 Name WRtcMinute Table 23-13 WRtcMinute Register Type Reset Comment Read/Write 0x0 None

23.11.2.12.

WRtcHour

The WRtcHour is the port to write the RtcHour counter. When CountLoad is set to 1, the value of WRtcHour will be loaded to the RtcHour counter. This register is effective when the user defines the RTC_CONTWR macro. Bit 4:0 Name WRtcHour Table 23-14 WRtcHour Register Type Reset Comment Read/Write 0x0 None
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Technical Reference Manual 23.11.2.13.

WRtcDay

The WRtcDay is the port to write the RtcDays counter. When CountLoad is set to 1, the value of WRtcDay will be loaded to the RtcDays counter. This register is effective when the user defines the RTC_CONTWR macro. Bit 15:0 Name WRtcDay Table 23-15 WRtcDay Register Type Reset Comment Read/Write 0x0 None

23.11.2.14.

IntrState

The IntrState is the interrupt status register of RTC. The register records the status of each interrupt. Each bit of the register maps to one type of interrupt. The register must be cleared by the user. Bit 5:0 0 1 2 3 4 Name WRtcMinute rtc_sec rtc_min rtc_hour rtc_day rtc_alarm Table 23-16 IntrState Register Type Reset Comment Read/Write 0x0 None Read/Write Read/Write Read/Write Read/Write Read/Write 0x0 0x0 0x0 0x0 0x0 Indicate that rtc_sec interrupt has occurred. Indicate that rtc_min interrupt has occurred. Indicate that rtc_hour interrupt has occurred. Indicate that rtc_day interrupt has occurred. Indicate that rtc_alarm interrupt has occurred.

23.11.2.15.

RtcDivide

The RtcDivide represents the cycle number that the frequency divider will divide the EXTCLK into 1 Hz clock. If the RtcDivide Enable bit is set to one, the frequency divider will operate. Otherwise, the EXTCLK will pass to the RTC counters directly. For example, if EXTCLK is 32.768k Hz clock, then the DividerCycle of RtcDivide must be set to 0x8000 and the DividerEnable must be set to one. The divider will divide EXTCLK of 32.768k Hz clock into 1Hz clock. Bit 31 30:0 Name DividerEnable DividerCycle Table 23-17. RtcDivide Register Type Reset Comment Read/Write 0x0 Enable bit 0: Divider disable 1: Divider enable Read/Write 0x8000 Indicate the cycle number which divider will divide EXTCLK into 1 Hz clock.

23.11.2.16. RtcRevision The RtcRevision register records which revision of RTC the user is using. For example, if the value in the register is 0x10102, it represents the revision of RTC is version_1_1_r2. Bit Name Table 23-18. RtcRevision Register Type Reset Comment
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Technical Reference Manual 31:0 23.12. Timing 23.12.1. Write to RtcSecond Register
R tc S e c o n d A d d r e s s

RtcRevision

Read -

The revision of RTC

PC LK PADDR P W R IT E PSEL PEN ABLE PW DATA R tc S e c o n d

DATA1 DATA1

Figure 23-2. Write RtcSecond Register 23.12.2. Second Alarm

PCLK EXTCLK HZCLK RtcSecond rtc_secarm AlarmSecond

28

29

29 29

29

30

Figure 23-3. Second Alarm 23.12.3. Auto Second Alarm

PCLK EXTCLK HZCLK RtcSecond rtc_sec AlarmSecond

28

29

29 29

29

30

Figure 23-4. Auto Second Alarm 23.13. Programming Sequence After powering on the RTC, the user inputs the current time to the RtcRecord register. The programmer needs to calculate the RtcRecord value and write the value to the RtcRecord register through the APB bus. Then the programmer can enable the RTC by writing a 1 to bit 0 of the RtcCR. After enabling the RTC, the programmer can program the AlarmHour, AlarmMinute and AlarmSecond registers and the RtcCR to enable the rtc_alarm interrupt and auto alarm function. The CLK1Hz clock for RTC cannot be gated when the system is in sleep mode. The RTC needs to be awake to count the days.

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24. SD Memory Card Host Controller (SDC)

24.1. General Descriptions The MMC/SD supports both MMC and SD interface protocol. It supports hot insertion / removal detection. For SD, it also supports write-protect and 1-bit or 4-bit bus width for large data transfer without CPU intervention. It supports the following features: Supports the SD memory card protocol version. 2.0 o No SPI mode included Supports the multi-function and combo card 1/4-bit SD data transfer mode in the SDIO Supports the multiple block transfer interrupt Supports the read wait operation in the SDIO No SPI mode included Supports 3 data bus width mode: 1/4/8 bit Supports the Interrupt mode Hardware configurable AHB or APB Supports the SDIO bus protocol version. 1.10 o o o o

Supports the MMC bus protocol version. 4.1 o o o

Supports the AMBA 2.0 bus o Supports the DMA for large data transfers Configurable 16-/ 8-/4- word data FIFO depth Built-in generation and checks for the 7-/16-bit CRC data Variable clock rate o o 0 MHz ~ 50 MHz of the SD card 0 MHz ~ 52 MHz of the MMC card

Hot insertion/removal Write-protect for the SD card

Figure below shows the block diagram of the SD host controller.

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PCLK penable psel

SD HOST CONTROLLER

io_sd_dat 3 io_sd_dat 2 io_sd_dat 1 io_sd_dat 0 io_sd_clk io_sd_cmd_rsp

Data_unit Data FIFO CRC16 Checker & Generator APB Slave Controller Register Cmd_unit CRC7 Checker & Generator

APB BUS

pwrite pwdata [31:0] prdata [31:0] PRSTn

io_sd_cd io_sd_wp

VDD sdc_dma_req sdc_dma_ack sdc_intr DMA Logic Interrupt Logic Clock Divider IO_SD_POWER [4:0] Power Supply

Figure 24-1. Block Diagram of SD Host Controller. The main building blocks of the SD host controller are APB slave ports, SD master, CRC logic, power management and clock management. The following sections contain detailed descriptions of each building block. 24.2. APB Slave The APB Slave services the accesses to the controller registers and data FIFO. 24.3. Interrupt Logic The Interrupt Logic generates interrupt request signals according to the status register. For example, when response or data CRC check failed, etc., the SD controller will generate an interrupt request. 24.4. DMA Logic The DMA Logic generates a request signal to DMAC when data in FIFO is ready in read cycle, or when FIFO is empty in write cycle. When the sdc_dma_ack is asserted by DMAC, the sdc_dma_req will be deasserted by SD host controller. 24.5. Clock Divider In card identification mode, the maximum clock frequency is 400 KHz. During data transfer, the maximum clock rate cannot exceed 25 MHz for SD memory card, and 20 MHz for MultiMediaCard. Besides, if the host with FIFO having 512 bytes of data buffer would like to transfer data to a card with 1 Kbyte write
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SD BUS

paddr [6:0]

Technical Reference Manual sector, in order to maintain a continuous data transfer, the host controller will stop the clock to the card. Then the host will fill its internal buffer with another 512 bytes. After the second half of sector is ready in the host, it will continue the data transfer to the card by re-starting the clock supply. When the card clock is stopped, the command activated or the received response may also be pended in the command unit temporarily until sufficient clock cycles are re-started to the card. 24.6. CRC Checker and Generator A 7-bit CRC is appended to commands and checked for responses. For data transfer, a 16-bit CRC is added and checked for every block of data transfer. The result of CRC check will be recorded in the status register. 24.7. Controller Registers The register file can be divided into two groups: control registers and status registers. To activate a command or data transfer with memory card, the control registers should be programmed properly. Any condition, fail or success, about the handshaking with memory card will be reported in the status register. 24.8. SD Command / Data Unit The SD Command / Data Unit provides all functions specific to the SD card, such as command and data transfer. 24.9. FIFO The data FIFO is a half-duplex FIFO with a 4-word deep, 32-bit wide data buffer. 24.10. Programming Model 24.10.1. Summary of SD Host Controller Registers The SD host controller registers are shown in table below Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 Table 24-1. Summary of SD Host Controller Registers Type Width Description R/W 11 Command Register R/W 32 Argument Register R 32 Response Register0 R 32 Response Register1 R 32 Response Register2 R 32 Response Register3 R 7 Responded Command Register R/W 7 Data Control Register R/W 32 Data Timer Register R/W 16 Data Length Register R 13 Status Register W 11 Clear Register R/W 11 Interrupt Mask Register Reset Value 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000

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Technical Reference Manual Offset 0x34 0x38 0x3C 0x40 0x44 0x48 0x6C 0x70 0x74 0x9C 0xA0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Width 5 9 2 32 8 4 32 2 24 9 32 Description Power Control Register Clock Control Register Bus Width Register Data Window Register MMC interrupt response time reguster General-purpose output SDIO control register 1 SDIO control register 2 SDIO status register Feature register Revision register Reset Value 0000_0010 0000_00ff 0000_1001 0000_0042 0000_0000 0000_0000 0000_0000 0000_0000 -

24.10.2. Register Descriptions The following sections describe the SD host controller registers in detail. 24.10.2.1. Command Register (Offset == 0x00) The command register contains the command index and the related information. Before setting a new command to the command register, the device driver should make sure that the last command is finished or responded to. When SDC_RST is set, each register will be reset to its default value except Response Register0 ~ 3. Bit 9 will be automatically cleared by hardware when the internal command state machine activates. Table 24-2. Bit 31-11 10 9 8 7 6 5-0 Name Reserved SDC_RST CMD_EN APP_CMD LONG_RSP NEED_RSP CMD_IDX Type R/W R/W R/W R/W R/W R/W Command Register

Function If set, the SD host controller will be reset. If set, the command is enabled. This bit indicates the command is application specific. If set, this command waits for a 136-bit long response. If set, this command waits for a response from card. The command index is sent as part of a command.

24.10.2.2. Argument Register (Offset == 0x04) This register contains a 32-bit argument which is sent to a card as part of a command. Bit 31-0 Name CMD_ARG Table 24-3. Type R/W Argument Register (offset: 0x04) Function Argument of command

24.10.2.3. Response0-3 Register (Offset == 0x08, 0x0C, 0x10, 0x14) The response may be 48-bit (R1, R3 and R6) or 136-bit (R2) depending on the command type. Card status, which is part of a response, may be 32-bit or 127-bit. The card status reported from card will be saved in the register(s).

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Technical Reference Manual Table 24-4. Response0-3 Register Type Function R Card status sent by card

Bit 31-0

Name CARD_STA

In below table the most significant bit of the card status is received first. The LSB of RESPONSE0 is always 1 for long responses. Table 24-5. Short Response and Long Response. Short Response Long Response Card status [31:0] Card status [31:0] Unused Card status [63:32] Unused Card status [95:64] Unused Card status [127:96]

Register Name RESPONSE0 RESPONSE1 RESPONSE2 RESPONSE3

24.10.2.4. Responded Command Register (Offset == 0x18) This register contains the index of the last command that received a response. The RSP_CMD_IDX is meaningful only for R1- and R6-type responses and is read as 0x3f for R2- and R3-type responses.
Table 24-6.

Bit 31-7 6 5-0

Name Reserved RSP_CMD_APP RSP_CMD_IDX

Type R R

Responded Command Register. Function This bit indicates the command is application specific. Response command index

24.10.2.5. Data Control Register (Offset == 0x1C) Table below shows the bit assignment of the data control register. A counter loads the value from the BLK_SIZE, and starts to decrease when the data is transferred. It decreases to zero when a block of data is transferred. The SD host controller does not support multiple block read / write with a block size of 1byte or 2-byte. To read / write 1-byte or 2-byte data, the single block read / write command should be used. Besides, the device driver should not set a block size that the card does not support. Bit 6 will be automatically cleared by hardware when the internal data state machine activates. Bit 31-7 6 5 4 3-0 Name Reserved DATA_EN DMA_EN DATA_WRITE BLK_SIZE Table 24-7. Data Control Register. Type Function R/W Enable Data Transfer Cycle R/W 0: Disable DMA transfer ; 1: Enable DMA transfer R/W 0: Read data from card ; 1:Write data to card R/W Data size per block (bytes) Table 24-8. Data Block Length. BLK_SIZE Block Length (bytes) 15-12 Reserved 11 211 = 2048
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Technical Reference Manual 10 210 = 1024 . 3 23 = 8 2 22 = 4 1 21 = 2 0 20 = 1 24.10.2.6. Data Timer Register (Offset == 0x20) This register contains the data access timeout value. When the timer expires, the timeout status flag is set. Starting of a data transfer must be written to the data timer register and data block number register before being written to the data control register. Bit 31-0 Name DATA_TIMER Table 24-9. Data Timer Register Type Function R/W Data timeout period (in card bus clock period)

24.10.2.7. Data Length Register (Offset == 0x24) This register contains the number of data bytes to be transferred. Starting of a data transfer must be written to the data timer register and data length register before being written to the data control register. The value in the data length register must be a multiple of the block size. Bit 31-16 15-0 Name Reserved DATA_LEN Table 24-10. Data Length Register. Type Function R/W Data bytes to be transferred

24.10.2.8. Status Register (Offset == 0x28) The status register is read-only. This register will be cleared by writing 1 to the corresponding clear register. 1. The FIFO_ORUN flag will only be asserted in read cycle, which means that read data is available in data FIFO and that CPU should read the data out. 2. The FIFO_URUN flag will only be asserted in write cycle, which means the FIFO is empty. CPU should send the write data to FIFO only when this bit is polled as 1. After the data is sent to FIFO, a 1 should be written to the corresponding clear register to clear this bit. This bit will first be set when DATA_EN and DATA_WRITE of the data control register (offset 0x1C) are set. 3. When a command that does not expect a response is sent, only the CMD_SENT bit will be set. When a command that expects a response is sent, either the RSP_CRC_OK or RSP_CRC_FAIL will be set. 4. When a block of data is transferred, either DATA_CRC_OK or DATA_CRC_FAIL will be set. The DATA_END bit will be set when data transfer is finished and FIFO is empty. 5. When WRITE_PROTECT is set as 1, the device driver should prevent all write type
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Technical Reference Manual commands from being sent to SD card. 6. Whenever the card is removed or inserted, CARD_CHANGE will be set as 1 (an interrupt will happen if the corresponding mask bit is set as 1), and the device driver should poll. CARD_DETECT bit to determine whether the card is inserted or removed. 7. It is the responsibility of the device driver to prevent all write type commands from being issued when bit 12, WRITE_PROT, is logic 1. 8. The WRITE_RPOT and CARD_DETECT bits directly provide the status of the pin. 9. The interrupt logic will generate the interrupt request signal sdc_intr when at least one of the selected status flags (except WRITE_PROT and CARD_DETECT) is high. A status flag will not generate an interrupt request if the corresponding mask flag is set as 0. Bit 31-13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved WRITE_PROT CARD_DETECT CARD_CHANGE FIFO_ORUN FIFO_URUN DATA_END CMD_SENT DATA_CRC_OK RSP_CRC_OK DATA_TIMEOUT RSP_TIMEOUT DATA_CRC_FAIL RSP_CRC_FAIL Table 24-11. Status Register Type Function R 1: Card is write-protected ; 0: Card is not write-protected R 0: Card is inserted ; 1: Card is removed R Card is inserted or removed R Data FIFO overrun R Data FIFO underrun R Data transfer finished R Command sent (no response required) R Data block sent / received and CRC check passed R Command response received and CRC check passed R Data read / programming timeout R Command response timeout R Data block sent / received but CRC check failed R Command response received but CRC check failed

24.10.2.9. Clear Register (Offset == 0x2C) The clear register is a write-only register. Writing a 1 to the corresponding clear register can clear the corresponding status register. Bit 31-11 10 9 8 7 6 5 4 3 2 Name Reserved CLR_CARD_CHANGE CLR_FIFO_O_RUN CLR_FIFO_U_RUN CLR_DATA_END CLR_CMD_SENT CLR_DATA_OK CLR_RSP_OK CLR_DATA_TIMEOUT CLR_RSP_TIMEOUT Table 24-12. Clear Register. Type Function W Clear CARD_CHANGE flag W Clear FIFO overrun flag W Clear FIFO underrun flag W Clear DATA_END flag W Clear CMD_SENT flag W Clear DATA_CRC_OK flag W Clear RSP_CRC_OK flag W Clear DATA_TIMEOUT flag W Clear RSP_TIMEOUT flag
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Technical Reference Manual 1 CLR_DATA_FAIL W Clear DATA_CRC_FAIL flag 0 CLR_RSP_FAIL W Clear RSP_CRC_FAIL flag 24.10.2.10. Interrupt Mask Register (Offset == 0x30) The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1. Bit 31-11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved Mask10 Mask9 Mask8 Mask7 Mask6 Mask5 Mask4 Mask3 Mask2 Mask1 Mask0 Table 24-13. Interrupt Mask Register. Type Function R/W Mask CARD_CHANGE flag R/W Mask FIFO_O_RUN flag R/W Mask FIFO_U_RUN flag R/W Mask DATA_END flag R/W Mask CMD_SENT flag R/W Mask DATA_CRC_OK flag R/W Mask RSP_CRC_OK flag R/W Mask DATA_TIMEOUT flag R/W Mask RSP_TIMEOUT flag R/W Mask DATA_CRC_FAIL flag R/W Mask RSP_CRC_FAIL flag

24.10.2.11. Power Control Register (Offset == 0x34) The power register controls the external power supply, if any. The supported voltage of the memory card is stored in OCR register. Since the operating voltage can be any value between 2.0V and 3.6V, an appropriate output voltage should be adjusted by the register. Bit 31-5 4 3-0 Name Reserved SD_POWER_ON SD_POWER Table 24-14. Power Control Register Type Function Control the external power supply on / off R/W 1: Power on ; 0: Power off R/W Control the external power supply output range

24.10.2.12.

Clock Control Register (Offset == 0x38)

In card identification mode, the maximum clock frequency is 400 KHz (fOD). During data transfer, the maximum clock rate (fPP) cannot exceed 25 MHz for SD memory card, and 20 MHz for MultiMediaCard. After the relative card address (RCA) is published by the card, the clock frequency can be switched from fOD to fPP. To avoid unpredictable results, do not change the clock rate or disable the clock while the command or data is in progress. Besides, stopping the memory clock should not violate the requirement of memory card spec. Table below shows the bit assignment of the clock control register. After the card initialization process, bit 7 should also be programmed to indicate what kind of card is detected. This bit is used for synchronization of output signals from memory card. Table 24-15. Clock Control Register
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Technical Reference Manual Function 1: SD_CLK is disabled ; 0: SD_CLK is enabled 1: SD memory card ; 0: MMC memory card Control the clock frequency of SD_CLK 6-0 CLK_DIV R/W SD_CLK = PCLK / 2x(CLK_DIV+1) 24.10.2.13. Bus Width Register (Offset == 0x3C) The bus width supported by an SD memory card is defined in SCR register. The value of bit 3 is always logic 1, which indicates the controller is implemented with a 4-bit memory data bus. Writing any value to bit 3 will have no effect. Bit 2 and bit 0 can be programmed by software to transfer data by a 4-bit or 1-bit data bus. If bit 3 is read as logic 0, the controller has only one card data bus. Bit 31-4 3 2 1 0 Table 24-16. Bus Width Register Name Type Function Reserved WIDE_BUS_SUPPORT R 1: 4-bit bus width is implemented WIDE_BUS R/W Bus width = 4 (DAT0-3) Reserved SINGLE_BUS R/W Bus width = 1 (DAT0) Bit 31-9 8 7 Name Reserved CLK_DIS CLK_SD Type R/W R/W

24.10.2.14. Data Window Register (Offset == 0x40) This register acts as a data port when APB device accesses the SD memory card. Whenever the address of an APB cycle matches the address of the data window register, it is forwarded as a data read / write cycle. Bit 31-0 Name DATA_WIN Table 24-17. Data Window Register Type Function R/W Data access port

24.10.2.15. MMC Interrupt Response Time (Offset ===0x44) This register indicates the timing that the MMC host will receive the R5 response after the MMC host send out CMD40 to the MMC card. The rsp_timeout interrupt will assert if the host did not receive response among the assigned time. Bit 7-0 Name MMC_INT_TIME Table 24-18 Type R/W MMC Interrupt Response Time Function MMC interrupt response time

24.10.2.16.

General Purpose Output (Offset === 0x48)

This register drives directly to the output signal of SDC Table 24-19. General Purpose Output

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Technical Reference Manual Bit 31:4 3:0 24.10.2.17. Name Sdc_gpo Type R/W Function Reserved Direct drive the level of the 4 general output ports

SDIO Control Register1

This register indicates the control part of the SDIO host. Table 24-20. SDIO Control Register (Offset: 0x6c) Bit Name Type Function The total block number for a data transfer This field should be set before the data transfer. The 31:15 SDIO_BLK_NO W/R maximum block number in a single data transfer is 131071, the minimum block number is 1. When a SDIO card inserts, set this bit to enable the SDIO 14 SDIO_EN W/R related function. 13 READ_WAIT_EN W/R If the SDIO card support the Read_Wait feature, set this bit If the host wants to initiate a multiple block transaction, set 12 SDIO_BLK_MODE W/R this bit Data size (Bytes) per block In a single block transaction, the maximum block size is 512. 11:0 SDIO_BLK_SIZE W/R In a multiple block transaction, the maximum block size is 2048. Once the SDIO_EN is set, this field records the data block size no matter it is the memory or IO data transfer. 24.10.2.18. SDIO Control Register2 (Offset == 0x70) This register indicates the control part of the SDIO host. Table 24-21. SDIO Control Register Bit Name Type Function 31:2 Reserved When the users need to abort the suspend transaction, this 1 Susp_cmd_abort W/R bit must be set first. Then the abort command can be sent. I This bit must be set before sending out the suspend 0 Susp_read_wait W/R command. The bus will keep the read-wait state until this bit is cleared. 24.10.2.19. SDIO Status Register (Offset === 0x74) This register indicates the status of SDIO host. Bit 31:24 23:17 16:0 Name FIFO_REMAIN_NO SDIO_BLK_CNT Table 24-22. SDIO Status Register Type Function Reserved This field records the number of the valid data (Words) W/R remained in the FIFO. This field records the number of the block remained in a data R transfer..

24.10.2.20. Feature Register (Offset == 0x9C) This register indicates the hardware feature implemented in FTSDC010.

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Technical Reference Manual Table 24-23. Feature Register Bit Name Type Function 31:9 Reserved 0: The SDC does not contain the CPRM function 8 CPRM_FUNCTION R 1: SDC contains the CPRM function FIFO_DEPTH 0x04: FIFO depth is 4 7:0 R 0x08: FIFO depth is 8 0x10: FIFO depth is 16 24.10.2.21. Revision Register (Offset == 0xA0) This register indicates the revision of FTSDC010. For example, if the returned value is 0x0001_0502, it means the revision of FTSDC010 is 1_5_r2. Bit 31:0 Name SDC_REVISION Table 24-24. Revision Register Type Function - Indicate the revision of SDC

24.11. Programming Sequence To read / write data from the SD memory card, the device driver should follow the steps below: 1. 2. 3. 4. 5. Set argument register for CMD16 (optional). Set command register for CMD16 (optional). Set data timer register. Set data length register. Set data control register. Whenever a data transfer is started, the DATA_EN bit should be set as 1. Although the DATA_EN is set, the data state machine will not be activated until the read / write command is sent to memory card. 6. Set argument register for a read / write type command. The device driver must make sure the last command is sent or responded to before setting a new command, since the contents of the argument and command registers are referred to by the host controller during the period of sending a command. 7. Set command register. Once the DATA_EN is set, the following command set in the register should be a read / write type command. The CMD_EN bit should be set as 1 to activate the host command state machine. Note: For commands that are not involved in data transfer, steps 5 and 6 should be skipped. The stop command (CMD12) register should be set after the multiple block read/write cycle is finished. Figure below shows the sequence of writing 512-byte data to SD memory card. To make sure the command is sent or responded to, the device driver should poll the status register (or rely on interrupt).
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Start

Set 0x20 Data Timer Register

SDC will assert sdc_dma_req

Set 0x24 Data Length Register as 0x200

DMAC sends 4 words to SDC, and then assert sdc_dma_ack

Set Data Control Register as 0x74

SDC will deassert sdc_dma_req

Set 0x04 Argument Register for CMD25

No 0x28 Status Register bit 7 = 1 Yes Set 0x00 Command Register as 0x24c (for STOP command)

Set 0x00 Command Register as 0x259

Goal: To write 512 bytes of data to SD memory card Suppose: 1. The block size of the card is set as 16 bytes 2. Multiple block write command CMD25, stop command CMD12 3. Use DMA to transfer data 4. FIFO depth = 4 5. Interrupt is disabled

End

Figure 24-2. Flow Chart of Sending 512-Byte Data to SD Memory Card

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25. Compact Flash Host Interface Controller (CFC)

25.1. General Descriptions The CFC provides a control interface to connect the CompactFlash cards. It supports common memory, I/O, and attribute memory function with 8/16-bit mode for accessing the resource on the CompactFlash card. The CFC supports card insert/remove detection. The CFC supports the following features:

CF specification version 1.4 Attribute memory access, common memory access and I/O access DMA and PIO mode Buffer and reset control function Programmable access cycle time for each access type Programmable 8/16-bit mode Active read/write buffer control function 64-byte buffer size DMA REQ/ACK for large data transfers

Note that the active buffer function is used to reduce the bus loading while transferring a block of data from or to CF card. The controller can perform a background read or write access from or to CF card using an internal register-based buffer. The data can be transferred faster from APB bus to the buffer. All card accesses should use the active buffer controller if CFC is applied to a standard APB device. Figure below shows the block diagram of the CF host interface controller.

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APB Bus PRESETn paddr[5:0] pwdata

DATA

penable

PCLK

psel

APB Slave

pwrite

Control

Control

DATA

Active Buffer data Register

Active Buffer Control Register

CF Host Status Register

Access CF Host Timing Control Register Configuration Register

DATA

prdata

cfc_data[15:0] cfc_addr[10:0]

Active Buffer Control

Control

cfc_nreg cfc_ncd1,cfc_ncd2 cfc_rdy cfc_nce cfc_noe Host Controller cfc_nwe cfc_niord cfc_niowr cfc_nwait cfc_niois16 cfc_reset cfc_bvd1 cfc_bvd2 cfc_nvs1, cfc_nvs2 cfc_pctrl[3:0] cfc_fctrl Power Switch VCC[1:0] CF Slot

ADDR

DATA

cfc_int_data_cmp_r cfc_req_r cfc_ack cfc_int_cd_r

cfc_io_int_r

Figure 25-1. Block Diagram of CF Host Interface Controller 25.2. APB Slave The APB slave receives the command and data from APB bus and passes them to the host interface controller. There are five related registers that can be accessed by APB in the CFC host interface controller. 25.3. Host Controller

The host controller will translate the APB access command in the corresponding command for the CompactFlash interface. The access timing configuration register is used to configure the access timing of the CF host interface controller. The host controller also monitors the card insertion, desertion and RDY/BSY events and informs the processor by asserting an interrupt. 25.4. Active Buffer Control
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Technical Reference Manual The active buffer controller is used to reduce the bus loading while transferring a large amount of data from / to CF card or to support the indirect accessing of standard APB. There is a block of register-based buffer that can be accessed from APB bus using single 32-bit read / write transfer. In block data write, the controller will move data from buffer to CF card in background while the buffer is not empty. If there is at least one empty slot in the active buffer, the controller will inform the master through cfc_req_r to transfer next data word into buffer until the last data word has been transferred. In block data read, the controller will move data from CF card to buffer in background while the buffer is not full. If the buffer is not empty, the controller will inform the master through cfc_req_r to receive the data word in buffer. The master that communicates with the buffer can be a CPU of DMA master. 25.5. Programming Model

25.5.1. Summary of CF Host Interface Controller Registers The CF Host Interface controller registers are shown in the following table: Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 x01C Table 25-1. Type R R/W R/W R/W R/W R/W R/W R/W Summary of CF Host Interface Controller Registers. Description CF Host Status Register CF Host Control Register Access Timing Configuration Register Active Buffer Controller Register Active Buffer Data Register Multi Sector Register Transfer Size Mode2 Enable Register Transfer Size Mode2 Counter Register Reset Value 0x0020 0xF000 0x0 0x0 0x0 0x0

25.5.2. Register Descriptions The following sections describe the CF host interface controller registers in greater detail. 25.5.2.1. CF Host Status Register (Offset == 0x00) This register shows the status of CF host interface controller. Bit 31-18 17 Name cfc_io_int_r Table 25-2. CF Host Status Register Type Description Reserved This signal will be asserted when CF card sets an interrupt R/W in I/O mode through pin cfc_rdy. 1. Card detection toggle interrupt. This interrupt will be asserted when the pin detects there is no card in slot and a R/W card is inserting, or when it detects there is a card in slot and the card is being removed. 2. Write 1 to clear the interrupt. These bits are 0100, which indicates the buffer size is 64 R bytes.
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15-12

Buffer Size

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Technical Reference Manual Bit 11 10 Name cfc_int_data_cmp_r Type R Description Reserved The current active buffer command is completed (read clear bit). Write 1 to clear this bit. If this bit becomes high, the active buffer is ready for data transfer (one word data). In read operation, this bit will be set high if there is at least one word data in the buffer. In write operation, this bit will be set high if there is at least one word slot free for writing. Note: If the transfer size of active buffer control register is less than 4 bytes, this bit will not be used to determine if the data buffer is ready. If the total transfer length is less than 4 bytes, use bit 10 (cfc_int_dma_r) to detect if the data is ready in read operation. Active buffer controller is enabled for transferring a sector of data. This bit will become low until the total length data has been transferred. Reserved Reserved Reserved Reserved Reserved This bit will be asserted high by host controller after the nCD1 and nCD2 are pulled low by CF card. The status change of this pin will also trigger a card insertion / desertion interrupt. Status of the 37th CF interface pin, RDY/nIREQ.

Buffer Data Ready

8 7-6 5 4 3 2 1 0

Buffer Active -

R -

Card Detect RDY/nIREQ

R R

25.5.2.2. CF Host Control Register (Offset = 0x04) This register controls the reset to the CF card. Bits 31-12 11 Name cfc_io_int_mask Table 25-3. Type R/W CF Host Control Register. Description Reserved 1: Mask the interrupt of cfc_io_int_r 0: Not mask the interrupt Note that even if this bit is high, the interrupt status will still be shown in CF Host Status Register. 1: Mask the interrupt of cfc_int_data_cmp_r 0: Not mask the interrupt Note that even if this bit is high, the interrupt status will still be shown in CF Host Status Register. 1: Mask the interrupt of card_detect_int_r 1: DMA mode, using DMA to transfer data 0: PIO mode, using processor to transfer data Reserved The CF host interface controller will treat the CF card as an 8-bit device if this bit is set. In 8-bit mode, any byte
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cfc_int_data_cmp_mask card_detect_int_mask DMA Transfer Mode 8bit Mode

R/W R/W R/W R/W

Technical Reference Manual access to CF card will use only D7-D0 to exchange the data. However, this bit will be ignored if current access type is 16-bit wide. The register out is directly connected to the RESET pin of CF interface. When this pin is high, the signal resets the CF card until this bit is set to zero. Output enable of control output signal of CF interface. When this pin is low, the following control outputs of CF interface will be floated: nOE, nIORD, nIOWR, nCE1, nCE2, nWE, RESET. This bit may be set to zero when system is entering sleep mode or when there is no CF card inserted in slot. Reserved

Reset

R/W

Float Control

R/W

3-0

25.5.2.3. Access Timing Configuration Register (Offset == 0x08) This register configures the access timing of CF host interface controller. Bits 31-16 15-14 13-12 11-8 7-4 3-0 25.5.2.4. Name BSIORW BSMOW BSIO BSM BSA Table 25-4. Access Timing Configuration Register Type Description Reserved R/W Timing configuration of nIORD/nIOWR pulse width R/W Timing configuration of nOE/nWE pulse width R/W I/O access timing configuration register R/W Common memory access timing configuration register R/W Attribute memory access timing configuration register

Attribute Memory Access Timing

Attribute Memory Read Timing Specification PCLK tc(R) nREG An nCE nOE tsu(A) Din

th(A)

Figure 25-2. Attribute Memory Read Timing Specification

Configuration Register Write Timing Specification PCLK tc(W) nREG An nCE tw(WE) nWE tsu(A) Dout
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Technical Reference Manual Figure 25-3. Configuration Register Write Timing Specification Table 25-5. Attribute Memory Access Timing Table Item Symbol Cycle Count Read Cycle Time tc 6 Address Setup Time tsu(A) 1 Address Hold Time th(A) 1 Write Cycle Time tc(W) 5 Write Pulse Width tw(WE) 3 Data Hold Time th(D) 1 Access Timing Cycle Count * (BSA+1) * PCLK Cycle Time 25.5.2.5. Common Memory Access Timing

Common Memory Write Timing Specification PCLK An nCE tw(WE) nWE tsu(A) nWAIT tv(WT_WE) Dout

th(D)

Figure 25-4. Common Memory Write Timing Specification

Common Memory Read Timing Specification PCLK An nCE tw(OE) nOE tsu(A) tv(WT_OE) nWAIT Din

th(A)

Figure 25-5. Common Memory Read Timing Specification Common Memory Access Timing Table Item Symbol Cycle Count Address Setup Time tsu(A) 1 OE Pulse Width tw(OE) BSMOW+2 WE Pulse Width tw(WE) BSMOW+2 Wait Delay Falling from OE [1] tv(WT_OE) 1 Wait Delay Falling from WE[1] tv(WT_WE) 1
[1]

Table 25-6.

The timing of host detecting the nWAIT status.

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Technical Reference Manual Address Hold Time Data Hold Time Access Timing 25.5.2.6. th(A) 1 th(D) 1 Cycle Count * (BSM+1) * PCLK Cycle Time

I/O Access Timing Specification

I/O Read Timing Specification PCLK nREG An nCE nIORD tsuA(IORD) tsuIOIS16(IORD) nIOIS16 nWAIT tdWT(IORD) Din

tw(IORD) thA(IORD)

Figure 25-6. I/O Read Timing Specification

I/O Write Timing Specification PCLK nREG An nCE nIOWR tsuA(IOWR) tsuIOIS16(IOWR) nIOIS16 nWAIT tdWT(IOWR) Dout

tw(IOWR) th(IOWR)

Figure 25-7. I/O Write Timing Specification Table 25-7. I/O Access Timing Table. Item Symbol Address Setup Time tsuA(IORD,IOWR) IORD/IOWR Pulse Width tw(IORD,IOWR) [2] IOIS16 Setup from IORD/IOWR tsuIOIS16(IORD,IOWR) Wait Delay Falling from IORD/IOWR[1] tdWT(IORD,IOWR) Address / Data Hold Time thA(IORD),th(IOWR) Access Timing Cycle Count * (BSIO+1) * PCLK Cycle Time 25.5.2.7. Active Buffer Control Register (Offset == 0x0C) The active buffer control register is used to control the action of the active buffer. Table 25-8. Bit
[2]

Cycle Count 2 BSIORW+3 1 1 1

Active Buffer Control Register Description

Name

Type

The timing of host detecting the nIOIS16 status.

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Technical Reference Manual Bit Name Type Description Transfer Size: 0000: reserved 0001: 1 byte 0010: 2 bytes 0011: 4 bytes 0100: 8 bytes 0101: 16 bytes 0110: 32 bytes 0111: 64 bytes 1000: 128 bytes 1001: 256 bytes 1010: 512 bytes 1011: 1024 bytes 1100: 2048 bytes 1101: reserved 1110: reserved 1111: reserved Note that for I/O mode, the masimum transfer size is 512 bytes only Read / Write Control. Defines the current access type. If this bit is high, the current transaction is a write access to CF card. If this bit is low, the current transaction is a read access from CF card. 0: Read operation 1: Write operation Increment target / source address by 2. If this bit is high, the read / write address will increase by 1 or 2, depending on the m8 bit, after each access. If this bit is low, the read / write address will keep the original value after each access. Access Type. 00: Attribute memory function 10: Common memory function 11: I/O function 01: Reserved Reserved Target / Source Address. The address will be used by active buffer control to access the CF card.

19-16

SIZE

R/W

15

RW

R/W

14

INCADR

R/W

13-12

TYPE

R/W

11 10-0

ADR

R/W

25.5.2.8. Active Buffer Data Register (Offset == 0x10) The data register is a read / write port for the master to access the buffer sequentially. Bit 31-0 Name Data Table 25-9. Active Buffer Data Register. Type Description The data register can be read or written by master only when the Buffer Ready bit is high in CF Host Status Register. Any access R/W to the data register while Buffer Ready bit is low will get an unpredictable result.

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Technical Reference Manual 25.5.2.9. Bit 7-1 Multi Sector Register (Offset == 0x14) Table 25-10. Multi Sector Register Name Type Description The number of PCLK the CFC will wait before checking cfc_rdy each time one sector is transferred. Multi-Sector Timeup R/W The CF card will be considered ready when cfc_rdy is high at this time, or the CF controller will wait until cfc_rdy becomes high before accessing the next sector. 0 = Disable Multi-Sector Read/Write Enable Multi-Sector R/W 1 = Enable Multi-Sector Read/Write Transfer Size Mode2 Enable Register (Offset == 0x18) Table 25-11. Transfer Size Mode2 Enable Register Name Type Description 0: The transfer size is decided by register 0x0C [19:16]. Trans_Size_Mode2_E R/W 1: The transfer size is decided by register 0x1C [16:0]. n Transfer Size Mode2 Counter Register (Offset == 0x1C)

25.5.2.10. Bit 0

25.5.2.11. Bit

16-0

Table 25-12. Transfer Size Mode2 Counter Register Name Type Description 17h0: 1 byte 17h1: 2 bytes 17h2: 3 bytes Trans_Size_Mode2_Cn 17h3: 4 bytes R/W t 17h4: 5 bytes --17hffff: 128K bytes Note: For IO mode, the max. transfer size is 512 bytes only.

25.6. DMA Handshaking Protocol The cfc_req_r will be asserted high if the CF host interface controller requests for the next transaction. The DMA controller will issue an APB transaction after receiving a request. After the DMA controller finishes the transaction, the cfc_ack will be asserted high to inform the CF host interface controller that the current transaction is completed. The CF host interface controller will de-assert the cfc_req_r to confirm the cfc_ack signal. If there is still data waiting to be transferred, the CF host interface controller will assert cfc_req_r high to proceed with the next transaction.
DMA Handshaking Protocol PCLK psel penable cfc_req_r cfc_ack

Figure 25-8. DMA Handshaking Protocol

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Technical Reference Manual 25.7. Programming Sequence

25.7.1. Work flow of Active Buffer Controller The write operation to Active Buffer Control Register will start transaction of a sector, so other registers must be programmed before doing write operation to this register. The Buffer Active bit in CF Host Status Register will be set high until the transaction is finished. Any read operation from Active Buffer Control Register will not trigger a transaction. The host controller will inhibit modifications to Active Buffer Control Register, CF Host Control Register and Multi-Sector Register until the current transaction is finished. 25.7.1.1. Read Operation 1. If the DMA controller is the master of this transaction, allocate a block of DMA buffer in memory and initialize the DMA controller properly. 2. 3. 4. 5. 6. 7. 8. Set proper values of the transfer size, read operation, address increment, access type, and starting address into Active Buffer Control Register to initialize the transaction. The Active Buffer Controller will proceed with the operation defined in Active Buffer Control Register to fill the buffer. If the master is the DMA controller, go to step 5. If the master is the processor, go to step 6. If there is at least one word data in the buffer, the CFC controller will send cfc_req_r to DMA controller to request data transfer of a single word. Go to step 7. The processor should check the Buffer Data Ready bit in status register to make sure the data buffer is ready before reading the Active Data Register. If the transfer size does not reach the pre-defined size in Active Buffer Control Register and there is at least one free slot for writing, repeat from step 3. If the last data in the buffer of the current transfer has been drained out, the host controller will assert the signal cfc_int_dma_r high to inform the processor that the current transaction is completed. 9. The read transaction is completed. Write Operation

25.7.1.2. 1. 2. 3. 4.

If the DMA controller is the master of this transaction, allocate a block of DMA buffer in memory and initialize the DMA buffer and DMA controller properly. Set proper values of transfer size, write operation, address increment, access type, and starting address into Active Buffer Control Register to initialize the transaction. The Active Buffer Controller will proceed with the operation defined in Active Buffer Control Register to fill the buffer. If the master is the DMA controller, go to step 5. If the master is the processor, go to step 6.

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Technical Reference Manual 5. 6. 7. 8. If there is at least one word-free slot in the buffer, the CFC controller will send cfc_req_r to DMA controller to request data transfer of a single word. Go to step 7. The processor should check the Buffer Data Ready bit in status register to make sure the data buffer is free before writing the Active Data Register. If the transfer size does not reach the pre-defined size in Active Buffer Control Register and there is at least one free slot for reading, repeat from step 3. If the last data in the buffer of the current transfer has been drained out, the host controller will assert the signal cfc_int_dma_r high to inform the processor that the current transaction is completed. 9. The write transaction is completed.

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26. UART and IrDA Controller

26.1. General Descriptions The aJ-200 includes three UARTs and one IrDA/UART device. The UART is a serial communication device that is backward compatible to the 16550 UART. The IrDA/UART controller is a serial communications element that implements the most common infrared communications protocols and communication device that is backward compatible to the 16550. The UARTs and IrDA/UART use the same programming model. The UART1 supports modem capability. The UART2 provides a partial set of modem control pins including CTSn and RTSn. The UART3 does not provide any modem control pins. The IrDA/UART4 includes a IrDA module that operates at half duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers. The four UARTs can support baud rates up to 1,152 Kbps. All UART pins are shared with GPIO pins under software control. It supports the following features: NS 16C550A-compatible UART Programmable baud rates up to 1152 Kbps Ability to add or delete standard asynchronous communications bits (start, stop, and parity) in the serial data Programmable baud rate generator that allows the internal clock to be divided by 1 to (216-1) to generate an internal 16 x clock Fully programmable serial interface:
o o o

5-, 6-, 7-, or 8-bit characters Even, odd, and no parity detection 1, 1.5, or 2 stop bit generation

Complete status reporting capability Ability to generate and detect line breaks Fully prioritized interrupt system controls Separate DMA requests for transmit and receive data services Break, parity, overrun, framing error simulation for UART mode UART1 provides 16-byte transmit FIFO and 16-byte receive FIFO UART2 provides 32-byte transmit FIFO and 32-byte receive FIFO UART3 provides 16-byte transmit FIFO and 16-byte receive FIFO IrDA 1.3 SIR with data rates up to 115.2 Kbps

The IrDA/UART4 controller supports the additional IrDA features:

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SIR pulse width is programmable as 1.6 s or 3/16 of the baud-rate pulse width IrDA 1.3 FIR support Multi-frame transmission and reception in FIR mode Back-to-back infrared frame transmission and reception in FIR mode 32-bit IEEE 802 CRC32 hardware CRC generators and checkers for FIR communications Provide 128-byte transmit FIFO and 128-byte receive FIFO Support DMA REQ/ACK for large data transfers

Figure below shows the block diagram of the UART and IrDA Communications Controller.
Shared I/O Mux Shared IO Mux

io_irda_sin io_irda_uclk

RxD1,2,3,4

Prescaler

Baudrate Generator

UART Interface
io_irda_sout

TxD1,2,3,4

PRSTn PCLK paddr[6:2] psel penable pwrite pwdata[7:0] prdata[7:0]

8 5

UART4
io_irda_rxl io_irda_sout

APB Interface

Tx FIFO 16,32,128 Bytes Rx FIFO 16,32,128 Bytes

SIR Logic

SIP Generator

UART4
io_irda_tx_r

FIR Logic Status FIFO

io_irda_rxh

Shared I/O Mux

IrDA_RXH

Configuration & Status Registers

irda_nddis

Interrupt Controller

irda_intr1 irda_intr2 irda_dma_req_r

irda_dma_ack

irda_tx_ack irda_rx_ack

Tx FIFO Controller

irda_ntxrdy irda_nrxrdy

Rx FIFO Controller
io_irda_ncts io_irda_nrts

CTS1,2n DSR1n RI1n DCD1n

Shared I/O Mux Shared I/O Mux Shared I/O Mux Shared I/O Mux

Shared I/O Mux Shared I/O Mux

io_irda_nout1 io_irda_nout2 io_irda_nout3

RTS1,2n DTR1n

io_irda_ndsr

io_irda_ndtr

io_irda_nri

Modem Control and Flags

io_irda_ndcd

Figure 26-1. Block Diagram of UART and IrDA Communications Controller

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Technical Reference Manual The main building blocks of IrDA Communications Controller are described below. 26.2. APB Interface

The APB interface services the accesses to the controller registers and data FIFOs. 26.3. Prescaler

The prescaler divides the io_irda_uclk by divisors of 1 to 25-1, and produces a pre-divided clock PB16XCLK to the baud rate generator. The prescaler also recovers the sampling clock from the received signal in FIR mode. The clock PB16XCLK derived from the prescaler is used to sample the received signal in FIR mode. 26.4. Baud Rate Generator

The baud rate generator is capable of dividing the pre-divided clock PB16XCLK by divisors of 1 to 216-1, and producing a 16 times baud clock B16XCLK. 26.5. Tx FIFO and Rx FIFO

Both Tx and Rx FIFOs are 8-bit wide, 16/32-location deep. CPU data written across the APB interface is stored in the Tx FIFO until read out by the transmit logic. Received data are stored in the receive FIFO by the receive logic until read out by the CPU across the APB interface. Both FIFOs can be disabled to act like a one-byte holding register. The FIFOs are enabled or disabled using the FIFO Control Register (FCR). When the FIFOs are disabled, the behavior is the same as if they had not been implemented. The UART working without FIFOs is what is commonly called the 16450 mode, due to the name of the industry standard UART without FIFOs. In SIR and FIR modes, the Tx FIFO and Rx FIFO should always be enabled. 26.6. Status FIFO

During data reception, the corresponding error bits, i.e. Parity Error, Framing Error and Break conditions, are stored in the Status FIFO (STFIFO). Disabling the Tx/Rx FIFOs will also disable the status FIFO. The status FIFO is also used in FIR mode. It is always an 8-level FIFO and is intended to support back-toback incoming frames in DMA mode. Each status FIFO entry contains both status information and frame length for a single frame. The status FIFO is flushed when hardware reset occurs or when the Rx FIFO is soft reset. The status and length information of received frames is loaded into the status FIFO whenever the DMA_EN bit in the MDR register is set to 1. 26.7. Configuration and Status Registers

The register files store data written, or to be read, across the AMBA APB interface. 26.8. Modem Control and Flags
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Technical Reference Manual This block controls the interface with the modem and provides the current state of the control lines from the modem (or peripheral device) to the CPU. 26.9. SIR Logic

The SIR logic includes SIR encoder and decoder. The encoder converts UART zeros to light pulses and ones to no pulses. The converted optical pulse duration can be 3/16 of a bit duration or 1.6 s by programming ACR [7]. The decoder will stretch a valid light pulse to a single bit cell of zero (low) level and no light pulses to ones (high). 26.10. FIR Logic The FIR logic includes FIR encoder / decoder and transmitter / receiver. The FIR encoder uses Four Pulse Position Modulation (4PPM) scheme, in which 2 bits of data (symbol) are encoded into a 4-bit cell chip. Each bit cell or chip is 125 ns wide, so each input byte (symbol) requires 2 s to send. Unlike SIR, chips with logic 1 will produce a light pulse, and chips with logic 0 will produce no light pulse. The decoder takes a valid light pulse as a single chip with logic one and no light pulses to zeros, and de-modulates the 4PPMencoded input signal to its raw data. 26.11. SIP Generator During the FIR mode of operation, the SIP generator sends a 1.6 s Serial Infrared Interaction Pulse (SIP) according to the setting of MDR [2] and ACR [4]. 26.12. Modes of Operation The UART/IrDA operates in three different modes. For proper operation, the device must be programmed correctly for each mode. The various modes of operation include: o o o Universal asynchronous receiver transmitter (UART) mode. All four UARTs support Slow-speed infrared (IrDA SIR) mode. Only UART4 supports this mode Fast-speed infrared (IrDA FIR) mode. Only UART4 supports this mode

Basic data communication involves at least two devices. In the data transmission mode, the first device transmits data and the second device receives the transmitted data. In the data reception mode, the second device transmits the data and the first device receives the data. When the FIrDA is configured for the UART mode, both data transmission and data reception can occur simultaneously, which is known as full duplex operation. In the infrared (IR) modes, either data transmission or data reception is possible at any time but not simultaneously, which is known as half duplex operation. 26.13. UART Mode The UART mode is the default mode of operation after power up and system reset. This mode uses a wired interface for serial communication with a remote device or a modem. The UARTs can operate in a
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Technical Reference Manual full-duplex mode, i.e. data transmission and reception can take place simultaneously. The UARTs in the UART mode works as a regular serial asynchronous communication controller that converts the parallel data received from the CPU or the DMA controller into serial data. It also converts the serial data received on the serial input terminal into parallel data. The character is commonly used to describe a word of data being transmitted serially. A character can have several possible word lengths, including 5-, 6-, 7- or 8-bit managed by this module. This mode is designed to support serial data communications with a remote peripheral device or modem using a wired interface. The controller provides transmit and receive channels that can operate concurrently to handle full-duplex operation. They perform parallel-to-serial conversion on data characters received from the CPU or a DMA controller, and serial-to-parallel conversion on data characters received from the serial interface. The format of the serial data stream is shown figure below.
Start DATA (B5h, 7-bit word length) Parity (odd) Stop

Sample Point

Figure 26-2. UART Data Representation and Sampling A data character contains 5 to 8 data bits. It is preceded by a start bit and is followed by an optional parity bit and a stop bit. Data is transferred in little endian order (least significant bit first). The UART mode is the default mode of operation after power up or reset. In fact, after reset, the 16450compatibility mode is selected. In addition to the 16450 and 16550 compatibility modes, IrDA modes are also available. When the FIR mode is selected, the interrupt sources are no longer prioritized. The additional features include transmitter FIFO threshold, DMA capability, and interrupts on transmitter empty. The clock for both transmit and receive channels is provided by an internal baud generator that divides the pre-scaled clock by any divisor value from 1 to 2 16 - 1. The output clock frequency of the baud generator must be programmed to be sixteen times the baud rate value. The baud generator input clock is derived from io_irda_uclk clock through a programmable prescaler. The PSR register determines the prescaler value. Its default value is 0x01. Both the communications format and baud rate must be programmed properly before operation. The communications format is programmed by setting the LCR register, while the baud rate is selected by programming the baud generator divisor registers (DLL and DLM). The software can read the status of the device at any time during operation. The status information includes state for FIFO, and any other

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Technical Reference Manual condition detected on the received data stream, like parity error, framing error, data overrun, or break event. 26.14. IrDA 1.3 SIR Mode This is the first operational mode that has been defined by the IrDA committee. It supports bi-directional data communication with a remote device using infrared radiation as the transmission medium. IrDA 1.3 SIR allows serial communication at baud rates up to 115.2 Kbaud. The format of the serial data is similar to the UART data format. Each data word is sent serially beginning with a zero value start bit, followed by 8 data bits, and ending with at least one stop bit with a binary value of one. Sending a single infrared pulse signals a zero. A one is signaled by not sending any pulse. The width of each pulse can be either 1.6s or 3/16ths of a single bit time. (1.6s equals 3/16ths of a bit time at 115.2 Kbaud). This way, each word begins with a pulse for the start bit. The device operation in IrDA SIR mode is similar to the operation in UART mode. The main differences are that, those data transfer operations are normally performed in half-duplex fashion. Selection of the IrDA SIR mode is controlled by the mode select bits in the MDR register. Each data byte starts with a start bit (0), 1 byte of data, and then ends with at least a stop bit (1). Each serial data bit is encoded before transmission and decoded after reception. A 1 is decoded with no IR pulse and a 0 is decoded by sending 3/16ths of one bit time IR pulse. Similarly, the received serial pulse is decoded as a 0 and the absence of an IR pulse is decoded as a 1.
Transmit Data

IR Output

3/16

3/16

Figure 26-3. SIR Encoding 26.15. IrDA 1.3 FIR Mode The UART4 supports both IrDA 1.3 FIR mode, with data rates of 4.0 Mbps. Details on the frame format, encoding schemes, CRC sequences, etc. are provided in the appropriate IrDA documents. The FIR transmitter front-end section adds the preamble as well as Start and Stop flags to each frame and encodes the transmit data into a Four Pulse Position Modulation (4PPM) data stream. The FIR receiver front-end section strips the preamble and flags from the inbound data stream and decodes the 4PPMencoded data while also checking for coding violations. The FIR front-end also automatically appends CRC sequences to the transmitted frames and checks for CRC errors on received frames. 26.15.1.
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Technical Reference Manual There are two ways a transmission frame can be properly terminated in FIR mode: frame-length method and set-EOT bit method. The two methods are described as follows: 26.15.1.1.

Frame-Length Counter method

This method can be used when data transfers are performed in either PIO or DMA mode. This method is selected when the MDR [3] bit equals 0. The CPU writes the frame-length value to the TXLENH and TXLENL registers. The device automatically attaches an ending flag to the frame when the number of bytes transmitted becomes equal to the TXLENH and TXLENL value. This method also allows a large data block to be automatically split into equal-size back-to-back frames and can add an equal-size or different-size frame in PIO or DMA mode. The length of the last frame is defined in the registers LSTFMLENH and LSTFMLENL. The number of frames to be transmitted is defined in LSTFMLENH [7:5]. For example, when LSTFMLENH [7:5] are programmed as zeros, the data in Tx FIFO will always be transmitted as equal-size frames (the 4-byte CRC is not shown in the figure for simplification): When LSTFMLENH [7:5] are programmed as non-zeros, say 3, the data in Tx FIFO will always be transmitted as three (3) equal-size frames plus one (1) equal- or different-size frame:
TXLEN TXLEN TXLEN TXLEN

Note: When MDR [2] bit is set as 0, the SIP will not be issued until all back-to-back frames are transferred, i.e. Tx FIFO is empty. 26.15.1.2. Set-EOT bit method

This method is used when data transfers are performed in PIO mode. This method is selected when the MDR [3] bit equals 1. The CPU writes a 1 to the SET_EOT bit of the ACR register just before it writes the last byte to the Tx FIFO. When the CPU writes the last byte to the Tx FIFO, the device internally sets the tag bit for that particular byte in the Tx FIFO. As the UART in the transmission mode reads bytes from the Tx FIFO, the flag-bit information is used to attach an ending flag and properly terminate the frame. 26.15.2. FIR Data-Receive Method in PIO mode

When the data reaches the set threshold level of the Rx FIFO, the device interrupts the CPU. When the CPU is interrupted, it reads the FMIIR_PIO to identify the source of the interrupt. When the source of the interrupt is the FMIIR_PIO [0] bit and not the FMIIR_PIO [4] bit, the CPU goes to the threshold mode as follows. 26.15.2.1. Threshold Mode

During threshold mode, the CPU reads a number of bytes (determined by the Rx FIFO threshold level)

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Technical Reference Manual from the Rx FIFO. For example, when the Rx threshold value is set to be 16, the CPU can perform 16 consecutive read operations from the Rx FIFO. When the source of interrupts is the FMIIR_PIO [4] bit, the CPU should read the RXFF_CNTR to determine the number of data bytes in the Rx FIFO when an end-offrame (EOF) flag is detected. 26.15.2.2. Serial Infrared Interaction Pulse During the FIR mode of operation, the transmitter sends a 1.6s Serial Infrared Interaction Pulse (SIP) at least once every 500 ms. The purpose of this special pulse is to inform the slow device (in SIR mode) that the high-speed device involved in data transaction is currently occupied. When the MDR [2] bit is a 0 (the default value), the IrDA/UART4 in the transmission mode always sends a 1.6s pulse at the end of a transmission frame. However, when bit MDR [3] is a 1, the transmission of a 1.6s pulse depends on the value of ACR [4]. The CPU keeps a timer and sets the ACR [4] at least once in every 500ms. When the MDR [3] is set as 1, the IrDA/URAT4 in transmission mode sends a 1.6s pulse only if the ACR [4] bit is a 1. The advantage to this approach over the default value (always sending 1.6s pulse at the end of a frame) is that the IrDA/UART4 in the transmission mode need not send the special 1.6s pulse at the end of every frame. Sending a 1.6s pulse at the end of every frame may increase overhead.
8.7s 1.6s

Serial Infrared Interaction Pulse

Figure 26-4. Serial Infrared Interaction Pulse 26.16. Tx FIFO Underrun in FIR Mode An underrun during data transmission occurs when the CPU fails to supply the data to the Tx FIFO. The Tx FIFO becomes empty before the end of the frame is transmitted. When an underrun occurs, the IrDA/UART4 closes the frame with an ending flag but attaches an incorrect CRC value. The receiving device detects the CRC error and discards the frame. The IrDA/UART4 sets an internal flag and further transmission of data is disabled. The CPU must reset the Tx FIFO and read the RESUME register. This read operation clears the internal flag. 26.17. Rx FIFO Overrun in FIR Mode An overrun occurs during data reception if the CPU cannot timely read out data from the Rx FIFO and the Rx FIFO is overwritten. When an overrun occurs in PIO mode, the IrDA/UART4 interrupts the CPU with the FMIIR_PIO [2] bit and discards the remaining portion of the frame. When an overrun occurs, the
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Technical Reference Manual IrDA/UART4 sets an internal flag and the receive operation of the next frame is disabled. Before the next frame can be received, the CPU must reset the Rx FIFO and read the RESUME register. This read operation clears the internal flag. When an Rx FIFO overrun occurs in DMA mode, the receiver continues to receive further frames. The status of data reception will be reported in the status FIFO. 26.18. St FIFO Overrun in FIR Mode The St FIFO overrun occurs during data reception if the CPU cannot timely read out data from the St FIFO and the St FIFO is overwritten. The St FIFO overrun occurs only in DMA mode. The IrDA/UART4 interrupts the CPU with the FMIIR_DMA [2] bit and stops receiving the next frame. Then the IrDA/UART4 sets an internal flag and the receive operation of the next frame is disabled. Before the next frame can be received, the CPU may read out data from St FIFO or reset St FIFO and read the RESUME register. This read operation clears the internal flag. 26.19. DMA Operation in FIR Mode The DMA mode of data transfer is used to achieve faster data transfer when the IrDA/UART4 is operating in the FIR mode. In a multi-application environment, where multiple applications are running at the same time, the DMA mode should be used to keep up with the high rate of data transfer without having underrun during data transmission or overrun during data reception. Frames can be transmitted and received backto-back. 26.20. DMA Data-Transmit Mode In DMA mode, packets are automatically fragmented into equal-sized frames, (decided by the TXLENH and TXLENL register values) and properly transmitted. The last portion of the packet, which may be different from the (TXLENH, TXLENL) register values, can be transmitted back-to-back by programming LSTFMLENL and LSTFMLENH registers properly. If LSTFMLENH [7:5] are programmed as zeros, the interrupt FMIIR_DMA [5] bit is generated to inform the CPU whenever a frame is transmitted. If LSTFMLENH [7:5] are programmed as non-zeros, the interrupt FMIIR_DMA [5] bit is generated to inform the CPU the data transmission is completed when all frames are transmitted. The FTUART010 asserts the irda_dma_req_r signal when the number of bytes in the Tx FIFO falls below the set trigger level and de-asserts the irda_dma_req_r when the irda_dma_ack is sampled high. 26.21. DMA Data-Receive Mode The DMA controller controls the data reception of back-to-back frames. The back-to-back frames are transferred to memory and the status of each received frame is stored in the Status FIFO that can hold up to 8 entries. Each entry in the Status FIFO corresponds to one received frame. Each entry stores the
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Technical Reference Manual length of each received frame and the error-status of that frame. The CPU reads the Status FIFO entries to locate the frame boundaries and status of individual frames inside memory. The Status FIFO has 4 interrupt levels, which are 1, 4, 7, and 8. In a data receive transaction, the receiver expects to receive 1 to 7 frames. When the number of received frames becomes equal to or greater than the set threshold value in the Status FIFO, the IrDA/UART4 generates an interrupt FMIIR_DMA [0] bit. After the CPU receives the Status FIFO interrupt (FMIIR_DMA [0 ] bit), it reads the STFF_STS register to determine the error-status of that frame. The Status FIFO Received Frame Length Low (STFF_RXLENL) and the Status FIFO Received Frame Length High (STFF_RXLENH) are read to determine the length of the frame. The CPU checks the content of the bit STFF_STS [5] which is set to a 1 when this entry of Status FIFO is valid. If this bit is found to be a 0, the CPU should stop reading the STFF_RXLENL and STFF_RXLENH. The STFIFO timeout interrupt (bit FMIIR_DMA [1]) is set at 1 ms. This is useful when the number of frames in a data receive transaction is less than the set Status FIFO threshold level. When the CPU receives a Status FIFO timeout interrupt, it should read STFIFO_STS, STFF_RXLENL, and STFF_RXLENH registers until bit STFF_STS [4] is 0 (indicates entry invalid). The STFIFO Time-out Conditions are: At least one entry is in the STFIFO, and More than 1 ms has elapsed since the last byte was loaded into the STFIFO from the receiver logic, and More than 1 ms has elapsed since the CPU read the last entry from the STFIFO.

The FTUART010 asserts the irda_dma_req_r signal when the Rx FIFO is not empty. The irda_dma_req_r is de-asserted when the irda_dma_ack is sampled high. An overrun in the Rx FIFO in the DMA mode is handled differently than in the programmed I/O mode. When an overrun occurs in the Rx FIFO, during any frame, data reception is terminated and the receiver state machine waits for the next frame. It continues to receive the further frames. The RXFIFO_ORUN is set to a 1 in the STFF_STS register for the frame in which Rx FIFO overrun has occurred. 26.22. Programming Model 26.22.1. Summary of UART and IrDA Communications Controller Registers Table 26-1. Summary of UART/SIR Mode Registers Offset Type Width Name Description UART / Infrared SIR Mode R 8 RBR Receiver Buffer Register 0x00 W 8 THR Transmitter Holding Register 0x04 R/W 4 IER Interrupt Enable Register R IIR Interrupt Identification Register 0x08 8 W FCR FIFO Control Register
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Technical Reference Manual Offset Type Width Name 0x0C R/W 8 LCR 0x10 R/W 7 MCR R LSR 0x14 8 W TST 0x18 R 8 MSR 0x1C R/W 8 SPR Registers accessible when DLAB =1 0x00 0x04 R/W R/W 8 8 DLL DLM PSR MDR ACR TXLENL TXLENH MRXLENL MRXLENH PLR FMIIR_PIO 0x3C R 5 FMIIR_DMA FMIIER_PIO 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 26.22.2. 26.22.2.1. R/W R R R R R/W R R R/W R/W 5 FMIIER_DMA 5 8 5 8 8 5 8 8 STFF _STS STFF_RXLENL STFF_RXLENH FMLSR FMLSIER RSR RXFF_CNTR LSTFMLENL LSTFMLENH Description Line Control Register Modem Control Register Line Status Register Testing Register Modem Status Register Scratch Pad Register Baud Rate Divisor Latch Least Significant Byte Baud Rate Divisor Latch Most Significant Byte Prescaler Register Mode Definition Register Auxiliary Control Register Transmitter Frame Length Low Transmitter Frame Length High Maximum Receiver Frame Length Low Maximum Receiver Frame Length High FIR Preamble Length Register FIR Mode Interrupt Identification Register in PIO Mode FIR Mode Interrupt Identification Register in DMA Mode FIR Mode Interrupt Enable Register for PIO Mode FIR Mode Interrupt Enable Register for DMA Mode Status FIFO Line Status Register Status FIFO Received Frame Length Register Low Status FIFO Received Frame Length Register Low FIR Mode Link Status Register FIR Mode Link Status Interrupt Enable Register Resume Register Rx FIFO Count Register Last Frame Length Register Low Last Frame Length Register High Reset Value 0x00 0x00 0x60 0x00 0x00 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00 0x00 0x00

0x08 R/W 5 Infrared FIR Mode 0x20 R/W 7 0x24 R/W 8 0x28 R/W 8 0x2C R/W 5 0x30 R/W 8 0x34 R/W 5 0x38 R/W 2

Registers Descriptions Receiver Buffer Register (Offset == 0x00 for read)

The user can get the data by reading this read-only location. It is the data read port of the Rx FIFO or 1byte register depending on whether the FIFOs are enabled or not.

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Technical Reference Manual If the FIFOs are enabled. This location refers to the top of 16-byte FIFO (i.e. the next to be read). If the FIFOs are not enabled. This location refers to a 1-byte register (the bottom word of the receive FIFO) that receives the contents of the receiver shift register once a character has been assembled. Bit 7-0 Name RBR Table 26-2. Receiver Buffer Register Type Function R Receive Data Port Transmitter Holding Register (Offset == 0x00 for write)

26.22.2.2.

The transmitter holding register is used to write the transmitter holding register or the transmit FIFO depending on whether the FIFOs are enabled or not. If the FIFOs are enabled. Data written to this location is pushed onto the transmit FIFO. If the FIFOs are not enabled. Data written to this location is stored in the transmitter holding register (the bottom entry of the transmit FIFO). If the transmitted character width is less than 8 bits, it must be right-justified. Left bits (i.e. MSB) are dont care bits. For example, with a word length of 5 bits, writing 0xd3 or 0xf3 will result in the transmission of a 13h character. Before writing this register, the user must ensure that the UART is ready to accept data for transmission, for example checking that THR Empty flag is set in the LSR (see the description of this register below). Table 26-3. Transmitter Holding Register Type Function W Transmit Data Port Interrupt Enable Register (Offset == 0x04)

Bit 7-0

Name THR

26.22.2.3.

This register individually enables each of the possible interrupt sources. A logic 1 in any of these bits enables the corresponding interrupt, while a logic 0 disables it. For a detailed description of the interrupt sources, see the description of the Interrupt Identification Register (IIR) below. Bit 7:4 3 2 1 Name Reserved MODEM Status Receiver Line Status THR Empty Table 26-4. Interrupt Enable Register Type Function R/W This bit enables the Modem Status Interrupt when set to logic 1. This bit enables the Receiver Line Status Interrupt when set to R/W logic 1. This bit enables the Transmitter Holding Register Empty R/W Interrupt when set to logic 1.

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Technical Reference Manual Receiver Data Available This bit enables the Received Data Available Interrupt (and character reception timeout interrupts in the FIFO mode) when set to logic 1.

R/W

26.22.2.4. Interrupt Identification Register (Offset == 0x08) The main purpose of this register is to identify the interrupt with the highest priority that is currently pending. The FUART implements a priority encoder with four levels from highest priority to lowest priority, as follows: 1. 2. 3. 4. Receive Line Status (highest priority) Receive Data Ready and Character Reception Timeout (second priority) Transmitter Holding Register Empty (third priority) Modem Status (lowest priority)

Table below describes the different interrupt conditions and their codes of identification, together with their reset method. Bit 7:6 5 4 3 Table 26-5. Name Type FIFO mode enable R Reserve R TxFIFO full R FIFO mode only R Interrupt Identification Register Function These two bits are set when FCR [0] is set as 1. These two bits of the IIR are always logic 0. This bit is set as 1 when Tx FIFO is full. In the 16450 Mode, this bit is 0. In the FIFO mode, this bit is set along with bit 2 when a timeout interrupt is pending. These bits identify the highest priority interrupt that is pending. Table 569 below describes the different interrupt conditions and their codes of identification, together with their reset method. Note that for an interrupt source to be considered as pending, the corresponding bit in the IER must be enabled. This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending. 0 An interrupt is pending and the IIR contents may be used as a pointer to the appropriate interrupt service routine. 1 No interrupt is pending. Interrupt Control Table

2:1

Interrupt Identification Code

Interrupt Pending

Table 26-6. FIFO Mode Only Bit 3 0 0 Bit 2 0 1 Bit 1 0 1 Interrupt Identification Register Priority Bit 0 Level 1 ---0

Interrupt Set and Reset Functions Interrupt Source Description There is no interrupt pending. There is an overrun error, parity error, framing error or break interrupt indication
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Interrupt Reset Method None Read the Line Status Register (LSR)

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Technical Reference Manual Interrupt Identification Interrupt Set and Reset Functions Register Priority Interrupt Interrupt Source Bit 0 Level Type Description corresponding to the received data on top of the receive FIFO. Note that the FIFO error flag in LSR does not influence this interrupt, which is related only to the data on top of the Rx FIFO. This is directly related to the presence of a 1 in any of the LSR bits 1 to 4. In non-FIFO mode, there is received data available in the RHR register. In FIFO mode, the number of characters in the receive FIFO is equal to or greater than the trigger level programmed in FCR. The interrupt signal will stay active Received while the number of words in the FIFO stays higher than 0 Second Data that value and will be cleared Ready when the microprocessor reads the necessary words to make the number of words in the FIFO less than the trigger level. Note that this is not directly related to LSR bit 0, which always indicates that there is at least one word ready. There is at least one character in the receive FIFO and during a time corresponding to four characters at the selected Character baud rate, no new character 0 Second Reception has been received. Timeout A FIFO timeout interrupt will occur, if the following conditions exist: 1. At least one character is in the FIFO. 2. The most recent serial
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FIFO Mode Only Bit 3 Bit 2 Bit 1

Interrupt Reset Method

Read the Receiver Buffer Register (RBR).

Read the Receiver Buffer Register (RBR).

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Technical Reference Manual Interrupt Identification Interrupt Set and Reset Functions Register Priority Interrupt Interrupt Source Bit 0 Interrupt Reset Method Level Type Description character received was longer than 4 continuous character times ago (if 2 stop bits are programmed, the second one is included in this time delay). Write the Transmitter Holding Register (THR). In non-FIFO mode, the 1-byte Alternatively, reading the THR is empty. In FIFO mode, Transmitt Interrupt Identification the complete 16-byte transmit er Holding Register (IIR) will also FIFO is empty, so 1 to 16 0 Third Register clear the interrupt if this characters can be written to Empty is the interrupt type being THR. That is to say, THR currently indicated (this Empty bit in LSR is one. will not clear the flag in the LSR). A change has been detected in the Clear To Send (CTS), Data Set Ready (DSR) or Carrier Detect (CD) input Read the Modem Status Modem 0 Fourth lines or a trailing edge in the Register (MSR) Status Ring Indicator (RI) input line. That is to say, at least one of MSR bits 0 to 3 is one.

FIFO Mode Only Bit 3 Bit 2 Bit 1

26.22.2.5. FIFO Control Register (Offset == 0x08 for write) This is a write-only register at the same location as the IIR (the IIR is a read-only register). This register is used to enable and clear the FIFOs, and set the Rx FIFO trigger level. Table 26-7. Bit 7:6 5:4 3 Name RXFIFO_TRGL TXFIFO_TRGL DMA Mode Type W W W FIFO Control Register

Tx FIFO Reset

1 0

Rx FIFO Reset FIFO Enable

W W

Function Used to set the trigger level for the Rx FIFO interrupt. See table 571 Used to set the trigger level for the Tx FIFO interrupt. See table 571 This bit selects the UART DMA mode. The DMA mode affects the way in which the DMA signaling outputs pins (irda_nrxrdy and irda_ntxrdy) behave. Setting this bit to logic 1 clears all bytes in the Tx FIFO and resets its counter logic to 0. The shift register is not cleared, so any reception active will continue. This bit will automatically return to zero. Setting this bit to logic 1 clears all bytes in the Rx FIFO and resets its counter logic to 0. The shift register is not cleared, so any reception active will continue. This bit will automatically return to zero. Setting this bit to logic 1 enables both the transmit and receive FIFOs.
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Technical Reference Manual Changing this bit automatically resets both FIFOs. In FIR mode, the device driver should always set this bit as 1. Table 26-8. FCR Code Bit 7 Bit 6 0 0 0 1 1 0 1 1 FCR Code Bit 7 0 0 1 1 Bit 6 0 1 0 1 Receivers FIFO Trigger Level 32-Byte Receivers FIFO Trigger Level 1 character 8 characters 16 characters 28 characters 128-Byte Receivers FIFO Trigger Level 1 character 32 characters 64 characters 120 characters

16-Byte Receivers FIFO Trigger Level 1 character 4 characters 8 characters 14 characters 64-Byte Receivers FIFO Trigger Level 1 character 16 characters 32 characters 56 characters

FCR Code Bit 5 Bit 4 0 0 0 1 1 0 1 1 FCR Code Bit 5 Bit 4 0 0 0 1 1 0 1 1

Table 26-9. Transmitters FIFO Trigger Level 16-Byte Transmitters FIFO Trigger 32-Byte Transmitters FIFO Trigger Level Level 1 character 1 character 3 characters 8 characters 9 characters 16 characters 13 characters 28 characters 64-Byte Transmitters FIFO Trigger Level 1 character 16 characters 32 characters 56 characters 128-Byte Transmitters FIFO Trigger Level 1 character 32 characters 64 characters 120 characters

26.22.2.6. Line Control Register (Offset == 0x0C) This register controls the way in which transmitted characters are serialized and received characters are assembled and checked. Table 26-10. Line Control Register Bit 7 Name DLAB Type R/W Function Divisor Latch Access Bit (DLAB). This bit must be set in order to access the DLL, DLM and PSR registers which program the division constants for the baud rate divider and the prescaler.

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Technical Reference Manual Bit Name Type Function This bit causes a break condition to be transmitted to the receiving UART. When it is set to a logic 1, the serial output (io_irda_sout) is forced to the Spacing (logic 0) state. The break is disabled by setting bit 6 to a logic 0. The Break Control bit acts only on io_irda_sout and has no effect on the transmitter logic, so if several characters are stored in the transmit FIFO, they will be removed from this FIFO and passed sequentially to the Transmitter Shift Register which serializes them. This fact can be useful to establish the break time making use of the THR Empty and Transmitter Empty flags of the LSR. When bits 3, 4 and 5 are logic 1, the Parity bit is transmitted and checked as a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic 0, then the Parity bit is transmitted and checked as a logic 1. If bit 5 is a logic 0, Stick Parity is disabled. This bit is the Even Parity Select bit. When bit 3 is logic 1 and bit 4 is logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and Parity bit. This bit is the Parity Enable bit. When this bit is a logic 1, a Parity bit is generated (transmit data) or checked (receive data) between the last data word bit and Stop bit of the serial data. When bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1s is transmitted or checked. This bit selects the number of stop bits to be transmitted. If cleared, only one stop bit will be transmitted. If set, two stop bits (1.5 with 5-bit data) will be transmitted before the start bit of the next character. The receiver always checks only one stop bit. . This bit along with WL0 defines the word length of the data being transmitted and received. See table 574 for the possible selections. This bit along with WL1 defines the word length of the data being transmitted and received. Table 26-11. Parity setting table LCR Code Bit5 Stick Parity X 0 0 1 1 Bit4 Even Parity X 1 0 0 1 Bit3 Parity Enable 0 1 1 1 1 Parity Bit (Transmitted or Checked) Not transmitted or checked Even parity Odd parity 1 0

Set Break

R/W

Stick Parity

R/W

Even Parity

R/W

Parity Enable R/W

Stop Bits

R/W

1 0

WL1 WL0

R/W R/W

Table 26-12. Word Length and Stop Bits Setting Table LCR Code Bit2 Stop Bit 0 Bit1 WL1 0 0 1 Bit0 WL0 0 1 0 Character Length (bits) 5 6 7
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Technical Reference Manual 1 0 0 1 1 1 0 1 0 1 8 5 6 7 8

1.5 2

26.22.2.7.

Modem Control Register (Offset == 0x10)

By writing this register, the user can set the modem control outputs (io_irda_ndtr and io_irda_nrts). This register also controls the loop back mode, and provides general purpose outputs. Bit 7 6 5 4 3 2 1 0 Name Reserved Out3 DMAmode2 Loop Out2 Out1 RTS DTR Type R/W R/W R/W R/W R/W R/W R/W Table 26-13. Modem Control Register Function This bit controls the general purpose, active low, output io_irda_nout3 in the same way as bit 0 controls io_irda_ndtr. This bit is not found in the standard 16550 UART. This bit selects the UART/SIR DMA mode. The DMA mode2 affects the way in which the DMA signaling output pins (irda_nrxrdy and irda_ntxrdy) behave. Loop back mode control bit. Loop back mode is intended to test the UART or SIR communication. This bit controls the general purpose, active low, output io_irda_nout2 in the same way as bit 0 controls io_irda_ndtr. This bit controls the general purpose, active low, output io_irda_nout1 in the same way as bit 0 controls io_irda_ndtr. This bit controls the request to send active low output (io_irda_nrts) in the same way as bit 0 controls io_irda_ndtr. This bit controls the data terminal ready active low output io_irda_ndtr. A 1 in this bit makes io_irda_ndtr output a 0. When this bit is cleared, io_irda_ndtr outputs a 1.

When this UART is set in loop back mode, the following occurs: The serial output is connected internally to the serial input, so every character sent is looped back and received. The input pin io_irda_sin is not used and the output pin io_irda_sout is set to 1 (inactive state). The four modem control inputs are internally connected to the two modem control outputs plus the general purpose outputs. This way, io_irda_ncts is internally controlled by io_irda_nrts, io_irda_ndsr by io_irda_ndtr, io_irda_nri by io_irda_nout1 and io_irda_ndcd by io_irda_nout2. That is to say, there is a non-ordered correspondence between the four least significant bits of the MCR and the four most significant bits of the MSR. The modem control output pins are forced to their inactive state (high). The four modem control input pins io_irda_ncts, io_irda_ndsr, io_irda_nri and io_irda_ndcd are not

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Technical Reference Manual used. The two modem control output pins io_irda_ndtr and io_irda_nrts and the two user outputs io_irda_nout1 and io_irda_nout2 are set to 1 (inactive state).
Register MCR Bit7 Bit6 Bit5 Bit4 Bit3
Out2

Bit2
Out1

Bit1
RTS

Bit0
DTR

MSR

DCD

RI

DSR

CTS

Figure 26-5. Interconnection between MCR and MSR in Loop Back Mode 26.22.2.8. Line Status Register (Offset == 0x14 for read) This register informs the user of the status of the transmitter and the receiver. In order to get information about a received character, LSR must be read before reading that received character from RBR. Bit Name Table 26-14. Line Status Register Type Function If the FIFO is disabled (16450 mode), this bit is always zero. If the FIFO is active, this bit will be set as soon as any data character in the receivers FIFO has parity or framing error or R the break indication active. This bit is cleared when the CPU reads the LSR and the rest of the data in the receivers FIFO do not have any of these three associated flags on. This bit is 1 when both the THR (or Tx FIFO) and the TSR (Transmitter Shift Register) are empty. Reading this bit as 1 means that no transmission is currently taking place in the R io_irda_sout output pin, and that the transmission line is idle. As soon as new data is written in the THR, this bit will be cleared. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable bit (IER [1]) is set high. In non-FIFO mode, this bit is set whenever the 1-byte THR is R empty. If the THR holds data to be transmitted, this bit is immediately set when this data is passed to the TSR. In FIFO mode, this bit is set when the transmitters FIFO is completely empty, being 0 if there is at least one byte in the FIFO waiting to be passed to the TSR for transmission. This bit is set to 1 if the receivers line input io_irda_sin was held at zero for a complete character time. That is to say, the positions corresponding to the start bit, the data, the parity bit (if any) and the (first) stop bit were all detected as zeroes. Note that a Framing Error flag always accompanies this flag. R This bit is queued in the receivers FIFO in the same way as the Parity Error bit. When break occurs, only one zero character is loaded into the FIFO. The next character transfer is enabled after io_irda_sin goes to
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Transmitter Empty

THR Empty

Break Interrupt

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Technical Reference Manual Bit Name Type Function the marking state and receives the next valid start bit. This bit is cleared as soon as the LSR is read. This bit indicates that the received character did not have a valid stop bit (i.e., a 0 was detected in the (first) stop bit position instead of a 1). This bit is queued in the receivers FIFO in the same way as the Parity Error bit. When a framing error is detected, the receiver tries to resynchronize: if the next sample is again a zero, it will be taken as the beginning of a possible new start bit. This bit is cleared as soon as the LSR is read. When this bit is set, it indicates that the parity of the received character is wrong according to the current setting in LCR. This bit is queued in the receivers FIFO, so it is associated with the particular character that had the error. Therefore, LSR must be read before RBR: each time a character is read from RBR, the next character passes to the top of the FIFO and LSR is loaded with the queued error flags corresponding to this top-of-the-FIFO character. This bit is cleared as soon as the LSR is read. When this bit is set, a character has been completely assembled in the Receiver Shift Register without having free space to put it in the receivers FIFO or holding register. When an overrun condition appears, the result is different depending on whether the 16-byte FIFO is active or not: If the FIFO is not active, so that only a 1-character Receiver Holing Register is available, the unread data in this RBR will not be overwritten with the new character just received. If the FIFO is active, the character just received in the Receiver Shift Register will be overwritten, but the data already present in the FIFO is not changed. The Overrun Error flag is set as soon as the overrun condition appears. This bit is not queued in the FIFO if it is active. This bit is cleared as soon as the LSR is read. This bit is set if one or more characters have been received and are waiting in the receivers FIFO for the user to read them. It is cleared to a logic 0 by reading all of the data in the Receiver Buffer Register or the FIFO.

Framing Error

Parity Error

Overrun Error

Data Ready

26.22.2.9.

Modem Status Register (Offset == 0x18)

This register provides information about the status of the four modem control input pins. The four most significant bits directly provides the status of the pin, while the four least significant bits give information about changes in these pins. The four least significant bits can generate an interrupt (Modem Status interrupt) if enabled by the corresponding bit in the IER. The interrupt will be generated as soon as any of them is 1. They are reset to logic 0 whenever the Modem Status Register is read.

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Technical Reference Manual Table 26-15. Modem Status Register Name Type Function Data Carrier Detect (DCD), which is the complement of the DCD R io_irda_ndcd input. RI R Ring Indicator (RI), which is the complement of the io_irda_nri input. Data Set Ready (DSR), which is the complement of the io_irda_ndsr DSR R input. Clear To Send (CTS), which is the complement of the io_irda_ncts CTS R input. The delta-DCD flag. If set, it means that the io_irda_ndcd input has Delta DCD R changed since the last time the microprocessor read this bit. This bit is set when a trailing edge is detected in the io_irda_nri input Trailing edge R1 R pin; that is to say, when io_irda_nri changes from 0 to 1. If set, it means that the io_irda_ndsr input has changed since the last Delta DSR R time the microprocessor read this bit. If set, it means that the io_irda_ncts input has changed since the last Delta CTS R time the microprocessor read this bit. Scratch Pad Register (Offset == 0x1C) Table 26-16. Scratch Pad Register Name Type Function This 8-bit read / write register has no effect on the operation of the User Data R/W Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. Baud-Rate Divisor Latch (Offset == 0x00, 0x04 when DLAB = 1)

Bit 7 6 5 4 3 2 1 0

26.22.2.10. Bit 7:0

26.22.2.11.

The Divisor Latch is a 16-bit register, whose most significant byte is held in DLM and least significant byte is held in DLL. Division factors from 1 to 65535 can be programmed. The access to these two registers, located at addresses 1 and 0 respectively, is conditioned on the value of the DLAB bit in LCR register. The two registers can be written and read only if this bit is 1. Otherwise, the IER, RBR and THR will be accessed instead. These two registers, together with the Prescaler Register (PSR) select the speed at which the communication will occur. This is the baud rate at which characters will be transmitted and the expected baud rate for the characters that will be received. Only one baud rate is defined for both transmission and reception. The baud rate is defined as io_irda_uclk frequency divided by 16, divided by the contents of the PSR register, then divided by the contents of the Divisor Latch. When DLM and DLL are programmed as 0s, there is no output clock. It is recommended to program DLL and DLM as 0s for power saving in FIR mode. Bit 7-0
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Name DLL

Table 26-17. Baudrate Divisor Latch LSB Type Function R/W Baud Rate Divisor Latch Least Significant Byte
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Technical Reference Manual Table 26-18. Baud Rate Divisor Latch MSB. Type Function R/W Baud Rate Divisor Latch Most Significant Byte

Bit 7-0 26.22.2.12.

Name DLM

Prescaler Register (Offset == 0x08 when DLAB =1)

This five-bit register (PSR [4:0]) adds a second programmable division factor to obtain the desired baud rate (see Divisor Latch description above). The division factor is the value hold in this register, so the maximum factor is 31 and the minimum is 0. Bits 5 to 7 are always zero. This is a non-standard register (i.e., it is not present in the industry standard 16550 UART). The input clock io_irda_uclk is divided by integers from 1 to 31. When PSR is a 0 there is no input clock to divisor latch unit. So, programming DLL and DLM is useless when PSR is set as 0. The default value for the PSR register is 01 (Hex). This register is only accessible when the DLAB bit in LCR is set. Otherwise the Line Status Register will be accessed. Table 26-19. Prescaler Register Bit 7-6 5-0 Name Reserved PSR Type R/W Function Prescaler Value

26.22.2.13. Mode Definition Register Offset == 0x20) This register is used to select the operation mode. Bit 7 6 5 Name Reserved IR_INV_TX FIR_INV_RX Type R/W R/W Table 26-20. Mode Definition Register Function When set, the FIrDA generates inverted FIR or SIR pulse during transmission. This bit is provided to support optical transceivers with receive signals of opposite polarity (active high instead of active low). When set to 1, an inverter is placed on the receiver input signal path. In SIR mode, this bit is useless. When set to 1, DMA mode of operation is enabled. When data transfers are performed by a DMA controller transmit and/or receive data, interrupts in PIO mode should be disabled to avoid spurious interrupts. 0: Apply Frame Length Counter method 1: Apply Set End of Transmission bit method 0: The controller in transmission mode always sends a 1.6s pulse at the end of a transmission frame. 1: The transmission of a 1.6s pulse depends on the ACR [4]. The CPU should keep a timer and set the ACR [4] bit at least once in every 500ms. Bit 1 Bit 0 Operational Mode

4 3

DMA_EN FMEND_MD

R/W R/W

2 1:0

SIP_BYCPU MODE_SEL

R/W R/W

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Technical Reference Manual Bit Name Type Function 0 0 1 1

0 1 0 1

UART (default) SIR FIR Reserved

26.22.2.14. Bit 7 6-5 Name

Auxiliary Control Register (Offset == 0x24) Table 26-21. Auxiliary Control Register Type Function SIR pulse duration select. This bit determines the selection of either a 1.6s or a 3/16 of the baud-rate pulse width. R/W 0: 3/16 1: 1.6s Used to set the trigger level for the status FIFO interrupt. See R/W table 585 for more details. When MDR bit 3 equals to a 1 and CPU writes a 1 to this bit while FIR is transmitting, an SIR Interaction Pulse (SIP) occurs at the end of a transmission frame. When CPU writes a 1 to R/W this bit while FIR is idle, an SIP will be emitted immediately. This bit is cleared automatically by the controller at the end of 1.6s IR pulse data transmission. In FIR mode, the CPU can intentionally abort data transmission of a frame by writing a 1 to this bit. The default R/W value is a 0. Neither the end flag nor the CRC bits are appended to the frame. The CPU must reset the TX FIFO and clear this bit to 0 before next frame can be transmitted. In FIR mode, the CPU writes a 1 to bit 0 just before it writes the last byte to the Tx FIFO register. This bit is automatically R/W cleared to 0 in the next CPU write of the last byte to the FTUART010. When CPU sets this bit, TX_ENABLE should also be set as 1 to keep transmitting the last byte. R/W This bit is set to a 1 to enable data receptoin in all IR modes. This bit is set to a 1 to enable data transmission in all IR R/W modes. Table 26-22. Status FIFO Trigger Level

SIR_PW STFF_TRGL

SEND_SIP

FORCE_ABORT

2 1 0

SET_ EOT (End of transmission ) RX_ENABLE TX_ENABLE

ACR Code Status FIFO Trigger Level Bit7 Bit6 0 0 1 0 1 4 1 0 7 1 1 8 26.22.2.15. Transmit Frame-Length Register (Offset == 0x28, 0x2C) The TXLENL register along with the TXLENH register stores the value for the number of bytes of a data frame to be transmitted. The TXLENL register stores the lower 8 bits and the TXLENH register stores the upper bits.

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Technical Reference Manual The frame length value does not include any appended CRC bytes. The zero value is reserved and must not be used. Values from 1 to 213 - 1 can be used. To properly program TXLEN, the CPU must always write the lower value into TXLENL first and then the upper value into TXLENH. The upper 3 bits of TXLENH are reserved and must be written with 0s. Table 26-23. Transmit Frame Length Register Low Bit 7-0 Name TXLENL Type R/W Function Transmitter Frame Length Low Transmit Frame Length Register High

Table 26-24 Bit 7-5 4-0 Name Reserved TXLENH Type R/W -

Function Transmitter Frame Length High

26.22.2.16. Maximum Receiver Frame-Length (Offset == 0x30, 0x34) While receiving data, the maximum length of a frame is limited to the value written to the MRXLENL and the MRXLENH registers. The MRXLENL register stores the lower 8 bits and the MRXLENH register stores the upper bits. Any frame greater than the set maximum value will be reported as a size error in FMIIR. The maximum frame length value includes the 4-byte CRC field. Values from 5 to 2 13 - 1 can be used. The values from 0 to 4 are reserved and must not be used. Bit 7-0 Name MRXLENL Table 26-25. Maximum Receiver Frame-Length Low Type Function R/W Maximum Receiver Frame-Length Low Table 26-26. Maximum Receiver Frame-Length High Type Function R/W Maximum Receiver Frame-Length High

Bit 7-5 4-0

Name Reserved MRXLENH

26.22.2.17. Preamble Length Register (Offset == 0x38) The PLR specifies the number of the preambles for FIR. At 4Mbps (FIR), the FPL count number of additional PA bytes is inserted at the start of every frame, excluding brick walled frames. Table 26-27. Preamble Length Register Bit 7:2 1:0 Name Reserved FPL Type R/W Function Number of Preambles for FIR frames.

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Technical Reference Manual Table 26-28. Number of FIR Preambles FIR Preamble Length 16 (default) 4 8 32

FPL [1:0] 00 01 10 11

26.22.2.18. FIR Mode Interrupt Identification Register (Offset == 0x3C, PIO Mode) This register has two different definitions depending on whether the current data transfer mode is in PIO or in DMA mode. Bit 7:6 Name Reserved Table 26-29. FIR Mode Interrupt Identification Register Type Function This bit will be set under the following circumstance: If Set-EOT bit method is applied: Whenever a frame is transmitted, this bit will be set. If Frame-Length Counter method is applied: When LSTFMLENH [7:5] are programmed as 0s, this bit will be set at the end of each frame. When LSTFMLENH [7:5] are programmed as non-zeros, this bit will be set at the end of the last frame. Received end-of-frame interrupt pending. Bit 5 is set to a 1 when the receiver detects STO flag of a frame. This bit is cleared to a 0 when FMIIR_PIO is read. Transmit underrun interrupt pending. Bit 4 is set to a 1 when an underrun occurs in the transmit FIFO. This bit is cleared when FMIIR_PIO is read. Receiver FIFO overrun interrupt. Bit 2 is set to a 1 when an overrun occurs in the Rx FIFO. Overrun occurs when the CPU cannot read data fast enough from the Rx FIFO and there is no empty space available in the Rx FIFO register to store frame data. If an overrun occurs, the CPU has to service the overrun before the FTUART010 can receive data further. This bit is cleared to a 0 when FMIIR_PIO is read. Transmitter interrupt pending. Bit 1 is set to a 1 when the Tx FIFO level is below its trigger level. Receiver interrupt pending. Bit 0 is set to a 1 when the Rx FIFO level is equal to or above its trigger level.

FRM_SENT

EOF_DECTED

TXFIFO_URUN

RXFIFO_ORUN

1 0

TXFIFO_TRIG RXFIFO_TRIG

R R

26.22.2.19. Bit 7:6

FIR Mode Interrupt Identification Register (Offset == 0x3C, DMA Mode) Table 26-30. FIR Mode Interrupt Identification Register Name Type Function Reserved 602 5/5/2010 Version 2.1

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Technical Reference Manual Bit Name Type Function This bit will be set under the following circumstance: If Set-EOT bit method is applied: Whenever a frame is transmitted, this bit will be set. If Frame-Length Counter method is applied: When LSTFMLENH [7:5] are programmed as 0s, this bit will be set at the end of each frame. When LSTFMLENH [7:5] are programmed as non-zeros, this bit will be set at the end of the last frame. Receiver FIFO overrun interrupt. Bit 4 is set to a 1 when an overrun occurs in the Rx FIFO. Overrun occurs when the CPU cannot read data fast enough from the Rx FIFO and there is no empty space available in the Rx FIFO register to store frame data. If an overrun occurs, the CPU has to service the overrun before the FTUART010 can receive data further. This bit is cleared to a 0 when FMIIR_PIO is read. Transmit underrun pending. Bit 4 is set to a 1 when an underrun occurs in the data Tx FIFO. This bit is cleared to a 0 when FMIIR_DMA is read. Status FIFO overrun interrupt. Bit 2 is set to a 1 when an overrun occurs in the Status FIFO. Overrun occurs when the CPU cannot read data fast enough from the Status FIFO and there is no empty space available in the Status FIFO register to store information of received frames. If an overrun occurs, the CPU has to service the overrun before the FTUART010 can receive data further. This bit is cleared to a 0 when FMIIR_DMA is read. Status FIFO timeout interrupt pending. This bit is cleared to 0 by reading the Status FIFO. Status FIFO threshold interrupt pending. This bit is cleared to 0 by reading the Status FIFO until the number of valid entries is less than the set trigger level.

FRM_SENT

RXFIFO_ORUN

TXFIFO_URUN

STFIFO_ORUN

1 0

STFIFO_TIME OUT R STFIFO_TRIG R

26.22.2.20. Bit 7-6 5 4 3 2 1 0 26.22.2.21. Bit 7-6

FIR Mode Interrupt Identification Enable Register (Offset == 0x40, PIO Mode) Table 26-31. FIR Mode Interrupt Enable Register Name Type Function Reserved IRIIREN5 R/W Enable FRM_SENT Interrupt IRIIREN4 R/W Enable EOF_DECTED Interrupt IRIIREN3 R/W Enable TXFIFO_URUN Interrupt IRIIREN2 R/W Enable RXFIFO_ORUN Interrupt IRIIREN1 R/W Enable TXFIFO_TRIG Interrupt IRIIREN0 R/W Enable RXFIFO_TRIG Interrupt

FIR Mode Interrupt Identification Enable Register (Offset == 0x40, DMA Mode) Table 26-32. IrDA Mode Interrupt Enable Register Name Type Function Reserved 603 5/5/2010 Version 2.1

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Technical Reference Manual Bit 5 4 3 2 1 0 Name IRIIREN5 Reserved IRIIREN3 IRIIREN2 IRIIREN1 IRIIREN0 Type R/W R/W R/W R/W R/W Function Enable FRM_SENT Interrupt Enable TXFIFO_URUN Interrupt Enable STFIFO_ORUN Interrupt Enable STFIFO_TRIG Interrupt Enable STFIFO_TIME OUT Interrupt

26.22.2.22. Status FIFO Line Status Register (Offset == 0x44) This register returns the status byte at the bottom of the Status FIFO. If the LOST_FRM bit is 0, bits 0 to 4 indicate if any error condition occurred during reception of the corresponding frame. Error conditions will also affect the error flags in the LSR register. Bit 7:5 4 3 2 1 0 Name Reserved STS_VLD SIZE_ERR PHY_ERR CRC_ERR RXFIFO_ORUN Table 26-33. Status FIFO Line Status Register Type Function R When set to 1, the bottom Status FIFO entry contains valid data. Set to 1 when a frame exceeding the maximum length has been R received. Set to 1 when an illegal symbol is received or abort is detected R during reception. Set to 1 when a mismatch between the received CRC and the R receiver-generated CRC is detected. This bit is set to 1 when incoming characters or entire frames have R been discarded due to the RX_FIFO full.

26.22.2.23. Status FIFO Received Frame Length Register - Low (Offset == 0x48) This register must be read only when the STS_VLD bit in STFIFO_STS is 1. Upon reset, all bits are set to 0. Bit 7:0 Table 26-34. Status FIFO Received Frame Length Register Low Name Type Function RCVLENL R Least significant 8 bits of the received frame length.

26.22.2.24. Status FIFO Received Frame Length Register - High (Offset == 0x4C) This register must be read only when the STS_VLD bit in STFIFO_STS register is 1. Upon reset, all bits are set to 0. Reading this register removes the bottom STFIFO entry. So, when the STS_VLD is read as 1, the STFF_RXLENL and STFF_RXLENH must be read sequentially in order. Bit 4:0 Table 26-35. Status FIFO Received Frame Length Register High Name Type Function RCVLENH R Most significant 5 bits of the received frame length. FIR Mode Link Status Register (Offset == 0x50)

26.22.2.25.

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Technical Reference Manual Table 26-36. FIR Mode Link Status Register Bit 7 6 5 Name FIR_IDLE TXFIFO_EMPTY STFIFO_FULL Type R R R Function No FIR transaction is in progress. Tx FIFO is empty. When the Tx FIFO becomes empty, bit 6 becomes a 1 and when Tx FIFO is not empty, it becomes a 0. This bit is set to a 1 when the Status FIFO is full. Frame is longer than expected. Bit 4 is set to 1 when a frame exceeding the maximum length (set by MRXLENL register and the MRXLENH register) is received. When this error is detected, current frame reception is terminated. The data received in Rx FIFO is incomplete. Reception is stopped until the next BOF is detected. Bit 4 is cleared to a 0 when the FMLSR register is read. Physical error. In FIR mode, bit 3 is set to a 1 when an illegal symbol is received or abort is detected during reception. Bit 3 is cleared to a 0 when the FMLSR register is read. CRC error. When a bad CRC is detected on data reception, bit 2 is set to 1. Bit 2 is cleared to 0 when the FMLSR register is read. This bit is set to a 1 when the Status FIFO is empty. Rx FIFO is empty. When the Rx FIFO becomes empty, bit 0 becomes a 1 and when Rx FIFO is not empty, it becomes a 0.

SIZE_ERR

3 2 1 0

PHY_ERR CRC_ERR STFIFO_EMPTY RXFIFO_EMPTY

R R R R

26.22.2.26. FIR Mode Link Status Interrupt Enable Register (Offset == 0x54) Table 595 shows the bit assignment of FIR mode line status interrupt enable register. The interrupt enable registers determine which status flag generate an interrupt request by setting the corresponding bit to 1. Bit 7 6 5 4 3 2 1 0 Table 26-37. FIR Mode Link Status Interrupt Enable Register Name Type Function FMLSIER7 R/W Enable FIR_IDLE Interrupt FMLSIER6 R/W Enable TX_EMPTY Interrupt FMLSIER5 R/W Enable STFIFO_FULL Interrupt FMLSIER4 R/W Enable SIZE_ERR Interrupt FMLSIER3 R/W Enable PHY_ERR Interrupt FMLSIER2 R/W Enable CRC_ERR Interrupt FMLSIER1 R/W Enable STFIFO_EMPTY Interrupt FMLSIER0 R/W Enable RXFIFO_EMPTY Interrupt

26.22.2.27. Resume Register (Offset == 0x58) When transmit underrun or receive overrun occurs, this register should be read to resume normal operation. Reading the RBR (offset: 0x58) will obtain an indeterminate value. 26.22.2.28. Rx FIFO Count Register (Offset == 0x5C)

The Rx FIFO COUNT register represents the number of data bytes in the Rx FIFO. This register is useful when the number of remaining bytes of a frame received in Rx FIFO is below the set trigger level. When the FIFO is full, the RXFF_CNTR is 0x10 for FIFO with the size of 16-byte. The 4-byte CRC32 appended

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Technical Reference Manual to the frame is also received in Rx FIFO. Bit 7:5 4:0 Name Reserved RXFF_CNTR Table 26-38. Rx FIFO Count Register Type Function R The number of data bytes in the Rx FIFO.

26.22.2.29.

Last Frame Length Register Low (Offset == 0x60)

The LSTFMLENL register along with the LSTFMLENH register stores the value for the number of bytes of the last data frame to be transmitted. The LSTFMLENL register stores the lower 8bits and the LSTFMLENH register stores the upper bits. The frame length value does not include any appended CRC bytes. Values from 1 to 213- 1 can be used. To properly program LSTFMLEN, the CPU must always write the lower value into LSTFMLENL first and then the upper value into LSTFMLENH. The upper 3 bits of LSTFMLENH define the number of frames to be transmitted. Programming these 3 bits as all 0s indicates only one frame with length TXLEN is intended to be transmitted (if Frame-Length Counter method is applied or DMA mode is selected). Table 26-39. Last Frame Length Register Low Bit Name Type Function 7:0 LSTFMLENL R/W Last Transmitter Frame Length Low 26.22.2.30. Last Frame Length Register High (Offset == 0x64) Table 26-40. Last Frame Length Register High Bit 7:5 4:0 Name FRM_NUM LSTFMLENH Type R/W R/W Function Number of frames to be transmitted Last Transmitter Frame Length High

Table 26-41. Frame Number Decoding Table LSTFMLENH Bit7 Bit6 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit5 0 1 0 1 0 1 0 1 Number of Frames intended to transmit 1 2 3 4 5 6 7 8

26.23. Programming Sequence 26.23.1. SIR Mode The SIR mode of operation is similar to the UART mode except that data communication takes place in a slow-speed half-duplex manner. The method of data transfer is infrared instead of on a wired path. The modem control register (MCR) and the Modem Status Register (MSR) are not used.
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Technical Reference Manual The following register programming steps are required to receive or transmit data in SIR mode transmissions: 1. 2. Program the prescaler (PSR) register to ensure the prescaler output is approximately 1.843 MHz. the default PSR value is 0x01R Program the Baud Rate Divisor Latch Least Significant Byte (DLL) and the Baud Rate Divisor Latch Most Significant Byte (DLM) registers to select the desired communication baud rate for the UART mode. The baud rate is given by: Baud rate = 3. 4. f io_irda_uclk

PSR x DL x 16 Program the Mode Definition Register (MDR) to the SIR mode. Program the LCR register. Set character length to 8-bit Set number of Stop bits to 1 Disable Parity

26.23.2. 26.23.2.1.

SIR Data Transmission Mode SIR Data Transmission Mode

The following register programming steps are required for data transmission in the SIR mode: 1. Program the FCR register. Reset Tx FIFO and Rx FIFO Enable FIFO and set trigger level for Tx FIFO and Rx FIFO 2. Program the IER register to enable only the data transmission interrupts. Enable the THR Empty interrupt Disable the Receiver Line Status interrupt Disable the Receiver Data Ready interrupt 3. Program the ACR register bit 7 to select fixed 1.6 s or 3/16th pulse width and bit 0 to enable data transmission. 26.23.2.2. 1. 2. SIR Data Receive Mode.

Program the FCR register. Reset Tx FIFO and Rx FIFO Enable FIFO and set trigger level for Tx FIFO and Rx FIFO Program the IER register to enable data reception related interrupts. Enable Data Ready interrupt
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Technical Reference Manual Disable THR Empty 3. Write a 1 to the ACR register bit 1 to enable data reception. FIR Mode FIR Data Transmission Mode

26.23.3.
26.23.3.1. 1. 2.

The following register programming steps are performed for transmission in the FIR mode: Write a 6 to the PSR register. This divides 48-MHz input clock by 6 and generates 8-MHz internal clock for the FIR mode of operation. Set DLL and DLM registers to 0x0. Program the Mode Definition register (MDR) to: Select the FIR mode. Enable / disable the software control on the 1.6 s SIP pulse. Select the frame closing method (frame-length method or setEOT bit method) Enable / disable DMA mode of operation 3. 4. Program the PLR register to: Select the number of preambles PLR [1:0]. The default value is 16. If the frame-length method is selected for frame closing, program the TXLENL and TXLENH registers for the frame length. In multi-frame transmission, LSTFMLENL and LSTFMLENH should also be properly set. 5. Program the FCR register to: Reset Tx FIFO Select the Tx FIFO trigger level 6. 7. CPU writes a part of the frame (for a bigger frame) or the whole frame (a small frame such as a supervisory frame) in the Tx FIFO. This step is optional. Program the FMIIER register to enable only the transmitter related interrupts and disable the remaining interrupts. Enable the following: For programmed I/O mode Transmitter FIFO below threshold level interrupt enable (FMIIER [1]) Transmitter underrun interrupt enable (FMIIER [3]) Frame has sent interrupt enable (FMIIER [5]) For DMA mode Transmitter underrun interrupt enable (FMIIER [3]) Frame has sent interrupt enable (FMIIER [5]) Program the FMLSIER register to enable only the transmitter-related interrupts and disable the remaining interrupts.
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Technical Reference Manual Write a 1 to the ACR [0] bit to enable data transmission. FIR Data Receive Mode The following register programming steps are performed for receive in the FIR mode: 1. Program the Mode Definition Register (MDR) to: Select the FIR mode Enable / disable DMA mode of operation 2. Program the MRXLENL and MRXLENH registers for maximum receive-frame length value. The MRXLENL register stores the lower eight bits and the MRXLENH register stores the remaining upper bits. When the intended maximum receive-frame length is n, program the MRXLENL and MRXLENH registers to be n + 4. 3. Program the FCR register to: Reset Rx FIFO Select the Rx FIFO trigger level 4. Program the FMIIER register to enable only the receiver related interrupts and disable the remaining interrupts. Enable the following: For programmed I/O mode Rx threshold interrupt (FMIIER [0] bit) The Rx FIFO overrun interrupt (FMIIER [2] bit) The received end of the frame interrupt (FMIIER [4] bit) Write a 1 to the ACR [1] bit to enable data reception. For DMA mode Status FIFO threshold interrupt disable (FMIIER [0]) Status FIFO timeout interrupt disable (FMIIER [1]) Status FIFO overrun interrupt disable (FMIIER [2]) Program the FMLSIER register to enable only the receiver-related interrupts and disable the remaining interrupts. Write a 1 to the ACR [1] bit to enable data reception. This completes the programming of the registers for data reception and now the FTUART010 is ready to receive data. The device decodes the serial data, converts it from serial data to parallel data and stores the data bytes in the Rx FIFO. When the stored data in the Rx FIFO reaches the set threshold level, the device interrupts the CPU. When the CPU is interrupted, it reads the FMIIR to identify the source of the interrupt.

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Technical Reference Manual In PIO mode, when the source of the interrupt is the FMIIR [0] bit and not the FMIIR [4] bit, the CPU goes to the threshold mode. When the source of the interrupt is the FMIIR [4] bit and not the FMIIR [0] bit, the CPU reads RXFF_CNTR to determine how many bytes (including 4-byte CRC32) related to the received frame should be read out. If the source of the interrupt is the FMIIR [2] bit, there has been an overrun while receiving data and the CPU will need to service the overrun. 26.24. RS-232 Interface The figure below shows the connection between aJ-200 and RS-232 transceiver
RxD1 TxD1 CTS1n RTS1n DCD1n DSR1n RI1n DTR1n

RS-232 Transceiver

aJ-102

RxD2 TxD2 CTS2n RTS2n RxD3 TxD3 RxD4 TxD4 RS-232 Transceiver RS-232 Transceiver RS-232 Transceiver

Figure 26-6. RS-232 Interface 26.25. Infrared Interface The UART4/IrDA can be connected to a Vishay transceiver as shown in figure below. The TxD pin of the transceiver is connected to the IrDA_TxD. The transceiver has only one RxD pin that is used for both FIR and SIR operation. The RxD pin of the transceiver is connected to the IrDA_RXL and IrDA_RXH pins . The Mode pin of the transceiver needs to be programmed correctly so that it will operate properly in FIR mode. Connecting the programming output IrDA_MODE to the Mode pin of the transceiver can control the Mode pin by programming bit 6 of Modem Control Register (0ffset : 0x10).

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IrDA_TxD

Txd

aJ-102

IrDA_RXL IrDA_RXH GPIOx

Vishay Rxd Infared Transceiver

Mode

Figure 26-7. Interface with Vishay Transceiver Some transceivers, like HP HSDL-1100, require two receive pins, RXD-A and RXD-B. The AJ-200 can also be connected to this kind of transceivers as shown in Figure 195. RXD-A pin of the transceiver should be connected to the IrDA_RXL pin and is used to receive data in the SIR. RXD-B pin of the transceiver should be connected to the IrDA_RXH pin and is used to receive data in FIR. TxD pin of the transceiver is connected to IrDA_TxD pin

IrDA_TxD

TXD RXD_A HSDL-1100

aJ-102

IrDA_RXL IrDA_RXH

Infared RXD_BTransceiver

Figure 26-8. Interface with HSDL-1100

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27. Synchronous Serial Port Controller (SSP/I2S/AC97)

27.1. General Description The aJ-200s provides a SSP channel and I2S/AC97/SPI channel. Synchronous Serial Port Controller (SSPC) is a full-duplex synchronous serial interface and can connect to a variety of external analog-todigital (A/D) converters, audio and telecom Codecs, touch panel control chips, and other devices that use serial protocols for transferring data. The SSPC supports Texas Instrument SSP, Motorola SPI, and National Semiconductor Microwire protocol. The I2S/AC97/SPI controller provides Philips I2S and Intel AC-link protocol, and SPI protocol. In AC97 mode, for recording, the AC97 Codec sends digitized audio samples and the controller stores them in memory. For playback or synthesized audio production, the processor retrieves the stored audio samples and sends them to the Codec through the AC-link. The external digital-to-analog converter (DAC) in the Codec then converts the audio sample to an analog audio waveform. In IS mode, the controller transfers digitized audio samples between the system memory and an external IS Codec. When the controller operates in master mode, it supports serial rates up 15 MHz. The serial data formats may range from four (4) to thirty-two (32) bits in length. The SSP and I2S/AC97 controller use the same programming model. It supports the following features:

SSP controller supports TI SSP, Motorola SPI, and National Semiconductor Microwire I2S/AC97 controller provides Philips I2S and Intel AC-link Independent SSP clock to ease bit clock generation Master or slave mode Internally or externally controlled serial bit clock Internally or externally controlled frame / sync Programmable frame / sync polarity Programmable serial bit clock polarity, phase and frequency Programmable serial bit data sequence (MSB or LSB first) Programmable I2S format (including padding zero bits and right or left justification) Programmable threshold interrupt of transmit / receive FIFO Independently programmable interrupt enable / disable 16-word transmit FIFO and 16-word receive FIFO DMA REQ/ACK for large data transfers

Figure below shows the block diagram of SSP

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APB interface APB

reg_wr_a reg_rd_a reg_addr [2:0] reg_wdata [31:0] reg_rdata [31:0]

sclk_in

Register block

Register block

fs_in ac97_resetn_r

ssp_clk_oe ssp_fs_oe pbe [3:0] dam_reg_r dam_gnt ssp_intr sclk_out_r sspclk fs_out_r

Interrupt generation

TXFIFO RXFIFO

Transmit / receive control block

txd_r txd_oe_r rxd

Figure 27-1. Block Diagram of SSP/I2S/AC97/SPI Controller The main building blocks of SSP controller are APB interface, serial control block, and serial clock generator and transmit / receive control. The following sections contain detailed descriptions of each block. 27.2. APB Interface

The AMBA APB interface decodes the incoming signals from APB into read / write signals to FIFO. For some special usage, the APB interface provides active HIGH byte-enable input (dashed line in figure 27-1). If APB bridge can generate byte-enable, it can directly connect to APB interface, and the timing of byteenable should be the same as PWRITE. If standard APB is used, the four byte-enable inputs must be tied to HIGH (cannot float). The byte-enable information affects the operation of FIFO. 27.3. Register Block

The register block can accept register read / write from APB interface. It also provides property information to other blocks in the SSP. For more details about register contents, please refer to the section entitled Programming Model. 27.4. Interrupt Generation Control

The interrupt generation block collects information (FIFO full / empty, transmit / receive busy, etc.) from the transmit / receive control block and provides it to the register block as the register value. If interrupt conditions are matched, ssp_intr will be asserted. This block also generates DMA request signals, if needed.
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Technical Reference Manual 27.5. Serial Clock Generator

This block generates serial clock for communication, if required. The format of serial clock is defined via control register 0. Generally, clock will not start if SSP is not enabled. Once SSP is enabled and the clock running condition is matched (for example, TIs SSP is specified and the transmit FIFO is not empty, or I2S is specified), serial clock will start running. The frequency of serial clock in running depends on SCLKDIV register setting. This block also gives serial clock and frame / sync information to the transmit / receive control block to transmit / receive data to / from devices. 27.6. Transmit / Receive Control The main function of this block is to do parallel-to-serial transmission or serial-to-parallel reception to / from external devices. If master mode is specified and transmit FIFO is not empty, data in transmit FIFO will be read and shifted out via txd_r pin. Once the whole word is completely shifted out and transmit FIFO still contains valid data, the next data will be read and continuously shifted out. The received data can be shifted in via rxd. Once the reception is completed, the received word will be written into receive FIFO and the receive control logic will continue to receive another word. If half-duplex protocol is specified, the receive control logic will not start until transmission is completed. If slave mode is specified, SSP controller will start transmitting / receiving data when frame / sync is activated. Transmission and reception will continue until SSP is disabled or frame / sync is de-activated. If half-duplex protocol is specified, the transmit control logic will not start until reception is completed. Transmission and reception can be activated simultaneously if full-duplex protocol is specified. 27.7. SSP Operation This section describes the operation of synchronous serial port. Some control registers will be used without explanations, so please refer to the programming model for more details about the definition and explanation on the control registers. 27.7.1. SSP Reset SSP can be reset through APB reset (PRESETn). If PRESETn is pulled LOW, all logic and state in SSP will be reset to their initial value. Except PRESETn, if the user disables SSP, all states of SSP will go back to the IDLE state. The contents of SSP control register will not be reset when SSP is disabled. 27.7.2. SSP Serial Clock Ratio and Bit Rate The frequency of internally generated serial clock is controlled by the SCLKDIV in control register 1. The frequency of internally generated serial clock is determined by the following formula: Data will be transmitted or received depending on SCLK. So, the bit-rate of SSP is equal to the frequency of SCLK. If externally generated serial clock is specified, SCLKDIV will be ignored and all transfers depend on externally supplied SCLK. Because SSP has to synchronize externally generated SCLK to

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Technical Reference Manual SSPCLK, the frequency of externally generated SCLK is expected to be slower at least two times than SSPCLK. Figure below shows the relationship among PCLK, SCLK and sample point. Each triangle in black indicates the sample point (SSP transmits or receives data at that time).
SSPCLK sclk_in sclk_sync1 sclk_sync2

Figure 27-2. Relation Among SSPCLK, sclk_in and Sample Point 27.7.3. SSP Frame Format The SSP Controller provides either TI SSP, Motorola SPI, National Semiconductor Microwire or Philips I2S frame format. The following sections will give more details about each frame format. 27.7.4. Texas Instrument SSP Frame Format Figure 27-3 shows the frame format of TIs SSP for a single transfer.
SCLK FS TXD RXD TXD_OE

MSB

LSB

MSB

LSB

Figure 27-3. TIs SSP Frame Format for Single Transfer In this mode, FS is forced to LOW when no data transfer exists. In master mode, when transmit FIFO is not empty, transmit logic will read data from transmit FIFO into the shifting register. FS will then be pulled HIGH for one SCLK cycle. After first SCLK cycle, data in the shifting register will be shifted out at every rising edge of SCLK via txd_r until serial data length is reached. MSB of serial data will be transmitted / received first. If the LSB of current word is transmitted and FIFO still contains data, frame / sync will again

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Technical Reference Manual be pulled HIGH for one SCLK cycle and the data in FIFO will be read to continue transmitting. Figure below shows the continuous transfer waveform.
SCLK FS TXD RXD TXD_OE

MSB

LSB

MSB

MSB

LSB

Figure 27-4. TIs SSP Frame Format for Continuous Transfer In slave mode, if frame / sync is sampled as HIGH, transmit logic will read transmit FIFO data and start shifting it out. If transmit FIFO is empty, transmit logic still reads the transmit FIFO and the last word in transmit FIFO will be read and shifted out. Under this situation, transmit FIFO under-run interrupt will be issued if under-run interrupt is enabled. The receive logic will start receiving data simultaneously. During transmission / reception frame / sync will not be qualified until the data length is reached. If TIs frame format is specified, the bit sequence is from MSB to LSB, either in master mode or slave mode. The LSB setting in control register 0 will be ignored, and the SCLKPH and SCLKPO will be ignored, too. 27.7.5. Motorola SPI Frame Format Motorolas SPI is four-wire serial peripheral protocol. The frame format is completely controlled by the SCLKPO and SCLKPH. SCLKPO controls the polarity of SCLK when idle and SCLKPH determines the relationship between frame / sync and SCLK. Figure below shows the four modes of SPI under different combinations of SCLKPO and SCLKPH.

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frame / sync SCLKPO = 0 SCLKPO = 0 SCLKPO = 0 SCLKPH = 1 SCLKPO = 1 SCLKPH = 0 SCLKPO = 1 SCLKPH = 1

Figure 27-5. Relation between Frame / Sync SCLK of SPI As shown in figure above, if SCLKPH is specified as logic 1, serial clock will start running after half SCLK cycle after frame / sync is pulled active. If SCLKPH is specified as 0, serial clock will start running after one SCLK cycle after frame / sync is pulled active. If SCLKPO and SCLKPH have the same value, the transmit logic will transmit data at the falling edge of SCLK, and the receive logic will latch data at the rising edge of SCLK. If SCLKPO and SCLKPH are of opposite values, the transmit logic will transmit data at the rising edge of SCLK and the receive logic will receive data at the falling edge of SCLK. In master mode, if transmit FIFO contains data and SSP is enabled, the transmit logic will read transmit FIFO and shift it out at every transmit edge (depending on SCLKPO and SCLKPH) from MSB to LSB. The receive logic will simultaneously receive data. After LSB is transmitted / received, frame / sync will hold LOW for half or one SCLK cycle (depending on SCLKPH) and then pull HIGH if no data is in transmit FIFO. Received data will be written into receive FIFO. If there is still data in transmit FIFO, the transmit logic will restart to transmit data. In slave mode, if frame / sync is activated and SCLK starts running, transmit logic will start shifting the data in transmit FIFO even if transmit FIFO is empty. Transmit FIFO under-run interrupt will be issued if transmit FIFO is enabled. The receive logic will start receiving data simultaneously and received data will be written into receive FIFO. Either in master mode or slave mode, bit shifting sequence is from MSB to LSB. The LSB setting in control register 0 will be ignored. The polarity is fixed as low active, so FSPO in control register 0 is ignored. Figure below shows the frame format of Motorolas SPI frame format for single transfer and figure 27-7 shows the frame format of Motorolas SPI for continuous transfer.

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frame/sync

SCLK_PO = 0 SCLK_PH = 0 SCLK_PO = 0 SCLK_PH = 1 SCLK_PO = 1 SCLK_PH = 0 SCLK_PO = 1 SCLK_PH = 1 TXD RXD
MSB LSB

Figure 27-6. Motorolas SPI Frame Format for Single Transfer

frame/sync

SCLK_PO = 0 SCLK_PH = 0 SCLK_PO = 0 SCLK_PH = 1 SCLK_PO = 1 SCLK_PH = 0 SCLK_PO = 1 SCLK_PH = 1

TXD

MSB

LSB

MSB

Figure 27-7. Motorolas SPI Frame Format for Continuous Transfer In SPI frame format, the SCLK will stop toggling when idle, and usually frame / sync is used as a chipselect signal. 27.7.6. National Semiconductor Microwire Frame Format National Semiconductor Microwire frame format is similar to SPI except half-duplex transfer. That is, when transmitting, receive logic will be halted until a complete word is transmitted and vice versa. When transmit and receive handover, extra cycle is inserted. Data will be transmitted at the falling edge of SCLK

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Technical Reference Manual and received data will be latched at the rising edge of SCLK. Since the transmit and receive data length may be different, SSP controller provides independent data length programming for transmission and reception. The SSP controller in National Semiconductor Microwire frame format defines two phases. In master mode, the first phase is transmitting phase. If SSP is enabled and transmit FIFO contains data, transmit logic will shift data out from transmit FIFO to slave devices depending on the padding data length (PDL) specified in control register 1. Receive logic will be halted first. After transmission completes, SSP controller will check the serial data length (SDL) specified in control register 1. If SDL is specified as nonzero, SSP controller will enter into second phase to receive data and halt the transmit logic. If reception completes, SSP controller goes back to the first phase to transmit data if there are any data existing in transmit FIFO. In slave mode, the first phase is receiving phase. If SSP is enabled and SCLK starts running while frame / sync is activated, receive logic starts to receive data depending on the padding data length (PDL) specified in control register 1. After reception completes, SSP controller will check the serial data length (SDL) specified in control register 1. If SDL is specified as non-zero, SSP controller will enter into the second phase to transmit data and halt the receive logic. If transmission completes, SSP controller goes back to the first phase to receive data if SCLK and frame / sync are still active. Figure below shows the transfer format of National Semiconductor Microwire. The FSPO in control register 0 is set to 1.
FS SC LK TXD RXD TXD_O E D u m m y c y c le MSB LSB M SB LSB

Figure 27-8. National Semiconductor Microwire Frame Format for Single Transfer If there is still data in transmit FIFO, the transmit logic will continuously transmit data to TXD and then receive data from RXD. Figure below shows the frame format of continuous transfer.

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FS SCLK TXD RXD TXD_OE

MSB

LSB

MSB

LSB

MSB

Figure 27-9. National Semiconductor Microwire Frame Format for Continuous Transfer If National Semiconductor Microwire is specified, bit shifting sequence is from MSB to LSB. The LSB setting in control register 0 will be ignored. The SCLKPH and SCLKPO will be ignored, too. The polarity of frame / sync is user-specified. 27.7.7. Philips I2S Frame Format Philipss inter-IC sound (I2S) is used for serial audio. The frame / sync signal is used for channel selection. SSP controller in I2S frame format provides either stereo or mono mode. If stereo mode is specified, the frame / sync will change after a complete word is transmitted or received. The FSPO in control register 0 specifies the first channel. If FSPO is specified as logic 1, the first data word will be transmitted / received with frame / sync LOW. If FSPO is specified as 0, the first data word will be transmitted / received with frame / sync HIGH. The SSP controller in I2S frame format can act in either receiving or recording mode, or both. If transmit data output enable (TXDOE) in control register 2 is set to 1, the SSP can simultaneously transmit data in transmit FIFO via txd_r and latch received data into receive FIFO via rxd_in. If TXDOE is set to logic 0, the SSP is only in recording mode. That is, no data in transmit FIFO will be read and shifted out even if SSP is enabled.
SCLK FS(stereo) FS(mono) TXD / RXD

LSB

MSB

LSB

MSB

work n-1

work n

work n+1

Figure 27-10. Philips I2S Basic Frame Format

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Technical Reference Manual As shown in figure above, the FSDIST in control register 0 is set as 1. That is, first bit of data will be transmitted / received after one serial clock cycle after the channel select signal is changed. Figure below shows one variation of I2S frame format. In this case, the frame / sync width is larger than that of the serial data bits. The valid data bit is right justified to the whole frame. That is, extra padding data bits are inserted in front of valid data bits. The number of padding data bits is specified in PDL in control register 1 and the last bit of serial data is still valid for one serial clock after frame / sync change (FSDIST is set to one).
SCLK FS(stereo) FS(mono) TXD / RXD

MSB

LSB

Padding data

MSB

LSB

work n-1

work n

Figure 27-11. Possible Variation of I2S Frame Format (I) Figure below shows another variation of I2S frame format. In this case, the frame / sync width is also larger than that of the serial data bits, but the valid data bit is left justified to the whole frame. That is, extra padding data bits are inserted in back of valid data bits. The number of padding data bits is specified in PDL in control register 1 and the first bit of serial data is valid at the first serial clock after frame / sync change (FSDIST is set to zero).
SCLK FS(stereo) FS(mono) TXD / RXD

MSB

LSB

Padding data

MSB

Padding

work n

work n+1

Figure 27-12. Possible Variation of I2S Frame Format (II) 27.7.8. Intel AC-Link Frame Format The SSP provides single channel and masters only Intels AC-link protocol. Intels AC-link usually consists
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Technical Reference Manual of one TAG stream and 12 data streams. Figure below shows the frame format of Intels AC-link.

SLOT FS TXD

10

11

12

TAG

CMD ADDR

CMD DATA

PCM LERONT

PCM RERONT

LINE1 DAC

PCM CENTER

PCM LSURR

PCM RSURR

PCM LEE

LINE2 DAC

HSET DAC

IO CTRL

RXD

TAG

STATUS ADDR

STATUS DATA

PCM LEFT

PCM RIGHT

LINE1 DAC

PCM MIC

RSRVD

RSRVD

RSRVD

LINE2 DAC

HSET DAC

IO STATUS

Figure 27-13. Intels AC-Link Frame Format The TAG stream consists of 16-bit serial data and each DATA stream consists of 20-bit serial data. If AClink frame format is specified, the serial data length setting in control register 1 will be ignored. The SSP controller will automatically set the serial data length of tag and data phase to 16 and 20 respectively. The frame / sync signal is used as a SYNC signal in AC-link protocol and is only asserted during TAG phase. Intels AC-link starts transmitting / receiving data from MSB to LSB, and the first valid bit on the current frame appears after one bit time after frame / sync is asserted. The SSP controller will transmit data at the rising edge of serial clock and received data will be latched at the falling edge of serial clock.
SCLK FS TXD / RXD Start of current frame End of previous frame

Figure 27-14. Start of AC-Link Frame To reduce the unneeded slot data to be written into transmit FIFO or received from receive FIFO, Faradays SSP provides slot valid registers. There are totally 12 slot-valid control registers on AC-link frame (except TAG slot). If the corresponding control register is set to logic 1, the transmitted data will be retrieved from transmit FIFO and the received data will be written into receive FIFO. For example, if only the first and second slots are valid, the register setting should be 0x0000_0007, and only 3 words of data need be put into transmit FIFO for one AC-link frame. The same applies to transmit FIFO, where only 3 words of data will be written into receive FIFO. Figure below shows the relationship between the slot valid

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Technical Reference Manual bit and Tx / Rx FIFO.

Frame

TXD / RXD

TAG slot

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

SLOT 8

SLOT 9

SLOT 10

SLOT 11

SLOT 12

SLOT 1 VALID

SLOT 2 VALID

SLOT 3 VALID

SLOT 4 VALID

SLOT 5 VALID

SLOT 6 VALID

SLOT 7 VALID

SLOT 8 VALID

SLOT 9 VALID

SLOT 10 VALID

SLOT 11 VALID

SLOT 12 VALID

Tx FIFO

Rx FIFO

Figure 27-15. Relationship between Tx / Rx FIFO and Slot Valid The AC-link cold reset can be issued any time after the cold reset control bit is set. The SSP controller will pull ac97_resetn_r to LOW to reset the device. The period of reset is the number of SSPCLK clock cycles specified in SCLK_DIV. Figure 205 shows the waveform of AC-link cold reset.

SCLK FS ac97_resetn_r

Tsspclk*SCLK_DIV ACCRST is set to 1 SSP_EN is cleared ACCRST is cleared

Figure 27-16. AC-link Cold Reset The warm reset can only be enabled while SSP is disabled. If the warm reset bit (ACWRST) in control register 2 is set, frame / sync will be asserted for the number of SSPCLK cycles specified in SCLK_DIV. After reset is completed, the ACWRST in control register 2 will be cleared. Setting ACWRST to 1 while SSP_EN is asserted will take no effect. Figure below shows the warm reset of AC-link. Usually, bit clock from CODEC will start after some time. The user has to wait some time to enable SSP while CODECs bit clock is running.

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SCLK FS

Recovery time

Tsspclk*SCLK_DIV

ACWRST is set to 1

ACCRST is cleared

Figure 27-17. AC-link Warm Reset Another reset mechanism mentioned in AC97s specification is register reset. This type of reset can be controlled via software. 27.7.9. Transmit / Receive FIFO Read / Write Transmit FIFO and receive FIFO occupy the same address space. When data register is read, data from receive FIFO will be retrieved. When data register is written, written data will be stored into transmit FIFO. Due to the expansion of APB, Faradays SSP accepts byte-enable input from APB. If standard APB is used, the user has to tie byte-enable input to HIGH. Otherwise, it accepts active HIGH byte-enable. When writing to the transmit FIFO, if byte-enable is applied, the transmit FIFO write pointer will only advance when least significant byte is active. That is, when the last two bits of address are zero, SSP treats it as if the whole word had been written and advances its write pointer. Reading of the receive FIFO has the same mechanism. The read pointer of the receive FIFO only advances when least significant byte is read. Setup / Hold Time In master mode, the SSP controller issues data either at rising or falling edge of SCLK with no hold time. That is, the output data will change at the same time the SCLK changes phase. Because the serial clock is generated by SSP controller, the rising / falling edge can be predicted by SSP controller. So the received data will be latched by SSP controller at the rising or falling edge of SCLK and the setup / hold time depends on library cells. In slave mode, serial clock and frame / sync are external. The SSP controller uses the SSPCLK to synchronize the incoming signals including sclk_in and fs_in. SSP controller does double synchronization so that the setup / hold time of incoming data is required. Suppose that the data is latched at the falling edge of SCLK and transmitted at the rising edge of SCLK. Due to the double synchronization, the received data should have hold time at least two SSPCLK cycles and transmitted data should have output valid time at least two SCLK cycles as shown in figure 27-18

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SSPCLK sclk_in rxd txd rxd Trxhold Ttxvalid

Figure 27-18. Setup / Hold Time of SSP 27.8. DMA Interface If DMA transfer is enabled in interrupt control register, and if the transmit FIFO contains data under threshold or the receive FIFO contains data over threshold, DMA request will be asserted to DMA controller to request DMA transfer as shown in figure below, between two-stage synchronization existing in SSP controller. DMA grant from DMA controller will be synchronized by SSP controller. If the request is accepted by DMA, DMA request will be pulled LOW.
PCLK Ssp_dmareq_r dmagnt

Figure 27-19. DMA Interface Timing 27.9. Loop Back Mode Testing The loop back mode test takes effect only when SSP controller is specified in master mode. The received data from external source is disconnected and transmitted data is directly connected to received data. National Semiconductor Microwire is not suitable for loop-back-mode testing due to the half-duplex feature. If loop back mode is enabled while Microwire frame format is specified, the SSP controller will get halted. 27.10. Programming Model 27.10.1. Summary of SSP Control Registers Table 27-1. Summary of SSP Control Registers Base address = 0x99400000 Offset Type Description +0x00 R/W SSP control register 0 +0x04 R/W SSP control register 1 +0x08 R/W SSP control register 2
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Technical Reference Manual Base address = 0x99400000 Offset Type +0x0C R +0x10 R/W +0x14 RC +0x18 R/W +0x20 R/W 27.10.2. 27.10.2.1.

Description SSP status register SSP interrupt control register SSP interrupt status register SSP data register AC-link slot valid register

Reset Value 0x0000_0002 0x0000_4400 0x0000_0000 0x0000_0000 0x0000_1FFF

Register Descriptions SSP Control Register 0 (Offset == 0x00)

The following sections describe details of all SSP control registers. This register controls the generation and behavior of frame / sync. Table 27-2. Bit 31-15 Name Type R SSP Control Register 0

14-12

FFMT

R/W

11-10

9-8

FSDIST

R/W

LBM

R/W

LSB

R/W

FSPO

R/W

Description Reserved, and read as zero. Frame format This register defines the pre-defined frame format according to the following encoding: 000: Texas Instrument Synchronous Serial Port (SSP) 001: Motorolas Serial Peripheral Interface (SPI) 010: National Semiconductors Microwire 011: Philipss I2S 100: Intels AC-link 101 ~ 111: Not defined. If these values are set, SSPs operation will be unpredictable. Reserved and read as zero. Frame / sync and data distance. This register only takes effect when I2S frame format is specified. This register defines the relationship between frame / sync and data bits. If this register is set to zero, first bit of serial data will be valid in the first cycle of frame / sync. If nonzero is specified, FSDIST defines the number of SCLK cycles between first bit of valid received data and frame start. For standard I2S frame format, this register has to be set to 1. Loop Back Mode. If this register is set to 1, the transmitted data will be connected to received data internally. This is used for self-test only. If this register is set to 0, SSP operates in normal mode and transmitted / received data are independent. Bit sequence indicator. If this register is set to 0, most significant bit (MSB) of data word will be transmitted / received first. If this register is set to 1, least significant bit (LSB) of data word will be transmitted / received first. Frame / sync polarity. If this register is set to 0, frame / sync will be treated as active HIGH. If this register is set to 1, frame / sync will be treated as active LOW. This register takes no effect when I2S frame format is specified.

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Technical Reference Manual Bit Name Type Description Data justify. This register is only valid when I2S frame format is specified. If this register is set to 0 and if padding data length (PDL) in control register is not zero, the number of zeros specified in PDL will be appended in back of serial data. If this register is set to 1, padding data will be in front of serial data. Operation mode. If SSP, SPI or Microwire frame format is specified, this register specifies the operation modes as follows: 00: Slave mode 01, 10, 11: Master mode If I2S frame format is specified, this register defines the operation modes as follows: 11: Master stereo mode 10: Master mono mode 01: Slave stereo mode 00: Slave mono mode SCLK polarity. This bit only takes effect when either Motorolas SPI or National Semiconductors Microwire is specified. If this register is set to 0, SCLK will remain LOW when SSP is in idle state. If this register is set to 1, SCLK will remain HIGH when SSP is in idle state. SCLK phase. This bit only takes effect when either Motorolas SPI or National Semiconductors Microwire is specified. This register defines the relationship between SCLK and frame / sync. If this register is set to 0, SCLK will start toggling after one SCLK cycle time after frame / sync is activated. If this register is set to 1, SCLK will start running after half an SCLK cycle time after frame / sync is activated.

FSJSTFY

R/W

3-2

OPM

SCLKPO

R/W

SCLKPH

R/W

27.10.2.2.

SSP Control Register 1 (Offset == 0x04)

This register defines the clock divider and data length of transfer. Table 27-3. Bit 31-24 23-21 20-16 SDL Name PDL Type R/W R R/W SSP Control Register 1

15-0

SCLKDIV

R/W

Description Padding data length. This register is only relevant if Philips I2S or National Semiconductors Microwire frame format is specified. For more details about using this register, please refer to the text below. Reserved and read as zero. Serial data length. This register defines the bit length of transmit / receive data word. The actual data length equals the register value plus 1. If National Semiconductors Microwire is specified, this register defines the bit length of second phase (receive in slave mode or transmit in master mode). SCLK divider. This register defines the serial clock divider. Section 24.5.2 describes details about SCLK generation.

If Philipss I2S frame format is specified, PDL defines the bit length of padding bits in front / back of data word. If PDL is set to 0, no padding bit will be inserted. If non-zero value is specified, the actual number of zeros will be inserted / appended in front / back of data word.

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Technical Reference Manual If National Semiconductors Microwire frame format is specified, PDL defines the bit length of first phase (transmit in master mode and receive in slave mode), and the actual data length equals the register value plus 1. The maximum value of this register should not exceed the configured FIFO depth if National Semiconductors Microwire is specified. The minimum value of this register should be larger than one. The minimum value of SDL should not be smaller than 2, and the maximum value of this register is relevant to the configured FIFO width. 27.10.2.3. SSP Control Register 2 (Offset == 0x08) This register defines the SSP enable / disable and output enable of transmitted data. Table 608 shows the format of control register 2. Table 27-4. Bit 31-7 6 Name Type R R/W SSP Control Register 2

SSPRST

ACCRST

R/W

ACWRST

R/W

3 2

TXFCLR RXFCLR

W W

TXDOE

R/W

SSPEN

R/W

Description Reserved and read as zero. SSP reset. Software reset of SSP controllers state machine. Writing 1 to this bit will cause the SSP controller to be reset. Writing 0 takes no effect. AC-link cold reset enable. If this register is written as 1 and frame format is specified as AC-link, ac97_resetn_r will be pulled active to reset the CODEC. Once reset is completed, this bit will be cleared to zero. Writing 1 to this register will clear the SSP_EN bit. Please refer to 24.6.5 for more details about AC-link reset. AC-link warm reset enable. If this register is written as 1 and frame format is specified as AC-link while SSP is disabled, SSP controller will assert FS HIGH to enter into warm reset. Once reset is completed, this bit will be cleared to zero. Writing 1 to this bit while SSP is enabled will be ignored. Please refer to 24.6.5 for more details about AC-link reset. Transmit FIFO clear. This is a write only register. If this register is written as 1, all data in transmit FIFO will be cleared. Writing this bit as 0 takes no effect. Reading this register always gets a value of zero. Receive FIFO clear. This is a write only register. If this register is written as 1, all data in receive FIFO will be cleared. Writing this bit to 0 takes no effect. Reading this register always gets a value of zero. Transmit data output enable. This register is only valid when SSP slave mode is specified. In multiple-slave systems, it is possible for an SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems, the rxd line from multiple slaves could be tied together. To operate in such systems, the TXDOE may be cleared if SSP slave is not supposed to drive the txd_r line. When TXDOE is set, the SSP will drive data on the transmit data line; when TDOE is not set, the SSP will not drive data on the transmit data line. If I2S frame format is specified, this register defines either receiving / recording mode (0) or simultaneous transmitting / receiving (playing / recording) mode (1). SSP enable. If this register is set to 1, SSP will start transmit / receive data if possible. If this register is set to 0, all data in data FIFO will be
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Technical Reference Manual Bit Name Type Description cleared and serial data will stop toggling. Note that when SSP_EN bit is cleared during active operation, SSP will stop transmitting or receiving after the current word had been transmitted or received. If AC-link frame format is specified, the SSP_EN will be cleared if AC97CRST is set. Writing to this bit will be ignored if AC97 reset is in progress.

27.10.2.4. SSP Status Register (Offset == 0x0C) This register provides internal status of SSP for the user to take corresponding action. Table 27-5. Bit 31-17 16-12 11-9 8-4 3 2 1 0 BUSY TFNF RFF R R R RFVE R Name TFVE Type R R SSP Status Register

Description Reserved and read as zero. Transmit FIFO valid entries. This register indicates the number of entries existing in transmit FIFO which are waiting to be transmitted. Reserved and read as zero. Receive FIFO valid entries. This register indicates the number of entries existing in receive FIFO which are waiting for DMA or HOST processor to read. Reserved and read as zero. Busy indicator. If this bit is read as 1, it indicates SSP is transmitting and / or receiving data. If this bit is read as 0, it indicates SSP is idle or disabled. Transmit FIFO not full. This bit is set to 1 whenever the transmit FIFO is available for DMA or host processor to write. TFNF is cleared to 0 when the FIFO is completely full. Receive FIFO full. This bit is set to 1 whenever the receive FIFO is full. RFF is cleared to 0 when DMA controller or host processor reads data from receive FIFO.

27.10.2.5. Interrupt Control Register (Offset == 0x10) This register controls the generation of interrupt from SSP. Table 27-6. Bit 31-16 15-12 Name Type R R/W Interrupt Control Register

TFTHOD

11-8 7 6

RFTHOD

R/W R

AC97FCEN

R/W

Description Reserved and read as zero. Transmit FIFO threshold. If the valid data in transmit FIFO is equal to or less than the actual threshold, DMA request and / or interrupt will be asserted. If this register is set to zero, the interrupt will happen when transmit FIFO is completely shifted out. Receive FIFO threshold. If the valid data in receive FIFO is equal to or greater than the actual threshold, DMA request and / or interrupt will be asserted. If this register is set to zero, the interrupt will be disabled. Reserved and read as zero. AC97 frame complete. This register is valid only when AC-link frame format is specified. If this register is set to 1, interrupt happens when each AC97 frame is transmitted completely. If this register is set to 0,
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Technical Reference Manual Bit Name Type Description interrupt will not happen when each AC97 frame is transmitted completely. Transmit DMA request enable. If this register is set to 1, DMA request will be made when transmit FIFO threshold (TFLETH is set to 1) is hit. If this register is set to 0, no DMA request will be made. Receive DMA request enable. If this register is set to 1, DMA request will be made when receive FIFO threshold (RFGETH is set to 1) is hit. If this register is set to 0, no DMA request will be made. Transmit FIFO threshold interrupt enable. If this register is set to 1, interrupt will be made when the valid entries in transmit FIFO are less than or equal to threshold value. Receive FIFO threshold interrupt enable. If this register is set to 1, interrupt will be made when the valid entries in receive FIFO are greater than or equal to threshold value. Transmit FIFO under-run interrupt enable. If this register is set to 1, transmit FIFO under-run will cause SSP to assert interrupt. If this register is set to 0, interrupt will be masked even when transmit FIFO under-run happens. Receive FIFO over-run interrupt enable. If this register is set to 1, receive FIFO over-run will cause SSP to assert interrupt. If this register is set to 0, interrupt will be masked even when receive FIFO over-run happens.

5 4 3 2

TFDMAEN RFDMAEN TFTHIEN RFTHIEN

R/W R/W R/W R/W

TFURIEN

R/W

RFORIEN

R/W

27.10.2.6. Interrupt Status Register (Offset == 0x14) This register shows the current interrupt status. Bit 31-5 4 Name AC97FCI Type R RC Table 27-7. Interrupt Status Register Description Reserved and read as zero. AC97 frame complete interrupt. If AC-link frame is completed, this register will be set to 1 and interrupt happens. This register will be cleared when interrupt status register is read or SSP is disabled. Transmit FIFO threshold interrupt. If TFTHIEN is set to 1 and TFTHOD is set to non-zero, this bit is set to 1 when transmit FIFO is equal to or less than the threshold. If the valid entries in transmit FIFO are larger than TFTHOD, this bit will be cleared automatically. If TFTHIEN is set to 1 and TFTHOD is set to zero, this bit is set to 1 when the last data in transmit FIFO is completely shifted out. This register is never cleared to zero until user reads this register. Receive FIFO threshold interrupt. If RFTHIEN is set to 1 and receive FIFO is equal to or greater than the threshold, this bit will be set to 1. This register will be cleared to zero when interrupt status register is read. Transmit FIFO under-run interrupt. If transmit logic tries to retrieve data from empty transmit FIFO for transmission and TFURIEN is enabled, this register will be set to 1. This register will be cleared when the under-run condition is removed. Receive FIFO over-run interrupt. If this receive tries to receive data when
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TFTHI

R / RC

RFTHI

1 0

TFURI RFORI

R R

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Technical Reference Manual Bit Name Description receive FIFO is full, this register will be set to 1. This register will be cleared when the over-run condition is removed. SSP Transmit / Receive Data Register (Offset == 0x18) Type

27.10.2.7.

The SSP possesses separate transmit and receive FIFOs. Both are 32-bit wide but the size of transmit FIFO or receive FIFO can be configured separately (refer to Hardware Configurations for more details). Transmitted data and received data occupy the same address space. Write operation will write data into transmit FIFO and read operation will read data from receive FIFO. If the size of serial data length is less than 32-bit wide, data will be right justified automatically at the time of reception or transmission. 27.10.2.8. AC-Link Slot Valid Register (Offset == 0x20)

This register specifies the valid slot in one AC-link frame. If the corresponding slot valid bit is set to 0, the SSP controller will not read / write FIFO while the corresponding slot is transmitted / received. SSP controller only reads / writes FIFO while the corresponding slot valid is set to 1. Slot 0 (TAG slot) is always valid during transmission / reception. If AC-link function is not configured in SSP, this register will take no effect. Bit 31-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1-0 Name SLOT1V SLOT2V SLOT3V SLOT4V SLOT5V SLOT6V SLOT7V SLOT8V SLOT9V SLOT10V SLOT11V SLOT12V CODECID Type R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Table 27-8. AC97 Mask Control Register Description Reserved and read as zero This bit is always read as 1. 1st slot is valid. 2nd slot is valid. 3rd slot is valid 4th slot is valid 5th slot is valid 6th slot is valid 7th slot is valid 8th slot is valid 9th slot is valid 10th slot is valid 11th slot is valid 12th slot is valid Reserved and read as zero CODEC ID. These two bits indicate the CODEC ID which will be shifted out at TAG slog.

27.11. Programming Guideline This section illustrates the initialization sequence of the SSP controller. First of all, the user has to determine whether to use master mode or slave mode for their application. Once the mode is determined, just follow the initialization sequence given in master mode initialization of slave mode initialization to initialize SSP.
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Technical Reference Manual 27.11.1. 1. Master Mode Initialization

The following steps show the sequence of transmitting / receiving data to / from slave: Specify the frame format, operation mode (as master) and polarity of frame output. If Motorolas SPI is specified, specify SCLKPO and SCLKPH at the same time. if Philipss I2S is specified, specify the FSDIST at the same time. 2. 3. 4. 5. Specify the bit rate by setting serial clock divider and serial data length. If Intels AC-link frame format is specified, the serial data length will be ignored. Fill transmitted data into transmit FIFO. Enable transmit or receive interrupt and DMA request, if required. Enable SSP and turn on transmit data output enable. After the above steps, SSP controller will start transmitting / receiving data without users intervention. SSP will report FIFO status or transmitting / receiving status to the user if the corresponding interrupt is enabled. SSP will request DMA to transfer data if DMA is enabled. If all data in transmit FIFO is transmitted, SSP will report transmit data empty if interrupt is enabled. Note that SSP controller reports transmit FIFO empty before transmission is completed. That is, the transmit logic may be busy transmitting the last data out. The user has to monitor the SSP busy flag to confirm the completeness of the transmission. The frame / sync output is sensitive to the FIFO status. If the last data in transmit FIFO is complete and no more data is filled, the frame / sync will go back to IDLE state. For an application which is sensitive to action of frame / sync, the user has to pay attention to this situation. For example, the transfer of ATMELs AT25080 EEPROM must consist of command and data phase. In the ideal condition, transfer can be continued if transmit FIFO does not run out of data. If that happens, the chip-enable (usually frame / sync) goes back to de-select state and the next transfer has to be restarted by heading command phase. 27.11.2. 1. Slave Mode Initialization

The following steps show the sequence of transmitting / receiving data to / from master: Specify the frame format, operation mode (as slave) and polarity of frame output. If Motorolas SPI is specified, specify SCLKPO and SCLKPH at the same time. If Philipss I2S is specified, specify the FSDIST at the same time. The SSP controller in Intels frame format as slave mode is not allowed. 2. 3. Specify the serial data length. In National Semiconductors Microwire or Philipss I2S frame format, specify padding data length, if required. Fill the transmit FIFO, if needed.
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Technical Reference Manual 4. 5. Enable transmit or receive interrupt and DMA request, if required. Enable SSP and turn on transmit data output enable, if allowed. In slave mode, external master controls the action of SSP controller. The SSP controller will act upon dependent on frame / sync, serial clock input.

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28. DC Characteristics
28.1. Absolute Maximum Ratings Parameter Core power supply Input voltage of 1.8v I/O Input voltage of 3.3V I/O Input voltage of 3.3V I/O Storage temperature Rating -0.3 to 3.6 -0.3 to 2.1 -0.3 to 3.63 -0.3 to 3.63 -40 to 150 Unit V V V V 0 C

Symbol VCCK VIN18 VIN3 TSTG 28.2.

Recommended Operating Conditions Parameter Core power supply Power supply of I/Os Input voltage of 3.3V I/O Commercial ambient operating temperature operating up to 180 MHz Industrial ambient operating temperature up to 144 MHz I/O Pad Capacitance Parameter Input capacitance Output capacitance Bi-directional capacitance Condition Min. Typ. 3.2 3.2 3.2 Max. Unit pF pF pF Min. 1.65 2.97 2.25 1.62 0 0 -40 Typ. 1.8 3.3 2.5 1.8 3.3 25 25 Max. 1.98 3.63 2.75 1.98 3.63 75 85 Unit V V

Symbol VCCK VCC3IO VIN3 TA

V
V V
0

C C

28.3.

Symbol CIN COUT CBID 28.4.

DC Characteristics for XIN Crystal Descriptions Power supply for XIN crystal Input high voltage Condition 1.8V power supply CMOS Min. 1.62 0.7* VCCKXI N Typ. 1.8 Max. 1.98 Unit V V

Symbol VCCKXIN VIh

28.5.

DC Characteristics for OSLIN Crystal Condition 1.8V power supply CMOS Min. 1.62 0.7* Typ. 1.8 Max. 1.98 Unit V V

Descriptions Power supply for OSCLIN VCCKOSCL crystal VIh Input high voltage

Symbol

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Technical Reference Manual VCCKXO SCL 28.6. Characteristics for 25 MHz (Ethernet PHY) Descriptions Power supply for internal core cells and I/O to core interface Input high voltage Condition 1.8V power supply CMOS Min. 1.62 0.7* VCCK 25 0.005% 40 Typ. 1.8 25 50 Max. 1.98 25 + 0.005% 60 Unit V V MHz %

Symbol VCCK VIh

Reference frequency Reference clock duty cycle 28.7. Characteristics for 12 MHz (USB OTG PHY)

Symbol Descriptions Condition VIh Input high voltage LVTTL Reference frequency error less than 500PPM Reference clock duty cycle 28.8. DC Characteristics for 3.3V I/O Pins Descriptions Core power supply Power supply Input low voltage Input high voltage Switching threshold Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Input leakage current Tri-state output leakage current Condition Core area 3.3V I/O LVTTL LVTTL LVTTL LVTTL LVTTL IOL = 2 ~ 16 mA IOL = -2 ~ -16 mA Vin = 0 Vin = 3.3V Vin = 3.3V or 0

Min. 2.0 120.006 40

Typ. 12 50

Max. 12+0.0 06 60

Unit V MHz %

Symbol VCCK VCC3IO VIL VIh Vt VtVt+ VOL VOH RPU RPD Iin IOZ 28.9.

Min. 1.62 2.97 2.0 0.8 2.4 40 45 -10 -10

Typ. 1.8 3.3 1.5 1.1 1.6 75 75 1 1

Max. 1.98 3.63 0.8 2.0 0.4 190 190 10 10

Unit V V V V V V V V V K K A A

DC Characteristics for 2.5 V I/O Pins

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Technical Reference Manual Symbol VCCK VCC3IO VIL VIh Vt VtVt+ VOL VOH RPU RPD Iin Ioz Descriptions Core power supply Power supply Input low voltage Input high voltage Switching threshold Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Input leakage current Tri-state output leakage current Condition Core area 1.8V I/O CMOS CMOS CMOS CMOS CMOS IOL = 1.1 ~ 8.8 mA IOL = -2 ~ -8.8 mA Vin = 0 Vin = VCC3IO Vin = VCC3IO or 0 Min. 1.62 2.25 0.65* VCC3IO 0.25* VCC3IO 1.85 45 45 -10 -10 Typ. 1.8 2.5 1.15 0.94 1.4 110 115 1 1 Max. 1.98 2.75 0.25* VCC3IO 0.65* VCC3IO 0.4 290 290 10 10 Unit V V V V V V V V V K K A A

28.10. DC Characteristics for 1.8 V I/O Pins Symbol VCCK VCC3IO VIL VIh Vt VtVt+ VOL VOH RPU RPD Iin Descriptions Core power supply Power supply Input low voltage Input high voltage Switching threshold Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Input leakage current Condition Core area 1.8V I/O CMOS CMOS CMOS CMOS CMOS IOL = 2 ~ 16 mA IOL = -2 ~ -16 mA Vin = 0 Vin = VCC3IO Vin = VCC3IO or 0 Min. 1.62 1.62 0.7* VCC3IO 0.3* VCC3IO 0.75* VCC3IO 80 80 -10 Typ. 1.8 1.8 0.85 0.65 1.08 200 210 1 Max. 1.98 1.98 0.3* VCC3IO 0.7* VCC3IO 0.4 510 510 10 Unit V V V V V V V V V K K A

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Technical Reference Manual Ioz Tri-state output leakage current Vin = 0 -10 1 10 A

28.11. Power Consumption Operating conditions Normal mode @ 180 MHz for commercial temperature Normal mode @ 144 MHz for industrial temperature Standby mode Sleep mode 28.12. DC Characteristics for PLLs Symbol VCC18PLL Ipd Iop Isb V V
ih

Power consumption tbd tbd tbd tbd

Unit mW mW mW mW

Descriptions Analog supply voltage Power down current Operating current Power down Input logic level high Input logic level low

Condition PDN = 0 (PLL control register) PDN = H Reference clock toggles PDN = 1 Reference clock is either L or High

Min. 1.62 90% of VCCK

Typ. 1.8 -

Max. 1.98 5 3 1 10% of VCCK 5 300 300 70 50 40 600 500 350 1.1

Unit V A mA mA V V MHz MHz MHz ps ps ps ps ps ps ns

il

1 20 1 60 40 30 500 400 300 0.75

FREFX CKOUT FREF

PFD operating frequency FREF / MS [8:0] Output clock range Input clock range 20MHz CKOUT 40MHz 40MHz < CKOUT Cycle-to-cycle jitter 80MHz (RMS) 80MHz < CKOUT 300MHz 20MHz CKOUT 40MHz Cycle-to-cycle jitter (peak-to-peak) 40MHz < CKOUT 80MHz 80MHz < CKOUT 300MHz 20MHz CKOUT 50MHz, FRANGE = 0

cc

lt

Long-term jitter (RMS, 10s)

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Technical Reference Manual 50MHz < CKOUT 100MHz, FRANGE = 0 100MHz < CKOUT 200MHz, FRANGE = 1 200MHz < CKOUT 300MHz, FRANGE = 1 20MHz CKOUT 50MHz, FRANGE = 0 50MHz < CKOUT 100MHz, Long-term jitter (peak-to- FRANGE = 0 peak, 10s) 100MHz < CKOUT 200MHz, FRANGE = 1 200MHz < CKOUT 300MHz, FRANGE = 1 Lock-in time Input clock duty ratio 20MHz CKOUT 100MHz 100MHz < CKOUT 200MHz 200MHz < CKOUT 300MHz

20 45 40 35

0.5 0.45 0.15 4 3 3 1 0.3 -

0.75 0.8 0.35 6 4.5 3.5 1.5 1 80 55 50 65

ns ns ns ns ns ns ns ms % % % %

lock

DRin

DRout

Output clock duty ratio

28.13. DC Characteristics for DLL Symbol VCC18DL L Ipd Iop Isb V V Descriptions Analog supply voltage Power down current Operating current Power down Input logic level high Input logic level low Condition PDN = 0 (DLL control register) PDN = H Reference clock toggles PDN = 1 Reference clock is either L or High Min. 1.62 90% of VCCK Typ. 1.8 Max. 1.98 5 3 1 10% of Unit V A mA mA V V

ih

il

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Technical Reference Manual VCCK 100 300 300 70 50 20 600 500 200 0.4 0.125 0.125 0.05 2.5 0.9 0.75 0.25 0.5 80 55 60

FREFX CKOUT FREF J

cc

PFD operating frequency Output clock range Input clock range Cycle-to-cycle jitter (RMS)

FREF / MS [5:0]

5 20 5 20

50 30 15 500 300 125 0.15 0.1 0.1 0.025 1.5 0.7 0.5 0.2 0.2 -

MHz MHz MHz ps ps ps ps ps ps ns ns ns ns ns ns ns ns ms % % %

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20MHz CKOUT 40MHz 40MHz < CKOUT 80MHz 80MHz < CKOUT 300MHz

Cycle-to-cycle jitter (peak-to-peak)

20MHz CKOUT 40MHz 40MHz < CKOUT 80MHz 80MHz < CKOUT 300MHz

lt

Long-term jitter (RMS, 10s)

Long-term jitter (peakto-peak, 10s)

20MHz CKOUT 50MHz, FRANGE = 0 50MHz < CKOUT 100MHz, FRANGE = 0 100MHz < CKOUT 200MHz, FRANGE = 1 200MHz < CKOUT 300MHz, FRANGE = 1 20MHz CKOUT 50MHz, FRANGE = 0 50MHz < CKOUT 100MHz, FRANGE = 0 100MHz < CKOUT 200MHz, FRANGE = 1 200MHz < CKOUT 300MHz, FRANGE = 1

lock

Lock-in time Input clock duty ratio Output ratio clock duty 20MHz CKOUT 100MHz 100MHz < CKOUT

DRin DRout

45 40

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Technical Reference Manual 200MHz 200MHz < CKOUT 300MHz 28.14. USB OTG PHY 28.14.1. Symbol AVCC VCC ICC Electrical characteristics Descriptions Analog supply current Digital supply current Operating supply current Condition VCCHSRT and VCCA_U20 belong to AVCC group VCCK_U20 High speed operation at 480 MHz In suspend mode, current with 1.5 K pull-up resistor on pin RPU disconnected Analog I/O Pins (DP/DM) Condition |VI(DP) VI(DM)| Measured at the connection as an application circuit. Squelch is detected Squelch is not detected Disconnection is detected Disconnection is not detected Resistance Equivalent resistance Min. 300 Typ. Max. Unit mV Min. 3.0 1.62 Typ. 3.3 1.8 Max. 3.6 1.96 60 50 Unit V V mA A

35

65

ICC(susp) Suspend supply current

28.14.2.

Static Characteristics:

Symbol Descriptions USB 2.0 Transceiver (HS) Input Levels (Differential Receiver) VHSDIFF High speed differential input sensitivity VHSCM VHSSQ VHSDSC High speed data signaling common mode voltage range High speed squelch detection threshold High speed disconnection detection threshold

50 150 625 10 10 360 700 900 40.5

45

500 100 525 10 10 400 1100 500 49.5

mV mV mV mV mV mV mV mV mV mV

Output Levels VHSOI High speed idle level output voltage (differential) VHSOL High speed low level output voltage (differential) VHSOH High speed high level output voltage (differential) VCHIRPJ Chirp-J output voltage (differential) VCHIRPK Chirp-K output voltage (differential) RDRV Driver output impedance

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Technical Reference Manual used as internal chip Termination VTERM Termination voltage for pullup resistor on pin RPU USB 1.1 Transceiver (FS / LS) Input Levels (Differential Receiver) VDI Differential input voltage sensitivity VCM Differential common mode voltage Input Levels (Single-Ended Receivers) VSE Single-ended receiver threshold Output Levels VOL Low level output voltage VOH High level output voltage 28.14.3. Dynamic Characteristics: 3.0 3.6 V

|VI(DP)- VI(DM)| Analog I/O Pins (DP/DM) Condition CL = 50 pF; 10 to 90 % of |VOH VOL| CL = 50 pF; 90 to 10 % of |VOH VOL| First transition from idle mode excluded First transition from idle mode excluded CL = 200-600 pF; 10 to 90 % of |VOH VOL| CL = 200-600 pF; 90 to 10 % of |VOH VOL| Excluding the first transition from idle mode Excluding the first transition from idle mode

0.2 0.8 0.8 0 2.8

2.5 2.0 0.3 3.6

V V V V V

Symbol Descriptions Driver Characteristics High-Speed Mode tHSR High-speed differential rise time tHSF High-speed differential fall time Full-Speed Mode tFR Rise time of DP/DM tFF tFRMA Fall time of DP/DM

Min. 500 500 4 4 90 1.3 75 75

Typ. -

Max. 20 20 110 2.0 300 300 125 2.0

Unit ps ps ns ns % V ns ns % V

Differential rise/fall time matching (tFR / tFF) VCRS Output signal crossover voltage Low Speed Mode tLR Rise time of DP/DM tLF tLRMA Fall time of DP/DM

Differential rise/fall time 80 matching (tLR / tLF) VCRS Output signal crossover 1.3 voltage Driver Timing High Speed Mode Driver waveform requirement See eye pattern of template Follow template 1 1 described in USB rev. 2.0 spec
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Technical Reference Manual Full Speed Mode Propagation delay (VI, FSE 0, OE to DP, DN)

For detailed description of VI, FSE 0 and OE, please refer to USB rev. 1.1 spec.

15

ns

Low Speed Mode Not specified: Low speed delay time is dominated by the slow tLR and tLF Receiver Timing High Speed Mode (Template 4, USB 2.0 Spec.) Data source jitter and See eye pattern of template Follow template 4. receiver jitter tolerance 4 described in USB rev 2.0 spec Full Speed Mode tPLH(rcv) Receiver propagation delay For a detailed description of tPHL(rcv) (DP; DM to RCV) RCV, please refer to USB 1.1 spec. tPLH(single) Receiver propagation delay tPHL(single) (DP; DM to VOP, VON) 28.15. Power Consumption Operating conditions (Commercial temperature) Active mode 1.8V 160 MHz 3.3V Configuration registers: 1. AHBMCLKOFF = 0x0000 0C02 Ethernet Phy @ 1.8V 2. APBMCLKOFF = 0x0000 0000 Ethernet Phy @ 3.3V 3. CCR = 0x0000 0000 USB Phy @ 3.3V Total Turn off clock of LCD 160 MHz Configuration registers: 1. AHBMCLKOFF = 0x0000 1C02 2. APBMCLKOFF = 0x0000 0000 3. CCR = 0x0000 0000 Turn off clock of AES 160 MHz System configuration registers: 1. AHBMCLKOFF = 0x0000 2C02 2. APBMCLKOFF = 0x0000 0000 3. CCR = 0x0000 0000 Turn off clocks of 160 MHz VideoCapture, MediaCodec, Configuration registers: 1. AHBMCLKOFF = 0x0001 BE02 LCD, AES, DMA, Ethernet, and USB 2. APBMCLKOFF = 0x0002 0000 3. CCR = 0x3C80 0000 Standby mode 1.8V Standby instruction to deactive 3.3V JEMCore-II Ethernet Phy @ 1.8V LCD, AES, and DMA are inactive Ethernet Phy @ 3.3V
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15 15

ns ns

Power consumption 712 85 112 203 37 1149 1080

Unit mW mW mW mW mW mW mW

1042

mW

365

mW

607 86 114 206

mW mW mW mW
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Technical Reference Manual Other peripherals are active Configuration registers: 1. AHBMCLKOFF = 0x0000 3E02 2. APBMCLKOFF = 0x0002 0000 3. CCR = 0x3C80 0000 Sleep instruction to deactivate JEMCore-II All peripherals are inactive PLLs are deactivated USB Phy @ 3.3V Total 38 1051 mW mW

Sleep mode 1.8V 3.3V Ethernet Phy @ 1.8V Ethernet Phy @ 3.3V USB Phy @ 3.3V Total

4 3 0 0 0 7

mW mW mW mW mW mW

28.16. ESD and Latchup Description Human body mode (HBM) Machine mode (MM) Latch up Specification > 2KV > 200V > 200mA

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29. AC Characteristics
Unless otherwise specified, all AC timings are measured with the load of 30 pF. 29.1. AC Timing for SDRAM Interface

SDCLK Output Signal tov toh

SDCLK tds Output Signal

Parameter tOV tOH tDS tDH 29.2. 29.2.1. Write Cycle
SDCLK MADDR[24:0] SMC_CS[7:0]n MWEn MBEn[3:0] MDATA[31:0] MDATA[31:0]

thd

Description Output valid time from clock Output hold time from clock Data input setup time Data input hold time

Min 1.72 1.77 0.54

Max 3.73

Unit ns ns ns ns

AC Timing for SMC Interface

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Technical Reference Manual Parameters tAST tCTW {tEAT1, tAT1} tWTC tAHT {tETRNA, tTRNA} 29.2.2. Read Cycle
SDCLK MADDR[24:0] SMC_CS[7:0]n MBEn[3:0] MDATA[31:0]

Description Address setup time Chip select to write enable delay Write enable width Write enable to chip select delay Address hold time Around time

Min 0 0 3 0 2 {0

Max 4 4 257 4 5 255

Unit SDCLK cycle time SDCLK cycle time SDCLK cycle time SDCLK cycle time SDCLK cycle time SDCLK cycle time

Parameter tAST tCTW {tEAT1, tAT1} tWTC tAHT {tETRNA, tTRNA} 29.3.

Description Address setup time Chip select to write enable delay Write enable width Write enable to chip select delay Address hold time Around time

Min 0 0 3 0 2 {0

Max 4 4 257 4 5 255

Unit SDCLK cycle time SDCLK cycle time SDCLK cycle time SDCLK cycle time SDCLK cycle time SDCLK cycle time

AC Timing for I2C Interface

Parameter tsu. tDV tsu.STO

Description STA START setup time SDA valid time STOP setup time

Min see Note 1 see Note 2 see Note 3

Max see Note 1 see Note 2 see Note 3

Unit ns ns ns

Notes 1. START setup time = tpclk x count[9:0], where tpclk is the clock cycle time of PCLK, and count[9:0]
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Technical Reference Manual is CDR register. SDA valid time = tpclk x TSR[9:0], where tpclk is the clock cycle time of PCLK, and TSR[9:0] is TGSR register. STOP setup time = tpclk x count[9:0], where tpclk is the clock cycle time of PCLK, and count[9:0] is CDR register. AC Timing for SD Card Interface

2. 3. 29.4.

SD_CLK tov Output Signal

Note: SDIO, SD_CMD_RSP, SD_WP, SD_CD

SD_CLK tsu Output Signal

Note: SDIO, SD_CMD_RSP, SD_WP, SD_CD Parameter tOV tsu thd 29.5. Description Output data valid time Input data setup time Input data hold time Min 2.73 1.08 Max 6.1 Unit ns ns ns

thd

AC Timing for CCIT-656 Input

VCAP1&2&3_ICLK tsu Valid

Min 4.34 ns Max Unit ns

VCAP0&1&3_VD[7:0]
Parameter Tsu Description Pixel data bus setup time

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Technical Reference Manual 29.6. AC Timing for CCIT-656 Output

TVCLK

Tvalid

PIX_DO[7:0]
Parameter Tvalid 29.7. Description TVCLK to data bus valid delay Min Max 6.03 Unit ns

AC Timing for Sony 16-bit YUV Input Description Pixel data bus setup time Min 4.34 ns Max Unit ns

Parameter Tsu 29.8. 29.8.1. Cold Reset

AC Timing for AC97 Interface

Trst_low

Trst2clk

I2SCLK
Parameter Trst_low Trst2clk 29.8.2. Warm Reset
Trst_high

Description AC97_RESETn active low pulse width AC97_RESETn inactive to SCLK startup delay

Min 1 162.8

Max 40018

Unit ns ns

AC97FS

Tsync2clk

I2SCLK

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Parameter Tsync_high Tsync2clk

Description I2SFS active low pulse width I2SFS inactive to SCLK startup delay
Tclk_high

Min 1 162.8

Max

Unit s ns

29.8.3. AC Link Clock

Tclk_low

Tclk_period Tsync_high Tsync_low

I2SFS
Tsync_period

Parameter Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low

Description I2SCLK period I2SCLK high pulse width I2SCLK low pulse width I2SFS period I2SFS high pulse width I2SFS low pulse width

Min 36 36

Typ 81.4 20.8 1.3 19.5

Max 45 45 ns

Unit ns ns ns s s s

29.8.4. Data Input and Output

I2SCLK

Tco

AC97FS I2STxD
Tsetup Thold

I2SRxD

Valid

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Technical Reference Manual Parameter Tco Tsetup Thold Description Output valid delay from rising edge of I2SCLK Input setup to falling edge of I2SCLK Input hold from falling edge of I2SCLK Min 1 ns 2.6 ns 1 ns Typ 81.4 Max 45 45 ns Unit ns ns ns

29.8.5. Signal Rise and Fall Time

I2SCLK

Trise_clk

Tfall_clk

I2SFS

Trise_clk

Tfall_clk

I2STxD

Trise_clk

Tfall_clk

I2SRxD

Trise_clk

Tfall_clk

Parameter Trise_clk Tfall_clk Trise_fs Tfall_fs Trise_rx Tfall_rx 29.9.

Description X_AC97_BITCLK rise time X_AC97_BITCLK fall time X_AC97_FS rise time X_AC97_FS fall time X_AC97_RXD rise time X_AC97_RXD fall time

Min

Typ

Max 3.58 3.58 3.64 3.64 3.64 3.64

Unit ns ns ns

AC Timing for I2S Interface

Thc

Tlc T

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Technical Reference Manual Parameter T THC TLC TRC Description Clock period Clock high See Note Clock low See Note Clock rise time Min See Note 1 See Note 2 See Note 2 See Note 3 Typ Max Unit ns ns ns ns

3.58

Notes 1. T = (codecmclk period) x 2(SCLKDIV+1) 2. THC or TLC = (codecmclk period) x (SCLKDIV+1)

I2SCLK

Tst

Thr

I2SFS I2SRxD
Parameter Tsr Thr Description Signal setup time Signal hold time Min 2.18 1 Typ Max Unit ns ns

29.10. AC Timing for Ethernet PHY AC Specifications Parameters Reference frequency Reference clock duty cycle Transmitter Specifications Peak-to-peak differential output voltage Peak-to-peak differential output voltage, 2 x Vtxa Signal rise / fall time, Tr / Tf Output jitter Test Condition Min 25 - 0.005% 40 4.5 1.9 3 1.4 5 10 300 1.2 100 Typ 25 50 5 2 4 ns % 400 1.65 500 2 KOhm mV V Meters Max 25 + 0.005% 60 5.5 2.1 5 Unit MHz % V V ns

10BASE-T mode 100BASE-TX mode 100BASE-TX mode 100BASE-TX mode, scrambled idle signal 100BASE-TX mode

Overshoot, Vtxa Receiver Specifications Receive input impedance Differential squelch voltage 10BASE-T mode Common mode input voltage Maximum error-free cable length DC Specifications Parameter
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Min

Typ

Max

Unit
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Technical Reference Manual 3.3 V supply voltage 1.8 V supply voltage Total dissipative power Output jitter Overshoot, Vtxa 2.97 1.62 100BASE-TX mode 10BASE-TX mode Power down mode 100BASE-TX mode, scrambled idle signal 100BASE-TX mode 3.3 1.8 3.63 1.98 360 500 200 V V mW mW W

1.4 5

ns %

30. ESD and Latchup

Deescription Human Body Mode (HBM) Machine Mode (MM) Latch up Specification > 2kV > 200V > 200mA

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