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APPLICATION

NOTE
AP-476
ApiiI 1993
How to Implement
I
2
C Serial Communication
Using Intel MCS-51
Microcontrollers
SABRINA D QUARLES
APPLICATIONS FNOINFFR
Order Number 272319-001
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COPYRIGHT INTEL CORPORATION 1996
How to Implement I
2
C Serial Communication
Using Intel MCS-51 Microcontrollers
CONTENTS PAGE
INTRODUCTION 1
I
2
C-Bus System 1
I
2
C Hardware Characteristics 1
I
2
C Protocol Characteristics 2
MCS-51 Hardware Requirements 4
MCS-51 I
2
C Software Emulation
Modules 5
CONTENTS PAGE
MCS-51 and I
2
C-Bus Compatible ICs
System Implementation 6
I
2
C Software Emulation Performance 7
CONCLUSION 7
REFERENCES 7
AP-476
INTRODUCTION
Did you know that you couId impIement I
2
C function-
aIity using the InteI MCS-51 famiIy of miciocontioI-
Ieis! The I
2
C-bus aIIows the designei to impIement in-
teIIigent appIication-oiiented contioI ciicuits without
encounteiing numeious inteifacing piobIems. This bus
simpIicity is maintained by being stiuctuied foi eco-
nomicaI, efficient and veisatiIe seiiaI communication.
Pioven I
2
C appIications aie cuiientIy being impIement-
ed in digitaI contioI/signaI piocessing ciicuits foi audio
and video systems, DTMF geneiatois foi teIephones
with tone diaIing and ACCFSS.bus, a Iowei-cost aItei-
native foi the RS-232C inteiface used foi connecting
peiipheiaIs to a host computei.
This appIication note desciibes a softwaie emuIation
impIementation of the I
2
C-bus Mastei-SIave configuia-
tion using InteI MCS-51 miciocontioIIeis. It is iecom-
mended that the ieadei become famiIiai with the PhiI-
Iips Semiconductois I
2
C-bus Specification and the InteI
MCS-51 Aichitectuie. Howevei, it is possibIe to gain a
basic undeistanding of the I
2
C-bus and the I
2
C emuIa-
tion softwaie fiom this appIication note.
I
2
C-Bus System
The Intei-Integiated Ciicuit Bus commonIy known as
the I
2
C-bus is a bi-diiectionaI two-wiie seiiaI communi-
cation standaid. It is designed piimaiiIy foi simpIe but
efficient integiated ciicuit (IC) contioI. The system is
compiised of two bus Iines, SCL (SeiiaI CIock) and
SDA (SeiiaI Data) that caiiy infoimation between the
ICs connected to them. Vaiious communication config-
uiations may be designed using this bus, howevei, this
appIication note discusses onIy the Mastei-SIave system
impIementation.
Devices connected to the I
2
C-bus system can opeiate as
Masteis and SIaves. The Mastei device contioIs bus
communications by initiating/teiminating tiansfeis,
sending infoimation and geneiating the I
2
C system
cIock. On the othei hand, the SIave device waits to be
addiessed by the contioIIing Mastei. Upon being ad-
diessed, the SIave peifoims the specific function ie-
quested. An exampIe of this configuiation is a Mastei
ContioIIei sending dispIay data to a LFD SIave Receiv-
ei that wouId then output the iequested dispIay.
The configuiation desciibed above is the most com-
mon, howevei, at times the SIave can become a Tians-
mittei and the Mastei a Receivei. Foi exampIe, the
Mastei may iequest infoimation fiom an addiessed
SIave. This iequiies the Mastei to ieceive data fiom the
SIave. It is impoitant to undeistand that even duiing
Mastei Receive/SIave Tiansmission, the geneiation of
cIock signaIs on the I
2
C bus is aIways the iesponsibiIity
of the Mastei. As a iesuIt, aII events on the bus must be
synchionized with the Masteis SCL cIock Iine.
I
2
C Hardware Characteristics
Both SCL (SeiiaI CIock) and SDA (SeiiaI Data) aie bi-
diiectionaI Iines that aie connected to a positive suppIy
voItage via puII-up iesistois. Figuie 1 dispIays a typicaI
I
2
C-bus configuiation. Devices connected to the bus ie-
quiie open-diain oi open-coIIectoi output stage intei-
faces. As a iesuIt of these inteifaces, the iesistois puII
both Iines HIOH when the bus is fiee. The fiee state is
defined as SDA and SCL HIOH when the bus is not in
use.
SCL e Serial Clock
27231918
SDA e Serial Data
Figure 1 I
2
C MasterSlave Bus System
1
AP-476
One impoitant bus chaiacteiistic enabIed as a iesuIt of
this haidwaie configuiation is the wiied-AND func-
tion. SimiIai to the Iogic AND tiuth tabIe, when diiven
by connected ICs, I
2
C-bus Iines wiII not indicate the
HIOH state untiI aII devices veiify that they too have
achieved the same HIOH state. An I
2
C-bus system ie-
Iies on wiied-AND functionaIity to maintain appiopii-
ate cIock synchionization and to communicate effec-
tiveIy with extiemeIy high and Iow speed devices. As a
iesuIt, a ieIativeIy sIow I
2
C device can extend the sys-
tem cIock untiI it is ieady to accept moie data.
I
2
C Protocol Characteristics
This section wiII expIain a compIete I
2
C data tiansfei
emphasizing data vaIidity, infoimation types, byte foi-
mats, and acknowIedgment. Figuie 2-1 dispIays the
typicaI I
2
C piotocoI data tiansfei fiame. The impoitant
fiame components aie the START/STOP conditions,
SIave Addiess, and Data with AcknowIedgment. This
fiame stiuctuie iemains constant except foi the numbei
of data bytes tiansfeiied and the tiansmission diiec-
tion. It can be seen that aII functionaIity except Ac-
knowIedgment is geneiated by the Mastei and cuiient
tiansmittei. Figuie 2-2 dispIays a moie detaiIed iepie-
sentation focusing on specific timing sequences of con-
tioI signaIs and data tiansfeis.
27231919
Figure 2-1 I
2
C Protocol Data Transfer Frame
DATA VALIDITY
Figuie 3 shows the bit tiansfei piotocoI that must be
maintained on the I
2
C-bus. The data on the SDA Iine
must be stabIe duiing the HIOH peiiod of the SCL
cIock. The HIOH oi LOW state of SDA can onIy
change when the cIock signaI on the SCL is LOW. In
addition, these bus Iines must meet iequiied setup, hoId
and iise/faII times piesciibed in the timing section of
the I
2
C piotocoI specifications.
27231920
Figure 2-2 A Complete I
2
C Data Transfer
27231921
Figure 3 Bit Transfer on the I
2
C-Bus
2
AP-476
Control Signals
START and STOP conditions aie used to signaI the
beginning and end of data communications. A Mastei
geneiates a START condition (S) to obtain contioI of a
fiee I
2
C-bus by foicing a HIOH to LOW tiansition on
the SDA Iine whiIe maintaining SCL in its HIOH state.
This condition is geneiated duiing softwaie emuIation
in the MASTFR-CONTROLLFR subioutine de-
sciibed in anothei section. Again, START conditions
may be geneiated by a Mastei onIy when the I
2
C-bus is
fiee. This fiee bus state exists onIy when no othei Mas-
tei devices have contioI of the bus (i.e. both SCL and
SDA Iines aie puIIed to theii noimaI HIOH state).
Upon gaining contioI of the bus, the Mastei must
tiansfei data acioss the system. Aftei a compIete data
tiansfei, the Mastei must ieIease the bus by geneiating
a STOP (P) condition. The SFND
-
STOP subioutine
desciibed in a Iatei section ends data communications
by sending an I
2
C STOP.
Data Transfers
The SIave addiess and data being tiansfeiied acioss the
bus must confoim to specific byte foimats. The onIy
byte tiansmission iequiiement is that data must be
tiansfeiied with its Most Significant Bit (MSB) fiist.
Howevei, the numbei of bytes that can be tiansmitted
pei tiansfei is uniestiicted. Foi both Mastei Tiansmit/
Receive, the MASTFR
-
CONTROLLFR subioutine
desciibed in a Iatei section peifoims these functions.
Fiom Figuie 4, it can be seen that the SIave addiess is
one byte made up of a unique 7-bit addiess foIIowed by
a Read oi Wiite data diiection indicatoi bit. The Least
Significant Bit (LSB) data diiection indicatoi, aIways
deteimines the diiection of the message and type of
tiansfei being iequested by the Mastei-eithei SIave
Receive oi SIave Tiansmit. If the Mastei iequests the
SIave Receive functionaIity, the LSB of the addiessed
SIave wouId be set to 0 foi Wiite. Theiefoie, the
Mastei wouId Tiansmit oi Wiite infoimation to the
seIected SIave. On the othei hand, if the Mastei was
iequesting the SIave Tiansmit functionaIity, the LSB
wouId be set to 1 foi Read. As a iesuIt, the Mastei
wouId Receive oi Read infoimation fiom the SIave.
SFND
-
DATA and RFCV
-
DATA subioutines de-
sciibed Iatei send and ieceive data bytes acioss the bus.
MSB LSB
RW
Slave Address DDB
(7 bits Long)
Data
Direction Bit
Slave Transmitter LSB e 1 for Read Function
Slave Receiver LSB e 0 for Write Function
Figure 4 Slave Address Byte Format
Address Recognition
When an addiess is sent fiom the contioIIing Mastei,
each device in a system compaies the fiist 7 bits aftei
the START condition with its piedefined unique SIave
addiess. If they match, the device consideis itseIf ad-
diessed by the Mastei as eithei a SIave-Receivei oi
SIave-Tiansmittei, depending upon the data diiection
indicatoi. Due to the buss seiiaI configuiation, onIy
one device at a time may be addiessed and communi-
cated with at any given moment.
ACKNOWLEDGMENT
To ensuie vaIid and ieIiabIe I
2
C-bus communication,
an obIigatoiy data tiansfei acknowIedgment pioceduie
was devised. Figuie 5 dispIays how acknowIedgment
3
AP-476
27231922
Figure 5 Acknowledgement of the I
2
C-Bus
aIways affects the Mastei, Tiansmittei and Receivei.
Mtei eveiy byte tiansfei, the Mastei must geneiate an
acknowIedge ieIated cIock puIse. In Figuie 1, this cIock
puIse is indicated as the 9th bit and IabeIed ACK.
FoIIowing the 8th data bit tiansmission, the active
Tiansmittei must immediateIy ieIease the SDA Iine en-
abIing it to fIoat HIOH. To ieceive anothei data byte,
the Receivei must veiify successfuI ieceipt of the pievi-
ous byte by geneiating an acknowIedgment. An ac-
knowIedge condition is deIiveied when the Receivei
diives SDA LOW so that it iemains stabIe LOW dui-
ing the HIOH peiiod of the SCL ACK puIse. Con-
veiseIy, a not acknowIedge condition is deIiveied when
the Receivei Ieaves SDA HIOH. Set-up and hoId times
must aIways be taken into account and maintained
foi vaIid communications. SFND
-
BYTF and
RFCV
-
BYTF subioutines desciibed Iatei evaIuate
and/oi geneiate acknowIedgment conditions.
MCS-51 Hardware Requirements
The I
2
C piotocoI iequiies open-diain device outputs to
diive the bus. To satisfy this specification, Poit 0 on the
InteI MCS-51 device was chosen. By using open-diain
Poit 0, no additionaI haidwaie is iequiied to success-
fuIIy inteiface to the I
2
C-bus. Howevei, since Poit 0 is
designated as the I
2
C inteiface, it can no Iongei be used
to inteiface with FxteinaI Piogiam Memoiy. In oidei
foi a MCS-51 device to communication in this enviion-
ment, ASM51 softwaie emuIation moduIes weie deveI-
oped. This softwaie can onIy execute out of InteinaI
Memoiy. Poit 0 is now configuied foi Input/Output
functionaIity.
Figuie 6 diagiams the necessaiy haidwaie connections
of the deveIopment ciicuit. InteinaI Memoiy execution
is accompIished by connecting the FxteinaI Access
(FA) DIP pin 31 to V
CC
. The capacitoi attached to
RFSFT DIP pin 9 impIements POWFR ON RFSFT.
WhiIe the capacitois and ciystaI attached to XTAL1&2
enabIe the on-chip osciIIatoi, additionaI decoupIing ca-
pacitois can be added to cIean up any system noise.
AdditionaI MCS-51 infoimation can be found in the
1992 InteI Fmbedded MiciocontioIIeis and Piocessois
Handbook VoIume 1.
27231923
C1 e C2 e 30 pF
C3 e 10 pF
Figure 6 MCS-51 Hardware Requirements
4
AP-476
The ASM51 softwaie emuIation moduIes desciibed in
this appIication note wiII occupy appioximateIy
540 bytes of inteinaI memoiy. The devices iemaining
memoiy may be piogiammed with usei softwaie. The
foIIowing MCS-51 devices weie tested foi use in con-
junction with the I
2
C emuIation moduIes:
MCS-51
Crystal ROM
Register
Devices
Speeds EPROM
RAM
(MHz) Size
8751BH 12 4K 128 bytes
87C51 12 16 20 4K 128 bytes
87C51-FX Core 12 16 20 24 4K 128 bytes
87C51FA 12 16 20 24 8K 256 bytes
87C51FB 12 16 20 24 16K 256 bytes
87C51FC 12 16 20 24 32K 256 bytes
NOTE
The Internal memory setup described above eliminates the
option of using Port 0 to interface to External Memory
However this requirement should pose no problem for the
system designer due to the diverse MCS-51 product line
with various memory sizes offered by Intel
MCS-51 I
2
C Software Emulation
Modules
When devices Iike the MCS-51 do not incoipoiate an
on-chip I
2
C poit, I
2
C functionaIity can be achieved
thiough softwaie emuIation. The foIIowing softwaie
moduIes aie based upon thiee distinct tasks: bus moni-
toiing, time deIays and bus contioI. Fach task confoims
to the I
2
C piotocoI as specified by PhiIips Semiconduc-
tois.
The softwaie moduIes designed to impIement I
2
C func-
tionaIity aie compiised of macios and subioutines, each
independentIy deveIoped, yet both netwoiked to
achieve a desiied system function. Foi exampIe, the use
of macios was favoied to impIement ceitain timing de-
Iay Ioops. Macios aie extiemeIy fIexibIe and can be
changed to constiuct deIays of vaiying Iengths thiough-
out the softwaie. On the othei hand, subioutines aie
veiified ioutines that iequiie no additionaI changes. To
opeiate the bus at diffeient fiequencies, onIy the specif-
ic macios must be changed, not the piedefined subiou-
tines. The foIIowing ASM51 macios and subioutines
aie foi Mastei-SIave system contioI:
Macro Names Functions
DFLAY
-
3
-
CYCLFS DeIay Ioop foi X sec-
onds wheie X
e
time
pei cycIe 3
DFLAY
-
4
-
CYCLFS DeIay Ioop foi X sec-
onds wheie X
e
time
pei cycIe 4


DFLAY
-
8
-
CYCLFS DeIay Ioop foi X sec-
onds wheie X
e
time
pei cycIe 8
RFLFASF
-
SCL
-
HIOH ReIeases the SCL Iine
HIOH and waits foi
any cIock stietching ie-
quests fiom peiipheiaI
devices
Subroutine Names Functions
MASTFR
-
CONTROLLFR Sends an I
2
C START
condition and SIave Ad-
diess duiing both a
Mastei Tiansmit and
Receive
SFND
-
DATA Sends muItipIe data
bytes duiing a Mastei
Tiansmit
SFND
-
BYTF Sends one data byte Iine
duiing a Mastei Tians-
mit
SFND
-
MSO Sends a message acioss
the I
2
C bus using a pie-
defined foimat
RFCV
-
DATA Receives muItipIe data
bytes fiom an addiessed
SIave duiing a Mastei
Receive
RFCV
-
BYTF Receives one data byte
duiing a Mastei Receive
RFCV
-
MSO Receives a message
fiom the I
2
C bus using
a piedefined foimat
TRANSFFR Copies FPROM pio-
giammed data into Reg-
istei RAM
SFND
-
STOP Send an I
2
C STOP con-
dition duiing both a
Mastei Tiansmit/Re-
ceive
These ASM51 moduIes aie Iisted at the end of the ap-
pIication note in Appendix A.
5
AP-476
MCS-51 and I
2
C-Bus Compatible ICs
System Implementation
This section of the appIication note expIains the Mas-
tei/SIave system diagiammed in Figuie 1. The InteI
MCS-51 is the Mastei ContioIIei communicating with
two I
2
C SIave peiipheiaIs, the PCF8570 RAM chip
and SAAI064 LFD diivei. Infoimation ieIated to com-
municating with these specific SIave devices can be
found in the 1992 PhiIips I
2
C PeiipheiaIs foi Micio-
contioIIeis Handbook.
The MCS-51 I
2
C Softwaie FmuIation ModuIes Iocated
in Appendix A aie designed to demonstiate Mastei
ContioIIei functionaIity.
As desciibed above, the InteI 51 Mastei ContioIIei
tiansmits data to the RAM device, ieceives it back and
ie-tiansmits it to the LFD SIave diivei. By using the
SFND
-
MSO and RFCV
-
MSO subioutines, both
Mastei Tiansmit and Mastei Receive functionaIities
aie demonstiated. SIave addiesses used in these tians-
feis aie piedefined vaIues assigned by theii manufactui-
ei. These vaIues can be found in theii iespective data-
books.
An I
2
C Mastei Tiansmission consists of the foIIowing
steps:
1. Mastei poIIs the bus to see if fiee state exists
2. Mastei geneiates a START condition on the bus
3. Mastei bioadcasts the SIave Addiess expecting an
AcknowIedge fiom the addiessed SIave
4. Mastei tiansmits data bytes expecting acknowI-
edgment status foIIowing each byte
5. Mastei geneiates a STOP condition and ieIeases
the bus
An I
2
C Mastei/Receive tiansaction consists of the ex-
act same steps stated above FXCFPT:
4. Mastei ieceives data bytes sending an ACK to the
SIave Tiansmittei aftei ieceipt of each byte. The
Mastei signaIs ieceipt of the Iast data byte by ie-
sponding with the NOT AcknowIedge condition.
MASTER TRANSMITRECEIVE
Bus tiansmission and evaIuation is achieved by a nested
Ioop stiuctuie. SFND
-
DATA iepiesents the outei
Ioop which diiects data tiansfeis. The
MASTFR
-
CONTROLLFR subioutine poIIs the bus
to deteimine if any tiansactions aie in piogiess. Fiioi
checking is peifoimed at this IeveI by evaIuating the
foIIowing status fIags, BUS
-
FAULT and
I
2
C
-
BUSY. Based upon this infoimation, the Mastei
wiII eithei aboit the tiansmit pioceduie oi attempt to
send infoimation. If bus contioI is gianted as indicated
by cIeaied fIags, the Mastei sends a START condition
and the SIave addiess. On the othei hand, if eithei fIag
is set, the tiansmit pioceduie is aboited.
SFND
-
BYTF, the innei contioI Ioop, is iesponsibIe
foi tiansmitting 8 bits of each byte as weII as monitoi-
ing SIave acknowIedgment status. Fach bit tiansfei
fiom I
2
C-bus Iines checks foi possibIe seiiaI wait states.
Wait states occui when sIowei devices need to commu-
nicate on the bus with fastei devices. Due to the wiied-
AND bus function, a Receivei can hoId the cIock Iine
SCL LOW foicing the Tiansmittei into this state. Data
tiansfei may continue when the Receivei is ieady foi
anothei byte of data as indicated by ieIeasing the cIock
Iine SCL HIOH.
As stated in its section above, acknowIedgment is ie-
quiied to continue sending data bytes acioss the bus.
Howevei, situations may aiise when a Receivei can not
ieceive anothei byte of data untiI it has peifoimed some
othei function Iike seivicing inteinaI inteiiupts. If the
SIave Receivei does not iespond to a Mastei Tiansmit-
tei data byte, not acknowIedge couId indicate that it is
peifoiming some ieaI-time function that pievents it
fiom iesponding to I
2
C-bus communications. This situ-
ation shows the fIexibiIity and veisatiIity of the bus.
The Mastei Receive piocess aIso utiIizes the MAS-
TFR
-
CONTROLLFR subioutine to gain contioI of
the bus. When accepting data fiom the addiessed SIave,
in this case, RFCV
-
DATA is the outei contioI Ioop.
RFCV
-
BYTF, the innei contioI Ioop, is iesponsibIe
foi ieceiving 8 bits of each byte as weII as geneiating
the Masteis acknowIedgment condition. SimiIai to
tiansmission, successfuI ieceipt of each byte is con-
fiimed by diiving SDA LOW so that it iemains stabIe
LOW duiing the HIOH peiiod of the SCL ACK puIse.
Theiefoie, the Mastei stiII diives both SCL and SDA
Iines since contioI of the system cIock is its iesponsibiIi-
ty.
In both types of communication, Tiansmit/Receive,
tempoiaiy RAM iegisteis, BIT
-
CNT, BYTF
-
CNT,
SLV
-
ADDR, and stoiage buffeis, XMT
-
DAT,
RCV
-
DAT, ALT
-
XMT, aie integiaI paits of most
subioutines because they aie used foi impIementing the
I
2
C piotocoI. Piopei deIays aie impIemented using the
DFLAY
-
X
-
CYCLFS (X
e
any integei) macios.
They give the designei fIexibiIity to devise time deIays
of any iequiied Iength to satisfy system iequiiements.
Foi exampIe, to achieve the maximum bus speeds de-
sciibed in the next section, DeIay
-
X
-
CycIe macios
weie adjusted.
LastIy, the TRANSFFR subioutine is piovided to aI-
Iow piedefined communication data piogiammed in
the miciocontioIIeis FPROM to be tiansfeiied into
Registei RAM inteinaI to the 51 device. It achieves this
6
AP-476
when used in conjunction with the SFND
-
MSO and
RFCV
-
MSO subioutines. Howevei, when utiIizing
TRANSFFR, the designei must confoim theii design
to existing device Registei RAM avaiIabiIity and to the
foIIowing message foimat:
Slave Address of Bytes to be TransmittedReceived Data
Bytes (For Transmit Only)
The ASM-51 piogiam demonstiating a compIete Mas-
tei ContioIIei system is Iisted at the end of the appIica-
tion note in Appendix B. It wiites the numeiic data
that iepiesents the foIIowing dispIay
-
I
2
C to an I
2
C
compatibIe IC (PCF8570 RAM), ieads the vaIues back
into a buffei and tiansmits this buffei out to the PhiIips
I
2
C SAA1064 LFD diivei to dispIay the sequence.
I
2
C Software Emulation Performance
As demonstiated above, the InteI MCS-51 pioduct Iine
can successfuIIy impIement the I
2
C Mastei ContioIIei
functionaIity whiIe maintaining data integiity and ieIi-
abIe peifoimance. The system outIined in Figuie 1 was
evaIuated foi maximum bus peifoimance and adhei-
ence to aII I
2
C-bus specifications. Peifoimance chaiac-
teiization was conducted at vaiious ciystaI speeds on
aII devices Iisted in the MCS-51 Haidwaie Requiie-
ments section of this appIication note.
When designing I
2
C softwaie emuIation systems, keep
in mind that the designei has the fIexibiIity to impIe-
ment Iaige fiequency ianges up to the I
2
C-bus maxi-
mum. Howevei, by making softwaie changes to adjust
bus fiequencies, the newIy modified piogiam may no
Iongei meet iequiied specifications and desiied ieIiabiI-
ity standaids. Theiefoie, designeis shouId fiist aIways
take into consideiation the bus peifoimance IeveI they
want to ieach. Aftei deciding this, an appiopiiate ciys-
taI can be chosen to achieve that impIementation speed.
The tabIe beIow gives a few exampIes of system pei-
foimance foi two of the MCS-51 devices:
MCS-51 Crystal
I
2
C Bus
Devices Speed
Maximum
Performance
8751BH 12 MHz 667 kHz
87C51 (FX-Core) 24 MHz 800 kHz
CONCLUSION
As a iesuIt of this evaIuation, InteI MCS-51 miciocon-
tioIIeis can be successfuIIy inteifaced to an I
2
C-bus sys-
tem as a Mastei contioIIei. The inteiface communicates
by ASM51 softwaie emuIation moduIes that have been
tested on a wide aiiay of I
2
C devices ianging fiom seii-
aI RAMS, DispIays and a DTMF geneiatois. No com-
patibiIity piobIems have been seen to date. Theiefoie,
when consideiing the impIementation of youi next I
2
C-
bus Mastei ContioIIei seiiaI communication system,
you have the option of using the InteI MCS-51 Pioduct
Line.
REFERENCES
I
2
CBITSASM O. Ooodhue, PhiIips Semiconductois,
August 1992.
The I
2
C-Bus and How to Use It (Including Specifica-
tion) PhiIips Semiconductois, Januaiy 1992.
I
2
C Peripherals for Microcontrollers PhiIips Semicon-
ductois, 1992 Data Handbook.
OM1016 I
2
C Evaluation Board F. Rodgeis and O.
Moss, PhiIips Components AppIications Lab Auck-
Iand, New ZeaIand.
Programming the I
2
C Interface MitcheII Kahn, Senioi
Fngineei, InteI Coipoiation.
7
AP-476
APPENDIX A
2723191
A-1
AP-476
2723192
A-2
AP-476
2723193
A-3
AP-476
2723194
A-4
AP-476
2723195
A-5
AP-476
2723196
A-6
AP-476
2723197
A-7
AP-476
27231924
A-8
AP-476
APPENDIX B
2723198
B-1
AP-476
2723199
B-2
AP-476
27231910
B-3
AP-476
27231911
B-4
AP-476
27231912
B-5
AP-476
27231913
B-6
AP-476
27231914
B-7
AP-476
27231915
B-8
AP-476
AP-476
27231917
B-10