Spring 2008 J Grover

Switching & Logic

Name______________________________________ please print

Examination 2 CPLD, VHDL & Combinational Logic

You must use the symbols given on the exam paper. Changing symbols will significantly reduce your score. This examination is closed book and closed notes.
Answer the first fifteen questions for two points each by transfer the best answers to Table 1.

1. 6. 11.

2. 7. 12.

3. 8. 13.

4. 9. 14.

5. 10. 15.

Table 1 Best answers to multiple choice questions. 1. A programmable logic device in which the AND-array is programmable and the OR-array is fixed. A. PAL B. PLA C. Fixed Logic D. ROM 2. An industry-standard file that lists which "fuses" in the programmable logic device are intact and which are blown. A. Block Definition File B. VHDL File C. JEDEC File D. Vector Waveform File 3. A PAL16L8 has how many pins that may act as outputs? A. Sixteen B. Eight C. Twenty-Four (16+8) D. Two (16/8) 4. In an Entity statement, BUFFER is an example of? A. Signal Type B. Signal Port C. Signal Mode D. Concurrent Statement 5. The idea behind signal concurrency is that all signals in a simulation are executed at ______. A. a fixed time. B. the same time. C. a predetermined time. D. Eastern-Daylight Time. 6. Which of the following is an invalid name in VHDL? A. DECODE8 B. _WHAT_4 C. INVALID D. All are valid 7. The RANGE keyword is associated with what signal type? A. BIT_VECTOR B. STD_LOGIC C. INTEGER D. BUFFER 8. In STD_LOGIC forcing unknown is represented by what value? A. 'Z' B. 'U' C. 'W' D. 'X' 9. A digital circuit designed to detect the presence of a particular digital state is called: A. Multiplexer B. Decoder C. Parity Generator D. Encoder

10. The statement: Y <= '1' WHEN (D = 0 AND nG = '0') ELSE '0'; is an example of what type statement? A. ARCHITECTURE B. ENTITY C. PORT MAP D. SELECTED SIGNAL ASSIGNMENT 11. A _______ is a construct containing statements that are executed in a simulation if a signal in the sensitivity list changes. A. ENTITY B. PORT MAP C. CASE STATEMENT D. PROCESS 12. A circuit that generates a binary code at its outputs in response to one or more active input lines. A. Encoder B. Decoder C. Demultiplexer D. Shift-Register 13. Which of the following best represents the INOUT mode?

Figure 1 Schematic of VHDL Modes 14. A circuit that uses a binary decoder to direct a digital signal from a single source to one of several destinations. A. Decoder B. Multiplexer C. Demultiplexer D. Parity Generator 15. An error-checking system that requires a binary number to have an even number of 1s. A. Even Parity B. Parity C. Odd Parity D. Multiplexer

Your homework score out of 100 for the self-graded problem set was _______

16 Programmable Logic Devices (25 points)

Part A:

Figure 2 Schematic of Macrocell Part B There are four sets of equations with 0ne to 3 products. Each macrocell can support up to

Part C: If E1 were the only fuse for the output D1 that is left intact, which input should be selected on the macrocell multiplexer, top or bottom. The architecture of the macrocell is shown in Figure 2? Defend your answer.

16 Continued Part D: The notation in which the AND gate of Figure 2 is crossed-out is used to indicate what? Are the fuses intact or blown?

Part E: Could the function F = E1E2EE4 that requires 8 products be implemented in a single macrocell similar to the one shown in Figure 2? Defend your answer.

17. VHDL (25 points) Part A: Translate the VHDL module below to a completed truth table using the partial truth table of Table 2.

ENTITY example IS PORT( d : IN BIT_VECTOR(3 DOWNTO 0); y : OUT BIT); END example;

ARCHITECTURE a OF example IS BEGIN WITH d SELECT Y <= 0 WHEN 1010, 0 WHEN 0110, 0 WHEN 1111, 0 WHEN 0000, 1 WHEN others; END a;

Table 2 Problem 17A Truth Table

d(3) d(2) d(1) d(0) y

17 Continued Part B: Y <= (A XOR B AND C) OR (A AND B). Sketch the equivalent network for this statement using distinctive gate symbols

Part C: A VHDL design has five input ports labeled enable (MSB), read, write, select and compare (LSB) and three outputs labeled address_latch (MSB), data_enable, and strobe. Write a VHDL statement that concatenates all input lines into a signal called control. The signal is written with the most significant bit on the left. No entity or architecture statements necessary.

Part D: Write a series of VHDL statements that separate a signal called status into the output ports listed in Part C. The ports are written with the most significant bit on the left. . No entity or architecture statements necessary.

18 Combinational Logic Functions (20 points) Part A: For a generalized n-line-to-m-line decoder, what is the mathematical relationship between n and m?

Part B: Using a single 4-to-1 multiplexer, sketch the circuit for the following three variable Karnaugh-Map. Assume A and B are used for the S1 and S0 select bits. Use distinctive shape for multiplexer and label the output of the multiplexer as Y C AB (S1S0) 00 01 11 10 0 0 1 1 0 1 1 1 1 0

Part C: Construct a parity generator using three 2-input XOR gates. For the pattern 0110 determine whether your circuit generates even or odd parity. Draw the schematic.

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1. 2. Indicate on original page that problem is continued on this page. On this page indicate which part and problem number is continued here.

Example VHDL Statements

--Entity Example ENTITY __entity_name IS PORT( __input_name, __input_name : IN BIT; __input_vector_name : IN BIT_VECTOR(__high DOWNTO __low); __output_name, __output_name : OUT BIT); END __entity_name; --Architecture Example ARCHITECTURE a OF __entity_name IS SIGNAL __signal_name : BIT; SIGNAL __signal_name : BIT_VECTOR(__high TO __low); --Component Declaration goes here if used BEGIN -- Combinational statements END a; --With-Select WITH __expression SELECT __signal <= __expression __constant_value, __expression __constant_value, __expression __constant_value, __expression OTHERS; BEGIN WAIT UNTIL __clk_signal = '1'; END PROCESS __process_label; IF __expression THEN __statement; ELSIF __expression THEN __statement; ELSE __statement; END IF; CASE expression IS WHEN constant_value1 => statement1; statement2; WHEN constant_value2 => statement3; statement4; WHEN OTHERS => statement5; statement6; END CASE; __generate_label: FOR __index_variable IN __range GENERATE __statement; END GENERATE; __instance_name : __component_name PORT MAP ( __component_signal_1 => __user_signal_1, __component_signal_n => __user_signal_n);

WHEN WHEN WHEN WHEN

__process_label: PROCESS (__signal_name, __signal_name, __signal_name) VARIABLE __variable_name : STD_LOGIC; VARIABLE __variable_name : STD_LOGIC; BEGIN --sequential statements here END PROCESS __process_label; __process_label: PROCESS VARIABLE __variable_name VARIABLE __variable_name

GENERIC MAP (PARAMETER_1 => __constant_1, PARAMETER_n => __constant_n); LIBRARY __library_name; USE __library_name.__package_name.ALL;

: STD_LOGIC; : STD_LOGIC;

Operator Precedence
1. 2. 3. 4. 5. 6. 7. 8. binary logical operators: and or nand nor xor xnor (lowest precedence -- applied last) relational operators: = /= < <= > >= shift operators: sll srl sla sra rol ror adding operators: + & (concatenation) unary sign operators: + multiplying operators: * / mod rem miscellaneous operators: not abs ** parentheses (highest precedence -- applied first)