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UNIT-I

8085 Microprocessor Contents General definitions Overview of 8085 microprocessor Overview of 8086 microprocessor Signals and pins of 8086 microprocessor

The salient features of 8085 p are: t is a 8 !it microprocessor" t is manufactured with #$%OS technolog&" t has '6$!it address !us and hence can address up to ('6 ) memor& locations through 0 $0 "
0 '5

655*6 !&tes +6,-./

The first 8 lines of address !us and 8 lines of data !us are multiple1ed 020 3 024" 2ata !us is a group of 8 lines 20 3 24" t supports e1ternal interrupt re5uest" 0 '6 !it program counter +67/ 0 '6 !it stac8 pointer +S6/

Si1 8$!it general purpose register arranged in pairs: .79 2:9 ;<" t re5uires a signal =5> power suppl& and operates at *"( %;? single phase cloc8"

t is enclosed with ,0 pins 2 6 +2ual in line pac8age/"

Overview of 8085 microprocessor 8085 0rchitecture 6in 2iagram @unctional .loc8 2iagram

Instruction Set

8085 instruction set consists of the following instructions: 2ata moving instructions"

0rithmetic $ add9 su!tract9 increment and decrement" <ogic $ 0#29 OA9 BOA and rotate" 7ontrol transfer $ conditional9 unconditional9 call su!routine9 return from su!routine and restarts" nputCOutput instructions" Other $ settingCclearing flag !its9 ena!lingCdisa!ling interrupts9 stac8 operations9 etc" Addressing mode Register $ references the data in a register or in a register pair" Register indirect $ instruction specifies register pair containing address9 where the data is located" Direct, Immediate $ 8 or '6$!it data"

advantages of 8086 over 8085 are :


'"pipelining is emplo&ed ma8ing the ("data!us width increased to *"higher memor& of ,"some instructions such as %D< or 2 > are availa!le 5"increased instruction set ma8ing the e1ecution '6 '%." for multiplication programming faster" !its and division" easier"

808 Microprocessor

t is a '6$!it p" 8086 has a (0 !it address !us can access up to ((0 memor& locations +' %./ " t can support up to 6,- CO ports" t provides ',9 '6 $!it registers" t has multiple1ed address and data !us 020$ 02'5 and 0'6 3 0'E" t re5uires single phase cloc8 with **F dut& c&cle to provide internal timing" 8086 is designed to operate in two modes9 %inimum and %a1imum" t can prefetches upto 6 instruction !&tes from memor& and 5ueues them in order to speed up instruction e1ecution" t re5uires =5> power suppl&" 0 ,0 pin dual in line pac8age

0rchitecture of 8086
8086 has two !loc8s . D and :D" The . D performs all !us operations such as instruction fetching9 reading and writing operands for memor& and calculating the addresses of the memor& operands" The instruction !&tes are transferred to the instruction 5ueue" :D e1ecutes instructions from the instruction s&stem !&te 5ueue" .oth units operate as&nchronousl& to give the 8086 an overlapping instruction fetch and e1ecution mechanism which is called as 6ipelining" This results in efficient use of the s&stem !us and s&stem performance" . D contains nstruction 5ueue9 Segment registers9 nstruction pointer9 0ddress adder" :D contains 7ontrol circuitr&9 nstruction decoder9 0<D9 6ointer and nde1 register9 @lag register" !U" INT#R$A%R UNIT& t provides a full '6 !it !idirectional data !us and (0 !it address !us" The !us interface unit is responsi!le for performing all e1ternal !us operations"

Specifically it has the following functions: nstruction fetch9 nstruction 5ueuing9 Operand fetch and storage9 0ddress relocation and .us control" The . D uses a mechanism 8nown as an instruction stream 5ueue to implement a pipeline architecture. This 5ueue permits prefetch of up to si1 !&tes of instruction code" Ghen ever the 5ueue of the . D is not full9 it has room for at least two more !&tes and at the same time the :D is not re5uesting it to read or write operands from memor&9 the . D is free to loo8 ahead in the program !& prefetching the ne1t se5uential instruction" These prefetching instructions are held in its @ @O 5ueue" Gith its '6 !it data !us9 the . D fetches two instruction !&tes in a single memor& c&cle" 0fter a !&te is loaded at the input end of the 5ueue9 it automaticall& shifts up through the @ @O to the empt& location nearest the output" The :D accesses the 5ueue from the output end" t reads one instruction !&te after the
other from the output of the 5ueue" f the 5ueue is full and the :D is not re5uesting access

P K K

to operand in memor&" These intervals of no !us activit&9 which ma& occur !etween !us c&cles are 8nown as Idle state. f the . D is alread& in the process of fetching an instruction when the :D re5uest it to read or write operands from memor& or CO9 the . D first completes the instruction fetch !us c&cle !efore initiating the operand read C write c&cle" The . D also contains a dedicated adder which is used to generate the (0!it ph&sical address that is output on the address !us" This address is formed med !& com!ining the current contents of the code segment 7S register and the current contents of the instruction pointer 6 register" The . D is also responsi!le for generating !us control signals such as those for memor& read or write and CO read or write" #'#%UTION UNIT The :1ecution unit is responsi!le for decoding and e1ecuting all instructions" The :D e1tracts instructions from the top of the 5ueue in the . D9 decodes them9 generates operands if necessar&9 passes them to the . D and re5uests it to perform the read or write !&s c&cles to memor& or CO and perform the operation specified !& the instruction on the operands" 2uring the e1ecution of the instruction9 the :D tests the status and control flags and updates them !ased on the results of e1ecuting the instruction" f the 5ueue is empt&9 the :D waits for the ne1t instruction !&te to !e fetched and shifted to top of the 5ueue" Ghen the :D e1ecutes a !ranch or Hump instruction9 it transfers control to a location corresponding to another set of se5uential instructions" Ghenever this happens9 the . D automaticall& resets the 5ueue and then !egins to fetch instructions from this new location to refill the 5ueue

"(#%IA) $UN%TION" O$ *#N#RA) (UR(O"# R#*I"T#R" Acc+m+,ator register consists of ( 8$!it registers 0< and 0;9 which can !e com!ined together and used as a '6$!it register 0B" 0< in this case contains the low$order !&te of the word9 and 0; contains the high$order !&te" 0ccumulator can !e used for CO operations and string manipulation" !ase register consists of ( 8$!it registers .< and .;9 which can !e com!ined together and used as a '6$!it register .B" .< in this case contains the low$order !&te of the word9 and .; contains the high$order !&te" .B register usuall& contains a data pointer used for !ased9 !ased inde1ed or register indirect addressing" %o+nt register consists of ( 8$!it registers 7< and 7;9 which can !e com!ined together and used as a '6$ !it register 7B" Ghen com!ined9 7< register contains the low$order !&te of the word9 and 7; contains the high$order !&te" 7ount register can !e used as a counter in string manipulation and shiftCrotate instructions" Data register consists of ( 8$!it registers 2< and 2;9 which can !e com!ined together and used as a '6$ !it register 2B" Ghen com!ined9 2< register contains the low$order !&te of the word9 and 2; contains the high$order !&te" 2ata register can !e used as a port num!er in CO operations" n integer *($!it multipl& and divide instruction the 2B register contains high$order word of the initial or resulting num!er" "(#%IA) $UN%TION" O$ "(#%IA) (UR(O"# R#*I"T#R" "tac- (ointer +S6/ is a '6$!it register pointing to program stac8" !ase (ointer +.6/ is a '6$!it register pointing to data in stac8 segment" .6 register is usuall& used for !ased9 !ased inde1ed or register indirect addressing" "o+rce Inde. +S / is a '6$!it register" S is used for inde1ed9 !ased inde1ed and register indirect addressing9 as well as a source data address in string manipulation instructions" Destination Inde. +2 / is a '6$!it register" 2 is used for inde1ed9 !ased inde1ed and register indirect addressing9 as well as a destination data address in string manipulation instructions" The si and di registers +Source nde1 and 2estination nde1 / have some special purposes as well" Iou ma& use these registers as pointers +much li8e the !1 register/ to indirectl& access memor&" IouJll also use these registers with the 8086 string instructions when processing character strings" The !p register +.ase 6ointer/ is similar to the !1 register" IouJll generall& use this register to access parameters and local varia!les in a procedure" The sp register +Stac8 6ointer/ has a ver& special purpose $ it maintains the program stack" #ormall&9 &ou would not use this register for arithmetic computations" The proper operation of most programs depends upon the careful use of this register"

"#*M#NTATION& Since address registers and address operands are onl& '6 !its the& can onl& address 6,8 !&tes" n order toaddress the (0$!it address range of the 80869 ph&sicaladdresses +those that are put on the address !us/are alwa&s formed !& adding the values of one of the instruction is e1ecutedK The use of segment registers reduces the siLe ofpointers to '6 !its" This reduces the code siLe !ut also restricts the addressing range of a pointer to 6,8 !&tes" 6erforming address arithmetic within data structures larger than 6,8 is aw8ward" This is the !iggest draw!ac8 of the 8086 architecture" Ge will restrict ourslves to short programs where all of the code9 data and stac8 are placed into thesame 6,8 segment +i"e" 7S)2S)SS/" %ost of the registers contain dataCinstruction offsets within 6, -. memor& segment" There are four different 6, -. segments for instructions9 stac89 data and e1tra data" To specif& where in ' %. of processor memor& these , segments are located the processor uses four segment registers: Memor/ 6rogram9 data and stac8 memories occup& the same memor& space" 0s the most of the processor instructions use '6$!it pointers the processor can effectivel& address onl& 6, -. of memor&" To access memor& outside of 6, -. the 76D uses special segment registers to specif& where the code9 stac8 and data 6, -. segments are positioned within ' %. of memor& +see the MAegistersM section !elow/" '6$!it pointers and data are stored as: address: low$order !&te address=': high$order !&te (rogram memor/ $ program can !e located an&where in memor&" Nump and call instructions can !e used for short Humps within currentl& selected 6, -. code segment9 as well as for far Humps an&where within ' %. of memor&" 0ll conditional Hump instructions can !e used to Hump within appro1imatel& ='(4 to $ '(4 !&tes from current instruction" Data memor/ $ the processor can access data in an& one out of , availa!le segments9 which limits the siLe of accessi!le memor& to (56 -. +if all four segments point to different 6, -. !loc8s/" 0ccessing data from the 2ata9 7ode9 Stac8 or :1tra segments can !e usuall& done !& prefi1ing instructions with the 2S:9 7S:9 SS: or :S: +some registers and instructions !& default ma& use the :S or SS segments instead of 2S segment/" Gord data can !e located at odd or even !&te !oundaries" The processor uses two memor& accesses to read '6$!it word located at odd !&te !oundaries" Aeading word data from even !&te !oundaries re5uires onl& one memor& access" "tac- memor/ can !e placed an&where in memor&" The stac8 can !e located at odd memor& addresses9 !ut it is not recommended for performance reasons +see M2ata %emor&M a!ove/" Reserved ,ocations: 0000h $ 0*@@h are reserved for interrupt vectors" :ach interrupt vector is a *($!it pointer in format segment: offset" @@@@0h $ @@@@@h $ after A:S:T the processor alwa&s starts program e1ecution at the @@@@0h address"

segment registers to the '6$!it address to form a (0$!it address" The segment registers themselves onl& contain themost$significant '6 !its of the (0$!it value that iscontri!uted !& the segment registers" The least significantfour !its of thesegment address are alwa&sLero" .& default9 the 2S +data segment/ is used fordata transfer instructions +e"g" %O>/9 7S+codesegment/ is used with control transfer instructions+e"g" N%6 or 70<</9 and SS is used with the stac8pointer +e"g" 6DS; or to saveCrestore addresses during70<<CA:T or #T instructions/"

:1ercise: f 2S contains 0'00;9 what address will !e written !& the instruction %O> O(000;P90<K f 7B contains ''((;9 S6 contains '(*,;9 and SS contains (000;9 what memor& values will change and what will !e their values when the 6DS; 7B

%ode segment +7S/ is a '6$!it register containing address of 6, -. segment with processor instructions" The processor uses 7S segment for all accesses to instructions referenced !& instruction pointer + 6/ register" 7S register cannot !e changed directl&" The 7S register is automaticall& updated during far Hump9 far call and far return instructions" "tac- segment +SS/ is a '6$!it register containing address of 6,-. segment with program stac8" .& default9 the processor assumes that all data referenced !& the stac8 pointer +S6/ and !ase pointer +.6/ registers is located in the stac8 segment" SS register can !e changed directl& using 6O6 instruction" Data segment +2S/ is a '6$!it register containing address of 6,-. segment with program data" .& default9 the processor assumes that all data referenced !& general registers +0B9 .B9 7B9 2B/ and inde1 register +S 9 2 / is located in the data segment" 2S register can !e changed directl& using 6O6 and <2S instructions" #.tra segment +:S/ is a '6$!it register containing address of 6,-. segment9 usuall& with program data" .& default9 the processor assumes that the 2 register references the :S segment in string manipulation instructions" :S register can !e changed directl& using 6O6 and <:S instructions" t is possi!le to change default segments used !& general and inde1 registers !& prefi1ing instructions with a 7S9 SS9 2S or :S prefi1"

808 $)A* R#*I"T#R $,ags is a '6$!it register containing E '$!it flags: Overflow @lag +O@/ $ set if the result is too large positive num!er9 or is too small negative num!er to fit into destination operand"

2irection @lag +2@/ $ if set then string manipulation instructions will auto$decrement inde1 registers" f cleared then the inde1 registers will !e auto$incremented" nterrupt$ena!le @lag + @/ $ setting this !it ena!les mas8a!le interrupts"

Single$step @lag +T@/ $ if set then single$step interrupt will occur after the ne1t instruction" Sign @lag +S@/ $ set if the most significant !it of the result is set" ?ero @lag +?@/ $ set if the result is Lero" 0u1iliar& carr& @lag +0@/ $ set if there was a carr& from or !orrow to !its 0$* in the 0< register" 6arit& @lag +6@/ $ set if parit& +the num!er of M'M !its/ in the low$order !&te of the result is even"

7arr& @lag +7@/ $ set if there was a carr& from or !orrow to the most significant !it during last result calculation

UNIT-II
ADDR#""IN* MOD#" O$ 808 &
Imp,ied $ the data valueCdata address is implicitl& associated with the instruction" Direct $ the instruction operand specifies the memor& address where data is located"

% 6 < :

# 6 D T

Register indirect $ instruction specifies a register containing an address9 where data is located" This addressing mode wor8s with S 9 2 9 .B and .6 registers" Register $ references the data in a register or in a register pair" Immediate $ the data is provided in the instruction" !ased :$ 8$!it or '6$!it instruction operand is added to the contents of a !ase register +.B or .6/9 the resulting value is a pointer to location where data resides" Inde.ed :$ 8$!it or '6$!it instruction operand is added to the contents of an inde1 register +S or 2 /9 the resulting value is a pointer to location where data resides !ased Inde.ed :$ the contents of a !ase register +.B or .6/ is added to the contents ofhan inde1 register +S or 2 /9 the resulting value is a pointer to location where data resides" !ased Inde.ed wit0 disp,acement :$ 8$!it or '6$!it instruction operand is added to the contents of a !ase register +.B or .6/ and inde1 register +S or 2 /9 the resulting value is a pointer to location where data resides"

0 # 2

O D T 6 D T

6 O A T

#STAD7T O# S:T O@ 8086: 20T0 TA0#S@:A #STAD7T O#S


G:#:A0< 3 6DA6OS: .IT: OA GOA2 TA0#S@:A #STAD7T O#S: %O> 6DS; 6O6 B7;G B<0T

T A 0 # S @ : A

# S T A D 7 T

# ODT S6:7 0< 022A:SS TA0#S@:A #STAD7T O#S <:0 <2S <:S @<0G TA0#S@:A #STAD7T O#S: <0;@ S0;@ 6DS;@ 6O6@ 02 T O# #STAD7T O#S: 022 027 #7 000 200 SD.TSD.TA07T O# #STAD7T O#S: SD. S.. 2:7 #:G 7%6 00S 20S %D<T 6< 70T O# #STAD7T O#S: %D< %D< 00% 2 > S O# #STAD7T O#S: 2> 2> 002 7.G 7G2

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. T %0# 6D<0T O# #STAD7T O#S


<OG 70< #STAD7T O#S: #OT 0#2 OA BOA T:ST

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D#7O#2 T O#0< TA0#S@:A #STAD7T O#S: 70<< A:T N%6 7O#2 T O#0< TA0#S@:A #STAD7T O#S: N0 C N#.: N0: C N#. N. C N#0: N.: C N#0 N7 N: C N? NG C N#<: NG: C N#< N< C N#G: N<: C N#G N#7 N#: C N#? N#O N#6 C N6O N#S NO N6 C N6: NS T:A0T O# 7O#TAO< #STAD7T O#S: <OO6 <OO6: C <OO6? <OO6#: C <OO6#? N7B? #T:AAD6T #STAD7T O#S: #T #TO A:T

: B T : A # 0 <

; 0 A 2 G 0 A :

rof. Krishna

S I # 7 ; A O #

? 0 T

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6AO7:SS 7O#TAO< #STAD7T O#S


@<0G S:T C 7<:0A #STAD7T O#S: ST7 7<7 7%7 ST2 7<2 ST 7<

# S T A D 7 T

O # S :

;<T G0 T :S7 <O7#O6 nstruction

Prof. Kumar

Krishna

2escription

AAA nstruction $ 0S7 0dHust after 0ddition AAD nstruction $ 0S7 adHust !efore 2ivision AAM nstruction $ 0S7 adHust after %ultiplication AA" nstruction $ 0S7 0dHust for Su!traction AD% nstruction $ 0dd with carr&" ADD nstruction $ 022 destination9 source AND nstruction $ 0#2 corresponding !its of two operands

Example
AAA nstruction $000 converts the result of the addition of two valid unpac8ed .72 digits to a valid ($digit .72 num!er and ta8es the 0< register as its implicit operand" Two operands of the addition must have its lower , !its contain a num!er in the range from 0$E"The 000 instruction then adHust 0< so that it contains a correct .72 digit" f the addition produce carr& +0@)'/9 the 0; register is incremented and the carr& 7@ and au1iliar& carr& 0@ flags are set to '" f the addition did not produce a decimal carr&9 7@ and 0@ are cleared to 0 and 0; is not altered" n !oth cases the higher , !its of 0< are cleared to 0" 000 will adHust the result of the two 0S7 characters that were in the range from *0h +Q0R/ to *Eh+QER/"This is !ecause the lower , !its of those character fall in the range of 0$E"The result of addition is not a 0S7 character !ut it is a .72 digit" #.amp,e& MO1 A2,0 3%,ear A2 for M"D MO1 A), 3!%D in A) ADD A),53Add !%D 5 to digit in A) AAA 3A245, A)45 representing !%D 556 AAD Instr+ction $ 022 converts unpac8ed .72 digits in the 0; and 0< register into a single !inar& num!er in the 0B register in preparation for a division operation" .efore e1ecuting 0029 place the %ost significant .72 digit in the 0; register and <ast significant in the 0< register" Ghen 002 is e1ecuted9 the two .72 digits are com!ined into a single !inar& num!er !& setting 0<)+0;S'0/=0< and clearing 0; to 0"

%icroprocessors and %icrocontrollers

Prof. Kumar

Krishna

#.amp,e& MO1 A',07050 AAD

3T0e +npac-ed !%D n+m8er 75 3After AAD , A240 and 3A)4590 :75;

0fter the division 0< will then contain the unpac8ed .72 5uotient and 0; will contain the unpac8ed .72 remainder" #.amp,e& AAD DI1 %2 3A'40 0< +npac-ed !%D for < decima, 3%24092 3Ad=+st to 8inar/ 8efore division 3A'400>? 4 >?2 4 < decima, 3Divide A' 8/ +npac-ed !%D in %2 3A) 4 @+otient 4 0< +npac-ed !%D 3A2 4 remainder 4 0> +npac-ed !%D

AAM nstruction $ 00% converts the result of the multiplication of two valid unpac8ed .72 digits into a valid ($digit unpac8ed .72 num!er and ta8es 0B as an implicit operand" To give a valid result the digits that have !een multiplied must !e in the range of 0 3 E and the result should have !een placed in the 0B register" .ecause !oth operands of multipl& are re5uired to !e E or less9 the result must !e less than 8' and thus is completel& contained in 0<" 00% unpac8s the result !& dividing 0B !& '09 placing the 5uotient +%S2/ in 0; and the remainder +<S2/ in 0<" #.amp,e& MO1 A), 5 MO1 !), < MU) !) 3M+,tip,/ A) 8/ !) , res+,t in A' AAM 3After AAM, A' 40?050 :!%D ?5; AA" nstruction $ 00S converts the result of the su!traction of two valid unpac8ed .72 digits to a single valid .72 num!er and ta8es the 0< register as an implicit operand" The two operands of the su!traction must have its lower , !it contain num!er in the range from 0 to E "The 00S instruction then adHust 0< so that it contain a correct .72 digit" MO1 A',09052 3!%D 95 "U! A), 9 3Min+s 9

%icroprocessors and %icrocontrollers

Prof. Kumar

Krishna

AA"

3 *ive A' 40807 0 :!%D 87; :a; 3A) 40055 5005 4A"%II 9 3!)40055 0505 4A"%II 5 3:9 - 5; Res+,t & 3A) 4 00000500 4 !%D 0>,%$ 4 0 3Res+,t & 3A)400000500 4!%D 0> 3%$ 4 0 NO !orrow re@+ired :8; TA) 4 0055 0505 4A"%II 5 T!) 4 0055 5005 4 A"%II 9 3: 5 - 9 ; Res+,t & 3A) 4 5555 5500 4 - > 3 in 7As comp,ement %$ 4 5 3Res+,ts & 3A) 4 0000 0500 4!%D 0> 3%$ 4 5 8orrow needed 6

"U! A), !) AA"

"U! A), !) AA"

ADD nstruction $ These instructions add a num!er from source to a num!er from some destination and put the result in the specified destination" The add with carr& instruction 0279 also add the status of the carr& flag into the result" The source and destination must !e of same t&pe 9 means the& must !e a !&te location or a word location" f &ou want to add a !&te to a word9 &ou must cop& the !&te to a word location and fill the upper !&te of the word with Leroes !efore adding" #'AM()#& ADD A),<>2 AD% %),!) 3Add immediate n+m8er <>2 to content of A) 3Add contents of !) p,+s 3carr/ stat+s to contents of %)6 3Res+,ts in %) 3Add contents of !' to contents 3of D' 3Add word from memor/ at 3offset B"IC in D" to contents of D'

ADD D', !' ADD D', B"IC

icroprocessors and %icrocontrollers

Prof. Kumar

Krishna

ADD

3 Addition of Un "igned n+m8ers %), !) 3%) 4 05550055 4555 decima, 3D !) 4 05005555 4 <9 decima, 3Res+,t in %) 4 55000050 4 59> decima, 3 Addition of "igned n+m8ers

ADD

%), !) 3%) 4 05550055 4 D 555 decima, 3D !) 4 05005555 4 D<9 decima, 3Res+,t in %) 4 55000050 4 - 7 decima,

3 Incorrect 8eca+se res+,t is too ,arge to fit in < 8its6 This 6erforms a !itwise <ogical 0#2 of two operands" The AND nstruction $ result of the operation is stored in the op' and used to set the flags" AND op5, op7 To perform a !itwise 0#2 of the two operands9 each !it of the result is set to ' if and onl& if the corresponding !it in !oth of the operands is '9 otherwise the !it in the result cleared to 0 " AND !2, %) 3AND 8/te in %) wit0 8/te in !2 3res+,t in !2 AND !',00$$03AND word in !' wit0 immediate 300$$26 Mas- +pper 8/te, ,eave 3,ower +nc0anged 3 AND word at offset B"IC in data 3segment wit0 word in %' 3register 6 Res+,t in %' register 6 3!' 4 50550055 05055550

AND %',B"IC