Experiment No.

5 Experiment Number 5 Digital Adders-Subtractors

Digital Logic Design

Objectives: To familiarize students with the functionality of digital adder-subtractor circuit. We will implement, operate, and investigate the operation of a 2-bit full adder from basic combinational 74LS logic. We will then operate the 74LS83 4-bit full adder to get the feel of the adder operation. Equipment and materials: 1. Digital trainer. 2. Some of IC's like: - 7400 Quadruple 2-input NAND gates. - 7408 Quad. 2 -input AND gates. - 7432 Quad. 2- Input OR gates. - 7486 Quad. 2-input XOR gates. - 7483 4bit full adders. 3. Wires A. HALF ADDER: A combinational logic circuit that performs the addition of two bits and produces the sum and carry is called a half adder as shown in Fig 4.1. In half adders, only two inputs are considered as operands; carry inputs are ignored.
A Half A dde r C ou t S UM A B C in Fu ll A dde r C ou t S UM

Figure 4.1 1. Connect the circuit as shown in Fig. 4.2 and record your data in table 1.
SW 1 SW 0 A B 1 2 1 2 3 S UM 3 L0 C ou t L1

Figure 4.2 Table 1 INPUTS A 0 0 1 1 B 0 1 0 1 -1Sum OUTPUTS Cout

Experiment No.5

Digital Logic Design

Q1. What is the relation between inputs & the carry outputs? ______________________________________________________________ Q2. What is the relation between inputs & the sum output? ______________________________________________________________

B.

FULL ADDER: The circuit that performs addition of three bits (two significant bits and a previous carry) and produces the sum and carry is called a full adder as shown in figure 4.1. Full adders are used to add three bits where one of them is the carry from the preceding adder. They have two outputs: the sum and the carry to the next stage.

1. Connect the circuit as shown in Fig. 4.3 and record your data in table 2.
SW 2 C in

SW 1 B SW 0 A

1 2 1 2

4 3 5 4 3 5

S UM L0

1 2

C ou t L1

Figure 4.3

Table 2 INPUTS OUTPUTS Cin B A Sum Cout 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

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Experiment No.5

Digital Logic Design

2. Connect the circuit as shown in Fig. 4.4 and record your data in table 3.
SW 2 C in

SW 0 SW 1

A B

1 2 1 2

4 3 5 3 4 5

S UM L0

6 9 10 8 C ou t L1

Figure 4.4

Table 3 INPUTS OUTPUTS Cin B A Sum Cout 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Q1. What are the relations between the outputs of Figure 4.3 and Figure 4.4?

Q2. Design and draw a block diagram of a 3-bit full adder using one half adder & two full adders only.

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Experiment No.5 C.

Digital Logic Design

4-Bit BINARY ADDER SUBTRACTOR: An n-bit binary adder can be constructed with n-full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder connected in chain. Such binary adders are available in IC form. Figure 4.5 shows the block diagram of 4-bit binary adder IC (74LS83). It can add two 4-bit numbers, say A (= A4 A3 A2 A1) and B (= B4 B3 B2 B1) and produce sum output S (= S4 S3 S2 S1). C0 is the initial carry input and C4 is the final carry output. The 7483 IC can be used as a 4-bit binary adder-subtractor with some modifications as shown in figure 4.6.

Figure 4.5 - Block diagram of 7483 IC

Figure 4.6 -4-

Experiment No.5

Digital Logic Design

It can be seen that the 7483 IC receives the first operand A directly and other operand B through XOR gates. Each XOR gates receives mode input M and one of the inputs of B. When M=0 the circuit is an adder and when M=1 it becomes subtractor as explained below. When M = 0, the initial carry C0 = 0, one of the input of each XOR gates is 0 and each XOR gate passes the other input to its output (because X0 = X). Thus the second input to 7483 IC is B and the circuit performs normal addition as follows: Initial carry First operand Second operand Sum output C4 C3 C2 C1 0 + A= A4 A3 A2 A1 + B= B4 B3 B2 B1 S = C4 S4 S3 S2 S1

When M = 1, the initial carry C0 = 1, one of the input of each XOR gates is 1 and each XOR gate produces the complement of its other input (because X1 = X). Thus the second input to 7483 IC is 1s complement of B. This 1s complement plus C0 (1) becomes 2s complement of B. Thus circuit adds 2s complement of B to A (i.e. subtraction by 2s complement). Initial carry First operand Second operand Sum output C4 C3 C2 C1 1 + A4 A3 A2 A1 + B4 B3 B2 B1 C4 S 4 S 3 S 2 S 1

A= 1s complement of B = S=

1. Connect the 7483 IC as shown in Fig. 4.6. Note that A4, A3, A2, and A1 are connected to SW3, SW2, SW1, and SW0 respectively. B4, B3, B2, and B1 are connected to SW7, SW6, SW5, and SW4 respectively. Connect M to pulser switch to have a logic 1 or logic 0. Record your data in table 4. Table 4 M=0 Inputs A4A3A2A1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 B4B3 B2B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Outputs C4 S4S3S2 S1 Inputs A4A3A2A1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 B4B3 B2B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 M=1 Outputs C4 S4S3S2 S1

Questions: 1. How many full-adders in the 7483 IC? _______________________________________. 2. If M=0, what is the output of the XOR gates in figure 4.6? ___________________. 3. Measure the propagation delay time in the 4-bit parallel adder? ____________________. 4. During addition or subtraction. When is C4 =1? ______________ , _________________.

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