Accessing I/O devices

Single Bus Arrangement - A simple arrangement to connect I/O devices to a computer. The bus enables all the devices connected
to it to exchange information. It consists of three sets of lines used to carry address, data, and control signals.

Memory-Mapped I/O Arrangement- I/O devices and the memory share the same address space

*I/O devices operate at speeds that are vastly different from that of the processor.
*SIN status input flag. When this flag is set to 1, the programs reads the input data register.

Program-controlled I/O - The processor repeatedly checks a status flag to achieve the required synchronization between the
processor and an input or output device.

Direct Memory Access - A technique used for high-speed I/O devices.

Interrupt - sending hardware signal to the processor.

Interrupt-request line- one of the bus control lines.

* By using interrupts, waiting for an I/O device to become read can be eliminated

Interrupt Service Routine - the routine executed in response to an interrupt request.

Interrupt-acknowledge Signal - Inform the device that its request has been recognized so that it may remove its interrupt-request
signal.

INTERRUPTS – a signal indicating the need for attention or a synchronous event in software indicating the need for a change in
execution.

Hardware interrupt -causes the processor to save its state of execution via a content switch and begin execution of an interrupt
handler.

Interrupt Service routine -the routine executed in response to an interrupt request.

Interrupts
-Maskable interrupt - is a hardware interrupt that may be ignored by setting a bit in an interrupt mask register’s bit-mask.
-Non-maskable interrupt –is a hardware interrupt that does not have a bit-mask associated with it.
-Software interrupt - an interrupt generated within a processor by executing an instruction.
-Interprocessor interrupt - a special case of interrupt that is generated by one processor to interrupt another processor in a
multiprocessor system.
-Spurious interrupt - a hardware interrupt that is unwanted.

ENABLING AND DISABLING INTERRUPTS

-A fundamental facility found in all computers is the ability to enable and disable interruptions as desired.
-Some means of enabling and disabling interrupts must be available to the programmer.
-It is essential to ensure that this active request signal does not lead to successive interruptions, causing the system to
enter an infinite loop from which it cannot recover.

SEVERAL MECHANISMS TO AVOID PROBLEMS

-The first possibility is to have the processor hardware ignore the interrupt-request line until the execution of the first
instruction of the interrupt-service routine has been completed.
-Suitable for a simple processor with only one interrupt-request line, is to have the processor automatically disable
interrupts before starting the execution of the interrupt-service routine.
-The processor has a special interrupt-request line for which the interrupt-handling circuit responds only to the leading
edge of the signal.

HANDLING MULTIPLE DEVICES

STATUS REGISTER - is a collection of flag bits for a processor.
POLLING SCHEME – interrogation of the IRQ bits for identifying devices.

* The first device encountered with its IRQ bit set is the device that should be serviced.
VECTORED INTERRUPTS
-Is an alternative for polling schemes that reduces the time involved
-The device requesting for an interrupt may identify itself directly to the processor through special codes.
The code may represent the starting address of the interrupt-service routine for that device.
The code length is typically in the range of 4-8 bits.

INTERRUPT NESTING
A multiple-level priority organization means that during execution of an interrupt service routine, interrupt requests will be
accepted from some devices but not from others, depending upon the device’s priority.

Privileged Exception – a special type of interrupt when there is an attempt to execute a privileged instruction while in the
user mode.

CONTROLLING DEVICE REQUEST

At the device end, an interrupt-enable bit in a control register determines whether the device is allowed to generate an
interrupt request.
At the processor end, either an interrupt enable bit in the PS register or a priority structure determines whether a given
interrupt request will be accepted.

E X C E P T I O N - often used to refer to any event that causes an interruption

Kinds of Exceptions
-Recovery from Errors
-Exception-Service Routine
-takes appropriate action to recover from the error or to inform the user about it.
Debugging
Debugger -helps the programmer find errors in a program.

2 important facilities of debugger:

Trace Mode -an exception occurs after execution of every instruction.
Breakpoints -the program being debugged is interrupted only at specific points selected by the user.

Privilege Exception
Privileged Instruction -modifies the priority of the processor.
Operating System - Responsible for coordinating all activities within a computer.
-Makes extensive use of I/O operations.
-Incorporates the interrupt-service routines for all devices connected to a computer.
-Provides a variety of services to application programs.
The OS includes:
Multitasking – a mode of operation in which a processor executes several user programs at the same time.
Time slicing – with this technique, each program runs for a short period called a time slice.
OSINIT – set interrupt vectors.
SCHEDULER – an OS routine whose function is to determine which user program should run in the next time slice. It
saves all the information that will be needed later when the execution of a program is resumed.
Program State – the information saved by the SCHEDULER. It includes register contents, the program counter, and the
processor status word.
Processor Status Word – it contains the condition flags and other information such as priority level.

PROCESS
Running – the program is currently being executed.
Runnable – the program is ready for execution but is waiting to be selected by the SCHEDULER.
Blocked – the program is not ready to resume execution for some reason.
OSSERVICES – examine stack to determine requested operation.
IOINIT – a routine that is responsible for starting I/O operations.
Device Driver - is a computer program allowing higher-level computer programs to interact with a hardware device.
IODATA – poll devices to determine source of interrupt.
END – a flag that is set to 1 if the character is a carriage return.

Use of Interrupts in OS
 -Enables the operating system to assign priorities, switch from one user program to another, implement security and
protection features, and coordinate I/O activities.
-Can be used to call different parts of the OS, depending on the service being requested.

Processor Examples
ARM Interrupt Structure
ARM Processor
Advanced RISC (Reduced Instruction Set Computer) Machines has a simple yet powerful exception-handling
mechanism.

5 Sources of Exceptions
External interrupt-request lines (IRQ).
Fast Interrupt Request (FIQ).
Software Interrupt Instruction (SWI).
External Abort following a bus error.
Attempt to execute an undefined instruction.

Exceptions are handled according to the following priority structure:

1. Reset
2. Data Abort
3. FIQ
4. IRQ
5. Prefetch Abort
6. Undefined Structure

When the processor accepts an interrupt, it takes the following actions:

1. It saves the return address of the interrupted program in register14 of the corresponding mode.
2. It saves the contents of the current processor status register (CPSR) in the corresponding SPSR (Saved Processor Status
Register).
3. It changes the mode bits in CPSR according to the type of interrupt.
4. It branches to the interrupt-service routine starting at the appropriate vector address.

*The ARM Processor uses a pipelined structure.

Pipelined Structure - an instruction is fetched before the execution of the preceding instruction is completed.

ARM Processor
Stacks and Nesting
ARM Interrupt Mechanism - stores the return address in a register and does not automatically implements a stacking mechanism
to allow subroutine or interrupt nesting.

68000 Interrupt Structure

-The 68000 Interrupt Structure has eight interrupt priority levels
-The priority at which the processor is running at any given time is encoded in three bits of the processor status word with level 0
being the lowest priority
-A request is accepted only if its priority is higher than that of the processor except for level 7 requests.

Two Types
a. Internal Interrupt
-The internal interrupt is a Software Interrupt.
-Generated when the 68000 executes a software interruption called TRAP or by some undesirable event.
b. External Interrupts
-has seven level of external interrupt [1-7]
-Level 0 indicates no interrupt service is requested
-Levels 1 to 6 are level-sensitive
-Level 7 is edge triggered

Level Triggered interrupt – always generate an interrupt whenever the level of the interrupt source is asserted.
Edge Triggered interrupt – triggered only on the rising edge of the assertion of the interrupt request line. It cannot share the same
interrupt line.

*The 68000 checks for and accepts requests for interrupts only between instructions
*Level 7 are non maskable interrupt, always acknowledged and has the highest priority
*The processor automatically saves the contents of the program counter and the processor status word at the time of the
interruption.

*Once the 68000 has decided to acknowledge an interrupt request, it pushes the PC and SR onto the stack, enters supervisor state
by setting S-bit to 1, Clears TF to inhibit tracing and updates the priority mask bits

Trace Bit (T) -Enables a special type of interrupt called a trace exception
Supervisor bit (S) - Determines whether the processor is running in the Supervisor mode (S=1) or User mode (S=0)
RTE (Return-from-exception) - At the end of the exception processing, this instruction restores the 68000 to USER mode

Autovector facility – instead of sending a vector number, the device can activate a special bus control line to indicate that it wished
to use the autovector facility. The processor chooses one of seven vectors provided for this purpose based on the priority level of
the interrupt request.

Pentium Interrupt Structure

*Occurences of some interrupt and exception events causes the processor to branch to an interrupt service routine

-Advanced Programmable Interrupt Controller (APIC) – This interrupt controller implements a priority structure among different
devices and then sends an appropriate vector number to the processor for each device.
-EFLAGS – processor status register (INTEL)
-Interrupt Enable Flag (IF) – controls whether the processor should be interrupted or not, IF=1, INTR interrupts are accepted
-Trap Flag (TF) – enables trace interrupts after every instruction.
-I/O Privilege Level (IOPL) – shows the privilege level of the current program
-Statement Register – register that points to the base of the current segment being addressed
-EIP(Extended Instruction Pointer) – the address of the instruction the processor was executing at the time of the interrupt/
ESP – Extended Stack Pointer

*Pentium processor has 4 levels of privilege (0-3).

*Where Level 0 is the most highly privileged level
*Switching from one level to another involves a number of checks implemented in a mechanism called a gate

The processor takes the following actions:

1. Push processor Segment Register, CS, and EIP onto stack pointed by ESP
2. If exception resulting from an abnormal execution condition, it pushes code on the stack
3. Clears the IF
4. Fetches the starting address from Interrupt Descriptor Table
After servicing the IRQ, the interrupt-service routine returns to the interrupted program.
IRET pops EIP,CS and the processor SR from the stack into the corresponding registers, thus restoring the processor state
Direct Memory Access - The capability provided by some computer bus architectures that allows data to be sent directly from an
attached device (such as a disk drive) to the memory on the computer's motherboard.

DMA controller – performs the functions that would normally be carried out by the processor when accessing the main memory.

*To initiate transfer, the processor sends the starting address, quantity, destination.
*When the entire block is transferred, the controller informs the processor by raising an interrupt signal.
*OS is also responsible for suspending the execution of one program and starting another
*The program is in blocked state if the transfer involves DMA

Blocked State – cannot continue execution until all resources becomes available

R/W bit determines the direction of the transfer. When set to 1, performs read operation which transfers data from meory to the
device.
IRQ, the controller sets the IRQ bit to 1 when it has requested an interrupt
IE, when this flag is set to 1, it causes the controller to raise an interrupt after it has completed transferring a block of data
When the controller has completed transferring a block of data and is ready to receive another command, the Done flag is set to 1.
DMAC options for data transfer
a. CYCLE STEAL- A read or write signal is generated by the DMAC, and the I/O device either generates or latches the
data. The DMAC effectively steals cycles from the processor in order to transfer the byte, so single byte transfer is
also known as CYCLE STEALING

b. BLOCK or BURST mode – To achieve block transfers, some DMAC’s incorporate an automatic sequencing of the
value presented on the address bus. A register is used as a byte count, being decremented for each byte transfer,
and upon the byte count reaching zero, the DMAC will release the bus. When the DMAC operates in burst mode, the
CPU is halted for the duration of the data transfer

Bus Arbitration -The process by which the next device to become the bus master is selected and bus mastership is transferred to it

Bus Mastering – A method of enabling different device controllers on the bus to “talk” to one another without having to go through
the CPU

Two Approaches
a. Centralized Arbitration
Bus Request Line - This is a wired-OR line: the controller only knows that a request has been made by a
device, but doesn't know which device made the request.
Bus-Grant – If a device made a request, it will take control of the bus when it receives the asserted Bus Grant
Line and will leave the Bus Grant line negated for the next device in the chain. If the device didn’t request the
bus, then it will assert the BUS grant line for the next device in the chain.
- If more than one device makes a request at the same time, then the device that is closer will ger rhe
bus known as daisy chaining.

b. Distributed Arbitration
The Distributed arbitration means that all devices waiting to use the bus have equal responsibility in carrying out
the arbitration process, without using a central arbiter