Asynchronous Sequential Logic

For most figures:

We know dont we?

We have learned how to analyze and design circuits with memory, dont we?

We have designed really complicated circuits and can do so for any problem, right?
How about taking a look at our lovely latch circuit?

Asynchronous sequential circuits

No clock pulses Change of an internal state occurs when there is a change in the inputs. More difficult to design/analyze than synchronous sequential circuits. Useful in cases where speed is important. More economical to use. Combinational circuits with feedback loops (connected through delayed lines). Secondary variables: input end of the feedback loops., e.g. Y1, y2, yk.

Example

One input: x Two feedback loops Two excitation variables: Y1 and Y2 Two secondary variables: y1 and y2

Transition table

Y1 = xy1 + xy2 Y2 = xy1 + xy2 The input (x) is also part of the state Stable states are the circled ones where Y1 = y1 and Y2 = y2

Understanding the transition table

Four stable states: y1y2x = {000,011,110,101} If y1y2x = 000 and x: 0 1 Then Y1Y2x = 011

Procedure for analysis

Determine all feedback loops Assign Yi's (excitation variables), yi's (the secondary variables) Derive the Boolean functions of all Yi's Plot each Y function in a map Construct the state table Circle the stable states

Flow table

A flow table is a state transition table with its internal state being symbolized with letters

output

(a) is called a primitive flow table since it has only one stable state in each row
8

Designing an asynch. seq. ckt.

Assign a=0 b=1

Race conditions

Race conditions occur when two or more state variables are supposed to change simultaneously due to a change in the input. For instance: From y1y2=00 to y1y2 = 11 Three possible transitions: 00 11 00 10 11 00 01 11 Critical vs non-critical race conditions

10

Non-critical races

Three possible transitions: 00 11 00 10 11 00 01 11 If all possible transitions lead us to the same final state, then it is a noncritical race.

11

Critical races

Three possible transitions: 00 11 00 10 11 00 01 11 If different transitions lead to different final states, then it is a critical race.

12

Cycles

Cycle: a unique sequence of unstable states that the circuit goes.

13

Unstability

Y = (x1 y)x2 = x1x2 + x2 y If x1x2y = 111 Y = 0 If x1x2Y = 110 Y = 1 Oscillation between 1 and 0. Y will be a square wave.

14

SR latch - revisited

Forbidden input: 11

15

Asynchronous sequential circuits

No clock pulses Change of an internal state occurs when there is a change in the inputs. More difficult to design/analyze than synchronous sequential circuits. Useful in cases where speed is important. More economical to use. Combinational circuits with feedback loops (connected through delayed lines). Secondary variables: input end of the feedback loops., e.g. Y1, y2, yk.

17

Transition table

Y1 = xy1 + xy2 Y2 = xy1 + xy2 The input (x) is also part of the state Stable states are the circled ones where Y1 = y1 and Y2 = y2

18

Procedure for analysis

Determine all feedback loops Assign Yi's (excitation variables), yi's (the secondary variables) Derive the Boolean functions of all Yi's Plot each Y function in a map Construct the state table Circle the stable states

19

Flow table

A flow table is a state transition table with its internal state being symbolized with letters

output

(a) is called a primitive flow table since it has only one stable state in each row
20

Designing an asynch. seq. ckt.

Assign a=0 b=1

21

Race conditions

Race conditions occur when two or more state variables are supposed to change simultaneously due to a change in the input. For instance: From y1y2=00 to y1y2 = 11 Three possible transitions: 00 11 00 10 11 00 01 11 Critical vs non-critical race conditions

22

Critical races

Three possible transitions: 00 11 00 10 11 00 01 11 If different transitions lead to different final states, then it is a critical race.

23

Cycles

Cycle: a unique sequence of unstable states that the circuit goes.

24

Analysis example

25

26

Design with a latch

How were we designing in Sequential Logic?

WRONG!

27

Design Procedure

Gated latch with two inputs G and D. If G=1, then Q (latch output) should follow D. When G becomes 0, then the value of D at the time of the transition from G=1 to G=0 is retained at Q; i.e., once G becomes 0, the value of D does not change Q.
Inputs State a b c d e f
Let us start by giving a state to each row.

Output Q 0 1 0 0 1 1 Comments D=Q because G=1 D=Q because G=1 After state a or d After state c After state b or f After state e

D 0 1 0 1 1 0

G 1 1 0 0 0 0

29

Primitive flow table formation

Step 1: Stable states, and outputs are inserted. Since we allow only one of DG to change, put - to where they both change.

Inputs

Output

State
a

D
0

G
1

Q
0

Comments
D=Q because G=1

b
c

1
0

1
0

1
0

D=Q because G=1

After state a or d

d
e

1
1

0
0

0
1

After state c
After state b or f

After state e
30

Primitive flow table formation-2

Step 1: Stable states, and outputs are inserted. Step 2: Unstable states are determined. Outputs at these unstable states dont matter. Use - to indicate this.

31

Reduction of the flow table

32

Transition table
Set a=0 and b=1

33

Gated latch logic

34

Gated latch with SR latch

35

Assigning output to unstable states

Set the output of the transient state to 0 if the start and finish states have the output 0. Set the output of the transient state to 1 if the start and finish states have the output 1. Set the output of the transient state to - if the start and finish states have different outputs.

36

Design Procedure

Gated latch with two inputs G and D. If G=1, then Q (latch output) should follow D. When G becomes 0, then the value of D at the time of the transition from G=1 to G=0 is retained at Q; i.e., once G becomes 0, the value of D does not change Q.
Inputs State a b c d e f
Let us start by giving a state to each row.

Output Q 0 1 0 0 1 1 Comments D=Q because G=1 D=Q because G=1 After state a or d After state c After state b or f After state e

D 0 1 0 1 1 0

G 1 1 0 0 0 0

37

Primitive flow table formation

Step 1: Stable states, and outputs are inserted. Since we allow only one of DG to change, put - to where they both change.

Inputs

Output

State
a

D
0

G
1

Q
0

Comments
D=Q because G=1

b
c

1
0

1
0

1
0

D=Q because G=1

After state a or d

d
e

1
1

0
0

0
1

After state c
After state b or f

After state e
38

Primitive flow table formation-2

Step 1: Stable states, and outputs are inserted. Step 2: Unstable states are determined. Outputs at these unstable states dont matter. Use - to indicate this.

39

Reduction of the flow table

40

Transition table
Set a=0 and b=1

41

Gated latch logic

42

Gated latch with SR latch

43

Assigning output to unstable states

Set the output of the transient state to 0 if the start and finish states have the output 0. Set the output of the transient state to 1 if the start and finish states have the output 1. Set the output of the transient state to - if the start and finish states have different outputs.

44

A formal procedure for reducing flow table

Any Equivalent States?

In (a,b), x=0 -> next states: (c,d) x=1 -> next states: (a,b) In (c,d), x=0 -> next states: (a,b) x=1 -> next state: d
45

If c=d, then we can say a=b. In other words, (a,b) implies (c,d).

A formal procedure for reducing flow table

Place a X for all pairs of states whose outputs differ. Fill in the remaining cells with values of implied states. For each confirmed implication, put a tick.

46

Implication table from the flow table

What happens if the circuit is not completely specified? Compatible states: two incompletely specified states that can be combined (i.e., there is no conflict! )

47

Merger Diagram for Finding Maximal Compatibles

Links are drawn between compatible states.

An n-state compatible is represented by an n-sided polygon with all its diagonals connected.

48

How to Merge using the Merger Diagram?

The resulting set of compatibles need to be: Covering: Contains all initial states.

Closed: Contains all the implied states.

The closed & covering set of compatibles determine the reduced flow table.

So, what is the subset of (a,b), (a,c,d), (b,e,f) that satisfy coverage and closedness? For coverage, (a,c,d) and (b,e,f) are sufficient. Do (a,c,d) and (b,e,f) satisfy closedness? Are the implied states of (a,c), (a,d), (c,d), (b,e), (b,e), (b,f) included in the selected set?

Another Example for Merger Diagram

50

Quizzzz
1. 2. 3.
Derive the implication table for the following transition table. Draw the merger diagram and determine the set of maximal compatibles. Determine the minimum set of maximal compatibles and draw the reduced transition table.

51

Hazards
A hazard is a condition in which a change in a single variable produces a momentary change in output when no change should occur.
All inputs are 1 at the beginning. When x2 becomes 0, due to delay caused by the NOT gate, Y may temporarily become 0.

60

Types of Hazards

61

Removing Hazards
Hazars are produced when changing from one term to another! This causes a problem because during the transition, neither of the terms might be 1. So, make redundant terms/groups so that the new terms make sure that the transition is covered.

62

The Circuit After Removing the Hazard

63

Another way to avoid hazards

Implement the circuit with SR latches!!! Why would this remove hazards?

64

Implementation with SR latches to avoid hazards

65

Essential Hazards

Due to delays, feedback loops might produce hazards. These hazards cannot be corrected by adding gates/terms. They can be avoided only by adjusting the delays in the feedback loops according to the delays in the input signals.

66

the last of the Asyncronous Logic part

Quiz

Check whether the following circuit has a hazard. If it does, remove the hazard by both
a) b) adding redundant terms to the Y function, implementing the circuit with SR-latches.

67