RAJALAKSHMI INSTITUTE OF TECHNOLOGY, CHENNAI - 602124 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

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EC2354

VLSI DESIGN

3003

1 CMOS TECHNOLOGY ! A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal IV effects, DC transfer characteristics - CMOS technologies, Layout design ules, CMOS !rocess enhance"ents, #echnology related CAD issues, Manufacturing issues 2 CIRCUIT CHARACTERI"ATION AND SIMULATION ! Delay esti"ation, Logical effort and #ransistor si$ing, %o&er dissi!ation, Interconnect, Design "argin, eliability, Scaling- S%IC' tutorial, De(ice "odels, De(ice characteri$ation, Circuit characteri$ation, Interconnect si"ulation 3 COM#INATIONAL AND SE$UENTIAL CIRCUIT DESIGN ! Circuit fa"ilies )Lo& !o&er logic design ) co"!arison of circuit fa"ilies ) Se*uencing static circuits, circuit design of latches and fli! flo!s, Static se*uencing ele"ent "ethodology- se*uencing dyna"ic circuits ) synchroni$ers 4 CMOS TESTING ! Need for testing- #esters, #e+t fi+tures and test !rogra"s- Logic (erification- Silicon debug !rinci!les- Manufacturing test ) Design for testability ) ,oundary scan 5 SPECIFICATION USING VERILOG HDL ! ,asic conce!ts- identifiers- gate !ri"iti(es, gate delays, o!erators, ti"ing controls, !rocedural assign"ents conditional state"ents, Data flo& and #L, structural gate le(el s&itch le(el "odeling, Design hierarchies, ,eha(ioral and #L "odeling, #est benches, Structural gate le(el descri!tion of decoder, e*uality detector, co"!arator, !riority encoder, half adder, full adder, i!!le carry adder, D latch and D fli! flo!TOTAL% 45 PERIODS TE&T#OOKS' .- /este and Harris0 CMOS VLSI D'SI1N 2#hird edition3 %earson 'ducation, 4556 4- 7ye"ura 8-%0 Introduction to VLSI circuits and syste"s, /iley 4554-

REFERENCES' . D-A %uc9nell : ;-'shraghian ,asic VLSI Design, #hird edition, %HI, 455< 4 /ayne /olf, Modern VLSI design, %earson 'ducation, 455< < M-8-S-S"ith0 A!!lication s!ecific integrated circuits, %earson 'ducation, .==> ? 8-,has9er0 Verilog HDL !ri"er, ,S !ublication,455. 6 Ciletti Ad(anced Digital Design &ith the Verilog HDL, %rentice Hall of India, 455< @- Sa"ir %alnit9ar, Verilog HDL- 1uide to Digital Design and Synthesis, <rd edition , %earson 'ducation 455<

LESSON PLAN
UNIT I CMOS TECHNOLOGY S N* 3 C/4/-.5;<( H*/6) T*,;1) H*/6) U+;5 T7R #**: P.=( N*

. 4 < ? @ A .5 .. .4 .<

A brief History-MOS transistor Ideal I-V characteristics C-V characteristics Non ideal IV effects DC transfer characteristics CMOS technologies Layout design ules CMOS !rocess enhance"ents #echnology related CAD issues, Manufacturing issues

. . . 4 4 4 . . . .

I . I I I I I I I I

#. #. #. #. #. #. #. #.

. ?4 ?6 6. @5, A<

=., .56 #. #. .5>

UNIT II CIRCUIT CHARACTERI"ATION AND SIMULATION S N* 3 C/4/-.5;<( H*/6) T*,;1) H*/6) U+;5 T7R #**: P.=( N*

.? .6 .@ .> .A

Delay esti"ation, Logical effort and #ransistor si$ing, %o&er dissi!ation, Interconnect, Design "argin eliability

. . . . .

II II II II II

#. #. #. #. #.

... .4. .4= .?6 .?A

.= 45 4. 44 4<

Scaling- S%IC' tutorial De(ice "odels De(ice characteri$ation Circuit characteri$ation Interconnect si"ulation

. . . . .

II II II II II

#. #. #. #. #.

.@5, .>= .=5 .=< 456 4.5

UNIT III COM#INATIONAL AND SE$UENTIAL CIRCUIT DESIGN S N* 3 C/4/-.5;<( H*/6) T*,;1) H*/6) U+;5 T7R #**: P.=( N*

4? 4@ 4> 4A 4= <5 <.

Circuit fa"ilies Lo& !o&er logic design ) co"!arison of circuit fa"ilies Se*uencing static circuits, circuit design of latches and fli! flo!s, Static se*uencing ele"ent "ethodology se*uencing dyna"ic circuitssynchroni$ers

4 . . . . . 4

III III III III III III III

#. #. #. #. #. #. .

4.@ 4?4 4?< 46. 4@6 4>6 4A?

UNIT IV CMOS TESTING S N* 3 C/4/-.5;<( H*/6) T*,;1) H*/6) U+;5 T7R #**: P.=( N*

<< <? <6 <@ <> <A <=

Need for testing- #esters, #e+t fi+tures and test !rogra"s Logic (erification Silicon debug !rinci!les Manufacturing test Design for testability ,oundary scan

. . . . . . 4

IV IV IV IV IV IV IV

#. #.

6<. 6<>

#. #. 6?4, 6?? #. #. #. 6?A 66=

UNIT V SPECIFICATION USING VERILOG HDL

S N* 3 C/4/-.5;<( H*/6)

T*,;1)

H*/6)

U+;5

T7R #**:

P.=( N*

?. ?< ?? ?6 ?> ?= 65 6. 64 6<

TE&T#OOK'

,asic conce!ts- identifiers, gate !ri"iti(es, gate delays o!erators, ti"ing controls !rocedural assign"ents conditional state"ents Data flo& and #L, structural gate le(el s&itch le(el "odeling Design hierarchies, ,eha(ioral and #L "odeling #est benches Structural gate le(el descri!tion of decoder, e*uality detector, co"!arator, !riority encoder, half adder, full adder, i!!le carry adder D latch and D fli! flo!

4 . . 4 4 . . . . .

V V V V V V V V V V

@ @ @ @ @ #. @ @ @ @

<A 4?= 46@ .<4 6@, @6 6=< @6 4.? 44? 44?

.- /este and Harris0 CMOS VLSI D'SI1N 2#hird edition3 %earson 'ducation, 4556
REFERENCES'

.- Sa"ir %alnit9ar, Verilog HDL- 1uide to Digital Design and Synthesis, <rd edition , %earson 'ducation 455<

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PRINCIPAL