Multiplication: More Complicated Than Addition Multiplying 1000 by 1001

Multiplication
Arithmetic for Computers 2

Multiplication
More complicated than addition
accomplished via shifting and addition
Multiplying 10002 by 10012
( )
( )
( )
( )
( ) { } ( ) { } ( ) { } ( ) X 2 y X 2 y X 2 y X 2 y P
X 2 y
X 2 y
X 2 y
X 2 y
y y y y Y
x x x x X
3
3
2
2
1
1
0
0
3
3
2
2
1
1
0
0
0 1 2 3
0 1 2 3
+ + + =
=
= Multiplicand 1000
2
Multiplier 1001
2
1000
00000
000000
1000000
Product 1001000
2
x
+
Multiplication : Algorithm I
Pn-1 =P
Pi
Pi-1
P0
X) (2 y X) (2 y X) (2 y X) (2 y
X) (2 y y 2 X Y X P
1 n
1 n
i
i
1 i
1 i
0
0
1 n
0 i
i
i
1 n
0 i
i
i
=
+ + + + + =
= = =

where, (2
i
X) is equivalent to X shifting i positions to the left.
X) (2 y P P
i
i 1 i i
+ =

Therefore, Multiplication is implemented by
1. Shifting X by y
i
bit at a time,
2. Adding the resulting terms.
1. Shifting X by y
i
bit at a time,
2. Adding the resulting terms.
yes
0. Initialization;
Load Multiplicand and Multiplier,
And Clear Product and iteration
2. Addition;
Add Multiplicand to Product in ALU,
And place the result in Product Register
LSB=1
Test LSB of Multiplier
1. Shifting;
Shift the Multiplicand Register left 1 bit
Shift the Multiplier Register right 1 bit
LSB=0
repetition < n ?
no
init X input1;
Y input2;
P 0;
iteration 0;
next if (Y
lsb
=1) {
add P P + X;
}
shift X shift-left X;
Y shift-right Y;
iteration++;
if (iteration<n) goto next;
end output P;
Y
lsb
Y
lsb
=1
2. Addition;
P P + X;
Y
lsb
=0
1. Shifting;
X shift-left X;
Y shift-right Y;
BEGIN
0. Initialization;
X input1;
Y input2;
P 0;
iteration 0;
yes
no
END
iteration < n ?
iteration++;
Multiplication : Example
Multiply 2
10
x 3
10
, or 0010
2
x 0011
2
0 Initial values 0011 0000 0010 0000 0000
0 Test of LSB 0011 0000 0010 0000 0000
1 Test of LSB 0001 0000 0100 0000 0010
2 Test of LSB 0000 0000 1000 0000 0110
3 Test of LSB 0000 0001 0000 0000 0110
1 Increment Repetition & Check 0001 0000 0100 0000 0010
Iteration Operation Multiplier Multiplicand Product
0 Addition 0011 0000 0010 0000 0010
1 Addition 0001 0000 0100 0000 0110
0 Shift Left Multiplicand 0011 0000 0100 0000 0010
0 Shift Right Multiplier 0001 0000 0100 0000 0010
Multiplication : Implementation I
Y
lsb
iteration
init X input1;
Y input2;
P 0;
iteration 0;
next if (Y
lsb
=1) {
add P P + X;
}
shift X shift-left X;
Y shift-right Y;
iteration++;
end output P;
Y input2;
Y
input2
Load
P
P 0;
output
output P;
Clear
iter
iteration 0;
Clear
P P + X;
+
Load
Add
Increment
X
input1
X input1;
X sl X;
ShiftLeft
Y sr Y;
ShiftRight
Load
Control
Unit
Multiplication : Implementation I
Multiplicand
X
Multiplier
Y
Product
P
2n-bit
ALU
Shift Left
Shift Right
Load
Add
Load
Load
Input1
Input2
Output
0
Ylsb
Counter
C
Clear
Clear
Increment
Control
Unit
iteration
n n
n
2n
2n
2n
2n
2n
Multiplication : Algorithm II
{ } { } { } { } { } { } X) (2 y X) (2 y X) (2 y X) (2 y X) (2 y 2 2 2 2 2 2
X) (2 y X) (2 y Y)2 (2 y 2 2 2
X) (2 y X)2 (2 y 2 2
X)2 (2 y 2 ) 2 2 2 X (2 y
X) (2 y y 2 X Y X P
n
1 n
n
2 n
n
3 n
n
1
n
0
1 1 1 1 1 1
n
1 n
n
2 n
3 n
0 i
3) (n i n
i
1 1 1
n
1 n
2 n
0 i
2) (n i n
i
1 1
1 n
0 i
1) (n j n
i
1
1 n
0 i
1) (n 1 n i
i
1 n
0 i
i
i
1 n
0 i
i
i

=
+ + + + + =
)
`
+
)
`
+ =
)
`
+ =
= =
= = =

( ) X) (2 y P 2 P
n
i 1 i
1
i
+ =


1. Adding the high of product with X by y
i
,
2. Shifting the resulting terms.
0. Initialization;
Load Multiplicand and Multiplier,
And Clear Product and iteration
2. Shifting;
Shift the Product Register right 1 bit
Shift the Multiplier Register right 1 bit
1. Addition;
Add Multiplicand to the high of Product,
And place the result in the high of Product Register
LSB=1
LSB=0
yes
repetition < n ?
no
init X input1;
Y input2;
P 0;
iteration 0;
next if (Y
lsb
=1) {
add PH PH + X;
}
shift P shift-right P;
Y shift-right Y;
iteration++;
end output [P];
Ylsb
Y
lsb
=1
Y
lsb
=0
0. Initialization;
X input1;
Y input2;
P 0;
iteration 0;
1. Addition;
PH PH + X;
2. Shifting;
P shift-right P;
Y shift-right Y;
BEGIN
iteration < n ?
yes
no
END
iteration++;
Multiply 2
10
x 3
10
= 6
10
, or 0010
2
x 0011
2
= 0110
2
0 Initial values 0011 0010 0000 0000
0 Test of LSB 0011 0010 0000 0000
1 Test of LSB 0001 0010 0001 0000
2 Test of LSB 0000 0010 0001 1000
3 Test of LSB 0000 0010 0000 1100
1 Increment Repetition & Check 0001 0010 0001 0000
Iteration Operation Multiplier Multiplicand Product
0 Addition 0011 0010 0010 0000
1 Addition 0001 0010 0011 0000
0 Shift Right Product 0011 0010 0001 0000
0 Shift Right Multiplier 0001 0010 0001 0000
Multiplication : Implementation II
Product
P
Multiplicand
X
Multiplier
Y
n bit
ALU
Shift Right
Shift Right
Load
Add
Load
Load
Input1
Input2
Output
Y
lsb
Counter
C
Clear
Clear
Increment
Control
Unit
iteration
n
n
n
n
n
n
n
2n
Multiplication : Algorithm III
Multiplier = the low of Product Register
0. Initialization;
Load Multiplicand,
Load Multiplier to the low of Product Register,
And Clear the high of Product, and iteration
repetition < n ?
1. Addition;
Add Multiplicand to the high of Product,
And place the result in the high of Product Register
2. Shifting;
Shift the Product Register right 1 bit
LSB=1
LSB=0
yes
no
Multiplication : Algorithm III
init X input1;
PL input2;
PH 0;
iteration 0;
next if (P
lsb
=1) {
add PH PH + X;
}
shift P shift-right P;
iteration++;
end output P;
P
lsb
P
lsb
=1
P
lsb
=0
0. Initialization;
X input1;
PL input2;
PH 0;
iteration 0;
1. Addition;
PH PH + X;
2. Shifting;
P shift-right P;
BEGIN
iteration < n ?
yes
no
END
iteration++;
Multiply 2
10
x 3
10
= 6
10
, or 0010
2
x 0011
2
= 0110
2
0 Initial values 0010 0000 0011
0 Test of LSB 0010 0000 0011
1 Test of LSB 0010 0001 0001
2 Test of LSB 0010 0001 1000
3 Test of LSB 0010 0000 1100
1 Increment Repetition & Check 0010 0001 0001
Iteration Operation Multiplicand Product
0 Addition 0010 0010 0011
1 Addition 0010 0011 0001
0 Shift Right Product 0010 0001 0001
Multiplication : Implementation III
Product
(PH) P (PL)
Multiplicand
X
n bit
ALU
Shift Right
Load
Add
Load
Input1
Input2
Output
Counter
C
Clear
Clear
Increment
Control
Unit
iteration
Load
Plsb
n
n
n
n
n
n
n
2n
Twos Complement Multiplication
( )
|
.
|
\
|
+ =
|
.
|
\
|
+ =
|
.
|
\
|
+ =
|
.
|
\
|
+ = =
2 n
0 i
2) (n i n
i
1
2 n
0 i
2) (n i n
i
2
2 n
0 i
i
i
2 n
0 i
i
i
)2 (2 y 2
)2 (2 y 2
) (2 y
y 2
X X
X X
X X
X Y X P
) 2 ( 2
) 2 ( 2
) 2 (
2
1
1
1
1
1
1
1
1
n
n
n
n
n
n
n
n
y
y
y
y
Plsb
P
lsb
=1
P
lsb
=0
0. Initialization;
X input1;
PL input2;
PH 0;
iteration 0;
1. Addition;
PH PH + X;
2. Shifting;
P shift-right P;
BEGIN
iteration < n-1 ?
yes
no
END
iteration++;
Plsb
P
lsb
=1
P
lsb
=0
3. Subtraction;
PH PH - X;
4. Shifting;
P shift-right P;
init X input1;
PL input2;
PH 0;
iteration 0;
loop if (P
lsb
=1) {
add PH PH + X;
}
shift P shift-right[P];
iteration++;
if (iteration<n-1) goto loop;
if (P
lsb
=1) {
sub PH PH - X;
}
shift P shift-right[P];
end output P;
Example: Multiply 2
10
x (-3)
10
,=(-6)
10
, or 0010
2
x 1101
2
= 1111 1010
2
Iteration Operations Multiplicand Product
0 0: Initial values 0010 0 0000 1101
1: Addition Prod=Prod+Mcand 0010 0 0010 1101 1
2: Shift right Product 0010 0 0001 0110
2 2: Shift right Product 0010 0 0000 1011
1: Addition Prod=Prod+Mcand 0010 0 0010 1011 3
3: Subtraction: Prod=Prod-Mcand 0010 1 1111 0101 4


Product
(PH) P (PL)
Multiplicand
X
n bit
ALU
Shift Right
Load
Sub
Load
Input1
Input2
Output
Counter
C
Clear
Clear
Increment
Control
Unit
iteration
Load
P
lsb
Add
F
n
n
n
n
n
n
n
2n
Booths Algorithm
A more elegant approach to multiplying signed number
Y= 0...00011111111000000 = 2
j
- 2
i
j j-1 i i-1 n-1
0
Ex. 001110=2
4
- 2
1
=16 - 2=14
Current
bit
Bit to the
right
Explanation Example
0 0 Middle of a run of 0s,
No arithmetic operation
00001111000
0 1 End of a run of 1s,
Addition operation
00001111000
1 0 Beginning of a run of 1s,
Subtraction operation
00001111000
1 1 Middle of a run of 1s,
No arithmetic operation
00001111000

P = X x Y = X x (2
j
- 2
i
) = 2
j
X - 2
i
X
Booths Algorithm
Example: Multiply 2
10
x 3
10
, or 0010
2
x 0011
2
0 0: Initial values 0010 0 0000 0011 0
1b: Subtraction Prod=Prod-Mcand 0010 1 1110 0011 0 1
2: Shift right Product 0010 1 1111 0001 1
2 2: Shift right Product 0010 1 1111 1000 1
1a: Addttion Prod=Prod+Mcand 0010 0 0001 1000 1 3

Booths Algorithm
Example: Multiply 2
10
x (-3)
10
, or 0010
2
x 1101
2
0 0: Initial values 0010 0 0000 1101 0
1a: Addition Prod=Prod+Mcand 0010 0 0001 0110 1 2

Booths Algorithm
P
lsb
,P
-1
01
10
1a. Addition;
PH PH + X;
2. Shifting;
P shift-right P;
BEGIN
iteration < n ?
yes
no
END
iteration++;
0. Initialization;
X input1;
PL input2;
PH 0;
iteration 0;
1b. Subtraction;
PH PH - X;
00,11
Booths Algorithm : Implementation
Product
(PH) P (PL)
Multiplicand
X
n bit
ALU
Shift Right
Load
Sub
Load
Input1
Input2
Output
Counter
C
Clear
Clear
Increment
Control
Unit
iteration
Load
P
lsb
Add
P
-1
F
P
-1
n
n
n
n
n
n
2n
Booths Algorithm : Control Design
Control Signal
P
lsb
,P
-1
01
10
S1 /
PH
load
,Add;
S3 /
P
shift-right
;
[C] < n ?
yes
no
END
Ci
ncrement
;
S0 /
X
load
,PL
load
, PH
clear
, C
clear
;
S2 /
PH
load
,Sub;
00,11
BEGIN
no
yes
Initialization
Addition Subtraction
Shifting
P
r
e
s
e
n
t

S
t
a
t
e
B
E
G
I
N
(
[
C
]
<
n
)
P
l
s
b
P
-
l
N
e
x
t

S
t
a
t
e
X
l
o
a
d
P
L
l
o
a
d
P
H
c
l
e
a
r
P
H
l
o
a
d
P
s
h
i
f
t
-
r
i
g
h
t
A
d
d
S
u
b
C
-
c
l
e
a
r
C
-
i
n
c
r
e
m
e
n
t
E
N
D
J
K
-
F
l
i
p
-
F
l
o
p

I
n
p
u
t
s
00
00
00
00
00
01
10
11
11
11
11
11
0 d d d
1 d 0 0
1 d 0 1
1 d 1 0
1 d 1 1
d d d d
d d d d
d 0 d d
d 1 0 0
d 1 0 1
d 1 1 0
d 1 1 1
S0
S1
S2
S3
Transition Table
00
11
01
10
11
11
11
00
10
01
11
10
1 1 1 0 0 0 0 1 0 0
1 1 1 0 0 0 0 1 0 0
1 1 1 0 0 0 0 1 0 0
1 1 1 0 0 0 0 1 0 0
1 1 1 0 0 0 0 1 0 0
0 0 0 1 0 1 0 0 0 0
0 0 0 1 0 0 1 0 0 0
0 0 0 0 1 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 1 0
0d 0d
1d 0d
0d 1d
1d 1d
1d 0d
1d d0
d0 1d
d1 d1
d0 d1
d1 d0
d0 d0
d0 d1
000 001 011 010 100 101 111 110
000 0 0 1 1 d d d d
001 0 0 0 0 d d d d
011 0 0 1 1 d d d d
010 0 0 1 1 d d d d
100 1 1 1 1 d d d d
101 1 1 1 1 d d d d
111 1 1 1 1 d d d d
110 1 1 1 1 d d d d

n) ([C] BEGIN
1
s <
1 lsb 0
p p s

Logic Function : J
1
) p (p s J
1 lsb 0 1
BEGIN

+ + =
Logic Function
=
=
=
+ + =
< =
= =
=
=
=
= = = =
0
0
1
1 lsb 0 1
0 1
0 1 increment right shif t
0 1
0 1
0 1 load
0 1 clear clear load load
K
J
K
) p (p s J
n) ([C] s s END
s s C P
s s Sub
s s Add
s s PH
s s C PH PL X
BEGIN
Control Design : State-table Method
Logic Diagram
Combinational
Logic
JK-Flip Flops
J
1
K
1
J
0
K
0
X
load
PL
load
PH
clear
C
clear
PH
load
Add
P
shift-right
C
-increment
END
BEGIN
P
lsb
P
-1
([C]<n)
y
1
~y
1
y
0
~y
0
clock
Division
Design Methodology
34
Division
The Sequential Digit by Digit Algorithm:
Case for a fixed dividend
V) (2 q R R
i
i 1 i i
=
+
0111 : Q= q
3
q
2
q
1
q
0
: Quotient
101 100110 : R
4
= Dividend D
000 : q
3
(2
3
V)
100110 : R
3
101 : q
2
(2
2
V)
10010 : R
2
101 : q
1
(2
1
V)
1000 : R
1
101 : q
0
(2
0
V)
011 : R
0
= Remainder R
Divisor V:
Divider need ...
2n-bits Subtractor
2n-bits Divisor-Register
Restoring Division Algorithm I
1. Subtract the Divisor from Remainder and place the result in the
Remainder
2a. When the result of the subtraction is positive, setting the new
Quotient bit to 1.
2a. When the result of the subtraction is negative, a restoring
addition is performed as following
V) (2 q R R
i
i 1 i i
=
+
V) (2 q R R
i
i i i
+ =
0. Initialization;
Load Dividend in Remainder,
and Load Divisor in high of register,
And Clear Quotient and iteration
repetition <= n ?
2a. Setting;
Setting the new rightmost bit of
Quotient Register to 1
Test Remainder
Remainder< 0
yes
no
1. Subtraction;
Subtract the Divisor Register from the Remainder Register,
And place the result in the Remainder Register;
2b. Restoring;
Restore the original value by adding the
Divisor to the Remainder Register
Remainder>= 0
3. Shifting;
Shift the Divisor Register right 1 bit;
Shift the Quotient Register to the left;
Restoring Division : Example
Divide 7
10
/ 2
10
, or 0000 0110
2
/ 0010
2
I t e r a t i o n O p e r a t i o n s Q u o t i e n t D i v i s o r R e m a i n d e r
0 0 : I n i t i a l v a l u e s 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1
1 : S u b : R = R - D ; 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 1
2 b : R e s t o r e : R = R + D 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1
1
3 : S h i f t D i v i s o r r i g h t ; S h i f t - L - Q 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1
1 : S u b : R = R - D ; 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 1 1
2 b : R e s t o r e : R = R + D 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1
2
1 : S u b : R = R - D ; 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1
2 b : R e s t o r e : R = R + D 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1
3
1 : S u b : R = R - D ; 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1
2 a : S e t t i n g : Q l s b = 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1
4
1 : S u b : R = R - D ; 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 5
2 a : S e t t i n g : Q l s b = 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1

init R dividend;
V dividor;
Q 0;
C 0;
loop R [R] - [V];
if (Rmsb=1) {
restore R [R] + [V];
} else {
Qlsb 1;
}
if ([C]<n) {
[C]++;
shift V shift-right[V];
Q shift-left[Q];
goto loop;
}
end output [Q];
output [RL];
1. Subtraction;
R [R] - [V];
3. Shifting;
V shift-right[V];
Q shift-left[Q];
[C] < n ?
R
msb
R
msb
=1
yes
no
R
msb
= 0
0. Initialization;
R Dividend;
V Divisor;
Q 0;
C 0;
2a. Setting;
Qlsb 1;
2b. Restoring;
R [R]+[V];
[C]++;
Restoring Division : Implementation I
Divisor
V
Quotient
Q
Remainder
R
2n bit
ALU
Shift Right
Shift left
Load
Add
Load
Clear
dividend
divisor
Output
n bits
0
Qlsb
Counter
C
Clear
Increment
Control
Unit
[C]
Sub
Rmsb
Output
n n
n
2n
2n
2n
2n
2n
2n
Restoring Division Algorithm II
The Sequential Digit by Digit Algorithm:
Case for a fixed divisor
0111 : Quotient Q
101 100110 : 2R
4
= Dividend D
000 : q
3
V q
3
=0
100110 : R
3
1001100 : 2R
3
101 : q
2
V q
2
=1
100100 : R
2
1001000 : 2R
2
101 : q
1
V q
1
=1
100000 : R
1
1000000 : 2R
1
101 : q
0
V q
0
=1
011 : R
0
= Remainder R
Divisor V:
V q 2R R
i 1 i i
=
+
Divider need ...
n-bits Subtractor
n-bits V-Register
0. Initialization;
and Load Divisor,
And Clear Quotient and iteration
repetition <= n ?
2a. Setting;
Setting the new rightmost bit of
Quotient to 1
Test Remainder
Remainder< 0
yes
no
1. Subtraction;
Subtract the Divisor Register from the left of Remainder Register,
And place the result in the left of Remainder Register;
2b. Restoring;
Divisor to the left of Remainder Register
Remainder>= 0
3. Shifting;
Shift the Remainder Register left 1 bit
Shift the Quotient Register to the left;
Divide 7
10
/ 2
10
, or 0000 0110
2
/ 0010
2
Iterati on Operati ons Quoti ent Di vi sor Remai nder
0 0: Ini ti al val ues 0000 0010 0000 0111
1: Sub: RH= RH-V; 0000 0010 1110 0111
2b: Restore: RH=RH+V 0000 0010 0000 0111
1
3: Shi ft Remai nder l eft; Shi ft-L-Q 0000 0010 0000 1110
1: Sub: RH= RH-V; 0000 0010 1110 1110
2b: Restore: RH=RH+V 0000 0010 0000 1110
2
1: Sub: RH= RH-V; 0000 0010 1111 1100
2b: Restore: RH=RH+D 0000 0010 0001 1100
3
1: Sub: RH= RH-V; 0000 0010 0001 1000
2a: Setti ng: Ql s b=1 0001 0010 0001 1000
4
1: Sub: RH= RH-V; 0010 0010 0001 0000 5
2a: Setti ng: Ql s b=1 0011 0010 0001 0000

init R dividend;
V divider;
Q 0;
C 0;
loop R R] - V;
if (R
msb
=1) {
restore R R + V;
} else {
Q
lsb
1;
}
if (C<n) {
C++;
shift R shift-left V;
Q shift-left Q;
goto loop;
}
end output Q;
output RH;
1. Subtraction;
RH RH - V;
C < n ?
R
msb
R
msb
=1
yes
no
R
msb
= 0
0. Initialization;
R Dividend;
V Divisor;
Q 0;
C 0;
2a. Setting;
Q
lsb
1;
2b. Restoring;
RH RH + V;
C++;
3. Shifting;
R shift-left R;
Q shift-left Q;
Restoring Division : Implementation II
Divisor
V
Quotient
Q
Remainder
R
n bit
ALU
Shift left
Shift left Load
Add
Load
Clear
dividend divisor
Output
Q
lsb
Counter
C
Clear
Increment
Control
Unit
C
Sub
R
msb
Output
n
n
n
n
n
n
n
2n
2n
Restoring Division Algorithm III
0. Initialization;
and Load Divisor,
And Clear iteration
repetition <= n ?
2a. Setting;
Set the most-right of Remainder
Register to 1
3. Shifting;
Shift the Remainder Register left 1 bit
(Rlsb=0)
Test Remainder
Remainder< 0
yes
no
1. Subtraction;
Subtract the Divisor Register from the left of Remainder Register,
And place the result in the left of Remainder Register;
2b. Restoring;
Divisor to the left of Remainder Register
Remainder>= 0
Divide 7
10
/ 2
10
, or 0000 0110
2
/ 0010
2
Iteration Operations Divisor Remainder
0 0: Initial values 0010 0000 0111 0
1: Sub: RH=RH - V; 0010 1110 0111 0
2b: Restore: RH=RH+V 0010 0000 0111 0
1
3a: Shift Remainder left 0010 0000 1110 0
1: Sub: RH=RH - V; 0010 1110 1110 0
2b: Restore: RH= RH+V 0010 0000 1110 0
2
1: Sub: RH=RH - V; 0010 1111 1100 0
2b: Restore: RH=RH+D 0010 0001 1100 0
3
3: Shift Remainder left 0010 0011 1000 0
1: Sub: RH=RH - V; 0010 0001 1000 0
2a: Setting: R - 1=1 0010 0001 1000 1
4
1: Sub: RH=RH - V; 0010 0001 0001 1
2a: Setting: R - 1=1 0010 0001 0001 1
5
3b: Shift Remainder left 0010 0010 0011 1
Restoring Division Algorithm III
init R dividend;
V dividor;
C 0;
loop R R - V;
if (R
msb
=1) {
restore R R + V;
} else {
R
-1
1;
}
if (C<n) {
C++;
shift R shift-left R;
goto loop;
}
end output RH;
R shift-left R;
output RL;
1. Subtraction;
RH RH - V;
C < n ?
R
msb
R
msb
=1
yes
no
R
msb
= 0
0. Initialization;
R Dividend;
V Divisor;
C 0;
2a. Setting;
R
-1
1;
2b. Restoring;
RH RH + V;
3b. Shifting;
R shift-left R;
C++;
3a. Shifting;
R shift-left R;
output RH;
output RL;
Restoring Division : Implementation III
Divisor
V
Remainder
R
n bit
ALU
Shift left
Load
Add
Load
dividend divisor
Output
(Remainder)
R
-1
Counter
C
Clear
Increment
Control
Unit
C
Sub
R
msb
Output
(Quotient)
R
-1
n
n
n
n
n
n
n
2n
2n
R
i
<0 R
i-1
<0 R
i-2
<0 R
i-r+1
<0
Non-Restoring Division Algorithm
1. In restoring division, ( ) < 0 then the result is restored to
2. In a restoration of the form, if (q
i
q
i-1
...q
i-r+1
q
i-r
) = (00...01) then
R
i+1
= R
i
= R
i-1
= ... = R
i-r+1
Therefore
V 2 R R
i
1 i i
=
+
V 2 R R
i
i i
+ =
)V 2 2 2 2 2 ( R
V ))2 2 2 2 (2 2 ( R
V 1))2 (2 2 ( R
V 2 R R
r i 1 r i 2 i 1 i i
1 i
r i 0 1 2 r 1 r r
1 i
r i r r
1 i
r i
1 i r i
+
+

+
+
+ + + + + + =
+ + + + + + =
+ + =
=
R
i-r
>=0
V 2 V 2 V 2 V 2 V 2 R
r i 1 r i 2 i 1 i i
1 i
+
+
+ + + + + =
Non-Restoring Division Algorithm
init R dividend;
V dividor;
C 0;
loop if (R
msb
=1) {
RH RH + V;
else {
RH RH - V;
}
if (R
msb
=1) {
R
lsb
0;
} else {
R
lsb
1;
}
if (C<n) {
C++;
shift R shift-left R;
goto loop;
}
if (R
msb
=1) {
RH RH + V;
}
end output RL;
output RH;
R
msb
=1
yes
no
R
msb
= 0
R
msb
=1
R
msb
= 0
R
msb
=1
R
msb
= 0
1a. Subtraction;
RH RH - V;
C < n ?
R
msb
0. Initialization;
R Dividend;
V Divisor;
C 0;
2a. Setting;
R
lsb
1;
3. Shifting;
R shift-left R;
C++;
1b. Addition;
RH RH + V;
R
msb
2b. Setting;
R
lsb
0;
R
msb
1b. Addition;
RH RH + V;
Non-Restoring Division : Example
Divide 7
10
/ 2
10
, or 0000 0110
2
/ 0010
2
I t e r a t i o n O p e r a t i o n s D i v i s o r R e m a i n d e r
0 0 : I n i t i a l v a l u e s 0 0 1 0 0 0 0 0 0 1 1 1
1 : S u b t r a c t : R H = [ R H ] - [ V ] ; 0 0 1 0 1 1 1 0 0 1 1 1 1
2 : S h i f t l e f t R e m a i n d e r 0 0 1 0 1 1 0 0 1 1 1 0
1 : A d d : R H = [ R H ] + [ V ] ; 0 0 1 0 1 1 1 0 1 1 1 0 2
1 : A d d : R H = [ R H ] + [ V ] ; 0 0 1 0 1 1 1 1 1 1 0 0 3
1 : A d d : R H = [ R H ] + [ V ] ; 0 0 1 0 0 0 0 1 1 0 0 0
2 : S e t : R l s b = 1 0 0 1 0 0 0 0 1 1 0 0 1
4
1 : S u b t r a c t : R H = [ R H ] - [ V ] ; 0 0 1 0 0 0 0 1 0 0 1 0 5
2 : S e t : R l s b = 1 0 0 1 0 0 0 0 1 0 0 1 1

Non-Restoring Division : Implementation
Divisor
V
Remainder
R
n bit
ALU
Shift left
Load
Add
Load
dividend divisor
Output
(Remainder)
R
-1
Counter
C
Clear
Increment
Control
Unit
C
n bits
Sub
R
msb
Output
(Quotient)
R
-1
n
n n
n
n
n
2n
Signed Division
The following equation must always hold:
Dividend= Quotient x Divisor + Remainder
Example
+7 / +2 = ?, - 7 / +2 = ?
+7 / - 2 = ?, - 7 / - 2 = ?
Rewriting basic formula to calculate the remainder:
Remainder= Dividend - Quotient x Divisor
Example
+7 / +2:= +3 +1, - 7 / +2:= - 3 - 1
+7 / - 2:= - 3 +1, - 7 / - 2:= +3 - 1
The correct signed division algorithm
negates the quotient if the signs of the operands are opposite,
makes the sign of the remainder match the dividend

Multiplication: More Complicated Than Addition Multiplying 1000 by 1001

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Multiplication: More Complicated Than Addition Multiplying 1000 by 1001

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Multiplication

Arithmetic for Computers 2

Therefore, Multiplication is implemented by

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