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# Solve the Following 1) Given the function F(A,B,X,Y) = AB + X'Y, the most simplified Boolean representation for F'

is (A) (AB)' + (X'Y) (B) A'*B' + XY' (C) (A'+ B')(X + Y') 2) (D) (AB + X'*Y)'

An equivalent representation for the Boolean expression A + A' is (A) 1 (C) A (B) 0 (D) A

3)

In general, a NOR-NOR circuit is equivalent to which of the following circuit types? (A) AND-AND (C) OR-AND (B) AND-OR (D) NOR-NOR

4)

A NOT gate has... (A) Two inputs and one output (C) One input and two outputs (B) One input and one output (D) None of above

5)

For the electrical symbol illustrated below to represent "1" as it's output, the inputs must be:

(A) one input "1" the other "0". (C) the top input "0", the bottom input "1". 6) Half adder circuit is ______? (A) Half of an AND gate (C) A circuit to add two bits together 7)

## (B) both inputs "1". (D) both inputs "0".

(B) Half of a NAND gate (D) none of above (B) Y=AB+AB (D) Y=AB+ AB

A XNOR gate has inputs A and B and output Y.Then the output equation is: (A) Y=A+B (C) Y=AB+AB

8)

Which is correct? (A) A.1=A (C) A+A=A (B) A.A=0 (D) A.A=0

9)

What is the result from the expression B + BF? (A) 0 (C) F (B) 1 (D) B

10) A+(B.C)= (A) A.B+C (C) A 11) Demorgans theorem is A.B+A.C (D) (A+B)(A+C)

## (B) A=A (D) (AB)=AB

12) If one wants to design a binary counter, preferred type of flip-flop is (A) D-type (C) Latch 13) MSI stands for _____________ (A) Middle Scale Information (C) Medium Scale Information (B) Middle Scale Integration (D) Medium Scale Information (B) SR-type (D) JK-type

14) A flip-flop is a binary cell capable of storing _____________ bit of information. (A) three (C) two (B) one (D) four

15) A register that can shift in both direction is called a _________ shift registers (A) Unidirectional (C) Bidirectional (B) Tridirectional (D) None

16) Which of the following flip-flops is free from race around problem? (A) T flip-flop (C) Master-Slave Flip-flop (B) SR flip-flop (D) none

17) S-R type flip-flop can be converted into D type flip-flop if S is connected to R through (A) OR Gate (C) AND Gate (B) Inverter (D) Full Adder

18) A demultiplexer is also known as _______________ (A) a data selector (C) a shift register 19) A particular Full Adder has (A) 3 inputs and 2 output (C) 2 inputs and 3 output (B) 3 inputs and 3 output (D) 2 inputs and 2 output (B) a bus transceiver. (D) a data distributer

20) If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be (A) Set (B) Reset (C) Indeterminate Solve the Following 1. The logic device shown in the following Figure is: (D) Complement

(a) (b)

(c) (d)

## an exclusive-OR gate. an AND gate.

2. An equivalent representation for the Boolean expression A' + 1 is: (a) A (b) A' (c) 1 (d) 0 3. The gate function illustrated is an equivalent representation for an

## AND gate NAND gate NOR gate XOR gate

4. In general, a NAND-NAND circuit is equivalent to which of the following circuit types? (a) AND-AND (b) AND-OR (c) OR-AND (d) NOR-NOR 5. In order for output 'Y' to be a"1", inputs A, B, and C must be:

## (a) (b) (c) (d)

A=1, B=0, C=0. A=0, B=0, C=0. A=1, B=0, C=1. A=0, B=1, C=0.

6. Which of the following is the Universal Flip-flop? (a) SR Flip-flop (b) JK Flip-flop (c) Master slave Flip-flop (d) D Flip-flop 7. On a Karnaugh map, grouping the 0s produces: (a) A Dont Care condition (b) A SOP Expression (c) A POS Expression (d) None of the above 8. How is the JK Flip-flop made to toggle? (a) J=0, K=0 (b) J=1, K=0 (c) J=1, K=1 (d) J=0, K=1 9. The logic gate arrangement shown in following figure performs the same function as:

## a NOR gate a NAND gate an exclusive-OR gate. an exclusive-NOR gate.

10. Simplification of the Boolean expression (A+B+C)(D+E)' + (A+B+C)(D+E) yields which of the following results? (a) A+B+C (b) D+E (c) A'B'C' (d) D'E' 11. Which of the following gates generates the truth table shown? x y | F ----------0 0 | 1 0 1 | 0 1 0 | 0 1 1 | 1 (a) OR gate (b) NAND gate (c) XNOR gate (d) XOR gate 12. The logic gate arrangement shown in following figure will produce the:

## (a) (b) (c) (d)

OR logic function AND logic function NAND logic function. NOR logic function.

13. A group of bits transmitted at the same time is referred to as: (a) A clock signal (b) Parallel data (c) Serial data. (d) All of the above. 14. The logic arrangement shown in following Figure is equivalent to:

## an OR gate an AND gate a NAND gate. a NOR gate.

15. Full adder is constructed by using . (a) Two Half Adder& one OR gate. (b) Two OR gate &one HA (c) One HA & two OR gate. (d) One OR gate & one HA 16. Another name for a multiplexer is: (a) a data selector. (b) a bus transceiver. (c) a shift register. (d) a data distributer. 17. Simplification of the Boolean expression AB + ABC + ABCD + ABCDE + ABCDEF yields which of the following results? (a) ABCDEF (b) AB (c) AB + CD + EF (d) 1 18. A two-input NAND gate will produce a logic 0 output when: (a) Both of the inputs are at logic 0 (b) Either one of the inputs is at logic 0 (c) Both of the inputs are at logic 1. (d) None of the above 19. In a computer _____ is capable to store single binary bit. (a) Capacitor (b) Flip flop (c) Register (d) Inductor 20. A.(B + C) = A.B + A.C is the expression of _________________ (a) Demorgan's Law (b) Commutative Law (c) Distributive Law (d) Associative Law

Chapter - 1
1. What is the output state of an OR gate if the inputs are 0 and 1? a.0 b.1

c.3

d.2

2. What is the output state of an AND gate if the inputs are 0 and 1? a.0 b.1 c.3 d.2 3. A NOT gate has... a. Two inputs and one output b. One input and one output c. One input and two outputs d. none of above 4. For the electrical symbol illustrated below to represent "0" as it's output, the inputs must be:

a. b. c. d.

one input "1" the other "0". both inputs "1". both inputs "0". the top input "0", the bottom input "1".

5. For the electrical symbol illustrated below to represent "1" as it's output, the inputs must be:

a. b. c. d.

one input "1" the other "0". both inputs "1". both inputs "0". the top input "0", the bottom input "1".

6. An OR gate has... a. Two inputs and one output b. One input and one output c. One input and two outputs d. none of above 7. Logic states can only be ___ or 0. a. 3 b. 2 c.1 d.0 8. The output of a ____ gate is only 1 when all of its inputs are 1 a. NOR b. XOR c. AND d. NOT 9. A NAND gate is equivalent to an AND gate plus a .... gate put together. a. NOR b. NOT c. XOR d. none 10. Half adder circuit is ______? a. Half of an AND gate b. A circuit to add two bits together c. Half of a NAND gate d. none of above

11. Identify that function generated by the logic circuit shown. a. F = ABCD b. F = A + B + C + D c. F = (A' + B')(C' + D') d. F = (A + B)(C + D) 12. Which of the following gates generates the truth table shown? x y | F ------+---0 0 | 0 0 1 | 1 1 0 | 1 1 1 | 0 a. b. c. d. OR gate NAND gate NOR gate XOR gate

13. Which of these are universal gates a. only NOR b. only NAND c. both NOR and NAND d. NOT,AND,OR 14. A XOR gate has inputs A and B and output Y.Then the output equation is: a. Y=A+B b. Y=AB+AB c. Y=AB+ AB d. Y=AB+AB 15. Which is correct? a. A.A=0 c. A+A=A'

b. A+1=A d. A'.A'=0

16. What is only combination on A, B and C inputs that produces a low level (0) on the output of any OR logic gate? a. A=0, B=0, C=1 b. A=1, B=0, C=0 c. A=1, B=1, C=1 d. A=0, B=0, C=0 17. Regarding AND logic gates we can state: a. The output will be 1 when all inputs are 1. b. The output will be 0 when one or more inputs are equal to 0. c. A two-input AND logic gate can be represented thru the formula Y = A x B (or Y = A B). d. All of above 18. What is the result from the expression G + GF? a. 0 b. 1

c. F d. G 19. A+(B.C)= a. A.B+C b. A.B+A.C c. A d. (A+B).(A+C) 20. A.0= a. 1 b. A c. 0 d. A or 1 21. Demorgans theorem is a. A.A=0 b. A=A c. (A+B)=A. B d. (AB)=A. B 22. Which of the following is Universal flip-flop a. JK flip-flop b. RS flip-flop c. Master slave flip-flop d. D flip-flop. 23. If one wants to design a binary counter, preferred type of flip-flop is a. D-type b. SR-type c. Latch d. JK-type. 24. S-R type flip-flop can be converted into D type flip-flop if S is connected to R through a. OR gate b. Inverters c. AND gate d. Full Adder 25. A D flip-flop can be made from a a. JK flip-flop and an inverter b. RS flip-flop c. RS flip-flop and an inverter d. both (a) and (b). 26. How is a J-K flip-flop made to toggle? a. J = 0, K = 0 b. J = 1, K = 0 c. J = 0, K = 1 d. J = 1, K = 1 27. On a master-slave flip-flop, when is the master enabled? a. when the gate is LOW b. when the gate is HIGH c. both of the above d. neither of the above 28. A J-K flip-flop is in a "no change" condition when ________. a. J = 1, K = 1 b. J = 1, K = 0

c. J = 0, K = 1 d. J = 0, K = 0 29. In a computer _____ is capable to store single binary bit. a. Capacitor b. Flip flop c. Register d. Inductor 30. A set of flip flops integrated together is called ____ a. Counter b. Adder c. Register d. None of the above 31. Which is correct: a. A.A=0 b. A+1=A c. A+A=A d. A.A=0 32. The boolean expression X = AB + CD represents a. two ORs ANDed together b. a 4-input AND gate c. two ANDs ORed together d. an exclusive-Or 33. The expression _________ is an example of Commutative Law for Multiplication. a. AB+C = A+BC b. A(B+C) = B(A+C) c. AB=BA d. A+B=B+A 34. An example of SOP expression is a. A + B(C + D) b. A'B + AC' + AB'C c. (A' + B + C)(A + B' + C) d. both (a) nad (b) 35. A.(B + C) = A.B + A.C is the expression of _________________ a. Demorgan's Law b. Commutative Law c. Distributive Law d. Associative Law 36. In a 4-variable K-map, a 2-variable product term is produced by a. a 2-cell group of 1s b. a 8-cell group of 1s c. a 4-cell group of 1s d. a 4-cell group of 0s 37. On a Karnaugh map, grouping the 0s produces a. a POS expression b. a SOP expression c. a "don't care" condition d. AND-OR logic 38. A particular Full Adder has a. 3 inputs and 2 output b. 3 inputs and 3 output c. 2 inputs and 3 output d. 2 inputs and 2 output 39. Half-Adder Logic circuit contains _____ XOR Gates. a. 1 b. 2

c. 4 d. 6 40. If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be a. Set b. Reset c. Invalid d. Clear