Fabrication and

Characterization of N- and
P-Type a-Si:H Thin Film
Transistors
Engineering Practical
Jeffrey Frederick Gold
Fitzwilliam College
University of Cambridge
Lent 1997
FABRICATION AND
CHARACTERIZATION OF
n- AND p-TYPE a-Si:H THIN
FILM TRANSISTORS
Jeffrey Frederick Gold
UNIVERSITY OF CAMBRIDGE
CAVENDISH LABORATORY
CAMBRIDGE CB3 OHE
Introduction
Herein we describe the fabrication and char-
acterization of n- and p-type amorphous sil-
icon thin film transistors (TFTs ). The pla-
nar, inverted-staggered, type A ( unpassivated)
TFTs described were fabricated as part of the
laboratory practicals of the 1996 MPhil pro-
gram in Microelectronic Engineering and Semi-
conductor Physics.
Fabrication
The fabrication procedures consisted of the fol-
lowing:
1. Substrate preparation in clean-room con-
ditions.
2. Deposition of silicon dioxide (Si 0 2 passi-
vation layer in PECVD system.
3. Annealing step was not performed (and
ultimately affected device quality).
4. Deposition of a-Si: H layer.
1
Figure 1: Geometry and composition of n-
channel "keyhole" a-Si :H TFT. illustration
adapted from [3].
5. Deposition of doped (n+ ) a-Si:H layer.
6. Deposition of chromium and aluminum
(only aluminum in the case of p- type
TFT) .
7. Photolithography of a-Si:H TFT channel
region.
8. Photolit hography of a-Si:H island region
(see Figure 3) .
9. Devices were never annealed because
fabrication processes failed (bonding of
photo-resist to exposed surfaces) near end
of fabrication procedure. All devices
described henceforth are from previous
years.
Cross-sectional view of TFTs is shown in Ta-
ble 1 below. The final geometrical configura-
tion and stratigraphy is given in Figures 1 and
2.
1m Glass Substrate
0 a-Si:H
Gate Insulator
Electrodes
n-type a-Si:H
Figure 2: Stratigraphy of inverted-staggered n-
channel type-A (unpassivated) TFT. illustra-
tion adapted from [3].
Figure 3: Talystep (SLOAN DECTAC II) mea-
surement showing lengthwise cross-section of
n-type keyhole structure.
Layer I Thickness
Aluminum 1000 A
Chromium 1000 A
n-type Si 500 A
a-Si:H 3000 A
Si02 5000 A
c-Si 0.5 mm
Table 1: Cross-sectional view of TFTs. In the
p-channel TFT, the chromium layer is missing.
Here, the bottom layer is the substrate.
2
Characterization
The bias stressing of the transistors consisted
of the following procedures:
1. Measurement of TFT "as is".
2. 0 Volt bias anneal.
3. Measurement of annealed TFT.
4. Bias stress TFT at +20 Volts at 75 C for
1000 sec.
5. Measurement of stressed TFT.
6. 0 Volt bias anneal.
7. Measurement of annealed TFT.
8. Bias stress TFT at -20 Volts at 75 C for
1000 sec.
9. Measurement of stressed TFT.
10. 0 Volt bias anneal.
11. Measurement of annealed TFT.
Discussion
P-channel devices were created by allowing
aluminum to diffuse into the amorphous sili-
con. In n-channel devices, a chromium barrier
layer was deposited before the deposition of
aluminum.
The physics of MOS (metal-oxide-silicon)
devices is relevant to our discussion of the elec-
trical characteristics of these devices [1][4]. In-
terface traps and oxide charges affected the de-
vice performances, although for hydrogenated
amorphous silicon, the defect density is greatly
reduced. These defects tend to control many
of the electrical characteristics of the material
and are responsible for the characteristic meta-
stability.
Bias Stressing of TFTs
In the bias stressing test, in which weak Si-Si
bonds were broken with resulting defect for-
mation by the injection of charge carriers at
the a-Si:H/insulator interface, we found that
device characteristics, such as electron J?O-
bilities, threshold voltages, and pre-threshold
slopes (PTS), for example, were altered. The
physics behind these device characteristics pro-
poses that the defect state density moves up-
ward past the Fermi level for the negative bias
stress and moves down for the positive bias
stress, according to the defect model [2]. Even
though the devices were bias annealed, there
was evidence of migration of device character-
istics, especially in the case of p-channel TFTs.
That is to say, the formation and destruction of
defect states was not as reversible in p-channel
devices as in the case of n-channel devices. In
the case of the positive bias stress test for the
p-channel devices, the drain current increased
after the test , indicating a higher threshold
voltage at the gate.
We extracted the following TFT parameters:
Bias State II Mobility I Vt I PTS
0 V Anneal 0.156678 30.2026 0.243092
+20 v 0.174701 31.7757 0.229528
0 V Anneal 0.153862 30.1007 0.244402
-20 v 0.025447 33.0822 0.079896
0 V Anneal 0.154425 30.3751 0.237142
Table 2: The effects of annealing and bias
stressing on n-channel device mobility, thresh-
old voltage (Vt), and pre-threshold slope
(PTS).
The sub-threshold voltage is of interest be-
cause it gives an indication of the density of
states in the bandgap. As the voltage in-
creases, the density of states move higher into
the bandgap region toward the conduction
band, first through a linear region, and then
3
I Bias State II Mobility I Vt I PTS
0 V Anneal -0.04121 -11.0199 -0.42323
+20 v -0.05310 -19.6468 -0.35233
0 V Anneal -0.04309 -11.4161 -0.37966
-20 v -0.05792 -24.7844 -0.54844
0 V Anneal -0.04428 -11.7321 -0.40778
Table 3: The effects of annealing and bias
stressing on p-channel device mobility, thresh-
old voltage (Vt), and pre-threshold slope
(PTS).
later, as the voltage increases, into a saturation
region. Amorphous silicon ( a-Si) is slightly n-
type by its very nature because of the higher
number of defects and higher dangling bond
density [2].
Threshold Voltages and Pre-
Threshold Slopes
Both n- and p-type devices, when subjected to
the +20 V and -20 V bias tests, demonstrated
that the threshold voltages increased (see Ta-
bles 2 and 3). This means that higher volt-
ages are required to activate the device, a facet
also realized from the rather "shallow" pre-
threshold slopes. The plots for pre-threshold
slopes are given in Figures 4 and 5.
C-V Characteristics
We observed the shifting of t he C-V charac-
teristic curves as a result of t he resident oxide
charge. The p-channel devices displayed more
hysteresis than n-channel devices.
Electron Mobility
Note that p-channel device mobilit y is off by
a factor of 3 from n-channel device mobility.
This is in keeping with the retarded mobilities
of holes with respect to elect rons. However ,
.26 r-.--r--.--.-r .......
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.06 L-....1........--1----'---'---'----L----<'--...___.____,
-25 -20 -15 -10 -5 0 5 10 15 20 25
Bias
Figure 4: N -channel Pre- Threshold Slope
(PTS) vs. Bias.
-.325
-.35
-.375
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til
.... -.425

1l
-.45
= -.475
= ..
-.5 ..c:
u

-.525
-.55
.....-
--:
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/ v
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r--- --

--

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"an
rtel TS
-.575
-25 -20 -15 -10 -5 0 5 10 15 20 25
Bias
Figure 5: P-channel Pre-Threshold Slope
(PTS) vs. Bias. P-channel devices displayed
more meta-stability than n-channel devices,
that is to say, device characteristic values in p-
channel devices did not readily return to initial
values after 0 V bias annealing as did n-channel
devices after stress testing.
4
.18
.16
.14

.12
.1
1l
.08
-5 .06
z .04
.02
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v
JP'
I
I
I
&N- har
--
'-""
ne M bil ty
-25 -20 -15 -10 -5 0 5 10 15 20 25
Bias
Figure 6: N-channel Mobility vs. Bias. Here
the 0 Volt data imply annealing was carried
out with no bias prior to measurement, as in
Table 2.
the mobilities exhibited in our n-channel de-
vices were approximately one order of magni-
tude less than expected values. The mobilities
for the bias stressing tests are plotted in Fig-
ures 6 and 7.
Conclusion
Device and fabrication failure made it difficult
to extract any meaningful data for analysis;
however, we characterized the devices and ex-
tracted such information as electron mobilities,
threshold voltages, and pre-threshold slopes
from the data obtained.
Acknowledgements
I would like to thank our lab assistants for their
lively discussions and enthusiasm throughout
the practicals. I would also like to express
my gratitude to my teammates, Jason Lin Tan
(Downing) and Steven Keller (Churchill).
-.042
,e. -.044 -
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-.05
] -.052 A I'.
; -054 -+---.11--- --- --
- . I
-.056 V 1-ch nnel ob lil]
-.058 ---- ....... ------- ...... .. ...... ---- -- ........ ......... ....... .. ......
-.06 L..-.L.........L-...1.-....J...-..J...-...J..-....1..-....1.-....L...-J
-25 -20 -15 -10 -5 0 5 10 15 20 25
Bias
Figure 7: P-channel Mobility vs. Bias. Here
the 0 Volt data imply annealing was carried out
with no bias prior to measurement, as in Ta-
ble 3. P--channel devices displayed more meta-
stability than n-channel devices, that is to say,
device characteristic values in p-channel de-
vices did not readily return to initial values
after 0 V bias annealing as did n-channel de-
vices after stress testing.
References
[1] Sze, S. M. Physics of Semiconductor
Devices, 2nd Edition. John Wiley & Sons
Ltd. , New York, 1981.
[2] Street, R. A. Hydrogenerated Amorphous
Silicon. Cambridge University Press, Cam-
bridge, 1991.
[3] The Fabrication and Characterisation of
Hydrogenated Amorphous Silicon Thin Film
Transistors (a-Si:H TFTs). Engineering
Department/ MESP Handout. Cambridge
University, 1996.
[4] Sze, S. M. Semiconductor Devices: Physics
and Technology. John Wiley & Sons Ltd., New
York, 1985.
5