Sie sind auf Seite 1von 2

MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!

##$##"4# % #4444##"4# md&o' c(o&)t on(*'ma &+com

Ana&,( ( and De( 'n o- a Lo.-/o&ta'e Lo.-0o.er Do)b&e-Ta & Com1arator


A2STRACT Design and analysis of Low-power, area efficient and high speed analog-todigital converters is pushing toward the use of dynamic comparators, which is used to maximize speed and power efficiency. In the existing design, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. ased on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low-power and fast operation even in small supply voltages. !ithout complicating the design and by adding few transistors, the positive feedbac" during the regeneration is strengthened, which results in remar"ably reduced delay time. #ost-layout simulation results in a $.%&- m '()* technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. +he maximum cloc" fre,uency of the proposed comparator can be increased to -.. and %.% /0z at supply voltages of %.and $.1 2, while consuming %.3 m! and %.4 !, respectively. +he standard deviation of the input-referred offset is 5.& m2 at %.- 2 supply. 34ISTING S5ST3M In the existing design dynamic comparator is constructed, where the circuit of a conventional double tail comparator is modified for low-power and fast

MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!##$##"4# % #4444##"4# md&o' c(o&)t on(*'ma &+com operation even in small supply voltages. !ithout complicating the design and by adding few transistors, the positive feedbac" during the regeneration is strengthened, which results in remar"ably reduced delay time. #ost-layout simulation results in a $.%&-m '()* technology confirm the analysis results. It is shown that in the implemented dynamic comparator both the power consumption and delay time are significantly reduced. 0RO0OS3D S5ST3M In the proposed system a digitally controlled dual tail comparator is designed with tunable threshold is designed. 6sing the auto tunable threshold a comparator is capable of generating the digital signal from analog input through a systematic manner which achieve tolerance and efficiency SO6T7AR3 R38UIR3M3NT Design 7nvironment8 9ILI:9 I*7 Language8 20DL *imulation8 ()D7L*I( ; 9ILI:9 I*7 *imulator 9ARD7AR3 R38UIR3M3NT 9ILI:9 *#<=+<: Development Device8 9'4*.$$7 oard