KALASALINGAM UNIVERSITY

(KALASALINGAM ACADEMY OF RESEARCH AND EDUCATION) DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE PLAN

Academic Year Course Code Course Name Year/Semester/Branch

: : : :

2010-2011 ECE5014 VLSI Design IV/VII/ECE 3-0-0 3 Sriram Sundar.S Sriram Sundar.S

Lecture-Tutorial-Practical : Credits Course coordinator Course instructor : : :

1.

Pre-requisite:
Students are expected to have knowledge in Digital logic & MOS transistor theory.

2.
1. 2. 3. 4.

Objectives:
Objective of the course is To teach the students about the issues involved in the custom design of digital circuits. To review CMOS processes and teach the students about static & dynamic logic. To teach the students about low-power design at both the system and unit level. To give the student experience doing a significant design using mask-level layout tools and from written specifications.

3.

Learning outcome and end use:

At the end of the course the student must be able to 1. Create models of moderately sized CMOS circuits that realize specified digital functions. 2. Apply CMOS technology-specific layout rules in the placement and routing of transistors and interconnect, and to verify the functionality, timing, power, and parasitic effects.

4.
Sl. No. T1

Text Books:
Author Names Neil H E Weste, Kamran Eshranghian Books Title Principles of CMOS VLSI Design : A System Perspective Publisher Name Addison Wesley Edition 2nd edition, 2002

5.
Sl. No. R1 R2 R3 R4

Reference Books:
Authors Douglas A Pucknell, Kamran Eshranghian Wayne Wolf Amar Mukerjee Caver Mead, Lynn Conway Books Title Basic VLSI Design Modern VLSI Design Introduction to NMOS and CMOS VLSI System Design, Introduction to VLSI Systems Publisher PHI Pearson Education PHI Addison Wesley Edition 3rd Edition, 2004 1997 1986 1980

6.
Sl. No. W1

Web resources:
Topic Name wafer processing, CMOS Technology Web Resource

W2

1. http://www.me.gatech.edu/jonathan.colton/me4210/waferproc.pdf 2. http://www.aw-bc.com/info/weste/assets/downloads/ch1.pdf 3. http://www.rose-hulman.edu/~simoni/Classes/EC551/MOSFab /invfab3d.pdf 1. http://bwrc.eecs.berkeley.edu/Classes/icdesign/ee141_s02/notes.html CMOS Design 2. http://www.eee.metu.edu.tr/~askar/EE618/CMOS%20Design%20Rules. rules pdf 3. http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html

Sl. No. W3 W4 W5 W6

Topic Name

Web Resource 1. http://people.bu.edu/rknepper/sc571/chapter1_files/index.html

Threshold voltage VLSI Course materials ppt nptel

1. http://people.bu.edu/rknepper/sc571/chapter2_files/lecture2_A_file s/v3_document.htm http://inst.eecs.berkeley.edu/~cs250/fa09/lectures/ 1. http://nptel.iitm.ac.in/video.php?courseId=1004&p=1 2. http://nptel.iitm.ac.in/courses/Webcourse-contents/IIT-%20Guwahati /ic_tech/index.html

7.
Topic No.

Lesson Plan:
Topic Name Unit- I Overview Text Books Number of Periods Cumulative Periods

1 2 3 4 5 6 7 8 9 10 11 12 13

VLSI Design Process Architectural Design Logical Design Physical Design Layout Styles, Full Custom Semi Custom approaches Overview of wafer fabrication wafer processing Silicon gate NMOS process CMOS process N well P well Twin Tub Silicon On Insulator NMOS and PMOS enhancement transistors Threshold voltage MOS device equations Basic DC equations Second order effect Small signal AC characteristics NMOS and CMOS inverter Inverter delay Pass Transistor Transmission gate Need for design rules Mead Conway design rules for the Silicon gate NMOS process CMOS N well / P well design rules Sheet resistance Area Capacitance Wiring Capacitance

T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1

1 1 2 1 1 1 1 1 2 1 1 1 1

1 2 4 5 6 7 8 9 11 12 13 14 15

Unit- II Basic Electrical Properties of MOS And CMOS Circuits

Unit- III Layout Design Rules 14 15 16 17 T1, R4 T1, R4 T1, R4 T1, R4 2 2 2 1 17 19 21 22

Topic No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Topic Name Unit- IV Logic Design Switch logic- Gate Logic Inverter Two input NAND and NOR gate- Other forms of CMOS logic Dynamic CMOS logic Clocked CMOS logic Pre-charged domino CMOS logic Structure Design Simple combinational logic design examples Parity generator Multiplexer Clocked sequential circuits 2 Phase clocking Charge storage Dynamic Register Element NMOS and CMOS dynamic shift register. Design of a 4 bit shifter 4 bit arithmetic processor ALU Subsystem Implementing ALU functions with an Adder Carry look ahead adders Multipliers Serial/ Parallel Multipliers Pipelined multiplier array Modified booths algorithm high density memory FSM PLA Control Implementation.

Text Books T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1

Number of Periods 2 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1

Cumulative Periods 24 25 26 27 28 29 30 31 32 33 34 35 37 39 40 41

Unit- V Sub System Design Process

8.

Portions for sessional examination I, II:

Sessional Examination I Sessional Examination II Title I, II Title III, IV

9.
i. ii. iii.

Related Magazines / Journals:

IEEE Transactions on Very Large Scale Integration Systems. IEEE Journal of Solid-State Circuits. Integration, the VLSI Journal (Elsevier).

10. Industries that can be visited / In-plant training:

i. ii. iii. Cadence Design Systems, Bangalore. SITAR (Society for Integrated Circuit Technology and Applied Research), Bangalore. Texas Instruments IC design center in Bangalore.

11. Related Experiments / projects:

i. ii. Designing a CMOS 16-Bit Parallel Adder Layout design of CMOS 4-Bit Ripple Counter

12. Evaluation Plan:

Sessional Examination I Sessional Examination II End Semester Examination Assignments / Quizzes / Tutorials 20% 20% 50% 10%

Prepared by

Verified by

Sriram Sundar.S

HoD/E.C.E (Dr.S.Durairaj)