Coding for to detect the sequence 110111 using VHDL: library ieee; use ieee.std_logic_1164.

all; entity seq_detector is port (x,clk,clr : in std_logic; z: out std_logic); end seq_detector; architecture detector of seq_detector is component my_dffbehavior port (d,clk,clr : in std_logic; q,qbar : inout std_logic); end component; signal d: std_logic_vector (1 to 3); signal y,yb: std_logic_vector (1 to 3); begin -- Excitation Input values for the flip-flops d(1) <= ( (y(2) and (not y(1)) and (not x)) or ((not y(2)) and (not y(1)) and x) ); d(2)<= ( (y(2) and (not y(1))) or (y(3) and y(1)) or ((not y(2)) and y(1) and x)); d(3) <= ( (y(2) and y(1) and x) or (y(3) and (not y(1)) and x)); -- Output of the flip-flops a1 : my_dffbehavior port map (d(1),clk,clr,y(1),yb(1)); a2 : my_dffbehavior port map (d(2),clk,clr,y(2),yb(2)); a3 : my_dffbehavior port map (d(3),clk,clr,y(3),yb(3)); -- Output function for the sequence detection z <= (y(3) and y(1) and x) after 1 ns; -- after 1 ns represents the delay to produce the output end detector;

Coding for the D Flip-Flop: library ieee; use ieee.std_logic_1164.all; entity my_dffbehavior is port (d,clk,clr : in std_logic; q,qbar : inout std_logic); end my_dffbehavior; architecture my_dffbehaviorarch of my_dffbehavior is begin process (d,clk,clr) begin if (clr = '1') then if (rising_edge (clk)) then q <= d; qbar <= not (d);

end if; else q <= '0'; qbar <= '1'; end if; end process; end my_dffbehaviorarch;

Coding for to detect the sequence 110111 using Verilog: module seq_detector (z,x,clk,reset); output z; input x,clk,reset; wire [1:8] t; -- To represent the minterms present in the flip-flop inputs wire [1:3] d; -- To represent the flip-flop excitation inputs wire [1:3]y; -- To represent the flip-flop true outputs wire [1:3]yb; -- To represent the flip-flop complement outputs wire xb; not g1(yb[1],y[1]); not g2(yb[2],y[2]); not g3(yb[3],y[3]); not g4(xb,x); and g5(t[1],y[2],yb[1],xb); and g6(t[2],yb[2],yb[1],x); and g7(t[3],y[3],y[1],xb); and g8(t[4],y[2],yb[1]); and g9(t[5],y[3],y[1]); and g10(t[6],yb[2],y[1],x); and g11(t[7],y[2],y[1],x); and g12(t[8],y[3],yb[1],x); or (d[1],t[1],t[2],t[3]); or (d[2],t[4],t[5],t[6]); or (d[3],t[7],t[8]); my_dffbehaviorvlog ff1 (y[1],yb[1],d[1],clk,reset); -- D1 flip-flop output my_dffbehaviorvlog ff2 (y[2],yb[2],d[2],clk,reset); -- D2 flip-flop output my_dffbehaviorvlog ff3 (y[3],yb[3],d[3],clk,reset); -- D3 flip-flop output and #10 (z,y[3],y[1],x); // delay '50'ns; -- Sequence Detector output endmodule -- t[1] to t[3] for D1 flip-flop minterms -- t[4] to t[6] for D2 flip-flop minterms -- t[7] to t[8] for D3 flip-flop minterms

-- Coding for the D Flip-Flop: module my_dffbehaviorvlog(q,qbar,d,clk,clr); output q,qbar;

input d,clk,clr; reg q,qbar; always @ (clr or negedge clk) begin if (~clr) begin q = 1'b0; qbar = 1'b1; end else begin q = d; assign qbar = ~q; end end endmodule