Sie sind auf Seite 1von 26

Computers & Problem Solving

Computer Project: ALUs and Karnaugh Maps

ENGI 1331H
de la Rosa-Pohl

University of Houston Diana de la Rosa-Pohl

Supplies
Brainpower (lots of it!)

de la Rosa-Pohl

Overview
1. Memory Review 2. Computer Architecture 3. Karnaugh Maps

de la Rosa-Pohl

MEMORY REVIEW
de la Rosa-Pohl

Memory Hierarchy
Hard Drive: mechanical magnetic slow cheap $ non-volatile huge Motherboard

RAM: on MBrd electrical fast $$ volatile SDRAM large

CPU Cache: on CPU electrical fast!! $$$ volatile SRAM small Registers: on CPU electrical fast!!! $$$$ volatile SRAM tiny

de la Rosa-Pohl

Sample Systems
Dell Computers
Low-end computers w/cache on CPU & Motherboard http://www.dell.com/content/topics/segtopic.asp x/inspironone?c=us&cs=19&l=en&s=dhs&~ck=mn
High-end computers w/all cache on CPU http://www.dell.com/us/p/alienware-area51alx/pd?refid=alienware-area-51-alx&~ck=mn
de la Rosa-Pohl

COMPUTER ARCHITECTURE
de la Rosa-Pohl

Computer Architecture
Simple ALU datapath

a = 1; b = 2 + 1; c = a + b;

de la Rosa-Pohl

Instruction Set Architecture (ISA)

The PIC microcontroller http://en.wikipedia.org/wiki/PIC_micro controller


de la Rosa-Pohl

Your ISA
See handout

de la Rosa-Pohl

KARNAUGH MAPS
de la Rosa-Pohl

Truth Table
1-bit Adder (a+b)

a
0 0

b
0 1

c
0 0

d
0 1

1 1

0 1

0 1

1 0

c
de la Rosa-Pohl

a b a b a b

1-bit Adder K-map


A

B
0

A
B 0
de la Rosa-Pohl

a 0 0 1 1

b 0 1 0 1

c 0 0 0 1

d 0 1 1 0

Truth Table
1-bit Subtractor (a-b)

a
0 0

b
0 1

c
0 1

d
0 1

1 1

0 1

0 0

1 0

c
de la Rosa-Pohl

a b a b a b

1-bit Subtractor K-map


A

B
0

A
B 0
de la Rosa-Pohl

a 0 0 1 1

b 0 1 0 1

c 0 1 0 0

d 0 1 1 0

Truth Table
1-bit Multiplier (a b)

a
0 0

b
0 1

c
0 0

d
0 0

1 1

0 1

0 0

0 1

de la Rosa-Pohl

c 0 d a b

1-bit Multiplier K-map


A

B
0

A
B 0
de la Rosa-Pohl

a 0 0 1 1

b 0 1 0 1

c 0 0 0 0

d 0 0 0 1

Truth Table
1-bit Divider (ab)

a
0 0

b
0 1

c
x 0

d
x 0

e
1 0

1 1

0 1

x 0

x 1

1 0

c
de la Rosa-Pohl

0 a b a b a b

d e

1-bit Divider K-map


A
B 0 0 1

a 0

b 0 1 0 1

c x 0 x 0

d x 0 x 1

e 1 0 1 0

1 A B 0 1 A B
de la Rosa-Pohl

0
0 1

1 1
0 1

0 1

K-map w/4 Input Variables


4-bit Counter
Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E F Outputs G H

de la Rosa-Pohl

K-map w/4 Input Variables


AB CD 00 00 01 11 10

01

11

10

de la Rosa-Pohl

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Inputs B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Output E 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

What about 5 Input Variables?!


Lets say you have input variables a-e and f is your output
4-variable K-map when e =0 4-variable K-map when e = 1

output

e (equations when e = 0) e(equations when e = 1)

de la Rosa-Pohl

But Wait!!!...What about 6 Input Variables?


Lets say you have input variables a-f
4-variable K-map when ef =00 4-variable K-map when ef = 01 4-variable K-map when ef = 10 4-variable K-map when ef = 11

output ef (equations when ef = 00) ef (equations when ef = 01) ef (equations when ef = 10)
de la Rosa-Pohl

ef (equations when ef = 11)

Introducingthe Multiplexer!
output ef (equations when ef = 00) ef (equations when ef = 01) ef (equations when ef = 10) ef (equations when ef = 11)

de la Rosa-Pohl

http://upload.wikimedia.org/wikipedia/commons/7/75/Multiplexer_4-to-1.svg

For Each Output Variable

de la Rosa-Pohl

de la Rosa-Pohl

Das könnte Ihnen auch gefallen