nTrace is a source code viewer and analyzer that operates on the KDB to display the design hierarchy and

source code (Verilog, VHDL, SystemVerilog, mi ed! "or selected design #loc$s% nTrace &uic$ly identi"ies signal connectivity in"ormation (drivers and loads! without any simulation overhead% 'ith the (SDB, the simulation results can #e #ac$)annotated in the source code and then nTrace can analyze and determine a signal*s active driver at a particular simulation time% Be"ore you #egin this tutorial, "ollow the instructions in the Be"ore +ou Begin chapter% ,e"er to the Launching Techni&ues chapter "or more in"ormation on starting the Verdi plat"orm and opening an nTrace window, which is the de"ault window% -lso re"er to the .ser /nter"ace chapter "or more details regarding the nTrace inter"ace%

nSchema is a schematic viewer and analyzer that generates interactive de#ug)speci"ic logic diagrams showing the structure o" selected portions o" a design% ,TL diagrams show the interconnection o" "inite state machines, storage elements, and multiple ers0 gate)level diagrams show the interconnection o" semiconductor vendor cells0 and special "lattened diagrams cut through the design hierarchy to isolate connected design elements% nSchema dynamically generate partial schematics to "ocus on the circuits o" interest within a large design% Be"ore you #egin this tutorial, "ollow the instructions in the Be"ore +ou Begin chapter% ,e"er to the .ser /nter"ace chapter "or general in"ormation on the nSchema "rame% The nSchema "rame is used to display auto)generated schematics and logical

diagrams, the "rame can #e undoc$ed to #e a standalone nSchema window, as shown in the e ample #elow1 nSchema generates the schematic "or #oth ,TL and gate)level designs% (or ,TL designs, the Verdi plat"orm e tracts certain types o" synthesizea#le "unction #loc$s "rom the HDL code, such as registers, latches, multiple ers, pure com#inatorial or se&uential circuits, etc% 'ith this capa#ility, you can get a clear picture o" the design intent, especially "or a design with which you are un"amiliar% -s "or gate)level designs, the Verdi plat"orm uses standard sym#ols, such as nand, nor, inverter, etc%, to ma$e the schematic more reada#le and understanda#le% To per"orm certain "unctions, such as signal tracing or intuitive searching, you can drag)and)drop items #etween windows to cross)lin$ the tools

n'ave is a state)o")the)art graphical wave"orm viewer and analyzer that is "ully integrated with the source code, schematic, and "low views o" the Verdi plat"orm% - wave"orm search engine com#ined with #ac$ward and "orward navigation allows you to search "or signal transitions, #us values, discrepancies, or userde"ined events easily% n'ave also o""ers "le i#le signal group management, usercustomiza#le glitch detection, a #uilt)in logic analyzer, logical operations, events, display o" delays #ac$)annotated "rom SD( "iles, mi ed analog2digital (-2D! display capa#ilities (including overlap, vertical zoom, delta and y,

arithmetic operations, analog) to)digital signal conversion, and others! and transaction2message display% Be"ore you #egin this tutorial, "ollow the instructions in the Be"ore +ou Begin chapter% ,e"er to the .ser /nter"ace chapter "or more details regarding the n'ave inter"ace% nState is a "inite state machine ((S3! viewer and analyzer that generates #u##le

diagrams "or visualization o" state machines that are automatically recognized #y the Verdi plat"orm when compiling the Verilog2VHDL source code modules% States and transitions are annotated with logic conditions and animated with simulation results% nState analyzes the simulation results to determine state and transition coverage% Be"ore you #egin this tutorial, "ollow the instructions in the Be"ore +ou Begin chapter% The Verdi plat"orm automatically recognizes any "inite state machines ((S3s!, and indicates them in nSchema #y means o" a sym#ol containing three lin$ed circles, as shown in the "igure #elow