Digital Electronics Lab Manual by M Shakeel

DIGITAL ELECTRONICS LAB MANUAL
ET-364(A)
FOR
rd
3 YEAR, DAE (ELECTRICAL)

PUNJAB BOARD OF TECHNICAL EDUCATION, LAHORE
NAME____________________________________
FATHERS NAME__________________________
ROLL NO__________________________________
BATCH_______2009-2012________
DEPATRMENT OF ELECTRICAL
Dr. ABDUL QADEER POLYTECHNIC

INSTITUTE
ELLAHABAD, 0494752820
DIGITAL ELECTRONICS LAB

DOS
1. Be regular to the lab.
2. Follow proper Dress Code.
3. Maintain Silence.
4. Know the theory behind the experiment
before coming to the lab.
5. Identify the different leads or terminals
or pins of the IC before making
Connection.
6. Know the Biasing Voltage required for
different families of ICs and connect the
power supply voltage and ground
terminals to the respective pins of the
ICs.
7. Know the Current and Voltage rating
of the ICs before using them in the
experiment.
8. Avoid unnecessary talking while doing
the experiment.
9. Handle the IC Trainer Kit properly.
10. Mount the IC Properly on the IC Zif
Socket.
11. Handle the microprocessor kit properly.
12. While doing the Interfacing, connect
proper voltages to the interfacing kit.
13. Keep the Table clean.
14. Take a signature of the In charge before
taking the kit/components.
15. After the completion of the experiments
switch off the power supply and return
the apparatus.
16. Arrange the chairs/stools and equipment
properly before leaving the lab.
.DON
TS
1. Do not exceed the voltage Rating.

2. Do not inter change the ICs while
doing the experiment.
3. Avoid loose connections and short

circuits.
4. Do not throw the connecting wires to

floor.
5. Do not come late to the lab.

6. Do not operate p/IC trainer kits
unnecessarily.
7. Do not panic if you dont get the

output
CONTENTS
Experiment No
Page. No
1. Verification of Gates
2. Half/Full Adder/Subtractor
3. Parallel Adder/Subtractor
4. 4-Bit Magnitude Comparator
12
5. MUX/DEMUX
13
6. Decoder and Encoder
15
7. BCD to Seven Segment Display
17
8. RS Flip-Flop
18
9. D Flip-Flops
19
10. JK Flip-Flops
20
11. Schmitt Trigger
21
12. Uses of IC555
22
13. Shift Registers
24
14. Counters
27
15. Memory Devices
30
16. 8085 Microprocessor
33
17. Project-1
18. Project-2
19. Project-3
Digital Electronics Lab Manual
The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken in
the centre). Each bus strip has two rows of contacts. Each of the two rows of
contacts are a node. That is, each contact along a row on a bus strip is connected
together (inside the breadboard). Bus strips are used primarily for power supply
connections, but are also used for any node requiring a large number of connections.
Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre
gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit
components into the contact receptacles and making connections with 22-26 gauge
wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good
practice to wire +5V and 0V power supply connections to separate bus strips.
Bus Strip
Often gap here
Terminal Strip
The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs
(Integrated circuits) used during the experiments. Incorrect connection of power to
the ICs could result in them exploding or becoming very hot - with the possible
serious injury occurring to the people working on the experiment! Ensure that the
power supply polarity and all components and connections are correct before
switching on power .
Building the Circuit
Throughout these experiments we will use TTL chips to build circuits. The steps for
wiring a circuit should be completed in the order described below:
1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to the power
and ground bus strips on your breadboard.
Page 1
4. Plug the chips you will be using into the breadboard. Point all the chips in
the same direction with pin 1 at the upper-left corner. (Pin 1 is often
identified by a dot or a notch next to it on the chip package)
5. Connect +5V and GND pins of each chip to the power and ground bus
strips on the breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire
between corresponding pins of the chips on your breadboard. It is better to
make the short connections before the longer ones. Mark each connection
on your schematic as you go, so as not to try to make the same connection
again at a later stage.
7. Get one of your group members to check the connections, before you turn
the power on.
8. If an error is made and is not spotted before you turn the power on. Turn
the power off immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips and
all equipment and return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition
as it was before you started.
Common Causes of Problems
1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the
circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.
In all experiments, you will be expected to obtain all instruments, leads, components
at the start of the experiment and return them to their proper place after you have
finished the experiment. Please inform the demonstrator or technician if you locate
faulty equipment. If you damage a chip, inform a demonstrator, don't put it back in
the box of chips for somebody else to use.
If you locate any errors in this manual, please e-mail:m_sh9t@yahoo.com
Example Implementation of a Logic Circuit
Build a circuit to implement the Boolean function F = / (/A. /B), please note that the
. You should use that notation during the write-up of your
notation /A refers to
laboratory experiments.
Quad 2 Input 7400
Hex 7404 Inverter
Page 2
The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small indented
circle above the first pin of the chip. Place your chips in the same direction, to save
confusion at a later stage. Remember that you must connect power to the chips to
get them to work.

Written by:
Muhammad Shakeel
Page 3

Experiment No: 1
VERIFICATION OF GATES
Date: __/__/____
Aim: - To study and verify the truth table of logic gates

Apparatus Required: -
All the gate ICs mention in the fig.
Procedure: -
1. Place the IC on IC Trainer Kit.

2. Connect VCC and ground to respective pins of IC Trainer Kit.
3. Connect the inputs to the input switches provided in the IC Trainer Kit.
4. Connect the outputs to the switches of O/P LEDs,
5. Apply various combinations of inputs according to the truth table and
Observe condition of LEDs.
6. Disconnect output from the LEDs and note down the corresponding
Multimeter voltage readings for various combinations of inputs.
2-Input AND Gate
74LS08
0
1
Y4
(V)
O/P
Y1
(V)
Y2
(V)
Y3
(V)
Y4
(V)
1
1
2-Input OR Gate
74LS32
Y3
(V)
4081
B
Y2
(V)
Y1
(V)
2-Input AND Gate
O/P
O/P
Y1
(V)
Y2
(V)
Y3
(V)
Y4
(V)
1
1
Page 4
2-Input OR Gate
A
4071
O/P
Inverter (NOT) Gate
Y2
(V)
Y3
(V)
Y4
(V)
Y1
(V)
74LS04
O/P Y1 Y2 Y3 Y4 Y4 Y4 Y4
(V) (V) (V) (V) (V) (V) (V)
Inverter (NOT) Gate

A
4009
O/P
Y1 Y2 Y3 Y4 Y4 Y4 Y4
(V) (V) (V) (V) (V) (V) (V)
0
1
2-Input NAND Gate

A
0
1
74LS00
O/P
Y3
(V)
Y4
(V)
Y2
(V)
Y3
(V)
Y4
(V)
Y2
(V)
2-Input NAND Gate
Y1
(V)
4011
O/P
Y1
(V)
1
1
Page 5
2-Input NOR Gate

A
74LS02
O/P
O/P
Y1
(V)
Y3
(V)
Y4
(V)
Y2
(V)
Y3
(V)
Y4
(V)
74LS86
O/P
Y1
(V)
2-Input XOR Gate
4030
O/P
Y1
(V)
Y2
(V)
Y3
(V)
Y4
(V)
Y2
(V)
Y3
(V)
Y4
(V)
1
1
2-Input XNOR Gate

A
Y2
(V)
4001
2-Input XOR Gate
Y4
(V)
Y3
(V)
2-Input NOR Gate
Y2
(V)
Y1
(V)
O/P
4077
Y1
(V)
1
1
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Conclusion:___________________________________________________________________
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Signature of the staff in charge
Page 7
Experiment No: 2
Date: __/__/____
HALF/FULL ADDER & HALF/FULL SUBTRACTOR
Aim: - To realize half/full adder and half/full Subtractor.

Apparatus Required: IC 74LS86, 74LS32, 74LS08, 74LS04 etc.
Procedure:1. Verify the Gates.

2. Make the connection as per circuit diagram.
3. Switch on VCC and apply various combinations of input according to the
Truth table.
4. Note down the output readings for half/full adder and half/full Subtractor
sum/difference and the carry/borrow bit for different combinations of inputs.
Logic Diagram of Half Adder
Truth Table
A
0
1
1
Sum Carry
0
1
Logic Diagram of Full Adder
Truth Table of full Adder
0
0
0
0
1
1
1
1
Inputs
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Outputs

Page 8
Logic Diagram of Half Subtractor
A
0
B
0
Logic Diagram of Full Subtractor
Di
1
1
Inputs
A
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
B
0
1
0
1
0
1
0
1
Outputs
Di
Conclusion:___________________________________________________________________
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Experiment No: 3
Date: __/__/____
Design and implementation of 4 bit binary Adder/ Subtractor:

Aim: - To design and implement 4 bit binary adder, 4 bit binary Subtractor and
adder/Subtractor using IC 7483.
Apparatus Required: IC 74LS83, 74LS86,74LS04
Procedure:1. Apply the Inputs to A1 to A4 and B1 to B4.

3. Switch on VCC and apply various combinations of input according to the
Truth table.
4. The truth tables of Adder, Subtractor and adder-Subtractor are noted down.
ICs Pin configuration
I
C
4
0
0
8
Adder
Page 10
Truth Table of Adder

A3
0
0
1
1
0
A2
0
1
0
1
1
A1
0
0
1
1
1
Subtractor:-
A0
1
1
0
1
1
B3
0
1
1
1
0
Truth Table of Subtractor

A3
0
0
0
1
1
A2
0
1
0
0
0
A1
1
0
1
1
0
A0
0
1
1
0
0
Adder / Subtractor
B3
0
0
0
0
1

B2
0
0
0
1
0
B1
1
1
1
1
1
B0
0
1
0
1
1
C4(V) S3(V) S2(V) S1(V) S0(V)
B2
0
0
1
1
1
B1
0
1
0
1
1
B0
1
1
1
0
1
C4(V) S3(V) S2(V) S1(V) S0(V)
Add=0
Subtract=1
Page 11
Truth Table of Adder / Subtractor

Input Data A
Input Data B
A4 A3 A2 A1 B4 B3 B2 B1 C out
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
0
1
1
Addition
S4 S3 S2
S1
Subtraction
Bout D4 D3 D2 D1
0
0
1
1
Conclusion:___________________________________________________________________
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Experiment No: 4
Date: __/__/____
4-bit magnitude comparator

Aim: - To Verify 4-bit magnitude comparator operation.
Apparatus Required: IC 74LS85
Procedure:1. Make the connection as per pin diagram of 74LS85 IC.

2. Switch on VCC and apply various inputs according to the function table.
3. Verify the output readings for different inputs according to function table.
Conclusion:___________________________________________________________________
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Experiment No: 5
Date: __/__/____
Multiplexer and De Multiplexer:

Aim: - To Verify truth table of Multiplexer and verify a De multiplexer.
Apparatus Required: IC 4514, 4515
Procedure:-

5. Switch on VCC and apply various inputs according to the Truth table.
6. Note down the output readings for Multiplexer and De Multiplexer.
8 input- Multiplexer
S0
S1
S2
0
0
0
1
1
1
1
1-16 line De Multiplexer
1
E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
O/P
Page 14
74LS139, 1 to 4 line De Multiplexer

G
0
0
0
0
1
1
0
1
Conclusion:___________________________________________________________________
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Experiment No: 6
Date: __/__/____
Decoder and Encoder

Aim: - To design and implement of Decoder and Encoder.
Apparatus Required: IC 4514, 45147
Procedure:-
1. Make the connection as per circuit diagram of 4514 shown in Experiment

No 5, for decoder circuit
2. Make the connection as per circuit diagram of 45147 given down for Encoder.
4. Note down the output readings for Decoder and Encoder.
Truth Table of Decoder:-
No
0
1
2
3
4
5
6
7
8
9
BCD inputs
A0 A1 A2
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H
L
L
H
L
L
A3
L
H
L
H
L
H
L
H
L
H
Decimal output
4
5
6
Encoder
Page 16
Truth Table of Encoder

Decimal Digit
0
1
2
3
4
5
6
7
8
9
BCD code
B
C
Conclusion:___________________________________________________________________
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Experiment No: 7
Date: __/__/____
BCD to Seven Segment Decoder

Aim: - To design and implement of BCD to seven segment Decoder.
Apparatus Required: IC 74LS47, seven segment display.
Procedure:-
1. Make the connection as per circuit diagram of 74LS47

3. Note down the output readings for Decoder using seven segment displays.
BCD to Seven segment Decoder/Driver
A0
0
0
0
0
0
0
0
0
1
1
A1
0
0
0
0
1
1
1
1
0
0
A2
0
0
1
1
0
0
1
1
0
0
A3
0
1
0
1
0
1
0
1
0
1
Digits a
0
1
2
3
4
5
6
7
8
9
Conclusion:___________________________________________________________________
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Experiment No: 8
Date: __/__/____
RS Flip Flop
Aim:- To Verify function of RS Flip-Flop.
Apparatus Required: IC 4043
Procedure:1. Make the connection as per circuit diagram.

3. Note down the output readings for RS Flip-Flop in truth table.
IC4043 Pin Diagram
Truth Table
Mode of
Operation
Conclusion:___________________________________________________________________
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Experiment No: 9
Date: __/__/____
D Flip Flop
Aim: - To Verify function of D Flip-Flop.
Apparatus Required: IC 4013

3. Note down the output readings for D Flip-Flop in truth table.
IC4013 Pin Diagram
Truth Table
CL
D
0
1
Conclusion:___________________________________________________________________
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Experiment No: 10
Date: __/__/____
JK Flip Flop
Aim: - To Verify function of JK Flip-Flop.
Apparatus Required: IC 4027 or 74LS76

3. Note down the output readings for JK Flip-Flop in truth table.
IC4027 Pin Diagram
CL J K
74LS76 Pin Diagram
Mode of
Operation
Conclusion:___________________________________________________________________
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Page 21
Experiment No: 11
Date: __/__/____
Schmitt Trigger
Aim: - To Verify function of Schmitt Trigger.
Apparatus Required: IC 4093 or 74LS13 or 74LS14

2. Switch on VCC and apply various inputs according to the circuit diagram.
3. Check the output wave form on oscilloscope.
IC4093Pin Diagram
Wave form
Conclusion:___________________________________________________________________
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Experiment No: 12
Date: __/__/____
Uses of IC 555
Aim: - To construct Astable and Monostable Multivibrator by using 555 timer
and Verify there functions.
Apparatus Required: IC 555 ,74LS13 or 74LS14

3. Check the output wave form on oscilloscope.
IC555 Pin Diagram
Circuit diagram of Astable 555 timer
In the astable timer, the out put voltage wave form is square wave. The width of this wave is
dependent on capacitor charging and discharging time. when the capacitor is charging the
output is high thats time period is:

When capacitor is discharging, output is low thats time period is:

and
Circuit diagram of Monostable 555 timer
In monostable timer, its output high for

several seconds or minutes when a
negative trigger pulse is applied on its
pin2.the time period of high output is
depend on capacitor charging time:

When capacitor charging complete, output
will low. Due to this resin this circuit is also
called one-short operation of 555 timer.
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Conclusion:___________________________________________________________________
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Experiment No: 13
Date: __/__/____
Shift Registers
Aim: - To Verify function of different shift resistors.
Apparatus Required: 74LS164 , 74LS65 ,4035

3. Check the output and note down in the truth table.
SIPO 74LS164
CLK
H
H
H
H
H
H
H
H
Serial
in
1
0
0
1
0
1
1
1
Conclusion:___________________________________________________________________
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PISO and SISO 74LS165
Conclusion:___________________________________________________________________
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PIPO 4035
Conclusion:___________________________________________________________________
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Experiment No: 14
Date: __/__/____
Counters
Aim: - To Verify function of different Counters.
Apparatus Required: 74LS164 , 74LS65 ,4035

3. Check the output and note down in the truth table.
74LS93, divide by 12 counter
74LS163, 4-bit synchronous counter
No. of
CP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Recycles)
Binary counting
sequence
Decimal
count
Page 28
74LS191, Synchronous 4-Bit Up/Down Counter with Mode Control
74LS197, 4-STAGE PRESETTABLE RIPPLE COUNTERS
Conclusion:___________________________________________________________________
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Experiment No: 15
Date: __/__/____
Memory Devices
Aim: - To study the function of different memory devices.
PIC12C67X EPROM Memory Programming Specification
1.0 PROGRAMMING THE

PIC12C67X AND PIC12CE67X
The PIC12C67X and PIC12CE67X can be programmed
using a serial method. In serial mode the
PIC12C67X and PIC12CE67X can be programmed
while in the users system. This allows for increased
design flexibility.
1.1 Hardware Requirements
The PIC12C67X and PIC12CE67X requires two programmable
power supplies, one for VDD (2.0V to 6.0V
recommended) and one for VPP (12V to 14V). Both
supplies should have a minimum resolution of 0.25V.
1.2 Programming Mode
The programming mode for the PIC12C67X and
PIC12CE67X allows programming of user program
memory, special locations used for ID, and the configuration
word for the PIC12C67X and PIC12CE67X.
24AA00 128 Bit I2C Bus Serial EEPROM
PIN DESCRIPTIONS
1. SDA Serial Data
This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open
Page 31
drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2. SCL Serial Clock
This input is used to synchronize the data transfer from

and to the device.
3. Noise Protection
The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
UVEPROM Built-in 8-bit single chip microcontroller
HM-6514 1024 x 4 CMOS RAM
Conclusion:___________________________________________________________________
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Experiment No: 16
Date: __/__/____
8085 Microprocessor
Aim: - To study the function of 8085 Microprocessor.
Address Bus:
The pins A8-A15 denote the address bus. They are used for the most significant bit of memory
address.
Address/Data Bus:
AD0-AD7 constitutes the Address/Data bus. They are time multiplexed. These pins are used for
least significant bits of address bus in the first machine clock cycle and used as data bus for
second and third clock cycle.
But what is a clock cycle? What is first clock cycle and second, third so on...
A clock cycle is nothing but the time taken between two adjacent pulses of the oscillator. In
simple words clock cycle refers to the transition between o volts to 5 volts and back to 0 volts. So
the first clock cycle means the first transition of pulse from 0volts to 5 volts and then back to 0
volts.
ALE: Address Latch Enable:
In the previous article we saw how ALE helps in demultiplexing the lower order address and data
bus. This signal goes high during the first clock cycle and enables the lower order address bits.
The lower order address bus is added to memory or any external latch.
IO/M:
Consider we have an address to be processed. But how do the processors know whether the
address is for memory or I/O functions? For this purpose a status signal called IO/M is used.
This distinguishes whether the address is for memory or IO. When this pin goes high, the address
is for an I/O device. While the pin goes low, the address is assigned for the memory.
S0-S1:
S0 and S1 are status signals which provides different status and functions depending on their
status.
Page 34
RD:
This is an active low signal. That is, an operation is performed when the signal goes low. This
signal is used to control READ operation of the microprocessor. When this pin goes low the
microprocessor reads the data from memory or I/O device.
WR:
WR is also an active low signal which controls the write operations of the microprocessor.
When this pin goes low, the data is written to the memory or I/O device.
READY:
READY is used by the microprocessor to check whether a peripheral is ready to accept or
transfer data. A peripheral may be a LCD display or analog to digital converter or any other.
These peripherals are connected to microprocessor using the READY pin. If READY is high
then the periphery is ready for data transfer. If not the microprocessor waits until READY goes
high.
HOLD:
This indicates if any other device is requesting the use of address and data bus. Consider two
peripheral devices. One is the LCD and the other Analog to Digital converter. Suppose if analog
to digital converter is using the address and data bus and if LCD requests the use of address and
data bus by giving HOLD signal, then the microprocessor transfers the control to the LCD as
soon as the current cycle is over. After the LCD process is over, the control is transferred back to
analog and digital converter.
HLDA:
HLDA is the acknowledgment signal for HOLD. It indicates whether the HOLD signal is
received or not. After the execution of HOLD request, HLDA goes low.
INTR:
INTR is an interrupt request signal. It has the lowest priority among the interrupts. INTR can be
enabled or disabled by using software. Whenever INTR goes high the microprocessor completes
the current instruction which is being executed and then acknowledges the INTR signal and
processes it.
INTA:
Whenever the microprocessor receives interrupt signal. It has to be acknowledged. This
acknowledgement is done by INTA. So whenever the interrupt is received INTA goes high.
RST 5.5, 6.5, 7.5:
These are nothing but the restart interrupts. They insert an internal restart function automatically.
All the above mentioned interrupts are maskable interrupts. That is, they can be enabled or
disabled using programs.
TRAP:
Among the interrupts of 8085 microprocessor, TRAP is the only non-maskable interrupt. It
cannot be enabled or disabled using a program. It has the highest priority among the interrupts.
PRIORITY ORDER (From highest to lowest)
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
RESET IN:
This pin resets the program counter to 0 and resets interrupt enable and HLDA flip-flops. The
CPU is held in reset condition until this pin is high. However the flags and registers wont get
affected except for instruction register.
RESET OUT:
This pin indicates that the CPU has been reset by RESET IN.
Page 35
X1 X2:
These are the terminals which are connected to external oscillator to produce the necessary and
suitable clock operation.
CLK:
Sometimes it is necessary for generating clock outputs from microprocessors so that they can be
used for other peripherals or other digital ICs. This is provided by CLK pin. Its frequency is
always same as the frequency at which the microprocessor operates.
SID:
This pin provides serial input data. The serial data on this pin is loaded into the seventh bit of the
accumulator when RIM instruction is executed.
RIM stands for READ INTERRUPT MASK, which checks whether the interrupt is masked or
not.
SOD:
This pin provides the serial output data. The serial data on this pin delivers its output to the
seventh bit of the accumulator when SIM instruction is executed.
Vcc and Vss:
Vcc is +5v pin and Vss is ground pin.
Thus the pin diagram and signals of 8085 microprocessor are explained in detail.
Conclusion:___________________________________________________________________
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Page 36
Project-1
Moving message display
Page 37

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DIGITAL ELECTRONICS LAB MANUAL

3 YEAR, DAE (ELECTRICAL)

Dr. ABDUL QADEER POLYTECHNIC

DIGITAL ELECTRONICS LAB

1. Do not exceed the voltage Rating.

3. Avoid loose connections and short

4. Do not throw the connecting wires to

5. Do not come late to the lab.

7. Do not panic if you dont get the

4. 4-Bit Magnitude Comparator

6. Decoder and Encoder

7. BCD to Seven Segment Display

11. Schmitt Trigger

12. Uses of IC555

13. Shift Registers

15. Memory Devices

16. 8085 Microprocessor

Digital Electronics Lab Manual

Often gap here

The breadboard. The lines indicate connected holes.

Building the Circuit

Digital Electronics Lab Manual

Quad 2 Input 7400

Hex 7404 Inverter

Digital Electronics Lab Manual

The complete designed and connected circuit

Digital Electronics Lab Manual

Digital Electronics Lab Manual

Aim: - To study and verify the truth table of logic gates

All the gate ICs mention in the fig.

1. Place the IC on IC Trainer Kit.

2-Input AND Gate

2-Input AND Gate

Digital Electronics Lab Manual

Inverter (NOT) Gate

Inverter (NOT) Gate

2-Input NAND Gate

2-Input NAND Gate

Digital Electronics Lab Manual

2-Input NOR Gate

2-Input XOR Gate

2-Input XNOR Gate

2-Input XOR Gate

2-Input NOR Gate

Digital Electronics Lab Manual

Signature of the staff in charge

Digital Electronics Lab Manual

HALF/FULL ADDER & HALF/FULL SUBTRACTOR

Aim: - To realize half/full adder and half/full Subtractor.

Procedure:1. Verify the Gates.

Logic Diagram of Full Adder

Truth Table of full Adder

Digital Electronics Lab Manual

Logic Diagram of Half Subtractor

Logic Diagram of Full Subtractor

Signature of the staff in charge

Digital Electronics Lab Manual

Design and implementation of 4 bit binary Adder/ Subtractor:

Procedure:1. Apply the Inputs to A1 to A4 and B1 to B4.

ICs Pin configuration

Digital Electronics Lab Manual

Truth Table of Adder

Truth Table of Subtractor

C4(V) S3(V) S2(V) S1(V) S0(V)