Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

EXPERIMENT NO.: 03 & 04 AIM OF THE EXPERIMENT: To design a Counter in Verilog HDL and implement it onto FPGA and to analyze the signals using ChipScope Pro Logic analyzer. REQUIREMENTS: 1. Computer 2. Xilinx ISE 13.1i VLSI Design Software 3. ChipScope Pro Analyzer from Xilinx 4. Spartan 3 Starter FPGA Board 5. 5 Volt DC Power Adapter for the FPGA Board 6. JTAG USB Cable

Theory: A typical FPGA Implementation flow is like the following:

Synthesis
Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA.

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Placement and Routing Place and route is a stage in the design of field-programmable gate arrays. As implied by the name, it is composed of two steps, Placement and Routing. The first step, Placement, involves deciding where to place all logic elements in a generally limited amount of space. This is followed by Routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process. FPGA Floor Plan In VLSI Design a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks. Pin Assignment using Constraint File (*.ucf) An Implementation constraint file is a mean to map the Actual pins of the FPGA to the input and output ports of the VHDL module we have designed. For Ximinx ISE it has the following format: Net PORT_NEME_1 Loc = Pin_Name_1; Net PORT_NEME_2 Loc = Pin_Name_2; For a better understanding, refer to the actual constraint file we have used in our project. Generation of configuration/Fuse File Once the VHDL code for the design has been written, i.e. the design entry part is done, Checked for any syntax error and if found rectified, simulated, synthesized and verified then after adding the implementation constraint file it is now time to generate the programming file, i.e. the actual file which will be downloaded into the FPGA, or we can say the FPGA will be configured as our Design. In other words the Hardware we were designing has now been implemented into the FPGA, i.e. the FPGA behaves as our Hardware. Programming the FPGA Device Once the Configuration file i.e. *.bit, has been generated it has to be downloaded into the FPGA by using certain Tools, i.e. IMPACT by Xilinx, or in our case since we are using a Digilent Board, a Tool by digilent known as Adept, can also be used for programming the FPGA device. Logic Analyser Once the Programming of the Device has been complete, the signals can be analysed using a Logic Analyser. In our case we will generate the logic analyser itself, in the Xilinx tool and view the Associated waveforms by ChipScope Pro, another tool by Xilinx.

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Procedure: 1. Create a new project with the following settings:

Project: Project Name: CounterInVerilog Description: Top Level Source Type: HDL Device: Device Family: Spartan3 Device: xc3s200 Package: ft256 Speed: -5 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISim (VHDL/Verilog) Preferred Language: Verilog 2. Create a new source, a Verilog Module and paste the following Code into it.
module counter( input rst, input clk, output [3:0] count ); reg [25:0] cnt; assign count[3:0] = cnt[25:22]; always @(posedge clk) begin if(rst) cnt <= 0; else cnt <= cnt + 1; end endmodule

3. Then create another source, i.e. an implementation constraint file (constraints.ucf) with the following mappings:
NET NET NET NET NET NET "count<0>" LOC = "count<1>" LOC = "count<2>" LOC = "count<3>" LOC = "clk" LOC = T9; "rst" LOC = L14; K12; P14; L12; N14;

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

In order to test the counter design we have to configure and insert the logic analyzer core in our design. Follow these steps: 4. In the New Source Wizard window, select ChipScope Definition and Connection File and specify the filename as debug. Click Next. 5. Now we have to associate this debug.cdc file with our desired top module. Thus select Counter from list of the modules. 6. Note that debug.cdc file has been added to your Sources list and is listed below the selected top module (Counter) in th Sources window. 7. Double click on debug.cdc to launch the ChipScope Pro Core Inserter application. This application will integrate the logic analyzer core into our counter design. Do not alter any settings on the first screen. Click Next.

8. To observe any signal, we have to specify the trigger. Logic analyzer core will start capturing the desired signal upon activation of trigger signal. In this example we want to monitor the counters counting action as soon as rst signal is deactivated. So we will create two trigger ports. One port will be rst signal and another port will be counters eight least significant bits. Set Number of trigger ports to 2. In TRIG0 frame set Trigger Width as 1 (since rst is one bit signal). In TRIG1 frame set Trigger Width as 8 (as we want to observe counters 8 least significant bits). Click Next. 9. Now in this window we will specify capture parameters. We want to use our trigger ports as data ports which will be recorded by logic analyzer. We also want to sample data on rising clock edge. In Sample On list select Rising. Set Number of samples to be recorded by changing Data Depth to 1024 samples. This will record 1024 samples from the trigger event. You can at the most record 16K samples. Select both check boxes in Trigger Ports Used As Data frame.

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Click Next.

10. Now we will specify which signal(s) to be used as Clock and Trigger. Click on Modify Connections. 11. Select the Clock signals Pane, then select clk_BUFG signal from the left hand side list and then click on Make Connection. This will add clk signal as the clock signal for logic analyzer. 12. Now select Trigger/Data signals pane. Select TP0 and connect rst_IBUF signal to CH0 channel. 13. Similarly click on TP1 pane and add connect counters lowe eight bits to eight channels. Click OK once you finish making connections. 14. Now in the main window click on Return to Project Navigator. It will ask for saving the project, click Yes. 15. Now we are ready to compile the entire counter design along with the logic analyzer core. 16. In the ISE, select top level module cntr and in the Processes pane double click on Analyze Design Using ChipScope. This will start the process to synthesize combined unit consisting of design under test (in this case counter) and the chipscope cores.

Debugging the design using ChipScope Analyzer tool:

Once the synthesis gets over, ISE will launch the Analyzer tool. Make sure that FPGA board is connected to PC. 17. Once the analyzer tool is running, click on Initialize JTAG Chainicon located at the top right corner of the window. This will initialize the JTAG chain and identify the devices found in the chain. A dialog box will appear showing the devices discovered. Click OK. 18. Now select the FPGA device from the JTAG chain, right click and then select Configure to specify the configuration bit stream file. 19. Select the bit stream file counter.bit from the bit stream folder. Then click OK.

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

20. IMPORTANT: After clicking OK, tool will load the bit stream file into FPGA and check the availability of debugging cores. If debugging core is found tool will show INFO: Found 1 Core Unit in the JTAG device Chain. Message in status window.

21. If you see Found 0 Core message instead, then either you have selected wrong bit stream file or something has gone wrong in one of the previous steps and debugging core has not been inserted properly into the design.

22. If everything is fine then you will see options for Logic Analyzer core inserted in our design. Now double click on the Trigger Setup element to launch trigger setup window. And for trigger port 0 (i.e. rst signal) specify the trigger Value 0. 23. This will make logic analyzer to trigger as soon as rst become zero and record 1024 samples on successive clock edges. Note that trigger signals are sampled on rising clock edge.

24. Double click on Waveform element to see the waveform.

25. Now everything is ready. To apply the settings and ARM the trigger click on the Play button. After that press the Down button on the development board to release the rst signal. This will trigger the logic analyzer. Once 1024 samples are recorded, this data will be transferred to PC and will be displayed in the waveform window. 26. Final data is uploaded on PC and displayed in waveform window.

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Purushottam Institute of Engineering & Technology Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering