telegraph

Papyrus scroll

Through the years,

man has always felt
the need to communicate ...
The struggle to defy time and space...
 Computer-Aided Design and
Manufacturing

Automobile assembly
line

The quest to make things easier ...

 phones

The quest to make

things better . . .
computers
And at the heart of these systems ...
 smaller than the
Is a microchip ... fingertip?
The POWER of

VLSI
VLSI is the art of integrating millions and
millions of transistors on a single die of
Silicon.

Its an ART, ART,

ART……
 Moore in 1969 stated that
silicon technology will
double number of
transistor’s every 18
months.

Moore’s Law…
And its really
happening !!!
The transistor was probably the
most important invention of the
20th Century…
ENIAC The first electronic
computer (1946)
Intel 4004 Micro-
Processor
Intel Pentium II Micro-
Processor
Intel Pentium III Micro-
Processor
Intel Pentium (IV) Microprocessor
Wafer Containing P-III
manufactured using the
0.13 micron process
technology.
 VLSI (Very large-scale integrated circuit) it is a
level of integration.
 There are different level of integration VLSI is
one of them.
 Level of integration Number of Gate/chip
SSI 2-20
MSI 20-200
LSI 200-2000
VLSI 2000 +
WHERE TO GO AFTER VLSI?

 ULSI (Ultra Large Scale Integration )

 GSI (Gigantic Scale Integration)

Who knows the next step? Maybe:

 UBSI (Unbelievably Big Scale Integration)
 VLSI Applications
♦ VLSI is an implementation technology for electronic circuitry
- analogue or digital
♦ It is concerned with forming a pattern of interconnected
switches and gates on the surface of a crystal of semiconductor
♦ Microprocessors
– personal computers
– microcontrollers
♦ Memory - DRAM / SRAM
♦ Special Purpose Processors - ASICS (CD players, DSP
applications)
♦ Optical Switches
♦ Has made highly sophisticated control systems mass-
producible and therefore cheap
PARAMETER’S FOR DESIGNER

 SPEED…..
 AREA…
 POWER…………
 COST…….
The advantageous of digital ICs
over the discrete components
♦ Size
– much smaller both transistor and wires.
– leads to smaller parasitic resistances,
capacitances and inductances
♦ Speed
– communication within the chips are much faster
than between a chips on PCB.
– High speed of circuits on-chip due to smaller
size.
The advantageous of digital ICs
over the discrete components
♦ Power Consumption
– Logic operation within
the chip consumes muc
h less power.
– smaller size -> smaller
parasitic capacitances a
nd resistance -> require
less power to drive the
circuit.
Advantages of IC at System
Level
♦ Smaller Physical Size
– can make a small electronic appliances. ie.
portableTV, handheld cellular telephone…
♦ Lower Power Consumption
– reduce total power consumption on a whole
electronic circuit.
– cheaper power supply which leads to a simpler
cabinet for power supply. Less heat, Fan may n
o longer be necessary.
Advantages of IC at System
Level
♦ Reduce Cost
– Reducing in number of components.
– Power Supply requirement.
– Cabinets
– The cost of building a whole system is reduce
eventhough Ics cost more.
Scaling
♦ The process of shrinking the layout in
which every dimension is reduced by a
factor is called Scaling.
♦ Transistors become smaller, less resistive,
faster, conducting more electricity and
using less power.
♦ Designs have smaller die sizes, higher yield
and increased performance.
Can Scaling Continue?
♦ Scaling work well in the past:
Year 1989 1992 1995 1997 1999 2001
Technology
(µm) 0.65 0.5 0.35 0.25 0.18 0.15

♦ In order to keep scaling work in the future,

many technical problems need to be solved.
Can Scaling Continue?
♦ Some characteristics of the transistors do
not scale uniformly, e.g., delay, leakage
current, threshold voltage, etc.
♦ Mismatch in the scaling of transistors and
interconnects. Interconnect delay has
increased from 5-10% of the overall delay
to 50-70%.
Technology Background
What is a Silicon Chip?
♦ A pattern of interconnected switches and gates on the
surface of a crystal of semiconductor (typically Si)
♦ These switches and gates are made of
– areas of n-type silicon
– areas of p-type silicon
– areas of insulator
– lines of conductor (interconnects) joining areas together
• Aluminium, Copper, Titanium, Molybdenum,
polysilicon, tungsten
♦ The geometry of these areas is known as the layout of the
chip
♦ Connections from the chip to the outside world are made
around the edge of the chip to facilitate connections to
other devices
Switches
♦ Digital equipment is largely composed of switches
♦ Switches can be built from many technologies
– relays (from which the earliest computers were built)
– thermionic valves
– transistors
♦ The perfect digital switch would have the following:
– switch instantly
– use no power
– have an infinite resistance when off and zero resistance when on
♦ Real switches are not like this!
 Semiconductors and Doping
♦ Adding trace amounts of certain materials to
semiconductors alters the crystal structure and can change
their electrical properties
– in particular it can change the number of free electrons or holes
♦ N-Type
– semiconductor has free electrons
– dopant is (typically) phosphorus, arsenic, antimony
♦ P-Type
– semiconductor has free holes
– dopant is (typically) boron, indium, gallium
♦ Dopants are usually implanted into the semiconductor
using Implant Technology, followed by thermal process to
diffuse the dopants.
IC Technology
♦ Speed / Power performance of available
technologies
♦ The microelectronics evolution
♦ SIA Roadmap
♦ Semiconductor Manufacturers 2001
Ranking
 SILICON

MOS TECHNOLOGY BIPOLAR TECHNOLOGY

TTL
NMOS ECL
PMOS LVTTL
CMOS
Metal-oxide-semiconductor
(MOS) and related VLSI
technology
♦ pMOS
♦ nMOS
♦ CMOS
♦ BiCMOS
♦ GaAs
Basic MOS Transistors
♦ Minimum line width
♦ Transistor cross section
♦ Charge inversion channel
♦ Source connected to substrate
♦ Enhancement vs Depletion mode devices
♦ pMOS are 2.5 time slower than nMOS due
to electron and hole mobilities
Fabrication Technology
♦ Silicon of extremely high purity
– chemically purified then grown into large crystals
♦ Wafers
– crystals are sliced into wafers
– wafer diameter is currently 150mm, 200mm, 300mm
– wafer thickness <1mm
– surface is polished to optical smoothness
♦ Wafer is then ready for processing
♦ Each wafer will yield many chips
– chip die size varies from about 5mmx5mm to
15mmx15mm
– A whole wafer is processed at a time
Fabrication Technology
♦ Different parts of each die will be made P-
type or N-type (small amount of other
atoms intentionally introduced - doping
-implant)
♦ Interconnections are made with metal
♦ Insulation used is typically SiO2. SiN is
also used. New materials being investigated
(low-k dielectrics)
Fabrication Technology
♦ nMOS Fabrication
♦ CMOS Fabrication
– p-well process
– n-well process
– twin-tub process
 Fabrication Technology
♦ All the devices on the wafer are made at the same time
♦ After the circuitry has been placed on the chip
– the chip is over glassed (with a passivation layer) to
protect it
– only those areas which connect to the outside world
will be left uncovered (the pads)
♦ The wafer finally passes to a test station
– test probes send test signal patterns to the chip and
monitor the output of the chip
♦ The yield of a process is the percentage of die which pass
this testing
♦ The wafer is then scribed and separated up into the
individual chips. These are then packaged
♦ Chips are ‘binned’ according to their performance
CMOS Technology
♦ First proposed in the 1960s. Was not seriously considered
until the severe limitations in power density and
dissipation occurred in NMOS circuits
♦ Now the dominant technology in IC manufacturing
♦ Employs both pMOS and nMOS transistors to form logic
elements
♦ The advantage of CMOS is that its logic elements draw
significant current only during the transition from one state
to another and very little current between transitions -
hence power is conserved.
♦ In the case of an inverter, in either logic state one of the
transistors is off. Since the transistors are in series, (~ no)
current flows.
♦ See twin-well cross sections
 BiCMOS
♦ A known deficiency of MOS technology is its limited load driving
capabilities (due to limited current sourcing and sinking abilities of
pMOS and nMOS transistors.
♦ Bipolar transistors have
– higher gain
– better noise characteristics
– better high frequency characteristics
♦ BiCMOS gates can be an efficient way of speeding up VLSI circuits
♦ CMOS fabrication process can be extended for BiCMOS
♦ Example Applications
– CMOS - Logic
– BiCMOS - I/O and driver circuits
– ECL - critical high speed parts of the system
MOSFET (Metal oxide semiconductor
field effect transistor)
 This transistor consist of three regions, labeled
source, gate and drain.
 If the source and drain regions are doped with N-
type material and substrate with P-type then it is
called as N-channel MOSFET.
 If the source and drain regions are doped with P-
type material and substrate with N-type then it is
called as P-channel MOSFET.
NMOS
 Majority carrier = electrons
 A positive voltage applied on the gate w.r.t (with
respect to) the substrate enhances the number of
electrons in the channel, and hence increases the
conductivity of the channel.
 If gate voltage is less than a threshold voltage Vt,
the channel is cut-off (very low current between
source & drain).
NMOS
GATE

INPUT = 0 INPUT = 1

OUTPUT=0 OUTPUT=1
PMOS
 Majority carrier = holes
 Applied voltage is negative w.r.t substrate.
PMOS
GATE

INPUT = 1 INPUT = 0

OUTPUT=0 OUTPUT=1
CMOS
 Challenge: build both NMOS and PMOS on a
single silicon chip
 NMOS needs a p-type substrate
 PMOS needs an n-type substrate
 But we can build in the same substrate by
changing doping type
CMOS

 CMOS can be expressed as a pull-up network

(consisting of p-channel MOS transistors, and
connected to Vdd) and a pull-down network
(consisting of n-channel transistors, and connected
to ground).
 Pull-up network and pull-down network are
complementary to each other.
 The output of this circuit has to be taken between
this two network.
CMOS

PULL UP
OUTPUT
INPUT

PULL
DOWN
CMOS INVERTER
VDD

INPUT OUTPUT
CMOS NAND GATE
VDD

B
CMOS NAND SWITCH MODEL
CLASSIFICATION OF VLSI
DESIGNS
 Analog Design
 ASIC’s (Application specific Integrated Circuit)
Design
 SOC (System on chip)
BASIC TYPES OF
PROGRAMMABLE LOGIC
 Simple Programmable Logic Devices(SPLDs)
 Complex Programmable Logic Devices(CPLDs)
 Field Programmable Gate Arrays (FPGAs)
ADVANTAGE OF
PROGRAMMABLE LOGIC
 Saves valuable board space and debug time.
 Requires less switching current and switching
o/p s.
 Faster time to market.
VLSI DESIGN FLOW
Design flow based on
 Specification: function, cost, etc.
 Architecture: large blocks.
 Logic: gates and registers.
 Circuits: transistor sizes for speed, power.
 Layout:
o Layout size determines fabrication cost.
o Determines parasitic; hence the circuit speed and
power.
VLSI DESIGN FLOW

SPECIFICATIO
N

ALGORITHM
DESIGN

DESIGN ENTRY

FUNCTIONAL
SIMULATION
CMOS Processing &
Fabrication
N Transistor Structure Review

Polysilicon Gate
SiO2
Insulator L D D
W
Source Drain
G SB G
n+ n+
channel

p substrate S S
substrate connected
n transistor to GND
 P Transistor Structure Review

Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel

n substrate S substrate connected
to VDD

p transistor
 Semiconductor Review
♦ Create by doping a pure silicon crystal
– Diffuse impurity into crystal lattice
– Changes the concentration of carriers
• Electrons
• Holes
– More doping -> more carriers available
n+
n
♦ n-type semiconductor (n or n+)
– Majority carrier: electrons
– Typical impurity: Arsenic (Column V) p+

♦ p-type semiconductor (p or p+)

– Majority carrier: holes
– Typical impurity: Boron (Column III)
Other key working materials
♦ Insulator - Silicon Dioxide (SiO2)
– Used to insulate transistor gates (thin oxide)
– Used to insulate layers of wires (field oxide)
– Can be grown on Silicon or Chemically Deposited
♦ Polysilicon - polycrystalline silicon
– Key material for transistor gates
– Also used for short wires
– Added by chemical deposition
♦ Metal - Aluminum (…and more recently Copper)
– Used for wires
– Multiple layers common
– Added by vapor deposition or “sputtering”
CMOS Processing
♦ Wafer Processing
♦ Photolithography
♦ Oxide Growth & Removal
♦ Material Deposition & Removal
♦ Diffusion of Impurities
♦ Putting it all together
A View of the Cleanroom

AMD’s Dresden Fab - Source: AMD Corporation www.amd.com

Creating Wafers - Czochralski
Method
♦ Start with crucible of
molten silicon
(≈1425oC)
♦ Insert crystal seed in
Molten
melt Crucible Silicon
♦ Slowly rotate / raise
seed to form single
crystal boule
♦ After cooling, slice
boule into wafers &
polish
 Definitions
♦ Wafer – a thin circular silicon
♦ Each wafer holds hundreds of dies
♦ Transistors and wiring are made from many layers
(usually 10 – 15) built on top of one another
– the first half-dozen or so layers define transistors
– the second define the metal wires between transistors
♦ Lambda (λ) – the smallest resolvable feature 
size imprinted on the IC; 
it is roughly half the length of the smallest 
transistor
– 0.2µm IC – the smallest transistors are
approximately 0.2µm in length (λ= 0.1µm)
Wafer Structure
♦ Current production:
200mm (10”)
♦ Newest technology:
300mm (12”)
Die ­ Single IC chip

300mm wafer
Image Source: Intel Corporation
Processing Wafers
♦ All dice on wafer processed simultaneously
♦ Each mask has one image for each die
♦ The basic approach:
– Add & selectively remove materials
• Metal - wires
• Polysilicon - gates
• Oxide
– Selectively diffuse impurities
♦ Photolithography is the key
Fabrication processes
♦ IC built on silicon substrate:
– some structures diffused into substrate;
– other structures built on top of substrate.
♦ Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
♦ Wires made of polycrystalline silicon
(poly), multiple layers of aluminum (metal).
♦ Silicon dioxide (SiO2) is insulator.
Photolithography
♦ Coat wafer with
photoresist (PR)
♦ Shine UV light through
mask to selectively
expose PR UV Light
Mask
♦ Use acid to dissolve Photoresist

exposed PR Wafer

♦ Now use exposed areas

for
– Selective doping
– Selective removal of
material under exposed
PR
Adding Materials
♦ Add materials on top of
Added Material 
silicon (e.g. Polysilicon)
– Polysilicon
– Metal
– Oxide (SiO2) - Insulator Silicon

♦ Methods
– Chemical deposition
– Sputtering (Metal ions)
– Oxidation
Oxide (Si02) - The Key Insulator
♦ Thin Oxide
– Add using chemical deposition
– Used to form gate insulator & block active areas
♦ Field Oxide (FOX) - formed by oxidation
– Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
– Used to insulate non-active areas SiN / SiO2

FOX FOX
SiO2 Thin Oxide

Silicon Wafer Silicon Wafer
Patterning Materials using
Photolithography
♦ Add material to wafer
Added Material 
♦ Coat with photoresist (e.g. Polysilicon)

♦ Selectively remove
photoresist
Silicon
♦ Remove exposed
material
♦ Remove remaining PR
Diffusion
♦ Introduce dopant via
epitaxy or ion implant Blocking Material 
e.g. Arsenic (N), (Oxide)

Boron (P)
Diffusion
♦ Allow dopants to
diffuse at high
temperature Silicon

♦ Block diffusion in
selective areas using
oxide or PR
♦ Diffusion spreads both
vertically, horizontally
CMOS Well Structures
♦ Need to accommodate both N, P transistors
♦ Must implement in separate regions - wellls
(tubs)
– N-well
– P-well
♦ Alternate approach: Silicon on Insulator
(SOI)
n well p well n epi p epi
p substrate n substrate n tub p tub insulator
n­well p­well twin­tub SOI
Detailed View - N-Well Process
♦ Overall chip doped as p substrate, tied to
GND
♦ Selected well areas doped n, tied to VDD

Gnd VDD

n+ n+ p+ p+
channel channel

p substrate n well
CMOS Processing - Creating an
Inverter
♦ Substrate
♦ Well
♦ Active
Areas
♦ Gates
♦ Diffusion
♦ Insulator
n well
P substrate
♦ Contacts wafer

♦ Metal
CMOS Mask Layers
♦ Determine placement
of layout objects
♦ Color coding specifies
layers
♦ Layout objects:
– Rectangles
– Polygons
– Arbitrary shapes
n well
♦ Grid types P substrate
wafer
– Absolute (“micron”)
– Scaleable (“lambda”)
Mask Generation
♦ Mask Design using Layout Editor
– user specifies layout objects on different layers
– output: layout file
♦ Pattern Generator
– Reads layout file
– Generates enlarged master image of each mask layer
– Image printed on glass reticle
♦ Step & repeat camera
– Reduces & copies reticle image onto mask
– One copy for each die on wafer
– Note importance of mask alignment
 Simple cross section

SiO2 metal3

metal2

metal1
transistor via

poly
n+ n+
p+
substrate
substrate
Transistor structure
n-type transistor:
 0.25 micron transistor (Bell
Labs)

gate oxide

silicide

source/drain

poly
Metal Layers
Current Trends in Fabrication
♦ Copper Interconnect
♦ Low-k dielectric for interconnect
♦ High-k dielectric for transistor gates
♦ Optical problems (and attempted fixes)
Copper interconnect
♦ Copper is a much better conductor than aluminum
♦ But, it tends to chemically react w/ silicon, oxide
♦ Fabrication of copper wires: “damascene” process
– Etch trenches in the surface where wires will be placed
– Coat with “secret chemical” (isolates Cu, silicon, oxide)
– Coat with layer of copper
– Polish wafer to remove copper except in trenches
Alternative Dielectrics
♦ Dielectric constant of SiO2: 3.9
♦ Problem: want to minimize coupling
capacitance between wires
– Solution: “low-k” dielectrics (featured in
130nm and below)
– Proposed materials would have approx K=3
♦ Problem: want to maximize electric field
under transistor gates
– Solution: “high-k” dielectrics (anticipated in
90nm and below)
– Proposed materials would have K>>4
Optical Problems
♦ Most photolithography is done using UV
with 248nm wavelength
♦ BUT… current geometries << 248nm =>
interference problems
♦ Fixes:
– Optical proximity correction (OPC)
– Phase-shifting masks
– Other light sources: 193nmUV, Extreme UV,
X-Rays
• E-beam lithography
Example - Phase Shifting Masks
♦ Normal mask - light spreads & overlaps
♦ Phase shifting mask - cancels overlap
♦ Drawback: requires 2 masks per litho. step
(Expensive)

Graphic source: Numerical Technologies

 After Fabrication- Testing and
Packaging

Figure Source: D. Patterson and J. Hennessey, Computer Organization and Design, Morgan Kafumann, 1996
 Jobs in VLSI
♦ Layout designers
♦ Circuit designers
♦ Architects
♦ Test engineers
♦ Fabrication engineers
♦ System designers
♦ CAD tool programmers
Thank you very much