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CY62256N

256-Kbit (32 K 8) Static RAM


256-Kbit (32 K 8) Static RAM

Features

Functional Description
The CY62256N is a high performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9 percent when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.

Temperature ranges Commercial: 0 C to +70 C Industrial: 40 C to +85 C Automotive-A: 40 C to +85 C Automotive-E: 40 C to +125 C High speed: 55 ns Voltage range: 4.5 V to 5.5 V operation Low active power 275 mW (max) Low standby power (LL version) 82.5 W (max) Easy memory expansion with CE and OE Features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed and power Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP, 28-pin (300-mil) narrow SOIC, 28-pin TSOP I, and 28-pin reverse TSOP I packages

Logic Block Diagram

INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER

I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5

32K x 8 Y ARRA

COLUMN DECODER

POWER DOWN

I/O6 I/O7

Cypress Semiconductor Corporation Document Number: 001-06511 Rev. *G

198 Champion Court

San Jose, CA 95134-1709 408-943-2600 Revised September 13, 2013

CY62256N
Contents
Product Portfolio .............................................................. 3 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Typical DC and AC Characteristics .............................. 10 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17

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CY62256N

Product Portfolio
Product Min CY62256NLL Commercial CY62256NLL Industrial CY62256NLL Automotive-A CY62256NLL Automotive-E 4.5 VCC Range (V) Typ
[1]

Power Dissipation Speed (ns) Max 5.5 70 55/70 55/70 55 Operating, ICC (mA) Typ
[1]

Standby, ISB2 (A) Typ[1] 0.1 0.1 0.1 0.1 Max 5 10 10 15

Max 50 50 50 50

5.0

25 25 25 25

Pin Configurations
Figure 1. 28-pin DIP and Narrow SOIC pinout Figure 2. 28-pin TSOP I and Reverse TSOP I pinout

Pin Definitions
Pin Number 110, 21, 2326 1113, 1519, 27 20 22 14 28 Type Input Input/Output A0A14. Address Inputs I/O0I/O7. Data lines. Used as input or output lines depending on operation Description

Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins Ground GND. Ground for the device Power Supply VCC. Power supply for the device

Note 1. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.

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CY62256N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ 65 C to +150 C Ambient temperature with power applied .......................................... 55 C to +125 C Supply voltage to ground potential (pin 28 to pin 14) ..........................................0.5 V to +7.0 V DC voltage applied to outputs in high Z State [2] ................................ 0.5 V to VCC + 0.5 V DC input voltage [2] ............................. 0.5 V to VCC + 0.5 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Latch-up current ................................................... > 200 mA

Operating Range
Range Commercial Industrial Automotive-A Automotive-E Ambient Temperature (TA) [3] 0 C to +70 C 40 C to +85 C 40 C to +85 C 40 C to +125 C VCC 5 V 10% 5 V 10% 5 V 10% 5 V 10%

Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current GND VI VCC GND VO VCC, output disabled VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC LL - Commercial LL - Industrial LL - Automotive-A LL - Automotive-E ISB1 Automatic CE power-down current TTL inputs Automatic CE power-down current CMOS inputs Max. VCC, CE VIH, LL - Commercial VIN VIH or VIN VIL, LL - Industrial f = fMAX LL - Automotive-A LL - Automotive-E ISB2 Max. VCC, LL - Commercial CE VCC 0.3 V, LL - Industrial VIN VCC 0.3 V, or VIN 0.3 V, f = 0 LL - Automotive-A LL - Automotive-E Test Conditions VCC = Min, IOH = 1.0 mA VCC = Min, IOL = 2.1 mA -55 Min 2.4 2.2 0.5 0.5 0.5 Typ [4] 25 25 25 0.3 0.3 0.3 0.1 0.1 0.1 Max 0.4 VCC + 0.5 0.8 +0.5 +0.5 50 50 50 0.5 0.5 0.5 10 10 15 Min 2.4 2.2 0.5 0.5 0.5 -70 Typ [4] 25 25 25 0.3 0.3 0.3 0.1 0.1 0.1 Max 0.4 VCC + 0.5 0.8 +0.5 +0.5 50 50 50 0.5 0.5 0.5 5 10 10 Unit V V V V A A mA mA mA mA mA mA mA mA A A A A

Notes 2. VIL (min) = 2.0 V for pulse durations of less than 20 ns. 3. TA is the Instant-On case temperature. 4. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.

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CY62256N

Capacitance
Parameter [5] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max 6 8 Unit pF pF

Thermal Resistance
Parameter [5] JA JC Description Test Conditions DIP 75.61 43.12 SOIC 76.56 36.07 TSOP 93.89 24.64 RTSOP 93.89 24.64 Unit C/W C/W Thermal resistance Still air, soldered on (junction to ambient) a 4.25 1.125 inch, 4-layer printed Thermal resistance circuit board (junction to case)

AC Test Loads and Waveforms


Figure 3. AC Test Loads and Waveforms
5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990 R1 1800 R1 1800 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 990 3.0 V GND 10% ALL INPUT PULSES 90% 90% 10% < 5 ns

5 ns

(a)

(b)
Equivalent to: TH VENIN EQUIVALENT 639 OUTPUT 1.77 V

Note 5. Tested initially and after any design or process changes that may affect these parameters.

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CY62256N

Data Retention Characteristics


Parameter VDR ICCDR Data retention current Description VCC for data retention LL Commercial LL Industrial/ Automotive-A LL Automotive-E tCDR tR[7]
[7]

Conditions [6] VCC = 2.0 V, CE VCC 0.3 V, VIN VCC 0.3 V, or VIN 0.3 V

Min 2.0 0

Typ [7] 0.1 0.1 0.1

Max 5 10 10

Unit V A A A ns ns

Chip deselect to data retention time Operation recovery time CY62256NLL-55 CY62256NLL-70

55 70

Data Retention Waveform


Figure 4. Data Retention Waveform
DATA RETENTION MODE VCC CE 3.0 V tCDR VDR 2 V 3.0 V tR

Notes 6. No input may exceed VCC + 0.5 V. 7. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.

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CY62256N

Switching Characteristics
Over the Operating Range Parameter [8] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z CE LOW to low Z
[9] [9, 10]

Description

CY62256N-55 Min 55 5 5 5 0 55 45 45 0 0 40 25 0 5 Max 55 55 25 20 20 55 20

CY62256N-70 Min 70 5 5 5 0 70 60 60 0 0 50 30 0 5 Max 70 70 35 25 25 70 25

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

OE HIGH to high Z

[9]

CE HIGH to high Z [9, 10] CE LOW to power-up CE HIGH to power-down


[11, 12]

Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z [9, 10] WE HIGH to low Z
[9]

Notes 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 10. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 11. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 12. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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CY62256N

Switching Waveforms
Figure 5. Read Cycle No. 1 [13, 14]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID

Figure 6. Read Cycle No. 2 [14, 15]


CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD ICC 50% ISB tHZOE tHZCE tRC

HIGH IMPEDANCE

Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW.

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CY62256N
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [16, 17, 18]
tWC ADDRESS

CE tAW WE tSA tPWE tHA

OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD

Figure 8. Write Cycle No. 2 (CE Controlled) [16, 17, 18]


tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATA IN VALID tHD tHA tSCE

Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [18, 20]


tWC ADDRESS

CE tAW WE tSA tHA

tSD DATA I/O NOTE 19 tHZWE DATA IN VALID

tHD

tLZWE

Notes 16. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied. 20. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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CY62256N

Typical DC and AC Characteristics


1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN = 5.0V TA = 25C NORMALIZED ICC ICC NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 ISB2 A 0.8 0.6 0.4 0.2 0.0 55 25 125 VCC = 5.0V VIN = 5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 55 25 VCC = 5.0V VIN = 5.0V 105 AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ISB STANDBY CURRENT vs. AMBIENT TEMPERATURE

SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25C

AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE

OUTPUT SINK CURRENT (mA)

1.6 1.4 1.2 1.0 0.8

140 120 100 80 60 40 20

VCC = 5.0V

VCC = 5.0V TA = 25C

0.6 55

25

125

0 0.0

1.0

2.0

3.0

4.0

SUPPLY VOLTAGE (V)

AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE

OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT (mA)

120 100 80 60 40 20

VCC = 5.0V TA = 25C

0 0.0

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

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CY62256N
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO DELTA tAA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5 V TA = 25 C TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC vs. CYCLE TIME

1.00

VCC = 5.0 V TA = 25 C VIN = 5.0 V

0.75

600

800 1000

0.50 10

20

30

40

SUPPLY VOLTAGE (V)

CAPACITANCE (pF)

CYCLE FREQUENCY (MHz)

Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Mode Deselect/power-down Read Write Output Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)

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CY62256N

Ordering Information
Speed (ns) 55 Ordering Code CY62256NLL55SNXI CY62256NLL55ZXI CY62256NLL55ZXA CY62256NLL55SNXE CY62256NLL55ZXE 70 CY62256NLL70PXC CY62256NLL70SNXC CY62256NLL70ZRXI CY62256NLL70SNXA Package Diagram Package Type Operating Range Industrial Automotive-A Automotive-E Commercial Industrial Automotive-A

51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) 51-85071 28-pin TSOP I (Pb-free) 51-85071 28-pin TSOP I (Pb-free) 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) 51-85071 28-pin TSOP I (Pb-free) 51-85017 28-pin (600 Mil) Molded DIP (Pb-free) 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) 51-85074 28-pin Reverse TSOP I (Pb-free) 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free)

Ordering Code Definitions


CY 62 256 N LL - XX XXX X

Temperature Grade: X = C or I or A or E C = Commercial = 0 C to +70 C; I = Industrial = 40 C to +85 C; A = Automotive-A = 40 C to +85 C; E = Automotive-E = 40 C to +125 C Package Type: XXX = SNX or ZX or PX or ZRX SNX = 28-pin SNC (Pb-free) ZX= 28-pin TSOP I (Pb-free) PX = 28-pin Molded DIP (Pb-free) ZRX = 28-pin Reverse TSOP I (Pb-free) Speed Grade: XX = 55 ns or 70 ns Low Power Nitride Seal Mask fix Density: 256 kbit Family Code: MoBL SRAM family Company ID: CY = Cypress

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CY62256N

Package Diagrams
Figure 10. 28-pin PDIP (1.480 0.550 0.195 Inches) P28.6/PZ28.6 Package Outline, 51-85017

51-85017 *E

Figure 11. 28-pin SNC (300 Mils) SN28.3 (Narrow Body) Package Outline, 51-85092

51-85092 *E

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CY62256N
Package Diagrams (continued)
Figure 12. 28-pin TSOP I (8 13.4 1.2 mm) Z28 (Standard) Package Outline, 51-85071

51-85071 *I

Figure 13. 28-pin TSOP I (8 13.4 mm) Package Outline - Reverse, 51-85074

51-85074 *G

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CY62256N
Acronyms
Acronym CMOS I/O SRAM TSOP VFBGA Input/Output Static Random Access Memory Thin Small Outline Package Very Fine-Pitch Ball Grid Array Description Complementary Metal Oxide Semiconductor

Document Conventions
Units of Measure
Symbol C A mA MHz ns pF V W degree Celsius microampere milliampere megahertz nanosecond ohm picofarad volt watt Unit of Measure

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CY62256N

Document History Page


Document Title: CY62256N, 256-Kbit (32 K 8) Static RAM Document Number: 001-06511 Revision ** *A *B *C ECN 426504 488954 2715270 2891344 Orig. of Change NXR NXR VKN / AESA VKN Submission Date See ECN See ECN 06/05/2009 03/12/2010 New data sheet. Added Automotive product Updated ordering Information table Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017) Added Table of Contents Removed L product information Updated Ordering Information table Updated Package Diagrams (Figure 10, Figure 11, and Figure 12) Updated Sales, Solutions, and Legal Information Updated Ordering Information. Added Ordering Code Definitions. Updated template and styles according to current Cypress standards. Added acronyms and units. Removed reference to AN1064 SRAM system guidelines. Updated operation recovery time parameter under Data Retention Characteristics on page 6. Updated package diagrams. Updated Package Diagrams: spec 51-85092 Changed revision from *D to *E. Updated in new template. Completing Sunset Review. Description of Change

*D *E

3119519 3329873

AJU RAME

01/04/2011 07/27/11

*F *G

3433878 4122787

TAVA VINI

11/09/11 09/13/2013

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CY62256N
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Technical Support
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Cypress Semiconductor Corporation, 2006-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-06511 Rev. *G

Revised September 13, 2013

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