Advanced Digital Design Project Description

Introduction: The purpose of the project is for you to demonstrate your skills in designing a substantial digital system using the Verilog/Synthesis techniques taught in class. This document describes the projects and turn-in requirements. These projects are supported by the tutorials prescribed with the class homeworks. All projects are to be done in student pairs. Submission Instructions: Project Plan: Can turn in one week late with a 10% penalty. Project Verilog and synthesis files: Can be turned in one week late with a 10% penalty. Please turn in the following: All Verilog files RTL view from complete synthesis run Simulation results file showing correct functioning Project report Project Report. Submitted electronically at the same time. Same penalty for late submission. Also bring a printed copy of the project report to your demonstration. Project Demonstrations take place in the weeks after project due-in and before the last day of classes. CANDIDATE PROJECT TOPICS: 1. SPI Master/Slave interface and on board demo: Maybe on a microcontroller board. 2. I2C Master/Slave interface and on board demo: Maybe on a microcontroller board. 3. RS232 interface and on board demo: Maybe on a microcontroller board. 4. RS485 full duplex, half duplex communication system design. (Group project also includes PCB board design) 5. VGA/LCD demo application. 6. Trimode Ethernet MAC core and on board demo: A PC demo with wireshark. 7. FFT core design.: Comparison of the design with Matlab results. 8. Object Tracking.: A real time demo. (Group project) 9. Image stabilization with frequency warping.: Real time demo with camera and display. (Group project) 10. Active noise cancellation. 11. OpenMSP430 implementation and on board demo. (Group project) 12. Encryption core design and on board test. 13. Real time video encoder design and on board demo. (Group project) 14. Colored Region Tracking. (Group project) 15. Lens Distortion Correction. (Group project) 16. Foveal Sensor. (Group project)

17. Range Imaging. (Group project) 18. Real Time Produce Grading. (Group project) 19. JPEG Encoder and on board test. (Group project) 20. USB Controller and on board test. (Group project) 21. Ray Tracing. 22. Embedded Nios II system. (Group project) 23. Embedded Microblaze system. (Group project) 24. Stepper motor control. 25. Bioinformatics application.

FROM MING BO LINS'S BOOK 26. Chapter 11, 14, 15 end chapter problems and problems 3.9, 8.14-15, 8.1721, 9.8-9, 9.14, 9.22, 10.9-16, 13.2-8, 16.14-15

***A Candidate Project Plan for Regular Expression Matching Problem Statement:

Anticipated Structure of Project There will be four main components to your project: Expression parser. This will be a piece of code (i.e. Software such as C), not Verilog, that can parse the specified rule set into a binary format that you will specify for your project. Test Bench. As well as starting and stopping the Verilog simulation, this will load both the traffic data and the processed expression data into your memory. It will also be used, just before ending the simulation, to write out a list of found matches from the memory. Memory. You can specify TWO 32-bit wide, 4096 word deep, 3 ported synchronous memories (two read and one write ports). You are limited to these two memories. The data payload provided will fit into ONE Of these memories. Logic. Multiple Verilog modules capturing your logic design, and perform the required functions. This will interface with the memory to use the expressions found there-in to process the traffic payload found there-in. It will write found matches back to the memory as described below. Output

Getting Started

***A Candidate Project Plan for Simple Expression Matching

Deliverables 1. Project Plan. Submit a simulatable specification of your design 2. Final report. A separate document outlines the specified format. 3. Verilog files. All your verilog files are to be submitted by wolfware. 4. Demonstration. You will be required to INDIVIDUALLY demonstrate your project. Demonstrations will occur after Verilog turn-in but before the last class.

General Instructions Project Plan Items to be included in this report include the following: Block diagrams of your design, clearly identifying any design hierarchy, all registers, all module I/O. Neat block diagrams are expected, not rough hand drawn sketches. Include a written description of the function of each module. E.g. For a multiplier, which multiplier algorithm are you planning to use. Any appropriate high-level (e.g. C) code showing the algorithm has been correctly captured. A project execution plan, including the following: Who is responsible for each module A verification plan. How do you intend to verify that the design works correctly? Who will be responsible for system verification? A risk assessment plan. Where are the greatest risks in this project? E.g. What areas of the design are you unsure of? Where are your greatest concerns in executing this project? Note, this section is intended for your benefit (so you can focus your efforts on the parts you are least sure of). Do not expect written feedback on your risk assessment plan. However, feel free to ask questions of the teaching team. A milestone chart, including anticipated dates for completing module design, design integration and design verification. Grading for this report will be as follows (out of 10): 9-10: All major design elements correctly identified; behavioral code complete with test cases. Neat and clear documentation. 7-8: At least one major design element missing, or C code incomplete, or confusing and poor documentation. 5-6: Scrappy, but honest, capturing some elements but conveying no real understanding of the design. 0-4: Extremely poor attempt. Main Project Report and Demo There are penalties for late turn-in. This date is set by the desire to complete grading these before you need to prepare for the final exam. Your project report is to include the following: Written description of your approach, including block diagram of your design, description of your verification strategy and a discussion of any part of the design, synthesis or verification that you consider tricky, novel or noteworthy. Specifically note and document your area and your throughput Full listings of the following: Verilog files, including test fixture Synthesis scripts -e.g. user constraints, synthesis settings. Extracts from RTL schematic, timing report. Plots from the final design.

Simulation run results (waveforms or equivalent) High level model of the design(e.g. pseudo code of the algorithm), if appropriate

The grading scheme for the final report and demonstration are attached below. Bonus points are awarded PRIMARILY on your demonstrated ability to maximize the design goal above. Some bonus points MAY be awarded to groups that make a contribution to the class project as a whole, beyond their individual design (this is rare). There are no other ways to earn bonus points. Final Project Grading Scoresheet

Bonus Data:

Written Comments: