Programming a Xilinx Configuration Device on the Production Board

During design development, the NanoBoard provides the ability to bootstrap the FPGA device located on the currently inserted Daughter Board, at power-up. Program download to the FPGA is carried out using dedicated Serial Flash RAM. When the design is moved to the Production board, using the bootstrapping functionality of the NanoBoard is no longer possible. To boot the target FPGA device on the Production board with the required design, that design must be programmed into a dedicated configuration device that resides on the board.

Summary
This application note describes the process of programming a Xilinx configuration device on the Production board, in order to provide bootstrapping functionality.

Preparation
In order to program the configuration device, the Production board must be included in the JTAG chain, so that all hard devices that it contains can be detected and displayed on the Hard Devices chain of the Devices view (in the software). Ensure, therefore, that the Production board is connected to a NanoBoard using one of the User Board headers and that both boards are subsequently powered-up.

Generating the Configuration File

Firstly, ensure that the required FPGA project is open in the Projects panel. Open the Devices view, if not already open. Ensure that the Live option is enabled as this enables the auto-board-recognition system. The Hard Devices chain will display any physical FPGA devices and configuration devices on the Production board, as well as an FPGA device on any Daughter Board currently plugged into the NanoBoard. Focus the FPGA device that will be booted using the configuration file. This is done simply by clicking on the icon for the device. In the drop-down field underneath the device's icon, make sure that the FPGA Project-Configuration combination targeting the physical device is correctly selected. In the Process Flow associated to the targeted device, expand the Build section. The last entry in the Build stage menu is Make PROM File (Figure 1). Click on the
Figure 1. Accessing the command to generate a PROM file.

icon, to the far right of this menu entry. The Options for PROM File Generation dialog will appear (Figure 2).

Figure 2. Accessing the options dialog for PROM file generation.

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Use the dialog to choose the target configuration device which resides on the Production board and to which the generated PROM file will be downloaded. Click inside the Value field to access a drop-down list of supported configuration devices (Figure 3). The drop-down list contains devices that fall into one of two categories: Configuration devices where a PROM file can be both generated and programmed. These are all JTAG-compliant devices a requirement in order to access the device for programming through the NanoBoard.
Figure 3. Choose from a range of supported configuration devices.

Configuration devices where only generation of the relevant PROM file is supported. These devices are not JTAG-compliant and therefore cannot be accessed for programming over the JTAG link. Special programming devices must be used to download the PROM file for these configuration devices.
1

Table 1. Supported JTAG-compliant configuration devices .

Device XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P XC18V01 XC18V02 XC18V04 XC18V256 XC18V512

Density 1 Mbit 2 Mbit 4 Mbit 8 Mbit 16 Mbit 32 Mbit 1 Mbit 2 Mbit 4 Mbit 256 kbit 512 kbit

Supply Voltage 3.3 V 3.3 V 3.3 V 1.8 V 1.8 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
4

Package

VO20 (20-pin Plastic Thin Small Outline Package)

VO48 (48-pin Plastic Thin Small Outline Package) FS48 (48-pin Plastic Thin Fine Pitch Ball Grid Array (0.8mm pitch))

PC20 (20-pin Plastic Leaded Chip Carrier) 2 SO20 (20-pin Small Outline Package) PC44 (44-pin Plastic Chip Carrier)
3 2

VQ44 (44-pin Plastic Quad Flat Package)

Table 2. Supported Non-JTAG-compliant configuration devices .

Device XC17V01

Density 1 Mbit

Supply Voltage 3.3 V

Package 5 PC20 (20-pin Plastic Leaded Chip Carrier) VO8 (8-pin Plastic Thin Small Outline Package) SO20 (20-pin Small Outline Package)

XC17V02 XC17V04 XC17V08

2 Mbit 4 Mbit 8 Mbit

3.3 V 3.3 V 3.3 V

PC20 (20-pin Plastic Leaded Chip Carrier) PC44 (44-pin Plastic Chip Carrier) VQ44 (44-pin Plastic Quad Flat Package) PC44 (44-pin Plastic Chip Carrier)

1 2 3 4 5

Each of these devices can be re-programmed up to 20,000 times. XC18V256, XC18V512 and XC18V01 only XC18V02 and XC18V04 only Each of these devices can be programmed once only. For each device, the range of package types are available in both Commercial and Industrial Temperature Grades

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XC17V16

16 Mbit

3.3 V

VQ44 (44-pin Plastic Quad Flat Package)

Once you have selected the required target configuration device, click OK to accept the selection and exit the dialog. The status display icon for the Make PROM File entry will change to red (file missing). To generate the PROM file, simply click on the Make PROM File text the status display icon will change to blue (running the command) and then eventually green, once the PROM file has been generated. A report file for the operation (FPGAProjectName.prm) can be accessed by clicking on the associated right of the Make PROM File entry. icon, located to the

The generated PROM file (FPGAProjectName.mcs) is stored in a folder with the same name as the configuration used for the associated project. This folder is located in accordance with the output path defined in the Options tab of the Options for Project dialog (Project Project Options). Note: The configuration file can be generated with the Devices view in Not Live mode. This mode could be used if you just wanted to generate PROM files for one or more configuration devices, without going on to program any of the physical devices configuration and/or FPGA thereafter.

Accessing Configuration Device Information

To access information for a physical device, from the Devices view choose the Browse Physical Devices command from the main Tools menu. The Browse Physical Devices dialog will appear, as illustrated in Figure 4.

Figure 4. Browsing physical devices for use in a design.

With the Vendors region of the dialog set to Xilinx, use the FPGA Families region to choose the required configuration device family 6 XC18V00 or XCF. The main region of the dialog will change to show all devices in the chosen family, with all supported devices represented by an X entry.

Information for the Non-JTAG-compliant XC17V00 family of configuration devices is not available from the Browse Physical Devices dialog.

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AP0111 Programming a Xilinx Configuration Device on the Production Board

Figure 5. Available and supported devices within a specified family (XC18V00 family shown).

The dialog will provide information on a chosen (and supported) device, including schematic symbol, PCB footprint and 3D model representations, where available. For further, detailed information with respect to any of the supported Xilinx configuration devices, consult the relevant Configuration PROM Data Sheet, available on the Xilinx website.

Erasing the Configuration Device

Before programming the configuration device, it is a good idea to clear its memory first. To do this, right-click on its icon in the Hard Devices chain and choose Reset Hard Device from the pop-up menu.

Figure 6. Flushing the configuration PROM device.

The erasing process will proceed, with progress shown in Altium Designer's Status bar.

Downloading the Configuration File

The configuration for a Xilinx configuration (PROM) device is stored in a PROM file, using the Intel MCS-86 format. This is an ASCII hex file with extension .mcs. To download the new configuration, right-click on the icon for the PROM in the Hard Devices chain of the Devices view and select Choose File and Download from the pop-up menu. The Choose Programming File For dialog appears. Use this dialog to navigate to the required programming file ( *.mcs) and click Open. A confirmation dialog will appear, asking whether you wish to verify the programming (of the PROM). At this stage, the configuration has not been downloaded. Click Yes to proceed with the download and verification cycle. The download and verification will take approximately 30-40 seconds to complete. The progress is shown in Altium Designer's Status bar. At the end of the cycle, an information dialog will appear with the result of the download. If any errors occur during the download and verification cycle, a warning dialog will appear. If this happens, power-down the Production board for a few seconds and then run the whole process again including the erasure of the PROM device's memory.

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Revision History
Date 08-Jan-2004 26-May-2005 29-Feb-2008 02-Aug-2011 Version No. 1.0 1.1 2.0 Revision New product release Updated for Altium Designer SP4 Updated for Altium Designer Summer 08 Updated template.

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