Working with Xilinx Devices and Place and Route Tools

Altium Designers FPGA development environment can be used to capture, synthesize, place and route and download a digital system design into an FPGA. Place and route, the process of implementing the design on the target silicon, requires an intimate understanding of the functionality and architecture of the device, a task best performed by software tools provided by the device vendor. The vendor software is operated by the Altium Designer environment, which automatically manages all project and file handling aspects required to generate the FPGA program file. There is a large degree of usercontrol over this process, which this application note details.

Summary
This application note provides an advanced Xilinx designer with information on how to control the Xilinx place and route software options and properties, and also includes information on libraries.

Introduction
Xilinx tools are integrated and accessed in the Altium Designer environment through the Devices view (View Devices View). This view allows step-by-step control over the entire FPGA design process, enabling you to program and debug your system design on the FPGA. For information on using the Devices view to process the design, see the Processing the Captured FPGA Design application note. This application note makes reference to a number of Xilinx documents. Users wishing to change any of the default settings should refer to these documents for details: Xilinx Development System Reference Guide, Constraints Guide, and XST User Guide. If you are not familiar with the Xilinx tools it is recommended that you start designing with the built-in default settings.

Supported Architectures
The system supports the latest Xilinx FPGA technology and includes both FPGA and PCB schematic library support. The following table summarizes the supported device technologies and the available library support, at the time of publication of this document. Device Technology CoolRunner-II CoolRunner XPLA3 Spartan-II Spartan-IIE Spartan-3 Spartan-3E Virtex Virtex-II Virtex-II PRO ArchitectureIndependent Library Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Architecture-Dependent FPGA Library Name (*.IntLib) Xilinx CoolRunner-II FPGA Xilinx CoolRunner-XPLA3 FPGA Xilinx Spartan-II FPGA Xilinx Spartan-IIE FPGA Xilinx Spartan-3 FPGA Xilinx Spartan3E FPGA Xilinx Virtex FPGA Xilinx Virtex-II FPGA Xilinx Virtex-II Pro FPGA Associated PCB Library Name (*.IntLib) Xilinx CoolRunner II Xilinx CoolRunner XPLA3 Xilinx Spartan-II Xilinx Spartan-IIE Xilinx Spartan-3 Xilinx Spartan-3E Xilinx Virtex Xilinx Virtex-II Xilinx Virtex-II Pro

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Device Technology Virtex-4 Virtex-E XC18V00 XC9500 XC9500XL XC9500XV XCF

ArchitectureIndependent Library Support Yes Yes N/A Yes Yes Yes N/A1
1

Architecture-Dependent FPGA Library Name (*.IntLib) Xilinx Virtex-4 FPGA Xilinx Virtex-E FPGA N/A
1

Associated PCB Library Name (*.IntLib) Xilinx Virtex-4 Xilinx Virtex-E Xilinx XC18V00 Xilinx PLD XC9500 Xilinx PLD XC9500XL Xilinx PLD XC9500XV Xilinx XCF

Xilinx XC9500 FPGA Xilinx XC9500XL FPGA Xilinx XC9500XV FPGA N/A1

FPGA Architecture-Independent Library

To maintain device independence, the system includes a large library of typical generic design components, the FPGA Generic Library. This integrated library can be found in the \Library\FPGA folder of the installation. For complete documentation with respect to the FPGA Generic Library, refer to the FPGA Generic Library Guide.

FPGA Architecture-Dependent Libraries

If device independence is not required the system also includes Xilinx FPGA libraries. These integrated libraries contain both the Unisim and Macro types of components. Vendor-specific integrated libraries are packaged according to the selection guide provided in the Xilinx Libraries Guide. This ensures that only specific components that are available with your target device are used in your design. The FPGA design libraries can be found in the \Library\Xilinx folder of the installation.

Xilinx Core Generator Component Support

Specialized cores that have been created using the Xilinx Core Generator can be used in your FPGA design. Once you have generated the core, you link the generated EDIF file to a schematic component, and place this component in your FPGA design. To create a component symbol from the EDIF file, open it in the software and select Design Create Schematic Part From File from the menus. The EDIF file must be placed in the FPGA project folder, or stored in a User pre-synthesized model folder (specified on the FPGA Synthesis page of the Preferences dialog (DXP Preferences)).

Integrated PCB libraries

There are also PCB design libraries available for many of the Xilinx programmable devices, in the \Library\Xilinx folder of the installation. These libraries include schematic symbols and PCB footprints, as well as 3-D models and signal integrity models where available.

Xilinx Place and Route Tools Configuration

The place and route tools are all accessed and configured from the Build stage of the Process Flow associated to the target physical device in the Devices view. To enable and display the Process Flow when the target device is a Xilinx FPGA you must:

Not applicable as these are configuration PROM devices.

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have the appropriate Xilinx place and route tools installed either the full tool suite or the freely downloadable version available from the Xilinx website and your design must be configured for a valid Xilinx target architecture. This is done by including a suitable device constraint in a project constraint file, which belongs to a current project configuration (Project Configuration Manager). For an example of creating a design and configuring it for a target FPGA, refer to the Getting Started with FPGA Design tutorial.

Build Options
The Build process allows interface with Xilinx tools and produces the bitstream (BIT) file to download into your FPGA. By clicking on the down arrow, a list of individual steps used to complete the Build process can be found. Click the Options icon adjacent to each stage to configure that feature. Errors or design rules that are not allowed for your target architecture or in the design will be picked up at each stage of the Build process. The location in the design and the error or warning is logged in a report file, accessed by clicking on the appropriate Report icon.

Options

Reports

For advanced users who want more control over the options passed to the Xilinx tools, each stage in the Build process is linked to a script file located in the \System folder of the installation. Be aware that these scripts are defaulted to standard optimization any changes should be carefully applied in consultation with the Xilinx Development System Reference Guide. Individual Build stages, options and the corresponding default script files are described in the following sections.

Translate Design
This stage invokes the Xilinx NGDBuild tool, translating the EDIF output from the FPGA project synthesis process to a Xilinx Native Generic Database (NGD) file and Xilinx Project Navigator project (NPL) file. In this process, a logic design rule check is also run to confirm that the design is fit for mapping to any target FPGA. For more information on options available with this process refer to chapter 6 of the Xilinx Development System Reference Guide. Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_NGBuild.Txt script file. NGDBuild switches can be configured in this file, in accordance with the Xilinx documentation. The Xilinx project can be opened in the Xilinx Project Navigator if required.

Map Design to FPGA

This stage invokes the Xilinx MAP tool, mapping the NGD file to the logic available in your target Xilinx FPGA. In this process, a physical design rule check is run to find physical and logical errors that may be present, depending on your target FPGA. The output of this process is an NCD (Native Circuit Description) file. For more information on options available with this process refer to chapter 8 of the Xilinx Development System Reference Guide. Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_MAP.Txt script file. Map switches can be configured in this file, in accordance with the Xilinx documentation.

Place and Route

This stage invokes the Xilinx PAR tool and uses the NCD file output from the MAP process to place and route. A placed and routed NCD file is produced, suitable for the bitstream generator. For more information on options available with this process refer to chapter 10 of the Xilinx Development System Reference Guide. Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_PlaceAndRoute.Txt script file. PAR switches can be configured in this file, in accordance with the Xilinx documentation.

Timing Analysis
This stage invokes the Xilinx Trace (timing reporter and evaluator) tool. This conducts static timing analysis on the design, based on the input timing constraint. It verifies that the design meets the timing constraints, generating a report on the analysis. For more information on options available with this process refer to chapter 13 of the Xilinx Development System Reference Guide.

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Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_Trace.Txt script file. Trace switches can be configured in this file, in accordance with the Xilinx documentation. Timing analysis can be switched off if required, click on the Timing Analysis Options icon.

Make BIT File

This stage invokes the Xilinx BitGen tool to produce a bitstream (BIT) file from the placed and routed design (NCD) file. The BIT file is used to download and program the FPGA, or to create a PROM file in the Make PROM File stage. For more information on options available with this process refer to chapter 15 of the Xilinx Development System Reference Guide. Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_BitGen.Txt script file. BitGen switches can be configured in this file, in accordance with the Xilinx documentation.

Make PROM File

This optional stage is used to generate a program file for a Xilinx configuration device. It is available once a target PROM has been selected by clicking on the Options icon. It invokes the Xilinx PromGen tool, whose output format is dependent on the selected target device. For more information on options available with this process refer to chapter 16 of the Xilinx Development System Reference Guide. Advanced options that are not present when you click on the Options icon can be accessed in the DefaultScript_Xilinx_PromGen.Txt script file. PromGen switches can be configured in this file, in accordance with the Xilinx documentation.

Xilinx Constraints Entry

Altium Designers FPGA design environment supports a range of constraints that are device independent. However, since not all FPGA families share the same technology there are also vendor constraints that can be used. The Xilinx tools support a range of constraints that allow you to take advantage of internal technology and other design options. For detailed information on Xilinx FPGA constraints refer to the Xilinx Constraints Guide. Xilinx constraints can be included with your design by adding the Xilinx User Constraint (UCF) files to the FPGA project. Multiple constraint files can be added, enable their use in the project by disabling the Ignore UCF file option, accessed by clicking the Options button associated with the Translate Design stage of the Build process.

Xilinx XST Synthesizer Configuration

The system includes a powerful built-in synthesis engine, which is used by default. It also supports use of the Xilinx XST synthesizer within the design environment. To enable an FPGA project to utilize this synthesis tool the project synthesis option must be set to XST Synthesizer. This is done by selecting Project Project Options from the menus, clicking on the Synthesis tab and choosing XST Synthesizer from the dropdown Synthesizer list. Once this is selected you must indicate the folder where the XST binary executable file resides, using the dropdowns associated browse button (). The Options region of the Synthesis tab will become populated with XST-related options. Configure these to best suit your design. For advanced users, options that are not present on the Synthesis tab can be accessed from the DefaultScript_XST_CPLD.Txt and DefaultScript_XST_FPGA.Txt script files located in the \System folder of the installation. XST switches must be configured in accordance with the Xilinx XST User Guide.

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Figure 1. Setting the Xilinx XST Synthesizer options

If you are not familiar with the Xilinx synthesis tools, it is recommended that you start designing with the built-in DXP or Altium synthesis engines.

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Revision History
Date 19-Dec-2003 12-Jul-2005 20-Sep-2005 12-Dec-2005 28-Feb-2008 02-Aug-2011 Version No. 1.0 1.1 1.2 1.3 2.0 Revision New product release Updated for Altium Designer SP4 Spartan-3E added to list of supported architectures Path references updated for Altium Designer 6 Updated for Altium Designer Summer 08 Updated template.

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