Symbolic Layout Compaction Review

David G. Boyer Bell Communications Research 331 Newman Springs Road Red Bank, NJ. 07701

Abstract: Symbolic layout and compaction is reacbin8 a mature status. l%is is demonstrated,in part. by the recent or imminent introductions of a number of commercial symboIic layout and compaction systems. The two most frequently used symbolic layout compaction approaches. constraint graph compaction and virtual grid compaction, are reviewed in this paper. The cummt status of these two approachesis presented by looking at the results of the ICCD87 compaction benchmark session.

grid. The compactor brings circuit elements as close together as design rule spacing requirements will allow. Some constraint graph compactors can also push apart circuit elements that are too close together. Locations are typically given to each circuit element. Some constraint graph compactors, however, group together circuit elements whose center lines share the same physical grid line, aad who are connected geometrically (electrically connected) aud give the groups locations. Constraint graph compactors are one-dimensional compactors and require at least one X compaction pass and one Y compaction pass. 2.1.1 Constraint Graph Generation The lint step necessary in constraint graph compaction is to build a directed constraint graph for tbe circuit. The nodes of the graph represent the circuit groups and the edges in the graph conuect groups that have potential design rule spacing requirements. Note, that if groups were not being used there would be a node in the graph for each circuit element. The weights of the edges anz the minimum spacing necessarybetween two nodes (circuit groups). The building of the constraint graph is the most time comuming part of constmint graph compaction and is, in the worst case, O(s). There is an edge between every pair of nodes in a worst case ccmstmintgraph. Only a small subset of the potential edges are actually needed for constraint graph compaction. A circuit element group typically will only have spacing requirements with its nearest neighbors. Many techniques for efficiently generating the constraint graph have been proposed Some of these will be mentioned below. One of the beat known techniques for building a constraint graph is the shadow-propagation method [HsU79] used in CABBAGE. This appmacb trims the sarcb space by only checking mask edges that e covered by a shadow that is caused by shining an imaginary light fium behind the group under consideration [figure 11. An edge is created in the circuit gmph between a group of circuit elements and the given group if the shadow falls on the group of circuit elements. l%e shadow-propagation method has an average complexity of O(N*.s) [HSU79]. Note that the shadow is one-half a design rule bigger (for most graph based approaches) than the element in order to account for diagonal constraints. This leads to mter &an minimal Euclidean spacings since an enlarged mctaugle is used to account for corner intemctions. ibis appearsto be strictly an implementation detail and not a restriction of the constraint graph approach. A number of techniques exist that matly improve the efficiency of coustraint generation and result in run times approaching O(NlogN), where N is the number of edges. A bitmap technique is used by [I-IED85] and is technically still O( @) but the actual time taken is reported to approach

1. Introduction Symbolic layout compaction research has reached a relatively mature state. This is demonstrated, in part, by the recent and imminent introductions of a number of commercial symbolic layout and compaction systems. This paper reviews the two main approaches to compaction, constraint graph compaction and virtual grid compaction. Constraint graph compactors typically produce smaller area results than virtual grid compactors, while virtual grid compactors typically run faster and inherently support abutted hierarchy. The first section in this paper reviews leaf cell compaction. Hierarchical compaction and pitchmatching am next tiewed. followed by a discussion of the ICCD87 compaction benchmark session. The paper concludeswith a summary. 2. Lfaf Cell Compaction Symbolic layout systemswith compaction are used to create full custom designs in a process independent fashion. Symbolic contacts, wires, and transistors are used to represent the different circuit elements of the target technology. A designer uses symbolic circuit elements rather thao mask geometries to create his/her design. A compaction program is responsible for creating the mask level description of a circuit. It spaces the circuit elements according to the design rules of a target process which are typically kept in a technology tie. The compactor can compact a symbolic cell for a new fabrication process simply by using a new technology file. Consequently, a designer does not usually have to redesign his/&z cinxdt to take advantage of a new fabrication process. Tracking an evolutionary process change can be done in as little as a day or two mY86]. Symbolic layout and compaction have been active areas of research over the past lifteon years [AKBIO] and although virtual grid and constraint graph compaction are the main techniques used today, quite a few other approaches have been tried Some of these are - the SLIM system [DUN801 which combines a shear line algorithm LAKE703 with the constraint graph approach, the two dimensional approach of Watanabe and Kedem -841 which uses a mathematical optimization technique to solve a two-dimensional constmint graph, and the local two-dimensional approach of Wolf [wOL83] which minimizes the area iu a preferred direction. A simulated annealing approach was recently reported by Mosteller @iOS87] which is a 2-D compaction approach that produces a curvilinear (non-Manhattan)layout. 2.1 Constraint Graph Compaction The CABBAGE @SU79] compactor of M.Y. Hsueh is the most widely known comtraint graph compaaor. I&. first repotted graph based approach was by Cho [CHO77]. III the constraint graph approach the designer typically places circuit element symbols on a fine grained physical

Agure 1. As x-shadow is blocked by B [REI87]. Ihere will be an edge betweenAandBiotheconstraintgraphandtherewillnotbeanedge between A and C.

25th ACM/IEEE Design Automation Conference@ Paper 26.1 Ct-l2540-3/88/0000/0383$01 .OO0 1988 IEEE
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O(N). excluding time to sort the edges. The intervening group method incrementaRy generates the constmint graph. This method effectively shadows vertices in the graph when a pair of vertices are coostrained to remain far enough apart F;IN84]. A combination of shadowing and Ibinning is used in [CR0871 which has worst case complexity of O(Nt.r). lbe perpendicular-plane-sweep method of Lengauer LEN831 was generaked by Burns IBUR87] resulting in coustmiut graph generation which approaches O(NlogN). AR the above techniques also attempt to minim&e the number of edges in tire graph because a stmightf~ard implementation of the shadow-propagation method leads to the generation of marry uunecessary edges.

2.13 Critital Path Anulysis The next step in constraint graph compaction is to determine the critical path through the graph. The goat of compaction is typically, to give a cell as small an area as it can+ consequently, nodes on the critical ,path am given their minimal location. The compaaor can place nodes that ate not on the critica! path in such a way to increase circuit performanoe, to minimize wire length, to optimixe fabrication yield, etc. Critical path analysis has worst-case complexity of O(VB) for graphs with upper bounds, and O(B) for graphs with only lower bounds. The slgorithm used by &LA831 determines the critical path for graphs with upper-bound constraints in O(LU) time, where L is the number of lower-bound edges and U is the number of upper-bound edges iu the graph. Event driven critical path analysis (fBUR87][CRO87]) results in near linear
Nn limes.

1I
*dl l

2.1.4 Wire Jogging Botb automatic jogging of wires aod wire length miuimixation (see next section) have received much attention in the last couple of years. This is, in part, due to the recent interest in chamel compaction ~BU85]. One of the first approaches to jogging wires was reported by Hsueh mSU79J. In this approach jogs in wires were introduced at torque points on a wire [figure 41. Wire jogging had limited success because it could reduce the sire iu one direction while,

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Pigure 2. The wire is given an upper bound constmint so that it remains attached to the contact wAT84].

2.1.2 Upper Bound Constraints Many coti graph compactors ILL4831 fBUR86J [CRO87] fBAL82] fKED84] permit upper-bound constraints (maxhnum iocatious) as well as lower-bound con%raints (minimum locatiotw) for compaction groups [figure 21. Typically, lowerbound constraints are tepresented as forward pointing edges from a node with positive weights, and upper-bound couHraints are represented as backward-pointing edges with negative weights. Dual corunaints signi8cantly complicate the compaction process and lead to the possibility of cycles in the graph. Positive cycles represent graphs that am unsolvable because of input errors and that have no realizable topology [fi@re 31. Detection of all the positive cycles in a graph is O(Nr) in complexity [CHO85]. There have been a number of approaches that have reduced this complexity by limiting tbe search space: identifying one cycle at a time is a common approach. Overconstraiued graphs that contain a single upper-bound constraint are detected in [DO85]. In [KIN841 the compactor consecutively ignores 0verconstNiuts until the graph can be solved. This results in au illegal layout. The compactor reported in fBur863 consecutively identities the worst overcoustmint in the critical path and reports it to the user. The complexity of this algorithm is O(VoRGE), where VoRG is the number of vertices with at least oue upper-bound constraint fanout vertex [BUR86].

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F

cl 5 cl
Pigure 4b. The result of the wire

Pigum 4a. A wine is jogged when ueighboriug groups apply a torque to it.

jog IHsu791.

potentially, increasing the size in the other direction. Recent attempts have focused on reducing the critical path in a cell: jog points are only introduced along the critical path. Jogs are introduced in the graph domain in [CRO87]. The critical path is updated after each wire is jogged a& the new critical path is then searched for the next wire to be jogged Tlhe process terminates when there are no wires on the critical pa& or there is not enough room left to introduce a now jog. A vertical jog is introduced. in a horixontal wire if there is a gap iu the X intervals between the fan-in vertices of the wire vertex and the fan-out vertices. This, in a sense, puts a torque on the wire vertex if the fan-in vertices aud the fan-out vertices an? also on the critical path, or at least tightly consttained Dais method has proven to be quite effective as will be seen in the benchmark section that follows. Wire jogging used in chauuel compaction reduces the cell siae in one direction. Contouring the wires to fill all the available space mO87] [SHl86] is the method typically employed. 2.15 Wire L.ength A4inimization EIements not on the critical compaction pass will typically tiud themselves pulled toward a cell edge because they are given their minimal legal spacing. This tends to increase wire length and reduce circuit performance. One of the tirst methods used to reduce wine length was the average slack merhod of Hsueh fJR%J79]. This approach uniformly distributed the empty space in a circuit amoug the elements that were not on the critical path. Burns @3UR86] uses a force-based heuristic that not only consider the effect of each wire layer but it also considers the cumulative effect of multiple wires connecting adjoining modules (vertices in SPARCS are hierarchicat so that a vertice could represent a module). This is effective in minimiziog wires in an hierarchical cell.

Figure 3. Object B is overcomtmined

within the U shape of object A

lW3871.

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Ihe approach used by Kingsley [KIN821 is similar to Schieles algorithm [SCH83] which pulls back elements that are not on the critical path as far back as they can go. The different wiring layers of the technology are given different weight factors, so that the diffusion layers, This approach is iterative in for example, are m inimized preferentially. nattlte. The method employed by Varadarahan in [CROSI] uses a non-iterative, event-driven algorithm to minimize the wire length. Groups of circuit elements wilt have preferential upward movement due to a wire connecting to it from above that needs its length to be minimized (wire widths are considered in this process as well as wire layers) [figure 51. The group is moved up until it is stopped by another group. These groups are merged if possible and move up together. When the merged group is stopped the composite group will be broken up and if the top group is not con&mined it wilt continue upward if it has a preferential upward movement. A gtobat optimum is nzported for this work and near linear run times are achieved due to its non-iterative approach.

Figure 6. (a) Intermediate compaction results. (b) Corresponding conshaint graph. (c) Box C is selected to be moved aud three candidate locations have been identified. (d) Result of moving box C and in (e) the updated constmint graph [SHI86]. Virtual grid compaction begins by 6rst examining spacings in one direction only (we will use the X direction as the 6rat compaction pass). Each X grid line is compared with parallel neighbotig X grid lines for spacing requirements. A spacing is required with a neighboring X grid if elements on two neighboring X grids have the same Y coordinate value. The 6nal spacing of an X grid will be the greatest spacing it has encountered with respect to its parallel neighbors. In onier to accommodate spacings that exert their influence over a number of symbolic grid lines, backtracking must be done. The grid tine to he placed is compared to previously placed columns until the distance between the current column ad the prior column exceeds some worst-case process value. During Y compaction (the secoud compaction pass) comer spacings ate accommodated. An element being placed during Y compaction is spaced against diagonal neighbors within the worst-case process window as well as against its adjacent neighbors. Alt diagonal spacing requirements are haudled duringthe second compaction pass.

Figure 5a. A cell after compaction [CRO87].

Rgwe 5b. Group B is moved up and it forms a new group with Group A.

Figure 5c. Group C moved up.

Figure Sd. New Group A formed by Shearing.

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2.1.6 Zone Refining Compaction The one dimensional constraint graph approach is enhanced and generalized in the ZORRO Zone-Relining approach in [SHI86]. Lateral movements are permitted in ZORRO, leading to locat twodimension24l compaction. The lateral movement of elements serves to shake individual components into more dense con6gurations [figure 61. ZORRO .%uts with the compacted results of a celt and proceeds to optimize these msults. ZORRO maintains dual X aud Y graphs to supporl the vertical spacing as welt as the laterat movement of the groups. The Zone-Relining approach gives denser layouts than one-dimensional compactors because it has more freedom in moving individual components.

2.2 Virtual Grid Compuction

Viial grid layout is a structured approach to symbolic design WSl]. The virtual grid is used to establish the relative placement of circuit elements and does not correspond to a physical grid [figure 71. In the virtual grid approach the compactor gives locations to the virtual grid lines, not to the circuit elements themselves. This imposes an arbitrary c&t on a virtual grid design: alt elements that fall on a virtual grid m given the same location.

Rgme 7. Virtual Grid Symbolic circuit.

Paper 26.1 385

2.2.1 Fence Compoctiun Fence compaction POYSS] eliminates the need

to do backtracking in a virtual grid compaction and is linear in nm time. The fence compaction technique is similar to the shadow-propagation method discussed above. lbe fence algorittau, in effect, combines the graph building step with analysis of the critical path. The virtual grid limits the potential locations of the symbolic elements. Ibis permits the use of a picket fence data sttuctum for each grid tine. A picket fence data structure records the last placement of each layer for the given process, ami thereby keeps tracJr of the necessary parallel neighbor information. There is a fence data structure for each Y grid line. Each fence, in turn, has one picket for each layer of the process that is being compacted for. Each picket comains a rectangle that represents the last placement of a rectaugle of the cmmsponding layer along the fence structures grid line. The contour of a given layer is captutud by the pickets for that layer. Dming the second compaction pass Y grid lines ate placed in much the same way as grid lines were placed during X compaction. Jn figme 8 the contour of the aluminum layer (the contems of the aluminum pickets contributed by aJl the fence data stmctmm) is depicted for the Y compaction of the circuit found in figum 7. Diagonal constraints am handled during this compaction pass and the actual Rucltdean distances for the cornem being spaced ate used.

Virtual segments am used in the approach presented in [KOLJ?6], rather than virtual grids. Placed circuit groups ate sorted by location in a doubly linked list in increasing order. Ihe placement of a new group is determined by spacing the sew group with respect to the groups in the doubly Linked list in demeasiug order. The group is spaced with ah groups until the distance between the group and the fixed location of a previously compacted group is large enough to accommodate a worst case design rule. Near linear run times ate reported for this work [KoL86]. Automatic element offsMing is ills0 done with this approach. A modified picket fence data structure is used in pOY87a]. A topological data structure is used to facilitate nearest neighbor access. Fast group identification as welt as fast compaction is possible since nearest neighbor iuformation can be obtained in constant time. The X compaction pass is similar to the X compaction pass presented above for virtual grid compaction except that gtoups are being placed instead of virtual grids (the fence structure is the same for both). During the Y compaction pass there is oue fence structure for each X group (not each X virtual grid). Y group placement is similar to Y grid placement. Run times as fast as those reported for a virtual grid compactor and area results as small as those produced by a constraint graph compactor have been reported for this work POY87al..

3. Hierarchical Compaction/Pitchmatching
The majority of the hierarchical compactors presented in the literature am hierarchical pitchmatchem [MN841 pNT85] m86]. In this paper the term hierarchical compactor will refer to programs that can compact a element/modtde with respect to other elements/modules aud wires. The elements/modules ate fixed in size (they are not stretchable). Programs that stretch cell so they can be abutted to each other will be referred to as pitchmatchers.

3.1 Pitchmotching
Both cons&m graph compaction systems and virtual grid systems suppmt pitchtnatohing. The common approach for both techniques today is to use a comurtdnt grr@ for the pitchmatching process. A number of other approaches have been tried with virtual grid pitchmatchers, including linear pmgmmming teclmiques, simulated amsealing , and a variety of heuristic

approach [ACK831.
ygrid-4 * virtual grid concept extends nalumlly to a pitchmatching env&nmml. Abutment points are identified between two cells when they share a common viatual grid (the edges of the two cells fall on the same &tad grid line) and when one or both have symbolic etements on the common bcsmdary. Cells are permitted to have coincident edges, but they are not permitted to overlap. The virtual grid helps to identify the pit&matching points in a module aud identities the connection points in neighboring cells that need to be aligned. lhem ate basicahy four steps that must be done in order to pitchmatch a module. The 6rst step is to compact the leaf cells to be pitchmatched to their minimal size. After a ceil is compacted the abutment points are identified and a parent constraint graph is ~0nstruUed. Once the parent graph is created it is then solved using the same longest path dgOfithm that was used in the leaf ceg compactor. Ihe cells pitches are matched by this process. The pit&matched port locations are then fed back to the leaf 0eR compactor rand all the leaf cells are recompacted with the pitchmatched port lo&ons as fixed constraints. After cells are pitchmatched they are tinally placed. One of the most active areas of research in constmint graph pit&matching has been with cetl abstraction. The celt abstraction inckrdes two COIII~OIO~~~S, the constraint graph that represents the cell in the parent, and the geometric model that is used to place the cell once it has been pitchmatched The most common constraint graph representation is to develop a port abstraction graph @IN821 WC861 wOL86] [CRO87]. Typically, the transitive closare of the constraints used for the leaf cell compaction is taken [wOL86] and the port abstraction graph results [figure 91. Only the vertices that correspond to the ports are retained in the graph. when a cell. is used hierarchicaRy its constraint graph can be replaced with its port abstraction graph.

Hgure 8. Y virtual grid 4 is being placed with respect to the alumhurm fence. The fence. outline conesponds to the already placed abuuinum layers.

2.2.2 Split Grid Compaction A split grid compactor starts with a virtual
grid layout. Ibe virtual grid is retained to organize the topology of the circuit. The grid lines ate split apart into distinct circuit groups which are co&ctious of circuit elements that lie on the same grid line and are electrically connected. The compactor gives locations to groups of circuit elements rather than virtual grid lines. Split grid compaction is a hybrid approach to compaction; it retains the simplicity and speed of virtual grid compaction and produces area results that am similar to those produced by a graph based compactor. A number of approaches have been used for split grid compaction [NyL87] [KOL86] @OY87a]. In the approach presented in cNyL87], groups sm identified and placed as close to the fence as possible. Upper bound constraints am handled for the element rectangles in this approach by using layer decoupling. Layer decoupling allows wires and contacts to slide with respect to a groups centerline (contacts ami wires can be offset).

Paper 26.1 386

3.2 Hierarchical Compaction

F@lre 9a. cell collstlaint

graph

Figme 9b. Ports identified

[REIW.

A hierarchical compactor can space fixed sired modules/e/elements with respect to other modules/elements lJ3UR87] pAU32]. In W approach UtOEA Contads, and modules axe treated in the same mmtner. Ihey are ali treated as cells and receive one. vertex in tbe constraint graph regardtess of the number of layers and terminals that comprise them. Arbitrary rectiliuear polygons cau be accommodated in SPARCS [BUR86] and novel device shapes, as welt as analog parts, can be used with this approach. To facilitate hierarchical compaction, a cell abstraction is generated that consists of protection frames t&El&I] and terminal frames [figure 111. The protection frames for a cell hide the details of a cells layers and represent them by bounding Manhattan polygons. The gmunlarity of these polygons is adjustable by the user. Terminal frames represent connection areas on each layer. The terminal frames and the protection frames are sufficient to describe tbe cell in the hierarchy ami serve as the cell abstraction. Ihe power in this approach is in the abitity to handle device shapes sod analog devices not traditionally found in symbolic layouts, as welJ as being able to accurately space adjacent modules [fignre 121. SPARCS csn also handle analog devices requiring symmetry using active constraints @UR86].

Pigure 9c. Port abstraction Braph The geometric model typically used is that elements not on a cell boundary are forced to be a half design rule from the. cell boundary. This inmes that when two cell edges are abutted, the elements that do not fall on the cell edge will always be design rule correct with respect to the neighboring ceil. This approach can be very expensive because elements that contain diftkion must be kept far enough from the edge iu order to permit the opposite diffusion type iu a neighboring cell. The scheme described in [TAN871 does not require this half design rule spacing. Another approach is to include some of the elements around the edge of a cell in the port abstraction (a donut [RE186]) so tbat an accurate placement of cell edges can be made [figure lo]. The most general approach is the approach used by Bums PUP871 that creates protection thmes for a cell. This is discussed in detail beiow. The ZORRO compactor uses a tkee step hierarchical compactioslpitchmatching process. The core of a cell is compacted while maintaining a terminal frame that has the terminals located at a predetermiued pitch. The compacted cell is then assembled with its neighbors (the terminal frames have been designed so that neighboring cells will abut). Tbe final step in the process is a compaction at the next level of the hierarchy where the cell cores are treated as tixed clusters. The terminal @tunes and other wires are compacted at this stage [SHI87]. This approach is a hierarchical compaction approach with river routing to take care of tk inter cell f2Jmuecliolls.

Figure 11. Cell dehnition and abstraction @UR87].

Rgure. 12. Two modules spaced by SPARCS (BUR87J.

l3gum 10. The constraint graph for a cell to be pit&matched donut abstractions W86].

showing the

Paper 26.1 387

4. Compaction Ben&ma& Ibe author conducted a benchmark session at the ICCD87 conference pOY87b]. IBe purpose of this session was to compare the performauce of different compaction approaches. For the details of the benclnnatking process see [BOY87b] and @3OY87c]. 4.1 Benchmark Results Four compactors participated in the session. The MACS compactor which [CR0871 is a constraint graph compactor that does automatic jog irtsertion and wire minimixation, the ZORRO [SHI87] and SIARCS [BUR87] compactors which were discussed above, and the Spnbolics virtual grid compactor FAN871 which does automatic contact offsetting. The results produced by the compactors were checked for design rule violations as well as netlist inconsistencies lBOY87cl. Ibe strengths and weaknesses of the different approaches can be found horn these results. The most noticeable result of the compaction benchmark session was the benefit of introdu&g jogs in the compacted layout. The compactors that iatrodnced jogs ia wires consisteatly produced smaller areas than those that did not. The MACS compactor [CR0871 is a constraint graph compactor that iatroduces jogs along the critical path in the constraint graph. The process is iterated on the critical path until there ate no wires on the current critical path, or there is not enough room to introduce any jog for wires on the current critical path. MACS redetetmines the critical path after each jog is inserted in an incremental, event-driven approach. The h%ACS compactor produces very good area results quickly with the use of event driven minimizea wire length. The MACS algorithms. It also effectively compactor, however, requites a large amount of memory. MACS also was not capable of pit&matching modules with arrayed instances at the time of the benchmark session. Ihe ZORRO compactor [SHI87], overall, produced the smallest area results. Ibis was achieved by using the local twodimensional compaction which resulted ia the introductJon of many jogs in wires. The draw back to this approach is the long ran time that is required. The Symbolics compactor is a virtual grid compactor that automatically offsets contacts. The strengths of this compactor ate its speed and its ability to handle large designs. It was the only compactor that participated in the session that could compact the 16x16 multiplier. The symbolics compactor was also used in the design of the 390,000 transistor Symbolics ivory LISP Processor [BAK87]. The SPARCS compactor is a hierarchical compactor that is designed to compact modules that consist of f&d modules of varied shapes and wires. An example should have been included in the benchmark set that was a block style layout to demonstrate this. A block style layout is a cell composed of modules of 6xed and varied sizes connected with routing wires. The abutted cells in the benchmark set had to be pit&matched by hand for SPARCS to compact them. The results produced by the SPARCS compactor were good and the efficiency of its hierarchical approach is seen by its fast run times. S. Conclusion There is currently a resurgence of interest in symbolic layout aud compaction with the recent or imminent introduction of a number of commercial symbolic layout systems @CAD, SDA, SCS, etc.). Symbolic layout and compaction has reached a relative1y mature stage; compacted results can be generated quickly and the compacted areas are quite good. The advantage of introducing jogs in wires can be seen from the results of the ICCD87 compaction benchmark session. While compaction is relatively mature, there ate still many areas that ate actively being researched. These areas include reduction of compaction run times, improved area efficiency, wire minimization. enhanced pit&matching aud hierarchical compaction schemes, and compaction for circuit perfomuauce, 6. Acknowledgements Deborah Rappaport assisted in preparing tbis paper in her usual expert fashion. I also would like to thank Jeff Burns for his comments and correctioas, his insights were very helpful and timely.

Example ~Compactor

-=

afa

143 x 157 x 160 x 140.5

Area (microns) 166=23738 180=28260 189=30240 x 171=24025.5

CPU w-4 9 11 52 430

Memory

MACS SPARCS Symbolics zorro ~~- afavg MACS SPARCS Symbolias zotlu ___~- Cl32 MACS SPARCS Symbol&

145QK 356K 164K 647K

142x145=20590 157x151=23707 154 x 154=23716 128.5 x 151=19403.5 627 x 354=221958 685 x 339=232215 675 x 330=222750 660~3223212520 309 x 252=7786a 343 x 255-87465 370 x 270=99900 312x252=78624 649 x 601=390049 654 x 638A17252 577 x 577.51333217.5 1285 x 1285=1651225 1276 x 1352=1725152 1138 x 1207.5=1374135 2524x2780=7016720 16 47 10 838 66 54 1904 89 245 11738 1 1073 205OK 215K 512K 614K 754K 840K 741K 2066K 32OOK 7754K ) 14400K 1

zkro ___-

~-mul2x2 MACS SPARCS Symbol& ~-mttl4x4 SPARCS Symbol&l zurro ~mttRtxl? ___SPARCS Symbol&
ZAXTO ~mttD6x16 ~Symbolics ~-

Table 1. Compsctioa beacbmti results. The area is in microns square preceded by the x and y dimension. Run times for the compactoru are reported for running on I VAX 8650. The memory usage is the peak memory needed for a g&n comp+ztor to compact an utampk. No two netlists for the Cl32 example wcpc the same.

7. References [ACK83] B. Ackland and N. Weste, An Automatic Assembly Tool for Vittual Grid Symbolic Layout, Proc, VLSI 83 (Trondheim), pp 457-466, Jan. 1983. [AKEI70] S.B. Akers, J.M. Geyer, and D.L. Roberts, IC hIask Layout with a Sit& Conductor Layer, Pmt. of the 7th Design Automation Conference, pp 7-16, June 1970. IBAI.821 M.W. Bales, Layout Rule Spacing of SymboIic Integrated Circuit Artwork, BRL Memo No. UCB/ERL M82/72, Univemity of CaIifomia, Berkeley, May 1982. lBAK87] C. Baker et al. The Symbolics Ivory Processor: a 40 Bit Tagged Architecture Lisp Microprocessor, Proc. of the IEEE Intematiomd Confereace oa Computer Design, pp 512515, Sept. 1983. [BOY831 D.G. Boyer and N. Weste, Virtual Grid Compaction using the Most Recejmt Layers Algorithm, Proc. of the IEEE International Conference 1011 Computer-Aided Design, pp 92-93, Sept. 1983. [BOY87a] D.G. Boyer, Split Grid Compaction for a Virtual Grid Symbolic Design System, Proc. of the IEBE International Conference on ComputerAided Design, pp 134-137, Nov. 1987.

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[BOY87b] D.G. Bayer, Symbolic Layout Compaction Benchmarks Intrvduuio~~ and Ground Rules, Proc. of the IBBE IntemationsI Conferenceon Computer De&n, pp 186191, Oct. 1987. [BOY87c] D.G. Boyer, Symbolic Layout Compaction Benchmarks Results, Proc. of the IBBB Iuternational Conference on Computer Design, pp 209-217, Oct. 1987. pUR86] J. Bums and AR. Newton, SPARCS: A New Constraint-Based IC Symbolic Layout Spacer, Proc. of the IEBB Custom Iotegrated Circuits
Confemce, pp 534-539, May 1986. [BUR87] J.L. Burns and A.R. Newton, Efficient Constraint Generation for

Himbical Compaction, Proc. of the IBBB InternationaI Conference on Computer Design, pp 197-200,Oct. 1987. [CAR871 C.W. Carpenter and M. Horowitz, Generatin Incremental VLSI Compaction Spacing Constraints, Proc. of the 2% Design Automation Conference,pp 291-297, June 1987. [CHO77] Y.E. Cho, A.J. Komnjak, and D.E. Stockton, FLOSS: An Approach to Automated Layout for High-Volume Designs, Proc. of the 141-b Design Automation Confemnce,pp 138-141,June 1977. [CHO85] Y.E. Cho, A Subjective Review of Compaction, Proc. of the ACM/lE@B 22nd Design Automation Conference,pp 396-404,June 1985. [CR0871 W.H. Cracker, C.Y. Lo, sud R. Varadarahan, MACS: a Module Assembly and Compaction System, Proc. of the IRE83 Internationl Conference on Computer Design, pp 205208, Oct. 1987. pEU85] D.N. Deutscb, Compacted Channel Routing, Proc. of the IBBE Intemational Conference on Computer-Aided Design, pp 223-225, Nov 1985. PO851 J. Do and W.M. Dawson, Spacer II: A Well-Behaved IC Layout Compactor, Proc. VLSI 85 International Conference, Tokyo, Japan pp 277-285, August 1985. pUN803 A.E. Dunlop, SLIM - The translation of Symbolic Layouts into Mask Data, Proc. of the 17th Design Automation Conference, June 1980, pp 595.602. @If!861 P. Bichenberger, Fast Symbolic Layout Translation for Custom VLSI Integrated Circuits, PhD thesis, Stanford University, March 1986. @NT851 G. Entenman and S.W. Daniel, A Pully Automatic Hierarchical Compactor, Proc. 22nd Design Automation Conference, pp 69-75, June 198% WY863 G.A. Hayward, A.M. Gottlieb, D.G. Boyer, T.J. Robe, and J.E. Berthold, High Speed CMOS Switching - A 16 X 16 Crosspoint Chip and SUppoN Functivns, 1986 International Zurich Seminar on Digital Communications,March 11,1986. HIBDSS] T. Hedges, W. Dawson, and Y. E. Cho, Bitmap Graph Build Algorithm for Compaction, Proc. of the IBBB International Conlbrence on Computer-Aided Design, pp 340-342, Nov. 1985. [HsU79] M.Y. Hsueh and D.O. Pederson,Computer-Aided Layout of LSI Circuit Building-Blocks, PhD Thesis, UCB/BRL M79/80, Univetuity of California at Berkeley, Dee 1979. lKBD84] G. Kedem and H. Watanabe, Graph Optimazation Techniques fro IC Layout and Compaction, IEBB Trans. on CAD of ICs Vo1.3,No.1, January 1984. -841 K.H. Keller, An Electronic Circuit CAD Framework, BRL Memo No. UCB/BRL M84/54, University of CaIifomia, Berkeley, July 1984. [KIN821 C. Kingsley, Barb An Integrated Circuit Design Language, Masters Thesis, Cahf. Institute of Tech., June 1982. [KIN841 C. Kingsley, A Hierarchical, Broor-Tolerant Compactor, proc. 2lSt Design Automation Conference,pp 126132, June 1984. [KOL861P- K~llarits~h and B. A~klaod, COORDJNATOR: A Complete Design-Rule Bnforccd Layout Methodology, proc. of the IBBB International COnfeIWXe on Computer Design, Oct. 1986. [LEN831 T. Lengauer, Efficient Algorithms for the Constraint Generation for Integrated Circuit Layout Compactiou, P, 9th Wodcshop on GrsiphtheoreticConceptsin Computer Science,June 1983. ILIAW Y.Z. Liao and C.K. Wong, An Algorithm fo Compact a VLSI SYmbofiCbYOUt With Mixed Constraints, IEEE Tmns. on CAD of It& Vol CAD-2 no. 2, pp 62-69. April 1983. m5] P.M. Maley, Compaction with Automatic Jog Introduction,

Chapel Hill VLSI Conference,pp 261-283,1985. wOS87] R.C. MosteIler, A.H. Prey, and R. Suaya, 2-D Compaction, a Monte Carlo Method, Advanced Research in VLSI Stanford 1987. pp 173-197. @EIW87] A.R. Newton, Symbolic Layout and Procedural Design, Design Systems for VLSI Circuits Logic Synthesis and Silicon Compilation, G. DeMicheli, A. Sangiovsnoi-VincenteIli and P. Antognetti Ed, pp 65-112, 1987. piYL87] L.S. Nyland, S.W. Daniel, aud D. Rodgers, Improving VhtualGrid Compaction Through Grouping, Proc. of the 24th IBBWACM Des@ Automation Conference,June 1987. [RB186] M.W. Reichelt and W.H. Wolf, An Improved Model for Hierarchical Constraint-Graph Compaction, Pnx. of the IBBB International Conference on Computer-Aided Design, pp 482-485, Sept. 1985. m87] M.W. Reich&, An Improved Cell Model for Hierarchical Layout Compaction, MS report, Msssachusetts Institute of Technology, May 1987. [SCH83] W.L. Schiele, Improved COmpaction by Minimized Length of Wires, Proc. 26th ACM/BBBI Design Automation Conference, pp 121127, June 1983. [SHE34 H. Shin, A. Sangiovatmi-Vincentelli, and C. Sequin, TwoDimensional Compaction by Zone Retinhtg. Proc. 23rd ACM/IBBE Design Automation Conference,pp 115-122,June 1986. [SHt87] H. Shin, A.L. Sangiovani-Vinccntelh, and C.H. Sequin, TwoDimensional Module Compactor Based on Zone-Relining, Proc. of the IBBE International Conference on Computer Des&u, pp 201-204, Oct.
1987. FAN871 D. Tan and N.H.E. Weste, Virtual Grid Symbolic Layout 1987,

Proc. of the IBEE International Conference on Computer Design, pp 192196, Oct. 1987. wAT84] H. Watanabe, IC Layout Generation and Compaction Using Mathematical Optimization, PhD Thesis, University of Rochester, 1984. IWESIl] N. Weste, Virtual Grid Symbolic Layout, Proc. 18th ACM/IBBB Design Automation Conference,pp 225-233. wOL83] W. Wolf, R. Mathews, J. Newkirk, and R. Dutton, TwoDimensional Compaction Strategies. Proc. of the IBBB International Conference on Computer-Aided Design, pp 90-91, Sept 1983. wOL85] W. Wolf, An Experimental Comparison of 1-D Compaction Algorithms, Qtapel I-MI VLSI Cvnfexmce, pp 165-180.1985. wOL86] W. Wolf, Sticks Compaction and Assembly, IBBB Design & Test of Computers,pp 57-63, June 1986. mO87] X.M. Xiong and B.S. Kuh, Nutcracker: Au Efficient and Intelligent Channel Spacer, Pmt. 24th ACM/IEEE Design Automation Conference,pp 298-304.

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