Release 14.5 - xst P.

58f (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.59 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.59 secs
--> Reading design: aes_192.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
*
Synthesis Options Summary
*
=========================================================================
---- Source Parameters
Input File Name
: "aes_192.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name
Output Format
Target Device

: "aes_192"
: NGC
: xc7vx330t-1-ffg1157

---- Source Options

Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm
Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction
Shift Register Extraction

:
:
:
:
:
:
:
:
:

aes_192
YES
Auto
No
LUT
Yes
Auto
Yes
YES

ROM Style
Resource Sharing
Asynchronous To Synchronous
Shift Register Minimum Size
Use DSP Block
Automatic Register Balancing

:
:
:
:
:
:

Auto
YES
NO
2
Auto
No

---- Target Options

LUT Combining
Reduce Control Sets
Add IO Buffers
Global Maximum Fanout
Add Generic Clock Buffer(BUFG)
Register Duplication
Optimize Instantiated Primitives
Use Clock Enable
Use Synchronous Set
Use Synchronous Reset
Pack IO Registers into IOBs
Equivalent register Removal

:
:
:
:
:
:
:
:
:
:
:
:

Auto
Auto
YES
100000
32
YES
NO
Auto
Auto
Auto
Auto
YES

---- General Options

Optimization Goal
Optimization Effort
Power Reduction
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
Hierarchy Separator
Bus Delimiter
Case Specifier
Slice Utilization Ratio
BRAM Utilization Ratio
DSP48 Utilization Ratio
Auto BRAM Packing
Slice Utilization Ratio Delta

:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:

Speed
1
NO
No
As_Optimized
Yes
AllClockNets
YES
NO
NO
/
<>
Maintain
100
100
100
NO
5

=========================================================================
=========================================================================
*
HDL Parsing
*
=========================================================================
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\xS.v" into library wo
rk
Parsing module <xS>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\S.v" into library wor
k
Parsing module <S>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\T.v" into library wor
k
Parsing module <T>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\table_lookup.v" into
library work
Parsing module <table_lookup>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\S4.v" into library wo

rk
Parsing module <S4>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\one_round.v" into lib
rary work
Parsing module <one_round>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\final_round.v" into l
ibrary work
Parsing module <final_round>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_D_192
.v" into library work
Parsing module <expand_key_type_D_192>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_C_192
.v" into library work
Parsing module <expand_key_type_C_192>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_B_192
.v" into library work
Parsing module <expand_key_type_B_192>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_A_192
.v" into library work
Parsing module <expand_key_type_A_192>.
Analyzing Verilog file "C:\Users\Admin1\Desktop\AESDES\pri\aes_192.v" into libra
ry work
Parsing module <aes_192>.
=========================================================================
*
HDL Elaboration
*
=========================================================================
Elaborating module <aes_192>.
Elaborating module <expand_key_type_D_192>.
Elaborating module <S4>.
Elaborating module <S>.
Elaborating module <expand_key_type_B_192>.
Elaborating module <expand_key_type_A_192>.
Elaborating module <expand_key_type_C_192>.
Elaborating module <one_round>.
Elaborating module <table_lookup>.
Elaborating module <T>.
Elaborating module <xS>.
Elaborating module <final_round>.
=========================================================================
*
HDL Synthesis
*
=========================================================================
Synthesizing Unit <aes_192>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\aes_192.v".
INFO:Xst:3210 - "C:\Users\Admin1\Desktop\AESDES\pri\aes_192.v" line 29: Output p
ort <out_1> of the instance <a11> is unconnected or connected to loadless signal

.
Found 192-bit register for signal <k0>.
Found 128-bit register for signal <s0>.
Summary:
inferred 320 D-type flip-flop(s).
Unit <aes_192> synthesized.
Synthesizing Unit <expand_key_type_D_192>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_D
_192.v".
Found 32-bit register for signal <k4a>.
Found 32-bit register for signal <k3a>.
Found 32-bit register for signal <k2a>.
Found 32-bit register for signal <k1a>.
Found 32-bit register for signal <k0a>.
Found 192-bit register for signal <out_1>.
Found 32-bit register for signal <k5a>.
Summary:
inferred 384 D-type flip-flop(s).
Unit <expand_key_type_D_192> synthesized.
Synthesizing Unit <S4>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\S4.v".
Summary:
no macro.
Unit <S4> synthesized.
Synthesizing Unit <S>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\S.v".
Found 8-bit register for signal <out>.
Found 256x8-bit Read Only RAM for signal <in[7]_GND_4_o_wide_mux_1_OUT>
Summary:
inferred 1 RAM(s).
inferred 8 D-type flip-flop(s).
Unit <S> synthesized.
Synthesizing Unit <expand_key_type_B_192>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_B
_192.v".
Found 32-bit register for signal <k4a>.
Found 32-bit register for signal <k3a>.
Found 32-bit register for signal <k2a>.
Found 32-bit register for signal <k1a>.
Found 32-bit register for signal <k0a>.
Found 192-bit register for signal <out_1>.
Found 32-bit register for signal <k5a>.
Summary:
inferred 384 D-type flip-flop(s).
Unit <expand_key_type_B_192> synthesized.
Synthesizing Unit <expand_key_type_A_192>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_A
_192.v".
Found 32-bit register for signal <k4a>.
Found 32-bit register for signal <k3a>.
Found 32-bit register for signal <k2a>.
Found 32-bit register for signal <k1a>.
Found 32-bit register for signal <k0a>.
Found 192-bit register for signal <out_1>.
Found 32-bit register for signal <k5a>.

Summary:
inferred 384 D-type flip-flop(s).
Unit <expand_key_type_A_192> synthesized.
Synthesizing Unit <expand_key_type_C_192>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\expand_key_type_C
_192.v".
Found 32-bit register for signal <k4a>.
Found 32-bit register for signal <k3a>.
Found 32-bit register for signal <k2a>.
Found 32-bit register for signal <k1a>.
Found 32-bit register for signal <k0a>.
Found 192-bit register for signal <out_1>.
Found 32-bit register for signal <k5a>.
Summary:
inferred 384 D-type flip-flop(s).
Unit <expand_key_type_C_192> synthesized.
Synthesizing Unit <one_round>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\one_round.v".
Found 128-bit register for signal <state_out>.
Summary:
inferred 128 D-type flip-flop(s).
Unit <one_round> synthesized.
Synthesizing Unit <table_lookup>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\table_lookup.v".
Summary:
no macro.
Unit <table_lookup> synthesized.
Synthesizing Unit <T>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\T.v".
Summary:
Unit <T> synthesized.
Synthesizing Unit <xS>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\xS.v".
Found 8-bit register for signal <out>.
Found 256x8-bit Read Only RAM for signal <in[7]_GND_11_o_wide_mux_1_OUT>
Summary:
inferred 1 RAM(s).
inferred 8 D-type flip-flop(s).
Unit <xS> synthesized.
Synthesizing Unit <final_round>.
Related source file is "C:\Users\Admin1\Desktop\AESDES\pri\final_round.v".
Found 128-bit register for signal <state_out>.
Summary:
inferred 128 D-type flip-flop(s).
Unit <final_round> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs
256x8-bit single-port Read Only RAM
# Registers
128-bit register

:
:
:
:

400
400
478
13

192-bit register
32-bit register
8-bit register
# Xors
128-bit xor2
32-bit xor2
32-bit xor5
8-bit xor2

:
:
:
:
:
:
:
:

17
48
400
295
1
66
44
184

=========================================================================
=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677

- Node <out_1_32> of sequential type is unconnected in block <a

- Node <out_1_33> of sequential type is unconnected in block <a
- Node <out_1_34> of sequential type is unconnected in block <a
- Node <out_1_35> of sequential type is unconnected in block <a
- Node <out_1_36> of sequential type is unconnected in block <a
- Node <out_1_37> of sequential type is unconnected in block <a
- Node <out_1_38> of sequential type is unconnected in block <a
- Node <out_1_39> of sequential type is unconnected in block <a
- Node <out_1_40> of sequential type is unconnected in block <a
- Node <out_1_41> of sequential type is unconnected in block <a
- Node <out_1_42> of sequential type is unconnected in block <a
- Node <out_1_43> of sequential type is unconnected in block <a
- Node <out_1_44> of sequential type is unconnected in block <a
- Node <out_1_45> of sequential type is unconnected in block <a
- Node <out_1_46> of sequential type is unconnected in block <a
- Node <out_1_47> of sequential type is unconnected in block <a
- Node <out_1_48> of sequential type is unconnected in block <a
- Node <out_1_49> of sequential type is unconnected in block <a
- Node <out_1_50> of sequential type is unconnected in block <a
- Node <out_1_51> of sequential type is unconnected in block <a
- Node <out_1_52> of sequential type is unconnected in block <a
- Node <out_1_53> of sequential type is unconnected in block <a
- Node <out_1_54> of sequential type is unconnected in block <a

10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.
WARNING:Xst:2677
10>.

- Node <out_1_55> of sequential type is unconnected in block <a

- Node <out_1_56> of sequential type is unconnected in block <a
- Node <out_1_57> of sequential type is unconnected in block <a
- Node <out_1_58> of sequential type is unconnected in block <a
- Node <out_1_59> of sequential type is unconnected in block <a
- Node <out_1_60> of sequential type is unconnected in block <a
- Node <out_1_61> of sequential type is unconnected in block <a
- Node <out_1_62> of sequential type is unconnected in block <a
- Node <out_1_63> of sequential type is unconnected in block <a

Synthesizing (advanced) Unit <aes_192>.

INFO:Xst:3226 - The RAM <r11/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<103:96>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t2/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t1/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|

----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t2/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p12>
|
|

----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t1/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t2/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
-----------------------------------------------------------------------

| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t1/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p33>
|
|
-----------------------------------------------------------------------

| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t2/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t1/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t0/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|

|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t3/t3/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|

----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b

e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t0/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t2/t3/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|

|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t0/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
-----------------------------------------------------------------------

INFO:Xst:3226 - The RAM <r11/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b

e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t1/t3/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t0/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|

|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r11/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r11/t0/t3/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s10<103:96>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r11/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t2/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t1/s0/

out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t2/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|

|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t1/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t2/s0/

out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t1/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t3/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|

|
addrA
| connected to signal <s9<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t2/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t1/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t0/s0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t0/s4
/out>

----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t3/t3/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<7:0>>
|
|

|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t0/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t2/t3/s4
/out>
-----------------------------------------------------------------------

| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t0/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|

|
doA
| connected to signal <r10/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t1/t3/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t0/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t1/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t2/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|

----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r10/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will b
e implemented as a BLOCK RAM, absorbing the following register(s): <r10/t0/t3/s4
/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s9<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r10/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p02>
|
|

----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
-----------------------------------------------------------------------

| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p23>
|
|
-----------------------------------------------------------------------

| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|

|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|

----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|

|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
-----------------------------------------------------------------------

INFO:Xst:3226 - The RAM <r9/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r9/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|

|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t2/s4/o

ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r9/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r9/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s8<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r9/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|

|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t2/s0/ou

t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|

|
addrA
| connected to signal <s7<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t3/s0/ou
t>

----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<31:24>>
|
|

|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t3/t3/s4/o
ut>
-----------------------------------------------------------------------

| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|

|
doA
| connected to signal <r8/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|

----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p01>
|
|

----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r8/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r8/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s7<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r8/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
-----------------------------------------------------------------------

| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p13>
|
|
-----------------------------------------------------------------------

| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|

|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|

----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|

|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
-----------------------------------------------------------------------

INFO:Xst:3226 - The RAM <r7/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r7/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|

|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t2/s4/o

ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|

|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r7/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r7/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s6<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r7/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t2/s0/ou

t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|

|
addrA
| connected to signal <s5<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t3/s0/ou
t>

----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<63:56>>
|
|

|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t0/s0/ou
t>
-----------------------------------------------------------------------

| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|

|
doA
| connected to signal <r6/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|

----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p11>
|
|

----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
-----------------------------------------------------------------------

| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r6/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r6/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s5<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r6/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p03>
|
|
-----------------------------------------------------------------------

| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|

|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|

----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|

|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
-----------------------------------------------------------------------

INFO:Xst:3226 - The RAM <r5/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|

|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t2/s4/o

ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|

|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t1/s4/o

ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r5/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r5/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s4<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r5/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|

|
addrA
| connected to signal <s3<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t3/s0/ou
t>

----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<95:88>>
|
|

|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t0/s0/ou
t>
-----------------------------------------------------------------------

| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|

|
doA
| connected to signal <r4/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|

----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p21>
|
|

----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
-----------------------------------------------------------------------

| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p00>
|
|
-----------------------------------------------------------------------

| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r4/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r4/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s3<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r4/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|

|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|

----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|

|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
-----------------------------------------------------------------------

INFO:Xst:3226 - The RAM <r3/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|

|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t2/s4/o

ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|

|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t1/s4/o

ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|

|
addrA
| connected to signal <s2<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r3/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r3/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s2<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r3/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t3/s0/ou
t>

----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<127:120>> |
|

|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t0/s0/ou
t>
-----------------------------------------------------------------------

| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|

|
doA
| connected to signal <r2/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|

----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p31>
|
|

----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
-----------------------------------------------------------------------

| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p10>
|
|
-----------------------------------------------------------------------

| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|

|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r2/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r2/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s1<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r2/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|

----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<103:96>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|

|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
-----------------------------------------------------------------------

INFO:Xst:3226 - The RAM <r1/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t1/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|

|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t3/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t2/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t1/s0/ou

t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t0/s0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p30>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|

|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p31>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p32>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t3/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p33>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p20>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t1/s4/o

ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p21>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p22>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t2/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p23>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t0/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|

|
addrA
| connected to signal <s0<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p10>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p11>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p12>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t1/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p13>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t0/s4/o
ut>

----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p00>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t1/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p01>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t2/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p02>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <r1/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <r1/t0/t3/s4/o
ut>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s0<103:96>>
|
|

|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <r1/p03>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a0/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a0/S4_0/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k0<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a0/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a0/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a0/S4_0/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k0<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a0/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a0/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a0/S4_0/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k0<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a0/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a0/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a0/S4_0/S_0/ou
t>
-----------------------------------------------------------------------

| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k0<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a0/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_4/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_4/S_0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_4/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_4/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_4/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_4/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|

|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_4/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_4/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_3/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_3/S_0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<63:56>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_3/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_3/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<55:48>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_3/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_3/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|

----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<47:40>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_3/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_3/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<39:32>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_2/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_2/S_0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<95:88>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_2/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_2/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<87:80>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|

----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_2/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_2/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<79:72>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_2/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_2/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<71:64>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_1/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_1/S_0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<127:120>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_1/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_1/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
-----------------------------------------------------------------------

| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<119:112>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_1/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_1/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<111:104>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <rf/S4_1/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <rf/S4_1/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <s11<103:96>> |
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to internal node
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a11/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a11/S4_0/S_0/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k11<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a11/k6a>
|
|
-----------------------------------------------------------------------

| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a11/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a11/S4_0/S_1/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k11<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a11/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a11/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a11/S4_0/S_2/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k11<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a11/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a11/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a11/S4_0/S_3/
out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k11<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a11/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a8/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a8/S4_0/S_0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|

|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k8<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a8/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a8/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a8/S4_0/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k8<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a8/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a8/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a8/S4_0/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k8<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a8/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a8/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a8/S4_0/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k8<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a8/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|

----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a5/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <a5/S4_0/S_0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k5<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a5/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a5/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a5/S4_0/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k5<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a5/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a5/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a5/S4_0/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k5<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a5/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a5/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a5/S4_0/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|

|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k5<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a5/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a2/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a2/S4_0/S_0/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k2<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a2/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a2/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a2/S4_0/S_1/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k2<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a2/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <a2/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be
implemented as a BLOCK RAM, absorbing the following register(s): <a2/S4_0/S_2/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k2<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a2/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
-----------------------------------------------------------------------

INFO:Xst:3226 - The RAM <a2/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be

implemented as a BLOCK RAM, absorbing the following register(s): <a2/S4_0/S_3/ou
t>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <k2<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <a2/k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------Unit <aes_192> synthesized (advanced).
Synthesizing (advanced) Unit <expand_key_type_C_192>.
INFO:Xst:3226 - The RAM <S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be imp
lemented as a BLOCK RAM, absorbing the following register(s): <S4_0/S_3/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <v5<31:24>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be imp
lemented as a BLOCK RAM, absorbing the following register(s): <S4_0/S_2/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <v5<7:0>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be imp
lemented as a BLOCK RAM, absorbing the following register(s): <S4_0/S_1/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|

|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <v5<15:8>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------INFO:Xst:3226 - The RAM <S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> will be imp
lemented as a BLOCK RAM, absorbing the following register(s): <S4_0/S_0/out>
----------------------------------------------------------------------| ram_type
| Block
|
|
----------------------------------------------------------------------| Port A
|
|
aspect ratio | 256-word x 8-bit
|
|
|
mode
| write-first
|
|
|
clkA
| connected to signal <clk>
| rise
|
|
weA
| connected to signal <GND>
| high
|
|
addrA
| connected to signal <v5<23:16>>
|
|
|
diA
| connected to signal <GND>
|
|
|
doA
| connected to signal <k6a>
|
|
----------------------------------------------------------------------| optimization
| speed
|
|
----------------------------------------------------------------------Unit <expand_key_type_C_192> synthesized (advanced).
WARNING:Xst:2677 - Node <a10/out_1_32> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_33> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_34> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_35> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_36> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_37> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_38> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_39> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_40> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_41> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_42> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_43> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_44> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_45> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_46> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_47> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_48> of sequential type is unconnected in bloc
k <aes_192>.
WARNING:Xst:2677 - Node <a10/out_1_49> of sequential type is unconnected in bloc

k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.
WARNING:Xst:2677
k <aes_192>.

- Node <a10/out_1_50> of sequential type is unconnected in bloc

- Node <a10/out_1_51> of sequential type is unconnected in bloc
- Node <a10/out_1_52> of sequential type is unconnected in bloc
- Node <a10/out_1_53> of sequential type is unconnected in bloc
- Node <a10/out_1_54> of sequential type is unconnected in bloc
- Node <a10/out_1_55> of sequential type is unconnected in bloc
- Node <a10/out_1_56> of sequential type is unconnected in bloc
- Node <a10/out_1_57> of sequential type is unconnected in bloc
- Node <a10/out_1_58> of sequential type is unconnected in bloc
- Node <a10/out_1_59> of sequential type is unconnected in bloc
- Node <a10/out_1_60> of sequential type is unconnected in bloc
- Node <a10/out_1_61> of sequential type is unconnected in bloc
- Node <a10/out_1_62> of sequential type is unconnected in bloc
- Node <a10/out_1_63> of sequential type is unconnected in bloc

=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs
256x8-bit single-port block Read Only RAM
# Registers
Flip-Flops
# Xors
128-bit xor2
32-bit xor2
32-bit xor5
8-bit xor2

:
:
:
:
:
:
:
:
:

400
400
6176
6176
295
1
66
44
184

=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r11/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r11/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r11/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si

ngle block RAM <r11/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r11/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r11/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r11/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r11/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r11/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r11/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r11/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r11/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the

single block RAM <r10/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <r10/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r10/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r10/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r10/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r10/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r10/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r10/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r10/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r10/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mu
x_1_OUT>, <r10/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the
single block RAM <r10/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r9/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r9/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r9/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r9/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r9/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si

ngle block RAM <r9/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r9/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r9/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r9/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r9/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r9/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r9/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r8/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r8/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r8/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r8/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r8/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r8/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r8/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r8/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r8/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r8/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r8/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si

ngle block RAM <r8/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r7/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r7/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r6/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r7/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r7/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r7/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r6/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r6/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing

le block RAM <r6/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r6/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r6/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r6/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r6/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r6/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r6/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r6/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r6/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r5/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r5/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r5/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r5/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r5/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r5/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r5/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r5/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing

le block RAM <r5/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r5/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r5/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r5/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r4/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r4/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r4/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r4/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r4/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si

ngle block RAM <r4/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r4/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r4/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r4/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r4/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r4/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r4/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r3/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r3/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r3/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r3/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r3/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r3/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r3/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r3/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r3/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r3/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r3/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si

ngle block RAM <r3/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r2/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r2/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r2/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r2/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r2/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t0/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r1/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t0/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r1/t1/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t1/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r1/t0/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t1/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing

le block RAM <r1/t1/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t2/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r1/t2/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t3/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r1/t2/t2/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t3/t3/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r1/t2/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t3/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t3/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <r1/t3/t0/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <r1/t3/t1/s0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t3/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t3/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t2/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t2/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t1/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t2/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t1/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t2/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t1/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t0/t0/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t0/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t1/t3/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <r1/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux
_1_OUT>, <r1/t0/t2/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <r1/t0/t1/s4/Mram_in[7]_GND_11_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a0/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a0/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a0/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a0/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_4/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a0/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a0/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_4/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a0/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <rf/S4_3/S_0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_4/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <rf/S4_3/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <rf/S4_4/S_3/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_3/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <rf/S4_4/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <rf/S4_3/S_1/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_3/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <rf/S4_3/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <rf/S4_2/S_2/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_2/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <rf/S4_2/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <rf/S4_2/S_1/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_1/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing

le block RAM <rf/S4_2/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>

INFO:Xst:2697 - Unit <MTP_> : the RAMs <rf/S4_2/S_3/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <rf/S4_1/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <rf/S4_2/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a11/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <rf/S4_1/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sin
gle block RAM <a11/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <rf/S4_1/S_3/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a11/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sin
gle block RAM <rf/S4_1/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a11/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux
_1_OUT>, <a11/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the si
ngle block RAM <a11/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a8/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a8/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a8/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a8/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a5/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a8/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a8/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a5/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a8/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a2/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a5/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a2/S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a5/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a2/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a5/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <a2/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_
1_OUT>, <a2/S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the sing
le block RAM <a2/S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_O
UT>, <S4_0/S_2/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the single blo
ck RAM <S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
INFO:Xst:2697 - Unit <MTP_> : the RAMs <S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_O
UT>, <S4_0/S_0/Mram_in[7]_GND_4_o_wide_mux_1_OUT> are packed into the single blo
ck RAM <S4_0/S_1/Mram_in[7]_GND_4_o_wide_mux_1_OUT1>
Optimizing unit <aes_192> ...
Optimizing unit <expand_key_type_C_192> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block aes_192, actual ratio is 4.
Final Macro Processing ...
Processing Unit <aes_192>
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift

:
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a0/k4a_0>.
<a0/k4a_1>.
<a0/k4a_2>.
<a0/k4a_3>.
<a0/k4a_4>.
<a0/k4a_5>.
<a0/k4a_6>.
<a0/k4a_7>.
<a0/k4a_8>.
<a0/k4a_9>.
<a0/k4a_10>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a0/k4a_11>.
<a0/k4a_12>.
<a0/k4a_13>.
<a0/k4a_14>.
<a0/k4a_15>.
<a0/k4a_16>.
<a0/k4a_17>.
<a0/k4a_18>.
<a0/k4a_19>.
<a0/k4a_20>.
<a0/k4a_21>.
<a0/k4a_22>.
<a0/k4a_23>.
<a0/k4a_24>.
<a0/k4a_25>.
<a0/k4a_26>.
<a0/k4a_27>.
<a0/k4a_28>.
<a0/k4a_29>.
<a0/k4a_30>.
<a0/k4a_31>.
<a0/out_1_64>.
<a0/out_1_65>.
<a0/out_1_66>.
<a0/out_1_67>.
<a0/out_1_68>.
<a0/out_1_69>.
<a0/out_1_70>.
<a0/out_1_71>.
<a0/out_1_72>.
<a0/out_1_73>.
<a0/out_1_74>.
<a0/out_1_75>.
<a0/out_1_76>.
<a0/out_1_77>.
<a0/out_1_78>.
<a0/out_1_79>.
<a0/out_1_80>.
<a0/out_1_81>.
<a0/out_1_82>.
<a0/out_1_83>.
<a0/out_1_84>.
<a0/out_1_85>.
<a0/out_1_86>.
<a0/out_1_87>.
<a0/out_1_88>.
<a0/out_1_89>.
<a0/out_1_90>.
<a0/out_1_91>.
<a0/out_1_92>.
<a0/out_1_93>.
<a0/out_1_94>.
<a0/out_1_95>.
<a0/out_1_96>.
<a0/out_1_97>.
<a0/out_1_98>.
<a0/out_1_99>.
<a0/out_1_100>.
<a0/out_1_101>.
<a0/out_1_102>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a0/out_1_103>.
<a0/out_1_104>.
<a0/out_1_105>.
<a0/out_1_106>.
<a0/out_1_107>.
<a0/out_1_108>.
<a0/out_1_109>.
<a0/out_1_110>.
<a0/out_1_111>.
<a0/out_1_112>.
<a0/out_1_113>.
<a0/out_1_114>.
<a0/out_1_115>.
<a0/out_1_116>.
<a0/out_1_117>.
<a0/out_1_118>.
<a0/out_1_119>.
<a0/out_1_120>.
<a0/out_1_121>.
<a0/out_1_122>.
<a0/out_1_123>.
<a0/out_1_124>.
<a0/out_1_125>.
<a0/out_1_126>.
<a0/out_1_127>.
<a1/out_1_128>.
<a1/out_1_129>.
<a1/out_1_130>.
<a1/out_1_131>.
<a1/out_1_132>.
<a1/out_1_133>.
<a1/out_1_134>.
<a1/out_1_135>.
<a1/out_1_136>.
<a1/out_1_137>.
<a1/out_1_138>.
<a1/out_1_139>.
<a1/out_1_140>.
<a1/out_1_141>.
<a1/out_1_142>.
<a1/out_1_143>.
<a1/out_1_144>.
<a1/out_1_145>.
<a1/out_1_146>.
<a1/out_1_147>.
<a1/out_1_148>.
<a1/out_1_149>.
<a1/out_1_150>.
<a1/out_1_151>.
<a1/out_1_152>.
<a1/out_1_153>.
<a1/out_1_154>.
<a1/out_1_155>.
<a1/out_1_156>.
<a1/out_1_157>.
<a1/out_1_158>.
<a1/out_1_159>.
<a1/out_1_160>.
<a1/out_1_161>.
<a1/out_1_162>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a1/out_1_163>.
<a1/out_1_164>.
<a1/out_1_165>.
<a1/out_1_166>.
<a1/out_1_167>.
<a1/out_1_168>.
<a1/out_1_169>.
<a1/out_1_170>.
<a1/out_1_171>.
<a1/out_1_172>.
<a1/out_1_173>.
<a1/out_1_174>.
<a1/out_1_175>.
<a1/out_1_176>.
<a1/out_1_177>.
<a1/out_1_178>.
<a1/out_1_179>.
<a1/out_1_180>.
<a1/out_1_181>.
<a1/out_1_182>.
<a1/out_1_183>.
<a1/out_1_184>.
<a1/out_1_185>.
<a1/out_1_186>.
<a1/out_1_187>.
<a1/out_1_188>.
<a1/out_1_189>.
<a1/out_1_190>.
<a1/out_1_191>.
<a2/out_1_0>.
<a2/out_1_1>.
<a2/out_1_2>.
<a2/out_1_3>.
<a2/out_1_4>.
<a2/out_1_5>.
<a2/out_1_6>.
<a2/out_1_7>.
<a2/out_1_8>.
<a2/out_1_9>.
<a2/out_1_10>.
<a2/out_1_11>.
<a2/out_1_12>.
<a2/out_1_13>.
<a2/out_1_14>.
<a2/out_1_15>.
<a2/out_1_16>.
<a2/out_1_17>.
<a2/out_1_18>.
<a2/out_1_19>.
<a2/out_1_20>.
<a2/out_1_21>.
<a2/out_1_22>.
<a2/out_1_23>.
<a2/out_1_24>.
<a2/out_1_25>.
<a2/out_1_26>.
<a2/out_1_27>.
<a2/out_1_28>.
<a2/out_1_29>.
<a2/out_1_30>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a2/out_1_31>.
<a2/out_1_32>.
<a2/out_1_33>.
<a2/out_1_34>.
<a2/out_1_35>.
<a2/out_1_36>.
<a2/out_1_37>.
<a2/out_1_38>.
<a2/out_1_39>.
<a2/out_1_40>.
<a2/out_1_41>.
<a2/out_1_42>.
<a2/out_1_43>.
<a2/out_1_44>.
<a2/out_1_45>.
<a2/out_1_46>.
<a2/out_1_47>.
<a2/out_1_48>.
<a2/out_1_49>.
<a2/out_1_50>.
<a2/out_1_51>.
<a2/out_1_52>.
<a2/out_1_53>.
<a2/out_1_54>.
<a2/out_1_55>.
<a2/out_1_56>.
<a2/out_1_57>.
<a2/out_1_58>.
<a2/out_1_59>.
<a2/out_1_60>.
<a2/out_1_61>.
<a2/out_1_62>.
<a2/out_1_63>.
<a4/out_1_128>.
<a4/out_1_129>.
<a4/out_1_130>.
<a4/out_1_131>.
<a4/out_1_132>.
<a4/out_1_133>.
<a4/out_1_134>.
<a4/out_1_135>.
<a4/out_1_136>.
<a4/out_1_137>.
<a4/out_1_138>.
<a4/out_1_139>.
<a4/out_1_140>.
<a4/out_1_141>.
<a4/out_1_142>.
<a4/out_1_143>.
<a4/out_1_144>.
<a4/out_1_145>.
<a4/out_1_146>.
<a4/out_1_147>.
<a4/out_1_148>.
<a4/out_1_149>.
<a4/out_1_150>.
<a4/out_1_151>.
<a4/out_1_152>.
<a4/out_1_153>.
<a4/out_1_154>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a4/out_1_155>.
<a4/out_1_156>.
<a4/out_1_157>.
<a4/out_1_158>.
<a4/out_1_159>.
<a4/out_1_160>.
<a4/out_1_161>.
<a4/out_1_162>.
<a4/out_1_163>.
<a4/out_1_164>.
<a4/out_1_165>.
<a4/out_1_166>.
<a4/out_1_167>.
<a4/out_1_168>.
<a4/out_1_169>.
<a4/out_1_170>.
<a4/out_1_171>.
<a4/out_1_172>.
<a4/out_1_173>.
<a4/out_1_174>.
<a4/out_1_175>.
<a4/out_1_176>.
<a4/out_1_177>.
<a4/out_1_178>.
<a4/out_1_179>.
<a4/out_1_180>.
<a4/out_1_181>.
<a4/out_1_182>.
<a4/out_1_183>.
<a4/out_1_184>.
<a4/out_1_185>.
<a4/out_1_186>.
<a4/out_1_187>.
<a4/out_1_188>.
<a4/out_1_189>.
<a4/out_1_190>.
<a4/out_1_191>.
<a5/out_1_0>.
<a5/out_1_1>.
<a5/out_1_2>.
<a5/out_1_3>.
<a5/out_1_4>.
<a5/out_1_5>.
<a5/out_1_6>.
<a5/out_1_7>.
<a5/out_1_8>.
<a5/out_1_9>.
<a5/out_1_10>.
<a5/out_1_11>.
<a5/out_1_12>.
<a5/out_1_13>.
<a5/out_1_14>.
<a5/out_1_15>.
<a5/out_1_16>.
<a5/out_1_17>.
<a5/out_1_18>.
<a5/out_1_19>.
<a5/out_1_20>.
<a5/out_1_21>.
<a5/out_1_22>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a5/out_1_23>.
<a5/out_1_24>.
<a5/out_1_25>.
<a5/out_1_26>.
<a5/out_1_27>.
<a5/out_1_28>.
<a5/out_1_29>.
<a5/out_1_30>.
<a5/out_1_31>.
<a5/out_1_32>.
<a5/out_1_33>.
<a5/out_1_34>.
<a5/out_1_35>.
<a5/out_1_36>.
<a5/out_1_37>.
<a5/out_1_38>.
<a5/out_1_39>.
<a5/out_1_40>.
<a5/out_1_41>.
<a5/out_1_42>.
<a5/out_1_43>.
<a5/out_1_44>.
<a5/out_1_45>.
<a5/out_1_46>.
<a5/out_1_47>.
<a5/out_1_48>.
<a5/out_1_49>.
<a5/out_1_50>.
<a5/out_1_51>.
<a5/out_1_52>.
<a5/out_1_53>.
<a5/out_1_54>.
<a5/out_1_55>.
<a5/out_1_56>.
<a5/out_1_57>.
<a5/out_1_58>.
<a5/out_1_59>.
<a5/out_1_60>.
<a5/out_1_61>.
<a5/out_1_62>.
<a5/out_1_63>.
<a7/out_1_128>.
<a7/out_1_129>.
<a7/out_1_130>.
<a7/out_1_131>.
<a7/out_1_132>.
<a7/out_1_133>.
<a7/out_1_134>.
<a7/out_1_135>.
<a7/out_1_136>.
<a7/out_1_137>.
<a7/out_1_138>.
<a7/out_1_139>.
<a7/out_1_140>.
<a7/out_1_141>.
<a7/out_1_142>.
<a7/out_1_143>.
<a7/out_1_144>.
<a7/out_1_145>.
<a7/out_1_146>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a7/out_1_147>.
<a7/out_1_148>.
<a7/out_1_149>.
<a7/out_1_150>.
<a7/out_1_151>.
<a7/out_1_152>.
<a7/out_1_153>.
<a7/out_1_154>.
<a7/out_1_155>.
<a7/out_1_156>.
<a7/out_1_157>.
<a7/out_1_158>.
<a7/out_1_159>.
<a7/out_1_160>.
<a7/out_1_161>.
<a7/out_1_162>.
<a7/out_1_163>.
<a7/out_1_164>.
<a7/out_1_165>.
<a7/out_1_166>.
<a7/out_1_167>.
<a7/out_1_168>.
<a7/out_1_169>.
<a7/out_1_170>.
<a7/out_1_171>.
<a7/out_1_172>.
<a7/out_1_173>.
<a7/out_1_174>.
<a7/out_1_175>.
<a7/out_1_176>.
<a7/out_1_177>.
<a7/out_1_178>.
<a7/out_1_179>.
<a7/out_1_180>.
<a7/out_1_181>.
<a7/out_1_182>.
<a7/out_1_183>.
<a7/out_1_184>.
<a7/out_1_185>.
<a7/out_1_186>.
<a7/out_1_187>.
<a7/out_1_188>.
<a7/out_1_189>.
<a7/out_1_190>.
<a7/out_1_191>.
<a8/out_1_0>.
<a8/out_1_1>.
<a8/out_1_2>.
<a8/out_1_3>.
<a8/out_1_4>.
<a8/out_1_5>.
<a8/out_1_6>.
<a8/out_1_7>.
<a8/out_1_8>.
<a8/out_1_9>.
<a8/out_1_10>.
<a8/out_1_11>.
<a8/out_1_12>.
<a8/out_1_13>.
<a8/out_1_14>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
3-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a8/out_1_15>.
<a8/out_1_16>.
<a8/out_1_17>.
<a8/out_1_18>.
<a8/out_1_19>.
<a8/out_1_20>.
<a8/out_1_21>.
<a8/out_1_22>.
<a8/out_1_23>.
<a8/out_1_24>.
<a8/out_1_25>.
<a8/out_1_26>.
<a8/out_1_27>.
<a8/out_1_28>.
<a8/out_1_29>.
<a8/out_1_30>.
<a8/out_1_31>.
<a8/out_1_32>.
<a8/out_1_33>.
<a8/out_1_34>.
<a8/out_1_35>.
<a8/out_1_36>.
<a8/out_1_37>.
<a8/out_1_38>.
<a8/out_1_39>.
<a8/out_1_40>.
<a8/out_1_41>.
<a8/out_1_42>.
<a8/out_1_43>.
<a8/out_1_44>.
<a8/out_1_45>.
<a8/out_1_46>.
<a8/out_1_47>.
<a8/out_1_48>.
<a8/out_1_49>.
<a8/out_1_50>.
<a8/out_1_51>.
<a8/out_1_52>.
<a8/out_1_53>.
<a8/out_1_54>.
<a8/out_1_55>.
<a8/out_1_56>.
<a8/out_1_57>.
<a8/out_1_58>.
<a8/out_1_59>.
<a8/out_1_60>.
<a8/out_1_61>.
<a8/out_1_62>.
<a8/out_1_63>.
<a10/out_1_128>.
<a10/out_1_129>.
<a10/out_1_130>.
<a10/out_1_131>.
<a10/out_1_132>.
<a10/out_1_133>.
<a10/out_1_134>.
<a10/out_1_135>.
<a10/out_1_136>.
<a10/out_1_137>.
<a10/out_1_138>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a10/out_1_139>.
<a10/out_1_140>.
<a10/out_1_141>.
<a10/out_1_142>.
<a10/out_1_143>.
<a10/out_1_144>.
<a10/out_1_145>.
<a10/out_1_146>.
<a10/out_1_147>.
<a10/out_1_148>.
<a10/out_1_149>.
<a10/out_1_150>.
<a10/out_1_151>.
<a10/out_1_152>.
<a10/out_1_153>.
<a10/out_1_154>.
<a10/out_1_155>.
<a10/out_1_156>.
<a10/out_1_157>.
<a10/out_1_158>.
<a10/out_1_159>.
<a10/out_1_160>.
<a10/out_1_161>.
<a10/out_1_162>.
<a10/out_1_163>.
<a10/out_1_164>.
<a10/out_1_165>.
<a10/out_1_166>.
<a10/out_1_167>.
<a10/out_1_168>.
<a10/out_1_169>.
<a10/out_1_170>.
<a10/out_1_171>.
<a10/out_1_172>.
<a10/out_1_173>.
<a10/out_1_174>.
<a10/out_1_175>.
<a10/out_1_176>.
<a10/out_1_177>.
<a10/out_1_178>.
<a10/out_1_179>.
<a10/out_1_180>.
<a10/out_1_181>.
<a10/out_1_182>.
<a10/out_1_183>.
<a10/out_1_184>.
<a10/out_1_185>.
<a10/out_1_186>.
<a10/out_1_187>.
<a10/out_1_188>.
<a10/out_1_189>.
<a10/out_1_190>.
<a10/out_1_191>.
<a9/out_1_127>.
<a9/out_1_126>.
<a9/out_1_125>.
<a9/out_1_124>.
<a9/out_1_123>.
<a9/out_1_122>.
<a9/out_1_121>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a9/out_1_120>.
<a9/out_1_119>.
<a9/out_1_118>.
<a9/out_1_117>.
<a9/out_1_116>.
<a9/out_1_115>.
<a9/out_1_114>.
<a9/out_1_113>.
<a9/out_1_112>.
<a9/out_1_111>.
<a9/out_1_110>.
<a9/out_1_109>.
<a9/out_1_108>.
<a9/out_1_107>.
<a9/out_1_106>.
<a9/out_1_105>.
<a9/out_1_104>.
<a9/out_1_103>.
<a9/out_1_102>.
<a9/out_1_101>.
<a9/out_1_100>.
<a9/out_1_99>.
<a9/out_1_98>.
<a9/out_1_97>.
<a9/out_1_96>.
<a9/out_1_95>.
<a9/out_1_94>.
<a9/out_1_93>.
<a9/out_1_92>.
<a9/out_1_91>.
<a9/out_1_90>.
<a9/out_1_89>.
<a9/out_1_88>.
<a9/out_1_87>.
<a9/out_1_86>.
<a9/out_1_85>.
<a9/out_1_84>.
<a9/out_1_83>.
<a9/out_1_82>.
<a9/out_1_81>.
<a9/out_1_80>.
<a9/out_1_79>.
<a9/out_1_78>.
<a9/out_1_77>.
<a9/out_1_76>.
<a9/out_1_75>.
<a9/out_1_74>.
<a9/out_1_73>.
<a9/out_1_72>.
<a9/out_1_71>.
<a9/out_1_70>.
<a9/out_1_69>.
<a9/out_1_68>.
<a9/out_1_67>.
<a9/out_1_66>.
<a9/out_1_65>.
<a9/out_1_64>.
<a6/out_1_127>.
<a6/out_1_126>.
<a6/out_1_125>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a6/out_1_124>.
<a6/out_1_123>.
<a6/out_1_122>.
<a6/out_1_121>.
<a6/out_1_120>.
<a6/out_1_119>.
<a6/out_1_118>.
<a6/out_1_117>.
<a6/out_1_116>.
<a6/out_1_115>.
<a6/out_1_114>.
<a6/out_1_113>.
<a6/out_1_112>.
<a6/out_1_111>.
<a6/out_1_110>.
<a6/out_1_109>.
<a6/out_1_108>.
<a6/out_1_107>.
<a6/out_1_106>.
<a6/out_1_105>.
<a6/out_1_104>.
<a6/out_1_103>.
<a6/out_1_102>.
<a6/out_1_101>.
<a6/out_1_100>.
<a6/out_1_99>.
<a6/out_1_98>.
<a6/out_1_97>.
<a6/out_1_96>.
<a6/out_1_95>.
<a6/out_1_94>.
<a6/out_1_93>.
<a6/out_1_92>.
<a6/out_1_91>.
<a6/out_1_90>.
<a6/out_1_89>.
<a6/out_1_88>.
<a6/out_1_87>.
<a6/out_1_86>.
<a6/out_1_85>.
<a6/out_1_84>.
<a6/out_1_83>.
<a6/out_1_82>.
<a6/out_1_81>.
<a6/out_1_80>.
<a6/out_1_79>.
<a6/out_1_78>.
<a6/out_1_77>.
<a6/out_1_76>.
<a6/out_1_75>.
<a6/out_1_74>.
<a6/out_1_73>.
<a6/out_1_72>.
<a6/out_1_71>.
<a6/out_1_70>.
<a6/out_1_69>.
<a6/out_1_68>.
<a6/out_1_67>.
<a6/out_1_66>.
<a6/out_1_65>.

Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found
Found

2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit
2-bit

shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift
shift

register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register

for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for
for

signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

<a6/out_1_64>.
<a3/out_1_127>.
<a3/out_1_126>.
<a3/out_1_125>.
<a3/out_1_124>.
<a3/out_1_123>.
<a3/out_1_122>.
<a3/out_1_121>.
<a3/out_1_120>.
<a3/out_1_119>.
<a3/out_1_118>.
<a3/out_1_117>.
<a3/out_1_116>.
<a3/out_1_115>.
<a3/out_1_114>.
<a3/out_1_113>.
<a3/out_1_112>.
<a3/out_1_111>.
<a3/out_1_110>.
<a3/out_1_109>.
<a3/out_1_108>.
<a3/out_1_107>.
<a3/out_1_106>.
<a3/out_1_105>.
<a3/out_1_104>.
<a3/out_1_103>.
<a3/out_1_102>.
<a3/out_1_101>.
<a3/out_1_100>.
<a3/out_1_99>.
<a3/out_1_98>.
<a3/out_1_97>.
<a3/out_1_96>.
<a3/out_1_95>.
<a3/out_1_94>.
<a3/out_1_93>.
<a3/out_1_92>.
<a3/out_1_91>.
<a3/out_1_90>.
<a3/out_1_89>.
<a3/out_1_88>.
<a3/out_1_87>.
<a3/out_1_86>.
<a3/out_1_85>.
<a3/out_1_84>.
<a3/out_1_83>.
<a3/out_1_82>.
<a3/out_1_81>.
<a3/out_1_80>.
<a3/out_1_79>.
<a3/out_1_78>.
<a3/out_1_77>.
<a3/out_1_76>.
<a3/out_1_75>.
<a3/out_1_74>.
<a3/out_1_73>.
<a3/out_1_72>.
<a3/out_1_71>.
<a3/out_1_70>.
<a3/out_1_69>.

Found 2-bit shift

Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Found 2-bit shift
Unit <aes_192> processed.

register
register
register
register
register

for
for
for
for
for

signal
signal
signal
signal
signal

<a3/out_1_68>.
<a3/out_1_67>.
<a3/out_1_66>.
<a3/out_1_65>.
<a3/out_1_64>.

=========================================================================
Final Register Report
Macro Statistics
# Registers
Flip-Flops
# Shift Registers
2-bit shift register
3-bit shift register

:
:
:
:
:

4544
4544
736
576
160

=========================================================================
=========================================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------=========================================================================
*
Design Summary
*
=========================================================================
Top Level Output File Name

: aes_192.ngc

Primitive and Black Box Usage:

-----------------------------# BELS
#
GND
#
INV
#
LUT2
#
LUT3
#
LUT4
#
LUT5
#
LUT6
#
VCC
# FlipFlops/Latches
#
FD
#
FDE
# RAMS
#
RAMB18E1
# Shift Registers
#
SRLC16E
# Clock Buffers
#
BUFGP
# IO Buffers
#
IBUF
#
OBUF

:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:

3530
1
8
1248
480
256
128
1408
1
5280
4544
736
200
200
736
736
1
1
448
320
128

Device utilization summary:

--------------------------Selected Device : 7vx330tffg1157-1
Slice Logic Utilization:
Number of Slice Registers:
Number of Slice LUTs:
Number used as Logic:
Number used as Memory:
Number used as SRL:

5280
4264
3528
736
736

out
out
out
out

of
of
of
of

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 5280
Number with an unused Flip Flop:
0 out of
Number with an unused LUT:
1016 out of
Number of fully used LUT-FF pairs: 4264 out of
Number of unique control sets:
2
IO Utilization:
Number of IOs:
Number of bonded IOBs:

449
449 out of

Specific Feature Utilization:

Number of Block RAM/FIFO:
Number using Block RAM only:
Number of BUFG/BUFGCTRL/BUFHCEs:

100 out of
100
1 out of

408000
204000
204000
70200

1%
2%
1%
1%

5280
5280
5280

0%
19%
80%

600

74%

750

13%

200

0%

--------------------------Partition Resource Summary:

--------------------------No Partitions were found in this design.
--------------------------=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 6216 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
--------------------------------------------------------------------------+----------------------------------------------------+-------+
Control Signal
| Buffer(FF name)
| Load |
-----------------------------------+--------------------------------------------

---------+-------+
N1(XST_GND:G)
| NONE(r1/t0/t2/s0/Mram_in[7]_GND_4_o_wide_mu
x_1_OUT1)| 400 |
-----------------------------------+----------------------------------------------------+-------+
Timing Summary:
--------------Speed Grade: -1
Minimum
Minimum
Maximum
Maximum

period: 3.049ns (Maximum Frequency: 327.976MHz)

input arrival time before clock: 0.555ns
output required time after clock: 0.681ns
combinational path delay: No path found

Timing Details:
--------------All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.049ns (frequency: 327.976MHz)
Total number of paths / destination ports: 20128 / 8896
------------------------------------------------------------------------Delay:
3.049ns (Levels of Logic = 2)
Source:
a5/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1 (RAM)
Destination:
r3/state_out_0 (FF)
Source Clock:
clk rising
Destination Clock: clk rising
Data Path: a5/S4_0/S_3/Mram_in[7]_GND_4_o_wide_mux_1_OUT1 to r3/state_out_0
Gate
Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------RAMB18E1:CLKARDCLK->DOBDO0
4 2.080 0.433 a5/S4_0/S_3/Mram_in[7]_GND
_4_o_wide_mux_1_OUT1 (a2/k6a<0>)
LUT2:I1->O
2 0.053 0.419 a2/Mxor_k3b_0_xo<0>1 (k2b<0>)
LUT6:I5->O
1 0.053 0.000 r3/Mxor_z3_0_xo<0>1 (r3/z3<0>)
FD:D
0.011
r3/state_out_0
---------------------------------------Total
3.049ns (2.197ns logic, 0.852ns route)
(72.1% logic, 27.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 448 / 320
------------------------------------------------------------------------Offset:
0.555ns (Levels of Logic = 2)
Source:
key<64> (PAD)
Destination:
s0_0 (FF)
Destination Clock: clk rising
Data Path: key<64> to s0_0
Gate
Net
Cell:in->out
fanout Delay Delay
---------------------------------------IBUF:I->O
2 0.000 0.491
LUT2:I0->O
1 0.053 0.000
_0_xo<0>1 (state[127]_key[191]_xor_1_OUT<0>)
FD:D
0.011

Logical Name (Net Name)

-----------key_64_IBUF (key_64_IBUF)
Mxor_state[127]_key[191]_xor_1_OUT
s0_0

---------------------------------------Total
0.555ns (0.064ns logic, 0.491ns route)
(11.5% logic, 88.5% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 128 / 128
------------------------------------------------------------------------Offset:
0.681ns (Levels of Logic = 1)
Source:
rf/state_out_127 (FF)
Destination:
out<127> (PAD)
Source Clock:
clk rising
Data Path: rf/state_out_127 to out<127>
Gate
Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FD:C->Q
1 0.282 0.399 rf/state_out_127 (rf/state_out_127
)
OBUF:I->O
0.000
out_127_OBUF (out<127>)
---------------------------------------Total
0.681ns (0.282ns logic, 0.399ns route)
(41.4% logic, 58.6% route)
=========================================================================
Cross Clock Domains Report:
-------------------------Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk
|
3.049|
|
|
|
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 106.00 secs
Total CPU time to Xst completion: 106.46 secs
-->
Total memory usage is 259304 kilobytes
Number of errors :
0 (
Number of warnings : 64 (
Number of infos
: 589 (

0 filtered)
0 filtered)
0 filtered)