Beruflich Dokumente
Kultur Dokumente
6.002 ELECTRONICS
ADMINISTRIVIA
What is engineering?
Purposeful use of science
?
Suppose we wish to answer this question:
What is the current through the bulb?
Apply Maxwell’s
∂B ∂φ B
Faraday’s ∇× E = − ∫ E ⋅ dl = − ∂t
∂t
∂ρ ∂q
Continuity ∇ ⋅ J = − ∫ J ⋅ dS = − ∂t
∂t
ρ q
Others ∇⋅E = ∫ E ⋅ dS =
ε0 ε0
Analogy
F
a?
Analogy
F
a?
Point-mass discretization
A
I
+ V
R and I=
V R
–
B
In EE, we do things
the easy way…
V
SB
B –
black box
Although we will take the easy way
using lumped abstractions for the rest
of this course, we must make sure (at
least the first time) that our
abstraction is reasonable. In this case,
ensuring that V I
are defined
for the element
I
A
+ SA
V I
V
SB must be defined
B – for the element
black box
∫ J ⋅ dS
SA
∫ J ⋅ dS
SB
∂q
∫ J ⋅ dS − ∫ J ⋅ dS = ∂t
SA SB
IA IB
from ell
ax w ∂q
M I A = I B only if =0
∂t
So let’s assume this
see
A&L
∂φ B
VAB defined when =0
∂t
So VAB = ∫AB E ⋅ dl outside elements
∂φ B
= 0 outside
∂t
∂q
More in = 0 inside elements
Chapter 1 ∂t bulb, wire, battery
of A & L
Demo
Exploding resistor demo
can’t predict that!
Pickle demo
can’t predict light, smell
For example —
a
R1 R4
R3
V
+ b d
–
R2 R5
R1 R4
R3
V
+ b d
–
R2 R5
∂φ B
∫ E ⋅ dl = − ∂t under DMD
0
∫ E ⋅ dl + ∫ E ⋅ dl + ∫ E ⋅ dl = 0
ca ab bc
+ Vca + Vab + Vbc = 0
Kirchhoff’s Voltage Law (KVL):
The sum of the voltages in a loop is 0.
Consider
S
I ca I da
a
I ba
S
I ca I
da
a
I ba
∂q
∫S J ⋅ dS = − ∂t under LMD
0
I ca + I da + I ba = 0
KVL:
∑ jν j = 0
loop
KCL:
∑jij = 0
node
CIRCUITS AND
6.002 ELECTRONICS
Amplifiers --
Small Signal Model
Review
MOSFET amp
VS
RL
vO
vI
iDS
1 vO vs vI
K
vO = VS − (vI −1)2 RL
valid for vI ≥ VT
and
vO ≥ vI – VT
K 2
(same as iDS ≤ vO )
2
v
O
V
S
5V
interesting vO = vI −VT
region for vO vO < vI −VT
1V
vI
VT
1V 2V
“interesting” region
for vI . Saturation
discipline satisfied.
But…
vO
VS
5V
vO = vI −VT
vO
1V
vI
vI
VT
1V 2V
Demo
Amplifies alright,
vI
but distorts
vO
Amp is nonlinear … /
(VI , VO )
~ 1V
vI
VT
1V ~ 2V
K (vI − VT )
2
vO = VS − RL
2
Amp all right, but nonlinear!
Hmmm … So what about our linear amplifier ???
Insight:
But, observe vI vs vO about some
point (VI , VO) … looks quite linear !
Trick vo looks
linear
∆vO VO vi
(VI ,VO )
VI
∆vI
Operate amp at VI , VO
Æ DC “bias” (good choice: midpoint
of input operating range)
Superimpose small signal on top of VI
Trick vo looks
linear
∆vO VO vi
(VI ,VO )
VI
∆vI
Operate amp at VI , VO
Æ DC “bias” (good choice: midpoint
of input operating range)
Superimpose small signal on top of VI
Response to small signal seems to be
approximately linear
Let’s look at this in more detail —
I graphically next
II mathematically week
III from a circuit viewpoint
6.002 Fall 2000 Lecture 10 8
I Graphically
VS
interesting RL
input signal
vO
∆vI +
–
VI
+
–
Offset voltage or bias
Graphically
VS
interesting
RL
input signal vO
∆vI +
–
VI
+
–
vO
VS operating
point
VO VI , VO
vO = vI −VT
vI
0 VT
VI
Good choice for operating point:
Notation —
Input: vI = VI + vi
total DC small
variable bias signal (like ∆vI)
bias voltage aka operating point voltage
Output: vO = VO + vo
Graphically,
vI vO
vi vo
VI
VO
0 t 0 t
II Mathematically
(… watch my fingers)
RL K
vO = VS − (vI −VT ) VO = VS − RL K (VI −VT )2
2 2
substituting vI = VI + vi vi << VI
RL K
vO = VS − ( [VI + vi ] − vT )2
RL K
= VS − ( [VI −VT ] + vi )2
= VS −
RL K
2
(
[VI −VT ]2 + 2 [VI − vT ]vi + vi 2 )
RL K
VO + vo = VS − (VI − VT )2 − RL K (VI −VT ) vi
2
From ,
gm related to VI
Mathematically
gm related to VI
vo = −g m RL vi
VI – VT is constant. So,
vo = − A vi
constant w.r.t. vi
Another way
RL K
vO = VS − (vI −VT )2
VS −
R K
L
2
v −V
I
(
T
2
)
d
vo = ⋅ vi
dv
I
v = V
I I
slope at VI
g m = K (VI −VT )
A = −g m RL amp gain
vO
VO
CIRCUITS AND
6.002 ELECTRONICS
vOUT = f (vI )
d
vout = f (vI ) ⋅ vi
dv I v I =VI
VS
vI = VI + vi RL
vO = VO + vo
vi +
–
VI +
–
behaves linear
for small
perturbations
vI
II Mathematical view
K (vI − VT )
2
vO = VS − RL
2
V − K (v − V )2 R
d S 2 I T L
vo = ⋅ vi
dv I
v I =VI
vo = − K (VI − VT ) RL ⋅ vi
gm related to VI
constant for fixed
DC bias
input signal
response
VI
vO
VO
v I = VT
− 1 + 1 + 2 KR LV S
v I = VT +
KR L
1. Gain g m RL ∝ VI
2. Input valid operating range for amp.
3. Bias to select gain and input swing.
2
∂ K (v − V )2
ids = 2 GS T ⋅ v gs
∂vGS vGS =VGS
vS = VS
large iS
signal + vS = VS
–
is +
vs vs = 0
–
DC source behaves
as short to small
signals.
large iR + v R = R iR
vR
signal R – ∂ ( RiR )
vr = ⋅ ir
∂iR iR = I R
vr = R ⋅ ir
ir +
small vr
signal R –
RL + V RL
vO – S vo
+ v iDS + vi ids
– I –
K
= (vI − VT ) ids = K (VI − VT ) ⋅ vi
2
iDS
2
ids RL + vo = 0
K
vO = VS − (vI − VT )2 RL
2 vo = −ids RL
vo = − K (VI − VT )RL ⋅ vi
= − g m RL ⋅ vi
Since small signal models are linear, our linear tools will now
apply…
Capacitors
and First-Order Systems
B C
A
5V
0V
5
A
0
5
Expect this, right?
B But observe this!
0
5 Expected
C Observed
0
Reading:
Delay! Chapters 9 & 10
6.002 Fall 2000 Lecture 12 2
The Capacitor
D
G n-channel MOSFET
symbol
S
drain
n s
m+ o i
gate e+ x l n-channel
t + i p
i MOSFET
a+ d
l + e n-channel c
+ o
n n
source
D
G
S
CGS
6.002 Fall 2000 Lecture 12 3
Ideal Linear Capacitor
+ + A d
++++
EA
- - C=
E ----- d
obeys DMD!
total charge on
capacitor
= +q − q = 0
i
q +
C v
–
q = C v
i
q +
C v
–
q = C v
dq
i=
dt
d (Cv )
=
dt
dv
=C
dt
E = 1 Cv 2
2
Thévenin Equivalent:
+
R C vC (t )
vI (t ) +
– –
vC − vI dvC
+C =0
R dt
dvC t ≥ t0
RC + vC = vI
dt vC (t0 ) given
units
of time
+
R C vC (t )
v I (t ) +
–
–
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC + vC = VI X
dt
vI (t ) = VI
vC (0 ) = V0 given
dvC
RC + vC = VI X
dt
vC (t ) = vCH (t ) + vCP (t )
total homogeneous particular
dVI
RC + VI = VI
dt
0
so, V0 = VI + A
or A = V0 − VI
−t
thus vC = VI + (V0 − VI ) e RC
also
dvC (V − VI ) −t
iC = C =− 0 e RC
dt R
vC
VI
V0
t
0
RC
5V 5V
−t −t
5 + 5e RC 5e RC
0V t 0V t
VO = 0V 5 VO = 5V 5
VI = 5V 0 VI = 0V 0
τ = RC
Remember
B
demo
Digital Circuit
vI R +
VI vI +
– C vC
–
t
0
vC (0 ) = VO
−t
vC = VI + (VO − VI ) e RC 1
vC
VI
time constant RC
VO
t
RC
VS VS
A
B
vA
5V CGS
X
t
0
1 Æ 0 at A
A
B
CGS
vA X
5V
t vB
0 5V ideal
1 Æ 0 at A observed
t
0
A
B
vA
5V CGS
X
t
0 vB
1 Æ 0 at A 5V
VOH
t
0 tr
rising delay of X
RL +
vI = VS + CGS vB
– –
vI = VS
for t ≥ 0
vB (0 ) = 0
From 1
−t
vB = VS + (0 − VS ) e RL CGS
vOH = VS − VS e RL CGS
Find tr :
−t r
VS e RL CGS
= VS − VOH
− tr VS − VOH
= ln
RL CGS VS
VS − VOH
t r = − RL CGS ln
VS
vOH = VS − VS e RL CGS
Find tr :
−t r
VS e RL CGS
= VS − VOH
− tr VS − VOH
= ln
RLCGS VS
VS − VOH
t r = − RL CGS ln
VS
e.g. RL = 1K VS = 5V
CGS = 0.1 pF VOH = 4V
−12 5−4
t r = −1 × 10 × 0.1 × 10
3
ln
5
= 0.16 ns
RC = 0.1 ns !
6.002 Fall 2000 Lecture 13 8
Falling Delay tf
Falling delay tf is
the t for which vB falls to VOL
RL vB (0 ) = VS
(5V )
VS +
– +
CGS vB
RON –
RL vB (0 ) = VS
(5V )
VS +
– +
CGS vB
RON –
X
Thévenin replacement …
RTH +
VTH +
– CGS vB
–
RTH = RL || RON
RON
VTH = VS
RON + RL
6.002 Fall 2000 Lecture 13 10
From 1
−t
Falling decay tf is
the t for which vB falls to VOL
−t f
VOL − VTH
or t f = − RTH CGS ln
VS − VTH
chip
pin 2
pin 1 v
CL
v:
ideal observed slow!
RL made RL small
RON made RON small
chip
pin 2
pin 1 v
CL
v:
ideal observed slow!
… but, disaster!
v: observed
expected
VIL
pin1
R0
ok
pin1 pin2
R0
R2
crosstalk!
CP
R +
v +
model for crosstalk: –
–
+
R0 –
R2
slower transitions!
Recall
R +
vI +
– C vC
–
v I = VI for t ≥0 vC (0 )
−t
vC = VI + (vC (0)− VI ) e RC 1
t
t ≥0 0
vC
VI
−t
vC = VI + (vC (0)− VI ) e RC
vC (0 )
t
0
Notice that the capacitor voltage for t ≥ 0 is
independent of the form of the input voltage
before t = 0 . Instead, it depends only on the
capacitor voltage at t = 0 , and the input voltage
for t ≥ 0 .
6.002 Fall 2000 Lecture 14 3
State
q=CV
Correspondingly,
zero state response or ZSR
−t
vC = VI − VI e RC 2
DIGITAL MEMORY
Why memory?
Or, why is combinational logic insufficient?
Examples
Consider adding 6 numbers on your
calculator
2+9+6+5+3+8
M+
store M The
NEC
d OUT View ¥
☺
d IN
store
dIN dOUT
* storage
C node
store
store = 1
C
dIN vC d
* OUT
store = 0
C
vC RL
5V
Stored value leaks away VOH
t
−t
T
from 2
RL C
vC = 5 ⋅ e
VOH
T = − RLC ln
5
store pulse width >> RON C
dIN dOUT
*
RIN
C buffer
store
Input resistance RIN
VOH
T = − RIN C ln
5
RIN >> RL
Better, but still not perfect.
Demo
dIN dOUT
*
C
store
Does this work?
store
dIN dOUT
*
C
store
Works!
Decoder
A d IN
00 S M
d OUT
B d IN A
01 S M
d OUT
a0 a1
2
Address d IN
C B
10 S M
d OUT
D d IN C
11 S M
d OUT
IN store
OUT
D
a0 a1 A B C D
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Second-Order Systems
5V 5V
Demo
50Ω
2KΩ 2KΩ
S
A C
B
+ large
– loop CGS
5V 5V
Demo
50Ω
2KΩ 2KΩ
S
C
A
B
+ large
– loop CGS
Relevant circuit:
2KΩ L
B
5V +
– CGS
5
vA
0 t
vB
2kΩ
0 t
vC
0 t
5
vA
0 t
vB
50Ω
0 t
vC
0 t
Huh!
L i (t )
+
+ C v(t )
vI (t ) – –
Node method:
dv
i (t ) = C Recall
dt
di
1 t
dv vI − v = L
∫ (vI − v) dt = C dt
L −∞ dt 1 t
∫ (vI − v) dt = i
L −∞
1 d 2v
(v I − v ) =C 2
L dt
d 2v
LC 2 + v = vI
dt
time2 v, i state variables
v = vP (t ) + vH (t )
For input
vI
V0
t
0
d 2 vP
LC 2 + vP = V0
dt
vP = V0 is a solution.
1 characteristic
B s =−
2
equation
LC
1
s=±j j = −1
LC
1
C Roots s = ± jω o ωo =
LC
General solution,
v( t ) = V0 − (e + e − jωot )
V0 jωot
so,
2
6.002 Fall 2000 Lecture 15 11
3 Total solution
e jx = cos x + j sin x
(verify using Taylor’s
expansion)
e jx + e − jx
= cos x
2
V0
0 π π ωo t
3π 2π
2 2
i (t )
CV0ωo
0 π π ωo t
3π 2π
2 2
− CV0ωo
4 Total solution is vP + vH ,
solve for remaining constants using
initial conditions.
What if we have:
iC + vC (0) = V
L C vC
– iC (0) = 0
iC + vC (0) = V
L C vC
– iC (0) = 0
or vC =
2
(e + e − jω o t )
V jω o t
vC = V cos ωot
iC = −CV ωo sin ωot
6.002 Fall 2000 Lecture 15 16
Example
vC
V
ωo t
2π
CVωo iC
ωo t
2π
− CVωo
EC
1
1 CV 2
C: CvC
2 2
2
ωo t
2π
EL
1 1
L : LiC
2 CV 2
2 2
ωo t
2π
1 1 1
Notice
2 2
CvC + LiC = CV 2
2 2 2
R L i (t )
+
vI (t ) +
– C v(t )
–
v(t )
no R
add R
t
Damped sinusoids with R – remember demo!
6.002 ELECTRONICS
Review
5V v
R
L
Motivation
Demo
vO
R vC
vi +
–
CGS
VBIAS +
–
Example:
iC
R +
vI +
– vC
–
0 t
Our Approach
Example:
iC
R +
vI
+
– vC
Determine vC(t)
e m e!
Effort
Ind ulg
Usual
approach
agony
sneaky approach
very
sneaky
easy
re
e
0
:0
ur
:
2
:
0
tu
1
2
11
11
ct
lec
le
is
t
Th
ex
N
1 Set up DE.
2 Find vp.
3 Find vH.
4 vC = vP + vH, solve for unknowns
using initial conditions
Usual approach…
1 Set up DE
dvC
RC + vC = vI
dt
= Vi cos ω t
2 Find vp
dvP
RC + vP = Vi cos ωt
dt
..
. gasp !
Vp complex amplitude
Fact 2: vI = Vi cos ωt
= real[Vi e jω t ] = real[vIS ]
Vi
= Re ⋅ e jω t
1+ jωRC
Vi (1 − jωRC ) jω t
= Re ⋅e
1 + ω 2 R 2C 2
Vi j φ jω t
= Re ⋅ e e , tan φ = −ωRC
1+ω R C
2 2 2
Vi j( ωt +φ )
= Re ⋅ e
1 + ω 2 R 2C 2
Vi
vP = ⋅ cos( ωt + φ )
1+ω R C2 2 2
−t
Recall, vH = Ae RC
1+ω R C
2 2 2
Done! Phew !
1+ω R C
2 2 2
Vp
∠Vp
Described as
SSS: Sinusoidal Steady State
Recall Vi Steps 3 , 4
Vp = were a waste of
1 + jωRC
time!
Vp 1
=
Vi 1+ jωRC
Vp 1
= e jφ where
Vi 1 + ω 2 R 2C 2
φ = tan −1 − ωRC
Vp 1
magnitude =
Vi 1 + ω 2 R 2C 2
Vp
phase φ : ∠ = − tan −1 ωRC
Vi
Vi cos ωt D.E.
drive V p cos[ωt + ∠V p ]
+
nightmare
particular
trig.
solution
algebraic
sneak
equation take
in
+ real
Vi e jωt
complex part
drive
algebra V p e jω t
Magnitude Plot
transfer function
Vp Vp 1
H ( jω ) = =
Vi Vi 1 + ω 2 R 2C 2
Vp
1
Vi
log
scale
ω
log 1
ω=
scale RC
Phase Plot
φ = tan −1 − ωRC
Vp
φ =∠
Vi
1
ω=
RC ω
0
log scale
π
−
4
π
−
2
CIRCUITS AND
6.002 ELECTRONICS
R +
vI = Vi cos ωt +
– C vO
–
Vp 3
vH
sneak 2
take 4
in complex
real total
Vi e jωt algebra
part
drive
The Sneaky Path
V p e jω t
Vi
1 + jωRC
Vp
= H ( jω ) transfer
1
=
Vi 1 + jωRC function
Vp
remember
Vi 1 demo
1
2
1 1
1 + ω 2 R 2C 2 ωRC
1
ω
ω=
RC
Bode plot break frequency
Vp 1
∠ ω=
Vi RC
0 ω
⎛ − ωRC ⎞ π
tan −1 ⎜ ⎟ −
⎝ 1 ⎠ 4
π
−
2
jω t dvC
iC iC = I C e iC = C
+ dt
vC C vC = VC e jω t I C e jω t = CVC jωe jω t
–
1
Capacitor VC = IC
j ωC
ZC
jω t diL
iL iL = I l e vL = L
+ dt
vL L vL = Vl e jω t Vl e jω t = LI l jωe jω t
–
Inductor Vl = jωL I l
6.002 Fall 2000 Lecture 17
ZL 6
The Impedance Model
In other words,
Ic Vc = Z C I c
capacitor
+ 1
Vc ZC ZC =
– j ωC
impedance
Il
inductor
+ Vl = Z l I l
Vl ZL
– Z l = j ωL
resistor Ir
+ Vr = Z r I r
Vr ZR
– Zr = R
+
vI +
– C vC
–
Impedance model:
ZR = R
Ic
+ 1
Vi +
– Vc ZC =
– jωC
1
jωC ZC
Vc = Vi = Vi
1 ZC + Z R
+R
jωC
1
Vc = Vi Done!
1 + jωRC
Vi R
Vr =
1
j ωL + +R
jωC
Vi jωCR
Vr =
− ω 2 LC + 1 + jωCR
Vi cos ωt V p cos[ωt + ∠V p ]
usual set
nightmare
circuit up
trig.
model DE
Vi cos ωt V p cos[ωt + ∠V p ]
usual set
nightmare
circuit up
trig.
model DE
take
Vi e jωt complex
real
drive algebra
part
Vi cos ωt V p cos[ωt + ∠V p ]
usual set
nightmare
circuit up
trig.
model DE
take
Vi e jωt complex
real
drive algebra
part
impedance-based complex
circuit model algebra
No D.E.s, no trig!
Vr jωRC Vi L C +
= + R Vr
Vi 1 + jωRC − ω 2 LC –
–
=
jωRC
⋅
(1 − ω 2 LC ) − jωRC
(1 − ω LC ) + jωRC (1 − ω 2 LC ) − jωRC
2
Vr ωRC
=
Vi (1 − ω 2
LC ) + (ωRC )
2 2
Observe
Low ω : ≈ ωRC
R
High ω : ≈
ωL
ω LC = 1 : ≈ 1
Low ω : ≈ ωRC
R
High ω : ≈
ωL
ω LC = 1 : ≈ 1
Vr
Vi
1 “Band Pass”
ωRC R
ωL
ω
1
LC
Remember this trick to sketch the form of
transfer functions quickly.
More next week…
6.002 Fall 2000 Lecture 17 14
CIRCUITS AND
6.002 ELECTRONICS
Filters
+
vI + C vC
–
–
ZR
+
Vi +
– ZC Vc
–
ZC
Vc = ⋅ Vi
ZC + Z R
1
Vc j ωC 1
= =
+ R 1 + jωRC
Vi 1
j ωC
+
Vi +
– ZC Vc
–
ZC 1
Vc = ⋅ Vi =
ZC + Z R 1 + jωRC
Vc
H (ω ) =
Vi
1 “Low Pass Filter”
ω
Demo
with audio
A
I ab +
R1 Vab
Vab RAB = = R1 + R2
I ab
R2
–
B
A
I ab +
R1 Vab
Vab Z AB = = R1 + jωL
I ab
j ωL
–
B
A
Z AB = R1 + Z C || R2 + Z L
R1
Z C R2
= R1 + + ZL
C R2 Z C + R2
R2
L = R1 + + jωL
1 + jωCR2
B
Z (ω )
L
Z R
C
ω
C ω
H (ω )
+ HPF
– High Pass Filter
ω
H (ω )
+ LPF
– Low Pass Filter
ω
H (ω )
+ HPF
–
ω
+
Vi +
– R Vr
–
Intuitively:
Vr
1
Vi
q
w fre L bloc
ks hig
k s lo h freq
bloc
C ω
1
ωo =
LC
Vr R
Vi
=
1 At resonance,
jω L + +R ω = ωo
jω C
j ω RC and
= ZL + ZC = 0,
1 − ω 2 LC + j ω RC
so Vi sees
Vr ω RC
= only R!
Vi (1 − ω 2
LC ) + (ω RC )
2 2
More later…
6.002 Fall 2000 Lecture 18 8
What about:
+ Vlc –
L C
Vi +
– R
Vlc
Vi Band Stop Filter
1 C open L open
R
+
Vi +
– L C Vo
Vo
Vi BPF
Cs
s hort ho
rt
L
ωo ω
antenna
demodulator
Vi +
– L C
amplifier
Thévenin
antenna
model
demodulator
Vi +
– L C
amplifier
signal filter
strength WBZ
10 KHz News
Radio
f
540 …1000 1010 1020 1030 … 1600 KHz
“Selectivity” important —
relates to a parameter “Q” for the filter. Next…
+
Vi +
– R Vr
–
Vr R
Recall, =
Vi R + jω L + 1
jω C
Vr
Vi
1
higher Q
1
2 Δω
bandwidth
ωo ω
ωo
Define Q = quality factor
Δω
high Q ⇒ more selective
ωο:
Vr R 1
= =
Vi R + jω L + 1 ⎛ L 1 ⎞
1 + j⎜ ω − ⎟
jω C ⎝ R ω CR ⎠
at ωο =0
1
ωo =
LC
Δω ?
R
Δω = ω1 − ω2 =
L
ωo
Q=
Δω
ωo ωo L ωo =
1
Q= =
R R LC
L
energy stored
Q = 2π
energy lost per cycle
1 2
L Ir
= 2π 2
1 2 2π
Ir R
2 ω0
ωo L
Q=
R
power
VS
+ port
+ vO output
input port
vI –
port –
–
Amplifier abstraction
VS
+
vI vO
+ +
vI v
– – – O
Function of vI
Function of vI
VS
power +
+ port –
input
port – output
port
+
–
−VS
+ +
vIN vOUT
– –
+ vO
i=0
v+
+
v +
Av
–
– v– A→∞
–
i=0
12V + VS = 12V
–
+ vO
vIN
–
− VS = −12V RL
–
12V +
Demo
vO active region
12V
saturation
vIN
− 10 μV 10μV
A ~ 106
− 12V but unreliable,
temp. dependent
R2
+ op amp
i=0
v+ vO
+ A(v + − v − )
vIN +
– – R1
−
v
–
i=0
R2
vO = A(v + − v − )
⎛ R2 ⎞
= A⎜ vIN − vO ⎟
⎝ R1 + R2 ⎠
⎛ AR2 ⎞
vO ⎜ 1 + ⎟ = AvIN
⎝ R1 + R2 ⎠
AvIN
vO =
AR2
1+
R1 + R2
10
vO ≈ vIN ⋅ 10
Gain:
determined by resistor ratio
insensitive to A, temperature, fab variations
e.g. vIN = 5V
Suppose I perturb the circuit…
(e.g., force vO momentarily to 12V somehow).
Stable point is when v+ ≈ v- .
Key: negative feedback Æ portion of
output fed to –ve input.
e.g. Car antilock brakes
Æ small corrections.
Antilock brakes
is it
turning?
yes/no c k
db a it’s
fee all about
Michelin control
no yes
release apply
cs
di
v. v. powerful brakes
v+ ≈ v−
We also know
i+ ≈ 0
i -≈ 0
R1 + R2
a vIN g vO = vIN
R2
+
vO
b vIN –
vIN +
– R1 f vIN
c vIN R2
e i=0
vIN
d R2
R2
vO ≈ vIN
R1 + R2
or vO = vIN
R2
with R1 = 0
R2 = ∞
+
vO
vIN +
–
–
vO ≈ vIN
Buffer
voltage gain = 1
input impedance = ∞
output impedance = 0
current gain = ∞
power gain = ∞
∂φ B Outside elements
=0
∂t
∂q Inside elements
=0
∂t
wires resistors sources
Allows us to create the lumped circuit
abstraction
i
+
v Lumped circuit element
-
KVL:
∑ jν j = 0
loop
KCL:
∑jij = 0
node
R1 R4
R3
+ b d
–
R2 R5
lots of unknowns
lots of equations
lots of fun
solve
Element Relationships
R
For R, V = IR
For voltage source, V = V0 +–
V0
For current source, I = I 0 J
Io
3 lumped circuit elements
+ +
ν1 R1 ν4 R4
– R3 –
+ + b d
ν 0 = V0 –
– +ν 3 –
+ +
ν2 R2 ν5 R5
– –
c
The Demo Circuit
i
+
ν Element e
-
c
L4
The Demo Circuit
R1 R2 R3 RN R1 + R2 + + RN
A … ⇔
B G1 G2 GN ⇔ G1 + G2 + GN
1
Gi =
Ri
V1 V2 V1 + V2
C +– +– ⇔ +–
D
I1 I2 ⇔ I1 + I 2
J
J
Example I =?
V + R1
–
R2 R3
I I
R1
V +
– V +
– R
R2 R3
R2 + R3
R2 R3
R = R1 +
R2 + R3
V
I=
R
V0
R1 R R4
3 e2
+ V e1
– 0
R2 R5 I1
Step 1
Step 2
V0
R1 R R4
3 e2
+ V e1
– 0
for
R2 R5 I1 convenience,
J
write
1
Gi =
Ri
KCL at e1
(e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0
KCL at e2
(e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0
Step 3
R1 R R4
3 e2
+ V e1
– 0
R2 R5 I1
J
1
Gi =
Ri
KCL at e1
(e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0
KCL at l2
(e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0
G1 + G2 + G3 − G3 e1 G1V0
=
− G3 G3 + G4 + G5 e2 G V + I
4 0 1
Solve
G3 + G4 + G5 G3 G1V0
e1 G3 G1 + G2 + G3 G4V0 + I1
e = (G1 + G2 + G3 )(G3 + G4 + G5 ) − G3 2
2
e = 3 4
(
G +G +G G V + G G V + I
5 1 0 3 4 0 1
)( ) ( )( )
1 G G +G G +G G +G G +G G +G G +G 2 +G G +G G
1 3 1 4 1 5 2 3 2 4 2 5 3 3 4 3 5
(same denominator)
G1 1 G2 1 1
= = G3 =
G5 8.2 K G4 3.9 K 1.5 K
I1 = 0
(
G G V + G +G +G G V + I
e = 3 10 1 2 3 40 1
)( )
( )(
2 G + G + G + G + G + G −G 2
1 2 3 3 4 5 3
)
1 1 1
G +G +G = + + =1
1 2 3 8.2 3.9 1.5
1 1 1
G3 + G4 + G5 = + + =1
1.5 3.9 8.2
1 1 1
× + 1×
e2 = 8.2 1.5 3.9 V
0
1
1− 2
1.5
Check out the
e2 = 0.6V0 DEMO
If V0 = 3V , then e2 = 1.8V0
+ ∞ input resistance
0 output resistance
– Gain “A” very large
i R1
v− –
v2 +
– v+ + +
v1 + R1 vOUT
– R2 –
+ R2 vOUT = v − − iR2
v = v1
R1 + R2 −
v − v
≈ v− = v− − 2 ⋅ R2
R1
v2 − v −
i= ⎡ R ⎤ R
R1 = v − ⎢1 + 2 ⎥ − v2 2
⎣ R1 ⎦ R1
R2 R + R2 R
= v1 ⋅ 1 − v2 2
R1 + R2 R1 R1
R2
= (v1 − v2 )
R1
subtracts!
6.002 Fall 2000 Lecture 20 3
Another way of solving —
use superposition
v1 → 0 v2 → 0
R2 R1
v+ + vOUT1
R1 v1 + R2
– – –
R2
v2 + vOUT2
– +
R1
R1 || R2
+ R1 + R2
R2 vOUT1 =v ⋅
vOUT2 = − v2 R1
R1
v1 ⋅ R2 R1 + R2
= ⋅
R1 + R2 R1
R2
= v1
R1
vOUT = vOUT1 + vOUT2
R2
= (v1 − v2 )
R1
Still subtracts!
6.002 Fall 2000 Lecture 20 4
Let’s build an intergrator…
+
vI +
–
∫ dt vO
–
–
t
1
vO = ∫ i dt
C −∞
vO is related to ∫ i dt
vC
vI + –
R
–
R vO = −vC
vI + +
– + vO t
1 vI
– vO = − ∫ dt
C −∞ R
We have our integrator.
6.002 Fall 2000 Lecture 20 7
Now, let’s build a differentiator…
d +
vI +
– vO
dt
–
+ dvI
vI – C i=C
dt
dvI
i is related to
dt
But we need to somehow convert current
to voltage.
C –
vI + + vC – vO
– +
vI = vC
dvI
i=C
dt
Demo vO = − RC
dvI
dt
6.002 Fall 2000 Lecture 20 9
CIRCUITS AND
6.002 ELECTRONICS
R1
+ vOUT
v IN +
– –
v + R2 vOUT
R1
v IN +
– v − +
– A(v + − v − )
vOUT = A(v + − v − )
= Av +
v − vIN
= A OUT ⋅ R1 + vIN
R1 + R2
AR1 AR1vIN
= vOUT − + AvIN
R1 + R2 R1 + R2
AR1 R1
vOUT 1 − = v A 1 −
IN R + R
R1 + R2 1 2
1 − R1
R +R R2
vOUT = 1 2
⋅ Av IN = − vIN
− AR 1 R1
R1 + R2
6.002 Fall 2000 Lecture 21 3
Representing dynamics of op amp…
v+ +
vo
+ R v* +
– C – Av*
(v + − v − )
v− –
+
vo
–
R3 R4
vo
Circuit model R2 A
R1 +
v+ +
+ R v* +
– C – vo
v− (v + − v − ) –
–
R3 R4
A
dv* *
RC + v = v+ − v_
dt vo R1 +
v+ = = γ vo
RC dvo vo R1 + R2
+ = v+ − v_
vo R3
=−
A dt A −
v = γ vo
+ R3 + R4
= ( γ − −γ ) vo
neglect
dvo 1 A − +
or +
+ ( γ − γ ) vo = 0
dt RC RC
dvo A − +
+ ( γ − γ ) vo = 0
dt RC
time −1
dvo vo RC
or + = 0 where T = − +
dt T A( γ − γ )
vo ( 0 ) = 0
vo
unstable
K neutral
stable
t
disturbance
v+ + vo
v− –
− VS
vo
+ VS
v+ − v−
0
− VS
vo
+
−
v →0 v
t
vi –
vo
+ R2
+ vo R1
v = R1
R1 + R2
e.g. R1 = R2
+
v = 7.5 vo = 15
vi VS = 15
vo = −15 v − = −7.5
vi –
vo
+ R2
+ vo R1
v = R1
R1 + R2
+ VS R1 e.g. R1 = R2
v = vo = +VS 15
R1 + R2 vi VS = 15
( vi = v − ) > v + v− < v+
v − > 7.5 v − < −7.5
− VS R1
vo = −VS − 15 v − =
R1 + R2
hysteresis
vi
− 7 .5 0 7 .5
Demo − VS
− 15
Demo
6.002 Fall 2000 Lecture 21 11
Without hysteresis
vi analog
vo to digital
vi
7.5
t
− 7.5
vC
–
vo
C + R1
vo
R1
2
vo
VS
VS v+
2 v−
vC
−
t
v
VS
−
2 v+
− VS
Assume vo = VS at t = 0
Demo vC = 0
6.002 Fall 2000 Lecture 21 13
Clocks in Digital Systems
We built an oscillator using an op amp.
t
can use as a clock
clock
a 1,1,0?
b When is the signal valid?
common timebase -- when to “look” at a signal
(e.g. whenever the clock is high)
Æ Discretization of time
one bit of information associated with
an interval of time (cycle)
6.002 Fall 2000 Lecture 21 14
CIRCUITS AND
6.002 ELECTRONICS
small batteries
Æ good
Today:
How long will the battery last?
in standby mode
in active use
Will the chip overheat and self-destruct?
+
+ C vO
vI
– –
Let us determine
standby power
active use power
Let’s work out a few related examples first.
V2
Power P = VI =
R
E = VIT
VS VS
RL
RL
vO
vI high vO vI low
RON RON
2
VS
P= P=0
RL + RON
T
T1 T2
S1 closed S1 open
S 2 open S 2 closed
t
i
assume
R1 vC = 0 at t = 0
VS +
– +
C vC
–
vC i
VS VS −t
VS R1C
R1 e
R1
t t
E = ∫ VS i dt
0
T1 2 −t
VS
=∫ e R1C
dt
0
R1
2 −t T1
VS
=− R1C e R1C
R1 0
−T1
= C VS 1 − e
2 R1C
2
≈ C VS if T1 >> R1C
I.e., if we wait long enough
1 2
C VS stored on C ,
2 Independent
1 of R!
2
E1 = C VS dissipated in R1
2
+
vC C R2
–
So, initially,
1
energy stored in capacitor = CVS
2
E1, E2 independent of R2 !
E = E1 + E2
1 2 1 2
= CVS + CVS
2 2
2
E = CVS energy dissipated in
charging & discharging C
Average power
E
P=
T
2
CVS
=
T
2
= CVS f
1
frequency f =
T
6.002 Fall 2000 Lecture 22 10
Back to our inverter —
VS
RL
vO
vIN RON C
vIN
T T
2 2
t
T 1
T=
f
VS +
– C
RON
T T
2 2
t
T 1
T=
f
1.25KW! 2.5W
problem ! not bad
must get rid of this α VS 2
α f
reduce VS
next
lecture 5 V → 1V
2.5 W → 150 mW
6.002 Fall 2000 Lecture 22 15
CIRCUITS AND
6.002 ELECTRONICS
Energy, CMOS
S1 S2
VS +
– C R2
1
T = T1 + T2 =
f
2
P = CVS f
1
Square wave input T= RL >> RON
2 f
VS 2 T
P= + CVS f >>" RC"
2 RL 2
Demo time constant
P STATIC P DYNAMIC
independent of f. related to switching
MOSFET ON half capacitor.
the time.
In standby mode,
In standby mode, half fÆ0,
the gates in a chip can so dynamic power is 0
be assumed to be on.
So P STATIC per gate is
still VS2 .
2RL
gates ⎣ 2 × 10 × 10
3
⎦
= 10 6 [1.25 milliwatts + 2.5 μ watts ]
1.25KWatts + 2.5Watts
problem ! not bad
• independent of f • αf
• also standby power • αVS2
(assume ½ MOSFETs reduce VS
ON if f Æ 0) 5VÆ1V
• must get rid of this! 2.5VÆ150mW
VS VS
RL
i RL
vO high
vI high vO low vI low
MOSFET
RON off
idea !
VS
vI high vO low
D
on when vGS ≥ VTN
G off when vGS < VTN
e.g. VTN = 1V
S
S
PU = pull up
G D
vI vO
+ D
– G PD = pull down
S
VS = 5V VS = 5V
RON p
vO vO
+ +
vI = 5V = 0V vI = 0V = 5V
– RON n –
Complementary
Called “CMOS logic”
MOS
(our previous logic was called “NMOS”)
vI vO
t
C f =
1
T
VS +
– C RON n
From
2
P = CVS f
Gates f P “keep
100 ~2.5 all
106 MHz watts Pentium? else
same”
300 ~15
2x106 MHz watts PII?
600 ~30
2x106 MHz watts PII?
~240
s p !
8x106 1.2 GHz watts
~1875
PIII?
ga
25x106 3 GHz watts PIV?
A VS 5V Æ 3V Æ 1.8V Æ 1.5V
~PIV Æ 170 watts Æ better, but high
5V 5V
0V S 5V S
on off
G D G D
VS e.g. F = A ⋅ B = A + B
short short when
when F A = 0 or B = 0,
is true,
else open open otherwise
A
Z
B short
when F short when
is true, A · B is true,
else open else open
m b er
reme gan’s law
eM o r
D
+
PCC – 5V DC
110V
60Hz
solar cells, 3V +
battery DC
PCC – 5V DC
DC-to-DC UP converter
R
Reading: Chapter 16 and 4.4 of A & L.
6.002 Fall 2000 Lecture 24 2
First, let’s look at the diode
iD ⎛ VvD ⎞
iD = I S e − 1 ⎟
⎜ T
+ ⎜ ⎟
⎝ ⎠
vD
I S = 10 −12 A
–
VT = 0.025V
Boltzmann’s constant
kT
VT = temperature in Kelvins
q charge of an electron
iD iD
vD vD
− IS mV V
iD
iD ≥ 0 Æ vD = 0
“short”
or
on
vD
vD < 0 Æ iD = 0 0
“open”
or
off
iD
Short segment
Open segment vD = 0
vD
iD = 0 0.6V
Consider 0.6V
+–
+
vI +
– R vO
–
vI is a sine wave
“Short segment”:
iD = (vI − 0.6 ) / R
+–
+
0.6V
vI ≥ 0.6 + vI R vO = vI − 0.6
–
–
“Open segment”:
iD = 0
+–
+
0.6V
vI < 0.6
+ vI R vO = 0
–
–
vI
vO
0.6
t
0.6V
+–
+
vI + C R vO
–
–
vO
t
C
current
pulses
charging
Demo capacitor
+
VI +
vS C vO load
DC –
switch
S –
vS
S S
closed open
t
T
Tp
The circuit has 3 states:
I. S is on, diode is off
i increases linearly
II. S turns off, diode turns on
C charges up, vO increases
III. S is off, diode turns off
C holds vO (discharges into load)
i
VI T
i (T ) = VI di
L slope = VI = L
L dt
i is a ramp
t
T
1
ΔE = energy stored at t = T : Li( T )2
2
2
VI T 2
ΔE =
2L
i
VI +
– S C
0 t
T T′ TP
1
ωO =
LC
i
VI T
L
0 t
T T′ TP
1
ωO =
LC
i
VI T
L
0 t
T T′ TP
1
ωO =
LC
+
VI +
– S C vO
–
C holds vO after T′
i is zero
Capacitor voltage
vO
0 t
T′ TP
+
VI +
– S C vO
–
C holds vO after T′
i is zero
until S turns ON at TP, and cycle repeats
I II III I II III …
Thus, vO increases each cycle, if there is no load.
vO
vO (n)
t
TP 2TP 3TP
6.002 Fall 2000 Lecture 24 18
What is vO after n cycles Æ vO(n) ?
Use energy argument … (KVL tedious!)
Each cycle deposits ∆E in capacitor.
1
2
ΔE = L i( t = T ) 2
1 VI T 2 2
ΔE = 2
2 L 1 ⎛ VI T ⎞
= L⎜ ⎟
2 ⎝ L ⎠
After n cycles, energy on capacitor
2
nVI T 2
nΔE =
2L
1
This energy must equal CvO ( n )2
2
2 2
1 nV T
so,
2
CvO ( n ) = I
2 2L
2
nVI T 2 1
or vO ( n ) = ωO =
LC LC
vO ( n ) = VI T ωO n
6.002 Fall 2000 Lecture 24 19
How to maintain vO at a given value?
+
VI + vO load
–
–
vO
pwm
control
compare
T change T
Tp + vref
–
2
VI T 2
recall ΔE =
2L
Problem R VO
“0” Æ “1” Vi
expected observed
VO “1” VO “1”
huh?
“0” t “0” t
in forbidden region!
R VO V1
very high
Vi impedance,
like open
circuit
Vi = 5V DC VO = 5V DC V1 = 5V DC OK
5V Vi
b.1
0V t
t=0
VO
5V
b.3
t
t=0 2T
b.2
5V V1
looks ok!
t
t=0 T
6.002 Fall 2000 Lecture 25 4
2.5
R
5
....
Vi R→
characteristic
impedance instantaneous R divider
finite propagation speed
of signals
5V 5V 5V
0 0 2T 0 T
5V VO
2. Keep wires short
EM O w ire 0 t
D mal l
e s 0
us
le l
Paral ation
in
5V VO term
3. Termination
2.5V t
O 0
DEM at the
R
add
end
More in 6.014
0 1
V 1 0
OK
driving a 50 Ω
resistor!
0
V
input
driving a 50 Ω
resistor! Why?
VS Ldi
dt
Inverter current
v inductor
VS
ideal
C
actual
ω
L actual
Disaster!
6.002 Fall 2000 Lecture 25 9
Why? DEMO
Consider
ok
C
R1 DEMO
R0
R2
dV
α
dt
dV
C
dt
crosstalk!
Solution
DEMO
small dV
dt
Recall
Vo
Vi expect
Vo
Vi
but, observe
Vo
Vi
5V
Vi
5V 5V + 3V
So, pullup has
0V 3V stronger drive
as output rises
z KVL: KCL: VI
∑Vi = 0 ∑ Ii = 0
loop node
R2 I
J
V +
–
Notice:
linear in e,V , I
No eV ,VI
terms
R2 I
J
V +
–
e = a1V1 + a2V2 + … + b1 I1 + b2 I 2 + …
Linear!
6.002 Fall 2000 Lecture 3 5
Linearity ⇒ Homogeneity
Superposition
Homogeneity
x1
x2 .
. y
.
⇓
αx1
αx2 .. αy
.
Superposition
x1a x1b
x2 a .
.. ya x2 b .
.. yb
⇓
x1a + x1b
x2 a + x2 b .
.. y a + yb
V1 0
0 y1 V2 y2
⇓
V1 + 0
0 + V2 y1 + y2
u r ce s
e nt so
e p e nd
ind only
i i
+ +
I =0 v
J
v
- -
open
R1
e
R2 I
V +
– J
I acting alone
e
R1
R1 R2
R2 I eI = I
J
V =0 R1 + R2
sum superposition
R2 R1 R2
e = eV + eI = V+ I
R1 + R2 R1 + R2
Voilà !
6.002 Fall 2000 Lecture 3 13
Demo
salt
water
constant
+
–
?
+
–
output shows
sinusoid superposition
J
–
J -
also
By superposition independent
of external
v = ∑ α mVm + ∑ β n I n + Ri excitement &
m n
behaves like
no resistance a resistor
units units
By setting All
∀n I n = 0, ∀mVm = 0, ∀n I n = 0,
i = 0 i = 0 ∀mVm = 0
independent of external
excitation and behaves like a
voltage “ vTH ”
J
–
network -
Thévenin equivalent
RTH i
+
+ vTH
– v E
-
+
V R2 I
J
–
i1 R1
RTH
+ VTH + I
V
– –
V − VTH
i1 =
R1 + RTH
VTH : +
VTH R2 I
J
VTH = IR2 -
RTH : +
RTH R2
RTH = R2 -
1
RTH
v
vTH
“V ”
OC
− I SC
i
J +
+ IN RTH = RN
–
J
+ v
– -
Norton
equivalent
VTH
IN =
RTH
… 101100 …
R2 V0
V1 +
–
+ V1 and V2
V2 – might represent the
outputs of two
sensors, for example.
By superposition,
R2 R1
V0 = V1 + V2
R1 + R2 R1 + R2
If R1 = R 2 ,
V1 + V2
V0 =
2
add noise on
this wire
Receiver:
huh?
HIGH LOW
5V 0V
TRUE FALSE
1 0
VS VR
5V “0” “1” “0” HIGH “0” “1” “0”
5V
2.5V t 2.5V t
0V LOW 0V
With noise
VN = 0.2V VS
VS
“0” “1” “0”
“0” “1” “0” 0.2V
5V t
2.5V t 2.5V t
0V
5V
1
1
1
0 0 0
0V
1 1
VH
3V
sender forbidden receiver
region
2V
VL
0 0
0V
“1” V 5V
H
“0” 0V V
L
0 1 0 1 receiver
5V
V
0H
V
IH
V
IL
V
0L
0V t
Z = X AND Y
X, Y, Z
Z = X • Y are digital signals
Boolean equation “0” , “1”
X AND gate
Y Z
Noise
X
Y Z
Z = X • Y
Z = X • Y
C = A + B Boolean equation
OR
A
B C
OR gate
More gates
B B X
Y Z
Inverter NAND
Z = X • Y
Digital Circuits
Implement: output = A + B • C
B
C B•C
A output
sender receiver
VOH VIH forbidden
VIL region
VOL
A B C
A
B C 0 0 1
NAND 0 1 1
1 0 1
1 1 0
D = (C ⋅ (A ⋅ B ))
3 gates here
C
if A=ON AND B=ON
C has H20
else C has no H20
OR gate
A
C
A B
V +
–
C =0
in
control out
C
in
out
C=1
VS
VOUT
Truth table for
C =0
C VOUT
VS 0 1
1 0
VOUT
C =1
VOUT c1 c2 VO
c1 0 0 1
0 1 1
c2
1 0 1
1 1 0
VOUT
c1 c2 VO
c1 c2 0 0 1
0 1 0
1 0 0
1 1 0
VS
D
A C D = (A ⋅ B) + C
B
G
gate
≡
S
source
D D
iDS
G off G on
vGS < VT S vGS ≥ VT S
VT ≈ 1V typically
+
vDS
+
vGS
– –
iDS
vGS ≥ VT
vGS < VT
vDS
iDS vs vDS
VS = 5V
RL
vOUT
B
A IN
A B
0V V v IN
T =1V 5V
The T1000 model laptop desires gates that satisfy
the static discipline with voltage thresholds. Does
out inverter qualify?
VOL = 0.5V VIL = 0.9V
VOH = 4.5V VIH = 4.1V
sender receiver
1: 5 5 1
4.5 V 4.1
OH VIH
0.9 VIL
0.5 VOL
0: 0 0 0
Our inverter satisfies this.
6.002 Fall 2000 Lecture 5 16
E.g.:
Does our inverter satisfy the static
discipline for these thresholds:
D D D
G G RON
G
S vGS < VT S vGS ≥ VT S
e.g. RON = 5 KΩ
G G RON
G
S vGS < VT S vGS ≥ VT S
MOSFET MOSFET
S model SR model
vGS ≥ VT
vGS ≥ VT
iDS iDS 1
RON
VS
RL Choose RL, RON, VS such that:
vOUT V R
C =1 RON v = S ON ≤ V
OUT R +R OL
vGS ≥ VT ON L
Nonlinear Analysis
SR MOSFET Model
X Analytical method
based on m1, m2, m3
X Graphical method
iD Hypothetical
+ nonlinear
V + vD D
–
- device
(Expo Dweeb ☺)
+ vD -
D
iD
iD = aebvD
iD
a
vD
0,0
(Curiously, the device supplies power when vD is negative)
6.002 Fall 2000 Lecture 6 5
Method 1: Analytical Method
Using the node method,
(remember the node method applies for linear or
nonlinear circuits)
vD − V
+ iD = 0 1
R
iD = aebvD 2
2 unknowns 2 equations
iD
2 iD = aebvD
a
vD
V vD
iD 1 iD = −
R R
V 1
R slope = −
R
vD
V
iD
V called “loadline”
1
R for reasons you
~ 0 .4 will see later
a
¼ vD
~ 0.5 V
1
e.g. V =1 vD = 0.5V
R =1 iD = 0.4 A
1
a=
4
b =1
iD iR
+
vI (t ) +
– vD LED AMP
-
light
intensity iR ∝ I R
I D ∝ iD
light intensity IR
vI music signal in photoreceiver
t LED: Light
Emitting
expoDweep ☺
vI (t ) iD (t ) light iR (t ) sound
nonlinear
linear
problem! will result in distortion
6.002 Fall 2000 Lecture 6 9
Problem:
The LED is nonlinear distortion
iD
iD
vD
t vD = vI
vD
t
iD
vD
t
vD
vD
t
What do we do?
Zen is the answer
… next lecture!
6.002 Fall 2000 Lecture 6 11
CIRCUITS AND
6.002 ELECTRONICS
Incremental Analysis
Nonlinear Analysis
X Analytical method
X Graphical method
Today
X Incremental analysis
iD iR
+
vI (t ) +
– vD LED AMP
-
light
intensity iR ∝ I R
I D ∝ iD
light intensity IR
vI music signal in photoreceiver
t LED: Light
Emitting
expoDweep ☺
vI (t ) iD (t ) light iR (t ) sound
nonlinear
linear
problem! will result in distortion
6.002 Fall 2000 Lecture 7 3
Problem:
The LED is nonlinear distortion
iD
iD
vD
t vD = vI
vD
t
iD
vD
t
ID small region
looks linear
(about VD , ID)
vD
VD
DC offset
or DC bias
Trick:
iD = I D + id
vi (t ) +
– +
vI vD LED
+ -
VI – vD = VD + vd
VI vi
iD
id
ID
vD
VD
very small
vd
VD vD
t
iD id
iD
ID ~linear!
t
Demo
Notation:
iD = I D + id
total DC small
variable offset superimposed
signal
1 d 2 f (v D ) 2
+ ⋅ ∆vD + "
2! dvD 2 v
D =VD
We can write
d f (v D )
X : I D + ∆iD ≈ f (VD ) + ⋅ ∆ vD
d vD vD =VD
id = a ebVD ⋅ b ⋅ vd
id = I D ⋅ b ⋅ vd small signal
behavior
constant linear!
id = I D ⋅ b ⋅ vd
A
slope at
iD
VD, ID
id
ID B
operating
point
vd
vD
VD
we are
approximating
A with B
+ vd -
behaves like:
id 1
R=
ID b
small signal circuit:
id
+ 1
vi + vd
– - I Db
Linear!
Dependent Sources
and Amplifiers
Today
Dependent sources
Amplifiers
+ f ( vI ) +
control output
vI vO port
port
– –
2-port device
Example 1: Find V
+
R V
–
independent
current
I = I0
source
V = I0R
Example 2: Find V
voltage +
R V
controled –
current
source K
I = f (V ) =
V
iI iO
K
f (vI ) =
+ vI +
+
R V vI vO
–
– –
K
V = IR = R
V
or V 2 = KR
or V = KR
= 10 −3 ⋅ 10 3
= 1 Volt
RL VS +
–
iIN iD
+ +
vI +
–
vIN vO
– –
iD = f (vIN )
e.g.
iD = f (vIN )
K
= (vIN − 1) for vIN ≥ 1
2
2
iD = 0 otherwise
Find vO as a function of vI .
RL
iIN iD
+ +
vI +
–
vIN vO
– –
iD = f (vIN )
e.g. iD = f (vIN )
K
= (vIN − 1) for vIN ≥ 1
2
2
iD = 0 otherwise
Find vO as a function of vI .
RL
vI vO
K
iD = (vIN − 1) for vIN ≥ 1
2
vI +
– 2
iD = 0 otherwise
Find vO as a function of vI .
RL
vI vO
K
iD = (vIN − 1) for vIN ≥ 1
2
vI +
– 2
iD = 0 otherwise
KVL
− VS + iD RL + vO = 0
vO = VS − iD RL
K
vO = VS − (vI − 1) RL for vI ≥ 1
2
2
vO = VS for vI < 1
Analog:
AMP
IN OUT
Input Output
Port Port
Besides the obvious advantages of being
heard farther away, amplification is key
to noise tolerance during communication
No amplification
10 mV
e
nois
1 mV
useful
signal
huh?
e
nois
AMP
not bad!
Valid region
5V 5V
VIH IN VOH
OUT
VIL
VOL
0V 0V
Digital System
IN OUT
5V 5V
VIH V OH
VIL
V OL
0V t 0V t
Power port
iI iO
Input +v Amplifier + v Output
port – I – O port
POWER
IN OUT
RL
vI vO
K
iD = (vIN − 1) for vIN ≥ 1
2
vI +
– 2
iD = 0 otherwise
KVL
− VS + iD RL + vO = 0
vO = VS − iD RL
K
vO = VS − (vI − 1) RL for vI ≥ 1
2
2
vO = VS for vI < 1
2
2
= 10 − ⋅10 −3 ⋅ 5 ⋅ 103 (vI − 1)
2
2
vO = 10 − 5 (vI − 1)
2
vO
VS
∆vO
vI
1 ∆vI
∆vO
>1 amplification
∆v I
6.002 – Fall 2002: Lecture 8 19
Plot vO versus vI
vO = 10 − 5 (vI − 1)
2
vI vO
0.0 10.00
1.0 10.00
1.5 8.75
0.1 change 2.0 5.00 1V change
in vI 2.1 4.00 in vO
2.2 2.80
2.3 1.50
2.4 ~ 0.00 Gain!
Demo Measure vO .
What
happens
here?
vI
1
Mathematically,
K
vO = VS − RL (vI − 1)
2
2
What
happens
here?
vI
1
However, from
K
iD = (vI − 1)2 for vI ≥ 1
2
VS
RL
vO
VCCS iD
vO K
i.e. vO = VS − RL (vI − 1)
2
2
where vO goes -ve
vI
Commonly K
iD = (vI − 1)
2
2
will no longer be valid when vO ≤ 0 .
e.g. iD saturates (stops increasing)
and we observe:
vO
vI
1
MOSFET Amplifier
Large Signal Analysis
a + b
+
–
v i = f (v )
a′ – b′
RL
vO
VCCS
K
iD = (vI − 1)
2
vI 2
+
– for vI ≥ 1V
= 0 otherwise
vO = VS − iD RL
K
(vI − 1)2
2
v B
A
i = f (v )
voltage controlled
current source
C
D S
G
S
vGS ≥ VT
?
vDS = vGS − VT
iDS iDS iDS vGS 1
n
vGS ≥ VT egio Saturation
region
de r
vGS ≥ VT vGS 2
T ri o
vGS3
iDS v+DS
+
vGS –
–
vDS = vGS − VT
iDS iDS iDS vGS 1
n
vGS ≥ VT egio Saturation
region
de r
vGS ≥ VT vGS 2
T ri o
vGS3
D
G
vGS < VT
D S
G D
iDS = f (vGS )
S G K
= (vGS − VT )
2
vGS ≥ VT 2
when
S vDS ≥ vGS − VT
vDS = vGS − VT
iDS iDS iDS vGS 1
n
egio
vGS ≥ VT Saturation
region
de r
vGS ≥ VT vGS 2
T ri o
vGS3
...
vGS < VT vGS < VT
vDS vDS vDS
vGS < VT
S MODEL SR MODEL SCS MODEL
for digital for analog
for fun!
designs designs
VS
RL
vO
G D K
vI iDS = (vI − VT )
2
S 2
in saturation
region
S 2
in saturation
region
VS
RL
vO
D K
G iDS = (vI − VT )
2
A
+ 2
vGS = vI + vI for vO ≥ vI − VT
–
S
–
RL
vO
D K
G iDS = (vI − VT )2 A
+ 2
vGS = vI + vI for vO ≥ vI − VT
– – S
2 vO ≥ vI − VT
vO = VS vI < VT
for
(MOSFET turns off)
2
vO ≥ vI − VT
for
⇓
2iDS
vO ≥
K
⇓
K 2
iDS ≤ vO
2
VS v0
B : iDS = −
RL RL
2 2
VS vO
B : DS
i = −
RL RL
iDS
VS K 2
iDS ≤ vO
RL 2
B Lo A
ad
li n vI
e
= vGS
vO
VS
iDS
VS K 2
iDS ≤ vO
RL 2
B A
vI
I DS VI
vO
VO VS
1 vO versus vI
1 vO versus vI
vO
K
VS − (vI − VT ) RL
2
VS 2
vO = vI − VT
gets into
triode region
vI
VT
Our
vI ≥ VT
K 2
Constraints vO ≥ vI − VT iDS ≤ vO
2
iDS K 2
iDS ≤ vO
2
VS
K
iDS = (vI − VT )
2
RL
2 vI
V v
iDS = S − O
RL RL
vO
VS
? vI = VT
vO = VS and iDS = 0
6.002 Fall 2000 Lecture 9 19
Large Signal Analysis
2 What are valid operating ranges
under the saturation discipline?
iDS K 2
iDS ≤ vO
2
K
iDS = (vI − VT )
2
2 vI
VS vO
iDS = −
RL RL
vO
− 1 + 1 + 2 KRLVS
vI = VT +
KRL vI = VT
− 1 + 1 + 2 KRLVS vO = VS and iDS = 0
vO =
KRL
VS vO
iDS = −
RL RL
6.002 Fall 2000 Lecture 9 20
Large Signal Analysis
Summary
1 vO versus vI
K
vO = VS − (vI − VT )2 RL
2