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RMR©2012 Maths is not everything Embedded Systems CPU Input/Output mechanisms Memory Buses and Aux I/O
RMR©2012 Maths is not everything Embedded Systems CPU Input/Output mechanisms Memory Buses and Aux I/O

RMR©2012

Maths is not everything

Embedded Systems
Embedded Systems
CPU Input/Output mechanisms Memory Buses and Aux I/O Input/Output interfaces Power Management
CPU
Input/Output mechanisms
Memory
Buses and Aux I/O
Input/Output interfaces
Power Management
RMR©2012 Maths is not everything UART
RMR©2012 Maths is not everything UART

RMR©2012

Maths is not everything

UART
UART
Maths is not everything RMR©2012 3 Asynchronous Transmission Máquina A Máquina B Tx A Rx
Maths is not everything RMR©2012 3 Asynchronous Transmission Máquina A Máquina B Tx A Rx
Maths is not everything RMR©2012 3 Asynchronous Transmission Máquina A Máquina B Tx A Rx

Maths is not everything

RMR©2012

3
3
Asynchronous Transmission
Asynchronous Transmission
is not everything RMR©2012 3 Asynchronous Transmission Máquina A Máquina B Tx A Rx B Rx
is not everything RMR©2012 3 Asynchronous Transmission Máquina A Máquina B Tx A Rx B Rx

Máquina A

Máquina B

Tx A Rx B Rx A Tx B 65H ‘e’ Bit Time Stop Bits Least
Tx A
Rx B
Rx A
Tx B
65H ‘e’
Bit Time
Stop Bits
Least Significant Bit
Most Significant Bit
Start Bit
Maths is not everything RMR©2012 DB9 pinout of a DTE DTE vs DCE Pinout of
Maths is not everything RMR©2012 DB9 pinout of a DTE DTE vs DCE Pinout of
Maths is not everything RMR©2012 DB9 pinout of a DTE DTE vs DCE Pinout of

Maths is not everything

RMR©2012

DB9 pinout of a DTE
DB9 pinout of a DTE
Maths is not everything RMR©2012 DB9 pinout of a DTE DTE vs DCE Pinout of a
Maths is not everything RMR©2012 DB9 pinout of a DTE DTE vs DCE Pinout of a
DTE vs DCE Pinout of a DCE? Common ground? Noise effects?
DTE vs DCE
Pinout of a DCE?
Common ground?
Noise effects?
Maths is not everything RMR©2012 DB9 pinout of a DTE DTE vs DCE Pinout of a
Maths is not everything RMR©2012 DB9 pinout of a DTE DTE vs DCE Pinout of a
Maths is not everything RMR©2012 RS-232 transmission example How do peers agree on timing?
Maths is not everything RMR©2012 RS-232 transmission example How do peers agree on timing?
Maths is not everything RMR©2012 RS-232 transmission example How do peers agree on timing?

Maths is not everything

RMR©2012

RS-232 transmission example
RS-232 transmission example
Maths is not everything RMR©2012 RS-232 transmission example How do peers agree on timing?
Maths is not everything RMR©2012 RS-232 transmission example How do peers agree on timing?
Maths is not everything RMR©2012 RS-232 transmission example How do peers agree on timing?
How do peers agree on timing?
How do peers agree on timing?
RMR©2012 Maths is not everything SPI
RMR©2012 Maths is not everything SPI

RMR©2012

Maths is not everything

SPI
SPI
Maths is not everything RMR©2012 Serial Peripheral Interface Serial Peripheral Interface
Maths is not everything RMR©2012 Serial Peripheral Interface Serial Peripheral Interface
Maths is not everything RMR©2012 Serial Peripheral Interface Serial Peripheral Interface

Maths is not everything

RMR©2012

Serial Peripheral Interface
Serial Peripheral Interface
Maths is not everything RMR©2012 Serial Peripheral Interface Serial Peripheral Interface
Maths is not everything RMR©2012 Serial Peripheral Interface Serial Peripheral Interface
Serial Peripheral Interface
Serial Peripheral Interface
Maths is not everything RMR©2012 What is SPI?
Maths is not everything RMR©2012 What is SPI?
Maths is not everything RMR©2012 What is SPI?

Maths is not everything

RMR©2012

What is SPI?
What is SPI?
Maths is not everything RMR©2012 What is SPI?
Maths is not everything RMR©2012 What is SPI?
Maths is not everything RMR©2012 What is SPI?
Maths is not everything RMR©2012 What is SPI?
Maths is not everything RMR©2012 SPI Basics d
Maths is not everything RMR©2012 SPI Basics d
Maths is not everything RMR©2012 SPI Basics d

Maths is not everything

RMR©2012

SPI Basics
SPI Basics
Maths is not everything RMR©2012 SPI Basics d
Maths is not everything RMR©2012 SPI Basics d
d
d
Maths is not everything RMR©2012 SPI Capabilities
Maths is not everything RMR©2012 SPI Capabilities
Maths is not everything RMR©2012 SPI Capabilities

Maths is not everything

RMR©2012

SPI Capabilities
SPI Capabilities
Maths is not everything RMR©2012 SPI Capabilities
Maths is not everything RMR©2012 SPI Capabilities
Maths is not everything RMR©2012 SPI Capabilities
Maths is not everything RMR©2012 SPI bus wiring B
Maths is not everything RMR©2012 SPI bus wiring B
Maths is not everything RMR©2012 SPI bus wiring B

Maths is not everything

RMR©2012

SPI bus wiring
SPI bus wiring
Maths is not everything RMR©2012 SPI bus wiring B
Maths is not everything RMR©2012 SPI bus wiring B
B
B
Maths is not everything RMR©2012 SPI signal functions s
Maths is not everything RMR©2012 SPI signal functions s
Maths is not everything RMR©2012 SPI signal functions s

Maths is not everything

RMR©2012

SPI signal functions
SPI signal functions
Maths is not everything RMR©2012 SPI signal functions s
Maths is not everything RMR©2012 SPI signal functions s
Maths is not everything RMR©2012 SPI signal functions s
s
s
SPI uses a “shift register” model of communications Master shifts out data to Slave, and
SPI uses a “shift register” model of communications Master shifts out data to Slave, and
SPI uses a “shift register” model of communications
SPI uses a “shift register” model of communications
SPI uses a “shift register” model of communications Master shifts out data to Slave, and shifts
SPI uses a “shift register” model of communications Master shifts out data to Slave, and shifts
SPI uses a “shift register” model of communications Master shifts out data to Slave, and shifts
Master shifts out data to Slave, and shifts in data from Slave
Master shifts out data to Slave, and shifts in data from Slave
of communications Master shifts out data to Slave, and shifts in data from Slave Maths is

Maths is not everything

RMR©2012

Two bus configuration models Maths is not everything Master and multiple independent slaves RMR©2012 Master
Two bus configuration models
Two bus configuration models
Two bus configuration models Maths is not everything Master and multiple independent slaves RMR©2012 Master and
Two bus configuration models Maths is not everything Master and multiple independent slaves RMR©2012 Master and
Two bus configuration models Maths is not everything Master and multiple independent slaves RMR©2012 Master and

Maths is not everything

Master and multiple independent slaves
Master and multiple independent
slaves

RMR©2012

Master and multiple daisy-chained slaves
Master and multiple daisy-chained
slaves
Maths is not everything RMR©2012 SPI clocking: there is no “standard way”
Maths is not everything RMR©2012 SPI clocking: there is no “standard way”
Maths is not everything RMR©2012 SPI clocking: there is no “standard way”

Maths is not everything

RMR©2012

SPI clocking: there is no “standard way”
SPI clocking: there is no “standard way”
Maths is not everything RMR©2012 SPI clocking: there is no “standard way”
Maths is not everything RMR©2012 SPI clocking: there is no “standard way”
Maths is not everything RMR©2012 SPI clocking: there is no “standard way”
Maths is not everything RMR©2012 SPI timing diagram Timing Diagram – Showing Clock polarities and
Maths is not everything RMR©2012 SPI timing diagram Timing Diagram – Showing Clock polarities and
Maths is not everything RMR©2012 SPI timing diagram Timing Diagram – Showing Clock polarities and

Maths is not everything

RMR©2012

SPI timing diagram
SPI timing diagram
Maths is not everything RMR©2012 SPI timing diagram Timing Diagram – Showing Clock polarities and phases
Maths is not everything RMR©2012 SPI timing diagram Timing Diagram – Showing Clock polarities and phases
Maths is not everything RMR©2012 SPI timing diagram Timing Diagram – Showing Clock polarities and phases
Timing Diagram – Showing Clock polarities and phases
Timing Diagram – Showing Clock polarities and phases
Maths is not everything RMR©2012 SPI example: decode what’s happening
Maths is not everything RMR©2012 SPI example: decode what’s happening
Maths is not everything RMR©2012 SPI example: decode what’s happening

Maths is not everything

RMR©2012

SPI example: decode what’s happening
SPI example: decode what’s happening
Maths is not everything RMR©2012 SPI example: decode what’s happening
Maths is not everything RMR©2012 SPI example: decode what’s happening
Maths is not everything RMR©2012 SPI example: decode what’s happening
Maths is not everything RMR©2012 SPI example: decode what’s happening
Maths is not everything RMR©2012 18 SPI tradeoffs: the pros and cons P
Maths is not everything RMR©2012 18 SPI tradeoffs: the pros and cons P
Maths is not everything RMR©2012 18 SPI tradeoffs: the pros and cons P

Maths is not everything

RMR©2012

18
18
SPI tradeoffs: the pros and cons
SPI tradeoffs: the pros and cons
Maths is not everything RMR©2012 18 SPI tradeoffs: the pros and cons P
Maths is not everything RMR©2012 18 SPI tradeoffs: the pros and cons P
P
P
RMR©2012 Maths is not everything I 2 C
RMR©2012 Maths is not everything I 2 C

RMR©2012

Maths is not everything

I 2 C
I 2 C
Maths is not everything RMR©2012 20 I2C bus I a I I
Maths is not everything RMR©2012 20 I2C bus I a I I
Maths is not everything RMR©2012 20 I2C bus I a I I

Maths is not everything

RMR©2012

20
20
I2C bus
I2C bus
Maths is not everything RMR©2012 20 I2C bus I a I I
Maths is not everything RMR©2012 20 I2C bus I a I I
I a I I
I
a
I
I
Maths is not everything RMR©2012 I2C bus architecture
Maths is not everything RMR©2012 I2C bus architecture
Maths is not everything RMR©2012 I2C bus architecture

Maths is not everything

RMR©2012

I2C bus architecture
I2C bus architecture
Maths is not everything RMR©2012 I2C bus architecture
Maths is not everything RMR©2012 I2C bus architecture
Maths is not everything RMR©2012 I2C bus architecture
Maths is not everything RMR©2012 22 I2C details T c S
Maths is not everything RMR©2012 22 I2C details T c S
Maths is not everything RMR©2012 22 I2C details T c S

Maths is not everything

RMR©2012

22
22
I2C details
I2C details
Maths is not everything RMR©2012 22 I2C details T c S
Maths is not everything RMR©2012 22 I2C details T c S
T c S
T
c
S
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line

Maths is not everything

RMR©2012

23
23
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line SDA
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line SDA

I2C physical layer

Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line SDA
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line SDA
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line SDA
Maths is not everything RMR©2012 23 I2C physical layer master 1 master 2 data line SDA
master 1 master 2 data line SDA clock line SCL + slave 1 slave 2
master 1
master 2
data line
SDA
clock line
SCL
+
slave 1
slave 2
SDL
+
SCL

© 2008 Wayne Wolf

© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C signaling
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C signaling
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C signaling

Maths is not everything

RMR©2012

I 2 C signaling
I 2 C signaling
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C signaling
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C signaling
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C signaling
Maths is not everything RMR©2012 25 I2C clock P t
Maths is not everything RMR©2012 25 I2C clock P t
Maths is not everything RMR©2012 25 I2C clock P t

Maths is not everything

RMR©2012

25
25
I2C clock
I2C clock
Maths is not everything RMR©2012 25 I2C clock P t
Maths is not everything RMR©2012 25 I2C clock P t
P t
P
t
Maths is not everything RMR©2012 26 I2C transaction a
Maths is not everything RMR©2012 26 I2C transaction a
Maths is not everything RMR©2012 26 I2C transaction a

Maths is not everything

RMR©2012

26
26
I2C transaction
I2C transaction
Maths is not everything RMR©2012 26 I2C transaction a
Maths is not everything RMR©2012 26 I2C transaction a
a
a
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34

Maths is not everything

RMR©2012

I2C bus transactions: start and stop conditions
I2C bus transactions: start and stop conditions
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34
Maths is not everything RMR©2012 I2C bus transactions: start and stop conditions 34

34

Maths is not everything RMR©2012 28 I2C address transmission e
Maths is not everything RMR©2012 28 I2C address transmission e
Maths is not everything RMR©2012 28 I2C address transmission e

Maths is not everything

RMR©2012

28
28
I2C address transmission
I2C address transmission
Maths is not everything RMR©2012 28 I2C address transmission e
Maths is not everything RMR©2012 28 I2C address transmission e
e
e
Maths is not everything RMR©2012 29 I2C data transmission
Maths is not everything RMR©2012 29 I2C data transmission
Maths is not everything RMR©2012 29 I2C data transmission

Maths is not everything

RMR©2012

29
29
I2C data transmission
I2C data transmission
Maths is not everything RMR©2012 29 I2C data transmission
Maths is not everything RMR©2012 29 I2C data transmission
Maths is not everything RMR©2012 29 I2C data transmission
Maths is not everything RMR©2012 29 I2C data transmission

© 2008 Wayne Wolf

© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C bus arbitration
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C bus arbitration
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C bus arbitration

Maths is not everything

RMR©2012

I 2 C bus arbitration
I 2 C bus arbitration
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C bus arbitration
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C bus arbitration
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C bus arbitration

© 2008 Wayne Wolf

© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C transmissions multi-byte write S
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C transmissions multi-byte write S
© 2008 Wayne Wolf Maths is not everything RMR©2012 I 2 C transmissions multi-byte write S

Maths is not everything

RMR©2012

I 2 C transmissions
I 2 C transmissions
Maths is not everything RMR©2012 I 2 C transmissions multi-byte write S adrs 0 data data
Maths is not everything RMR©2012 I 2 C transmissions multi-byte write S adrs 0 data data
multi-byte write
multi-byte write
S adrs 0 data data P
S
adrs
0
data
data
P
read from slave
read from slave
S adrs 1 data P
S
adrs
1
data
P
write, then read
write, then read
S adrs 0 data S adrs 1 data P
S
adrs
0
data
S
adrs
1
data
P
Maths is not everything RMR©2012 I2C bus transactions: data transfer
Maths is not everything RMR©2012 I2C bus transactions: data transfer
Maths is not everything RMR©2012 I2C bus transactions: data transfer

Maths is not everything

RMR©2012

I2C bus transactions: data transfer
I2C bus transactions: data transfer
Maths is not everything RMR©2012 I2C bus transactions: data transfer
Maths is not everything RMR©2012 I2C bus transactions: data transfer
Maths is not everything RMR©2012 I2C bus transactions: data transfer
Maths is not everything RMR©2012 I2C bus transactions: data transfer