SYNCHRONOUS 4-BIT UP/DOWN COUNTER

The SN54 / 74LS669 is a synchronous 4-bit up/down counter. The LS669 is a 4-bit binary counter. For high speed counting applications, this presettable counter features an internal carry lookahead for cascading purposes. By clocking all flip-flops simultaneously so the outputs change coincident with each other (when instructed to do so by the count enable inputs and internal gating) synchronous operation is provided. This helps to eliminate output counting spikes, normally associated with asynchronous (ripple-clock) counters. The four master-slave flip-flops are triggered on the rising (positive-going) edge of the clock waveform by a buffered clock input. Circuitry of the load inputs allows loading with the carry-enable output of the cascaded counters. Because loading is synchronous, disabling of the counter by setting up a low level on the load input will cause the outputs to agree with the data inputs after the next clock pulse. Cascading counters for N-bit synchronous applications are provided by the carry look-ahead circuitry, without additional gating. Two count-enable inputs and a carry output help accomplish this function. Count-enable inputs (P and T) must both be low to count. The level of the up-down input determines the direction of the count. When the input level is low, the counter counts down, and when the input is high, the count is up. Input T is fed forward to enable the carry output. The carry output will now produce a low level output pulse with a duration equal to the high portion of the QA output when counting up and when counting down equal to the low portion of the QA output. This low level carry pulse may be utilized to enable successive cascaded stages. Regardless of the level of the clock input, transitions at the P or T inputs are allowed. By diode-clamping all inputs, transmission line effects are minimized which allows simplification of system design. Any changes at control inputs (ENABLE P, ENABLE T, LOAD, UP/ DOWN) will have no effect on the operating mode until clocking occurs because of the fully independant clock circuits. Whether enabled, disabled, loading or counting, the function of the counter is dictated entirely by the conditions meeting the stable setup and hold times.

SN54/74LS669

SYNCHRONOUS 4-BIT UP/DOWN COUNTER

LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09

16 1

16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

Programmable Look-Ahead Up/ Down Binary/ Decade Counters Fully Synchronous Operation for Counting and Programming Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Fully Independent Clock Circuit Buffered Outputs CONNECTION DIAGRAM (TOP VIEW)
RIPPLE CARRY VCC OUTPUT QA 16 15 14 RIPPLE QA CARRY OUTPUT UP/DOWN CK 1 U/D 2 CK A 3 A OUTPUTS QB 13 QB QC 12 QC QD 11 ENABLE T LOAD 10 9

B 4 B

C 5 C

QD ENABLE T LOAD ENABLE D P 8 6 7 D ENABLE GND P

DATA INPUTS

FAST AND LS TTL DATA 5-1

SN54/74LS669
LOGIC DIAGRAM
(3) DATA P0 (9) LOAD (4) DATA P1 (5) DATA P2 (6) DATA P3

(7) ENP (10) ENT (1) U/D

RCO (15) (RIPPLE CARRY OUTPUT)

(2)

CP CP D CP D CP D CP D

QA (14)

QB (13)

QC (12)

QD (11)

GUARANTEED OPERATING RANGES

Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

FAST AND LS TTL DATA 5-2

SN54/74LS669

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits S b l Symbol VIH VIL VIK VOH P Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Others Enable T IIH I Input HIGH C Current Others Enable T Others IIL IOS ICC Input LOW Current Enable T Short Circuit Current (Note 1) Power Supply Current 20 0.8 100 34 mA mA mA 0.1 0.2 0.4 0.35 0.5 20 40 V A A mA mA mA VCC = MAX MAX, VIN = 0 0.4 4V VCC = MAX VCC = MAX VCC = MAX MAX, VIN = 7 7.0 0V 2.7 3.5 0.25 0.4 V V 2.5 0.65 3.5 0.8 1.5 V V Min 2.0 0.7 V Typ Max U i Unit V T Test C Conditions di i Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input p LOW Voltage g for All Inputs VCC = MIN, IIN = 18 mA , IOH = MAX, , VIN = VIH VCC = MIN, or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX MAX, VIN = 2 2.7 7V

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)

Limits S b l Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL P Parameter Maximum Clock Frequency Propagation Delay, Clock to RCO Propagation Delay, Clock to Any Q Enable to RCO U/D to RCO Min 25 Typ 32 26 40 18 18 11 29 22 26 40 60 27 27 17 45 35 40 Max U i Unit MHz ns ns ns ns T Test C Conditions di i

CL = 15 pF F

AC SETUP REQUIREMENTS (TA = 25C)

Limits S b l Symbol tW ts ts ts ts th P Parameter Clock Pulse Width Data Setup Time Enable Setup Time Load Setup Time U/D Setup Time Hold Time, Any Input Min 20 20 35 25 30 0 Typ Max U i Unit ns ns ns ns ns ns VCC = 5 5.0 0V T Test C Conditions di i

FAST AND LS TTL DATA 5-3

SN54/74LS669
PARAMETER MEASUREMENT INFORMATION
tw(clock) CLOCK INPUT 1.3 V ts LOAD INPUT 1.3 V ts DATA INPUTS A,B,C, and D 1.3 V th 3V 1.3 V 0V ts ENABLE P or ENABLE T 1.3 V ts UP/DOWN INPUT 1.3 V ts 1.3 V th 1.3 V 3V th 1.3 V 3V 1.3 V 0V th 0V tw(clock) 3V 1.3 V 1.3 V ts th 1.3 V 0V 3V 1.3 V 1.3 V 0V

VOLTAGE WAVEFORMS
3V ENABLE T INPUT 1.3 V tPHL RIPPLE CARRY OUTPUT 1.3 V 1.3 V 0V tPLH VOL 1.3 V VOH

FAST AND LS TTL DATA 5-4

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