Samsung SCX 1150 MFP Service Manual

Repair Manual
INKJET PRINTER(MFP)
SCX-1150F
CONTENTS
1. Block Diagram 2. Connection Diagram 3. Circuit Description 4. Schematic Diagrams
MAIN
USB AFE
LIU
MODEM & EXT_PHONE SEPERATING PART
TELEPHONE LINE TRANSFORMER
600/ / 600 Tx/ Rx
1. Block Diagram
Samsung Electronics
RING DETECTION PART
PC
MODEM
(33.6Kbps)
BUFFE
EXTERNAL PHONE DETECTION PART
P1284 CONN
MODEM CLOCK 28.224MHz
COLOR
MAIN CLOCK
EXTERNAL LINE
Jupi t er 3
10MHz
ARM7TDMI
MONO CARTRI DGE

MEM. SNTR Head Control I/F SCAN SNTR
Spi t f i r e RESET
PRINT HEAD(2PEN) 600DPI DOUBLE
SPEAKER
OPE
DERASTERIZER
UART 3
(Super cap 1F)
HEIGHT ENCORDER SENSOR

BACK UP
PAPER EXIT SENSOR
IEEE 1284 TIMERS

I / O PO R T INT. CNTR
CARRIAGE RETURN MOTOR

REAL TIME CLOCK
USB RTC Cl ock
FLASH (8Mbit) SDRA M (64Mbit)
KEY PANNEL
SCANNER
Thunder bol t
LINE FEED
MOTOR 48MHz /REQ /ACK
CCD Module
ADC SCAN MOTOR
(UNI - POLAR S TEP)
COVER OPEN SENSOR
POWER
+5V +11.75V
SMPS
+30V
ADF MODULE
SCANSTEPPER
DOC. DET SENSOR DOC. POS SENSOR
( 30V, 3. 3V) SDRAM (64Mbit)
+3.3V
IMAGE PROCESSOR OA-980
AC
ADF STEPPER MOTOR DRIVER
ADF
BLOCK DIAGRAM
Repair Manual
( 110~240V)
1-1
CONNECTION DIAGRAM
2. Connection Diagram
Refer to the Schematic diagram(See page 4-2)
Repair Manual Samsung Electronics
2-1
CIRCUIT DESCRIPTION
3. Circuit Description
MAIN PBA
3-1. GENERAL DESCRIPTION

Main circuit consists of mainly consists of CPU and the controller part with various types of built-in I/O device driver(built-in RISC Processor Core: ARM7TDMI), system memory part, OA980 controlling input of image received from media and conversion, CF(COMPACT storage card) interface part. The following nomenclatures by section is the same as those listed in the circuit diagram.
3-2. MEMORY MAP

The entire Addressing area provided by MAIN CONTROLLER(S3C46MOX(Jupiter3)) is 256MBytes from 0x00000000 to 0x10000000, and the Max. Address Range for each External Chip Select is 32M Byte or Half word from 0x000000 to 0x01FFFFFF and embodied with Big-Endian Bus interface. MEMORY area is divided into EXTERNAL ROM and RAM areas(See (Figure 1)), and the areas actually used are 8M/8M BYTES SDRAM and 1M BYTES ROM(FLASH MEMORY).
SDRAM(8MB)
USER MEMORY(3MB Start ~ ) 0xC300000 PIXEL TO LINE BUFFER(30KB) 0xC2CBC20 Chunk Buffer(8KByte) 0xC2C9C20 Read Print Buffer (32Byte) 0xC2C9C00 Swath Buffer(300KBy te) 0xC27EC00 Scan Buffer(810KB) 0xC1B4400 RGB Buffer(30KB) 0xC1ACC00 ECM Buffer(64KB) 0xC19CC00 RCP PC FAX Buffer(15KB) 0xC199000 JPEG DECODE BUFFER(64KB) 0xC099000 MDM Out Buffer(20KB) 0xC094000 MDM In Buffer(28KB) 0xC08D000 JPEG INPUT Buffer(220KB) 0xC056000 System AREA(344K) 0xC000000
0x0FFF_FFFF GCS 7 Area 0x0E00_0000 0x0DFF_FFFF GCS6 Area - DRAM(8MB) 0x0C00_0000 0x0BFF_FFFF Reserved 0x0A00_0000 0x09FF_FFFF GCS 4 Area - OA980 PO CS 0x0800_0000 0x07FF_FFFF GCS 3 Area - EXTENDED GPIO 0x0600_0000 0x05FF_FFFF GCS 2 Area - MODEM 0x0400_0000 0x03FF_FFFF GCS 1 Area - OA980 0x0200_0000 0x01FF_FFFF Special Registers 0x01C0_0000 0x000F_FFFF Program Area(1MB used) 0x0000_0000
Flash memory(1MB)
OASIS Rom Code : 256KB (Sector 15 ~ Sector 18) J3 ROM Code :704KB (Sector 4 ~ Sector 14) Backup Data(Sector 3:32KB) Not Used(Sector 1,2: 16 KB) Boot Rom Code(Sector 0 : 16KB)
<Figure 1. S3C46MOX(Jupiter3) MEMORY MAP>
3-1
CIRCUIT DESCRIPTION
3-3.DETAILED DESCRIPTION
3-3-1 BLOCK DIAGRAM and MAIN CONTROLLER description
3-3-1-1 General description
MAIN CONTROLLER(S3C46MOX(Jupiter3),U15) consists of this system consists of CPU(ARM7TDMI RISC PROCESSOR), 8K BYTES CACHE, DATA and ADDRESS BUS, PLL deriding input frequency and CLOCK CONTROL part, SERIAL COMMUNICATION part supporting UART, PRINT HEAD control part, PARALLEL PORT INTERFACE part, USB INTERFACE part, External DMA part for receiving data from external COLOR IMAGE PROCESSOR(OA980,U21), MEMORY and EXTERNAL BANK control part, SYNCHRONOUS SERIAL INTERFACE control part for interfacing Thunderbolt, and LF/CR Motor drive control and general purpose I/O control parts.(See Figure 2 )
3-3-2 S3C46MOX(Jupiter3) FUNCTION DESCRIPTION

3-3-2-1 SYSTEM CLOCK
There are two ways of Clock input method. One is the method to make Master Clock(MCLK) at the internal PLL by connecting X-tal and Capacitor to the outside, and another method is to use MCLK(When inputting 40MHz) directly, which supplies maximum 40MHz Clock to the EXTCLK terminal(PIN65). The range of frequency being input in case of using X-tal is limited to 4MHz~10MHz. This system uses SSCG(FS781) with a 10MHZ X-tal outside to make MCLK, and supplies Clock to the XIN terminal(PIN67) of ASIC by expanding Spectrum with bandwidth about 1.5% in comparison with the basic frequency by using this IC. Inside the ASIC, the PLL makes 66MHz MCLK signal, which is the basic operation frequency of the System. Also, this PLL makes 48MHz, the operation frequency of USB Controller.
3-3-2-2 DATA and ADDRESS BUS CONTROL 1. /RD & /WR

/RD & /WR SIGNAL are synchronized with the inside MCLK(66MHZ) and becomes active to Low. These signal are Strobe Signal used to Read or Write data when each Chip Select becomes active connected to /RD,/WR PIN of RAM, ROM, OA-980.
2. CHIP SELECT (/ROMCS, /IP_CS,/MED_CS,/SCS0,/SCS1)

- /ROMCS : FLASH MEMORY(U7) CHIP SELECT (LOW ACTIVE) - /IP_CS : OA-980(U21) CHIP SELECT (LOW ACTIVE) - /SCS1 : SDRAM(OPTION)(U12) CHIP SELECT (LOW ACTIVE) In case each Chip Select is low, it may Read or Write data.
3. D0 ~ D15
- 16BIT DATA BUS
4. A0 ~ A24
- ADDRESS BUS (A23 ~ A24 RESERVED)
3-2
MAIN
USB AFE P1284 CONN
LIU
MODEM & EXT_PHONE SEPERATING PART
TELEPHONE LINE TRANSFORMER
600/ / 600 Tx/ Rx
Samsung Electronics
RING DETECTION PART
PC
MODEM
(33.6Kbps)
BUFFE
EXTERNAL PHONE DETECTION PART
MODEM CLOCK 28.224MHz
COLOR
MAIN CLOCK
EXTERNAL LINE
Jupi t er 3
10MHz
ARM7TDMI
MONO CARTRI DGE

MEM. SNTR Head Control I/F SCAN SNTR
Spi t f i r e RESET
PRINT HEAD(2PEN) 600DPI DOUBLE
OPE
SPEAKER
HEIGHT ENCORDER SENSOR DERASTERIZER

UART 3
(Super cap 1F)
BACK UP
PAPER EXIT SENSOR
IEEE 1284 TIMERS

I / O PO RT INT. CNTR
CARRIAGE RETURN MOTOR
FLASH (8Mbit) SDRA M (64Mbit)
KEY PANNEL
SCANNER
<Figure 2. Block Diagram of Main Part>
Thunder bol t
REAL TIME CLOCK
RTC Cl ock USB
LINE FEED
48MHz /REQ /ACK
MOTOR
CCD Module
ADC
(UNI -POLAR STEP)
COVER OPEN SENSOR
SCAN MOTOR
POWER
+5V +11.75V
SMPS
SDRAM (64Mbit)
+30V
ADF MODULE
SCANSTEPPER
DOC. DET SENSOR DOC. POS SENSOR
( 30V, 3. 3V)
+3.3V
IMAGE PROCESSOR OA-980
AC
ADF STEPPER MOTOR DRIVER
ADF
CIRCUIT DESCRIPTION
Repair Manual
( 110~240V)
3-3
CIRCUIT DESCRIPTION
EXTCLK tRAD ADDR tRCD nGCSx Tacs tRWD nWE Tocs nGCSx nBEx 1 tRDD DATA tRDH Tacc Toch Tcah tRWD tRCD tRAD
<Figure 3. Flash Memory Read Timing>
EXTCLK tRAD ADDR tRCD nGCSx Tacs tRWD nWE Tocs nGCSx tRWBED nBEx Tcos Toch tRDD DATA tRDD tRWBED Tacc Toch Tcah tRWD tRCD tRAD
<Figure 4. Flash Memory Write Timing>
3-4
CIRCUIT DESCRIPTION
SCLK SCKE ADDR/BA tSAD AP/A10 tSCSD nGCSx tSRD nSRAS Trp nSCAS tSBED nBEx tSWD nWE tSDS DATA tSDH Tcl Trcd tSCD 1 tSAD
<Figure 5. SDRAM Read Timing>
3-5
CIRCUIT DESCRIPTION
SCLK SCKE 1 tSAD ADDR/BA tSAD AP/A10 tSCSD nGCSx tSRD nSRAS Trp nSCAS Trcd tSCD tSBED nBEx tSWD nWE tSDD DATA tSDD
<Figure 6. SDRAM Write Timing>
3-6
CIRCUIT DESCRIPTION
SCLK
SCKE
1 tSAD tSAD
ADDR/BA tSAD AP/A10 tSCSD nGCSx tSRD nSRAS Trp tSCD nSCAS Trc tSRD tSCSD
nBEx
1 tSWD
nWE
DATA
HZ
<Figure 7. SDRAM Write Timing>
3-7
CIRCUIT DESCRIPTION
SCLK
SCKE
1 tSAD tSAD
ADDR/BA tSAD AP/A10 tSCSD nGCSx tSRD nSRAS Trp tSCD nSCAS Trc tSRD tSCSD
nBEx
1 tSWD
nWE
DATA HZ
<Figure 8. SDRAM auto Refresh Timing>
3-8
CIRCUIT DESCRIPTION
SCLK tCKED SCKE tSAD ADDR/BA tSAD AP/A10 tSCSD nGCSx tSRD nSRAS Trp tSCD nSCAS 1 tSRD 1 1 Trc tSCSD 1 tSAD tCKED
nBEx
1 tSWD
nWE
DATA
HZ
HZ
<Figure 9. SDRAM Self Refresh Timing>
3-9
CIRCUIT DESCRIPTION
Parameter ROM/SRAM Address Delay ROM/SRAM Chip select Delay ROM/SRAM Output enable Delay ROM/SRAM read Data Setup time ROM/SRAM read Data Hold time ROM/SRAM Byte Enable Dalay ROM/SRAM Write Byte Enable Delay ROM/SRAM output Data Delay ROM/SRAM external Wait Setup time ROM/SRAM external Wait Hold time ROM/SRAM Write enable Delay DRAM Address Delay DRAM Row active Delay DRAM Read Column active Delay DRAM Output enable Delay DRAM read Data Setup time DRAM read Data Hold time DRAM Write Cas active Delay DRAM Cbr Cas active Delay DRAM Write enable Delay DRAM output Data Delay SDRAM Address Delay SDRAM Chip Select Delay SDRAM Row active Delay SDRAM Column active Delay SDRAM Byte Enable Delay SDRAM Write enable Delay SDRAM read Data Setup time SDRAM read Data Hold time SDRAM output Data Delay SDRAM Clock Enable Delay
Symbol tRAD tRCD tROD tRDS tRDH tRBED tRWBED tRDD tWS tWH tRWD tDAD tDRD tDRCD tDOD tDDS tDDH tDWCD tDCCD tDWD tDDD tSAD tSCSD tSRD tSCD tSBED tSWD tSDS tSDH tSDD tCKED
Min -
Typ. 12 11 11 1 5 13 14 14 1 5 14 12 11 11 12 1 5 14 12 13 14 4 4 4 4 5 5 4 0 8 5
Max -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
< ROM/SRAM Bus Timing Constants > (VDDP : 3.3V, VDDI : 2.5V, Ta =25C, PLCAP=70pf, Max/Min=typ. 30%)
3-10
CIRCUIT DESCRIPTION
3-3-2-3 EXTERNAL DMA part

The function of this part is to bring data from external DEVICE(OASIS:U21) by using GENERAL DMA. If DMA REQUEST(/IP_REQ) is sent from external DEVICE to S3C46MOX(JUPITER3:U15), DMA ACKNOWLEDGE SIGNAL(/IP_ACK) is activated and the GENERAL DMA is driven, so READ STROBE(/RD) in the external DEVICE to bring data from the external DEVICE requiring CHANNEL. To transfer this DATA to the DESTINATION MEMORY, the ADDRESS of the DESTINATION MEMORY, CHIP SELECT and WRITE STROBE(/WR) are generated to store. That is, if the EXTERNAL DMA is required by the external DEVICE, S3C46MOX(Jupiter3:U15) responds to drive the inside DMA CONTROLLER and then allocate GENERAL DMA to external CHANNEL so that the data may be transferred to MEMORY TO MEMORY or external DEVICE TO MEMORY.
For more details, see the circuit description, see the circuit description part of IMAGE PROCESSOR (5.3).
ing hour, minute, second, year, month, and day. While the power is on and the Crystal is being oscillation, the RTC Logic independently counts the time without control by Software and marks the value of hour, minute, second, year, month, and day at the appropriated Register. Software confirms the value of the Register and displays it at LCD.
3-3-2-6 PARALLEL PORT INTERFACE division

S3C46MOX(Jupiter3) has the Parallel Port Interface part enabling Parallel Interface with PC. This part is connected to PC through Centronics Connector in this system, which consists of /ERROR, PE, BUSY, /ACK, SLCT, /INIT, /SLCTIN, /AUTOFD, /STB and 245DIR as the part generating the main control signal used to drive PARALLEL COMMUNICATION. Data transmission method between this part and PC supports the method specified in P1284 Parallel Port Standard (http://www.fapo.com/ieee1284.html) of IEEE. That is, the Compatibility mode, the fundamental transmission method of print data, supports the Nibble Mode(4bits data) supporting the Data Uploading to PC, Byte Mode(8bits data), and ECP(Enhanced Capabilities Port : 8 bits data transmission & receiving) supporting two-way high speed transmission to PC. The Compatibility mode and ECP mode may be simply explained as follows. The Compatibility mode is generally called Centronics mode and is the protocol used for transmitting data by most of PC. The ECP mode provides two-way high speed communication as the protocol suggested for improved communication with peripheral equipments such as printer and scanner. The ECP mode provides two types of cycles in two-way transmission. They are data and command cycles. Command cycle again has Run-length count and Channel addressing types. First, RLE (Run Length Encoding) type, having 64-fold compressibility, is available for the real time data compression, and is used usefully for printer and scanner, which have to transmit large capacity of raster image having a series of same data. Next, Channel Addressing is proposed for addressing single structure of multi-device. For example, although the printer channel is processing the printer image when the fax/printer/scanner have one structure like this system, they may use parallel port for another use. This system does not apply to the parallel port Interface.
3-3-2-4 DRAM control part

Since S3C46MOX(Jupiter3) has the DRAM CONTROLLER build-in, it may be used by connecting DRAM with external memory. The Control mode of DRAM CONTROLLER provided by S3C46MOX(Jupiter3) is available for EARLY WRITE, NORMAL READ, PAGE MODE, and BYTE/HALF WORD ACCESS, and is supported even by EDO DRAM,and SDRAM as well as, Fast page DRAM. This system uses SDRAM, and the signal used for READ/WRITE uses /RD,/WR signal used for SYSTEM BUS CONTROL. It is supported with auto REFRESH and also by the Self-refresh mode for DRAM BACK UP. It consists of 2 Banks connected to common /SCS[1:0], /SCAS, /SRAS, /SCLK, /SCKE, /DQM[1:0], each of them may use up to 2M ~ 32M HALF WORD. In this system, 2 MB is applied as system memory. The area of DRAM is specified in the DRAM MEMORY MAP of Fig. 1, while the related TIMING DIAGRAM in Fig. 5, 6, 7, 8, 9.
3-3-2-5 RTC (REAL TIME CLOCK) part

RTC Circuit is logic for maintaining information of the current time, and it is operated in both conditions, Primary Power and Battery Back-up. Additional RTC IC is not used because RTC is built-in at MFP Controller. RTC Logic at inner part of ASIC accepts Crystal (32.768KHz:X3), which is inputted from outside, as a Clock Source, and it divides the Clock by every minute for mak-
3-11
CIRCUIT DESCRIPTION
<Figure 10. Compatibility Hardware Handshaking Timing>
1. Write the data to the data register. 2. Program reads the status register to check that the printer is not BUSY. 3. If not BUSY, then Write to the Control Register to assert the STROBE line. 4. Write to the Control register to de-assert the STROBE line.
BYTE 0
BYTE 1
<Figure 10-1. ECP Hardware Handshaking Timing (forward)>
1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD. 2. Host asserts nSTROBE low to indicate valid data. 3. Peripheral acknowledges host by setting BUSY high. 4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral. 5. Peripheral sets BUSY low to indicate that it is ready for the next BYTES. 6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low.
3-12
CIRCUIT DESCRIPTION
BYTE 0
BYTE 1
<Figure 10-2. ECP Hardware Handshaking Timing (reverse)>
1. The host request a reverse channel transfer by setting nINIT low. 2. The peripheral signals that it is OK to proceed by setting PE low. 3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high. 4. Peripheral asserts nACK low to indicate valid data. 5. Host acknowledges by setting nAUTOFD high. 6. Peripheral sets nACK high. This is the edge that should be used to clock the data into the host. 7. Host sets nAUTOFD low to indicate that it is ready for the next BYTES. 8. The cycle repeats, but this time it is a command cycle because BUSY is low.
3-13
CIRCUIT DESCRIPTION
3-3-2-7 USB INTERFACE PART

1. USB function description
As the mode of implementing low cost express PC Interface, USB was applied. At USB, PC plays the role of route hub simultaneously by existing in the highest level as the host. That is, the device supporting each USB is connected centering on PC. The device is available for Interface for the maximum of 127. USB cable is composed of total of a set of twisted pair and 2 power lines. Cables have two types. One is used for express transmission of 12Mbps and may be extended as long as 5m. The part for implementing USB function is included in S3C46MOX(Jupiter3). For Interface of USB, pull-up of 15K is interfaced to the data line of high level instruments, and, among data lines of lower level instruments, pull-up resistance of 1.5K is interfaced to any one. At this time, D+ line is pulled up for Full Speed device, and, for Low Speed device, D-line is pulled up. For upper level instruments(Host, HUB) speed of device is classified interfaced to low level by detecting any one among D+ and D-. If both lines are in the level of GND at the same time, device is judged that low device is not interfaced. In the transmission mode of USB, there are (1) Control transmission, (2) Interrupt transmission, (3) Bulk transmission, isochronous transmission. Control transmission is for Host to find out configuration information from USB device. This is conducted when device is interfaced. Interrupt transmission is used when small quantity of data is sent periodically. Interval value may be known from device in the case of initial setting. Bulk transmission is valid in case of trying to transmit data in large quantities or in case of transmitting them accurately. Isochronous transmission should be assured of bandwidth, and is used when transmitting large quantities of information. Data in voice is used where delay is not allowed but small error is allowed. At USB coding mode and bit stepping are being conducted. First, in case original data is 1, bit shall not change, and only when original data is 001, it shall be inverted. Only while data is 1, 1 and 0 shall be repeated. Also, in case 1, original data, is continued in 6 bit, 0 shall be inserted, Also, in the 1st phase of packet, data in the synchronized pattern shall be sent. About more detailed information regarding USB, see http//:www.usb.org.
2. operation description
This system, when Host and USB cables are connected, and when +5V is detected in power detector inside chip and Vbus(U15-98), 3.3V comes out through Pull-uP terminal. This is also connected to D+ in pattern of hardware and supports Full-speed. Utilizing Configuration Endpoint, EPO, in USB controller, Plug & Play function is operated. Exchange of information between PCs is accomplished through D+(U15-95) and D-(U15-96) terminals. This terminal decides transmission speed depending on connection of regulator output in USB controller, and decides size of signal following USB and SPFC. Signal of general D+ and D- terminals are same as Figure 10-3.
D+
D< Figure 10-3. USB Signal Line DIAGRAM >
3-14
CIRCUIT DESCRIPTION
3-3-2-8 HEAD control part

1. Entire description
As part to drive INKJET HEAD, it is composed of ACLK, AGATE, LDCS, LATCHCTL, PCLK, PDATA[3:0], PLOAD, PENABLE signals for controlling Spitfire of CR BD generating signal, which is driving Nozzle of Head, and PH_ID[1:0] and OK2Print signals receiving from Spitfire. Here,HEAD being used here is DOUBLE HEIGHT PRINT HEAD, and MONO is configured with 208 NOZZLE, and COLOR is with 192 NOZZLE.
4. Control Signal
The signal loaded on PDATAO - PDATA2 at Rising edge of LATCHCTL(Latch Control Nibble) is used as function as follows in Spitfire. - PDATA0 == ADIR > Low : ACLK is operated in Count Down, High : ACLK is operated in Count Up. - PDATA1 == When Fault Test > High, check whether P-Line of Head became short with GND. - PDATA2 == When Print Head ID Check > high, make sure that Check mode is set, and, after that, by using the PDATA0~PDATA2 LIne, make A1-A3 signal for sending, and Head ID shall come out with PH_IDn output. At this time ID could be displayed only if each Substrate heater is turned on. The signal loaded into PDATAO-PDATA3 at Rising edge of LDCS(LoadHtrcs) signal is used in the following functions in Spitfire. - PDATA0 == BLKHTR> High : Turn on Substrate Heater of Mono Head. - PDATA1 == COLHTR> High : Turn on Substrate Heater of Color Head. - PDATA2 == nHSM> Low : Enable Select Signal of Mono Head. - PDATA3 == nHSC> Low : Enable Select Signal of Color Head. When Substrate Heater is turned on, Over-current Check circuit is operated, automatically, and,if the current is above 750mA, the printer stops operation after OK2PRT becomes low.
The Timing diagam below shows signal timin for the P-line block
ACLK An PCLK PDATA PLOAD PENABLE Pn
<Figure 11 HEAD Control Part Timing Diagram>
2. A-LINE driving circuit

13 Address Lines are input into 13 Address Counters in sequence at Rising edge of ACLK signal, which is input serially into Spitfire. Output of this Counter was connected to each A-line driver, and this driver output becomes A-line signal. The sequence of signal input into Address Counter is decided by ADIR, and if it is ADIR=0, it is input in sequence of A13A1, and if it is ADIR=1, in sequence of A1 => A13. AGATE signal is used to reset Address Counter. If it becomes AGATE=1, A-Line output becomes Low state. The cycle of ACLK is 1.5 in minimum, and Sink current of each Driver is 60mA.
3. P-LINE drive circuit

P-Line values are clocked to 4-bit Serial to Parallel Shift Register Clock in Spitfire ASIC, and ASIC shall clock-in Pline NO. of fitting value at Rising Edge of PCLK. These values are latched to Holding register at Rising Edge of PLOAD. PLOAD Pulse Duration is 50n, and P-line value of Holding Register is done AND with PENABLE signal in order to generate appropriate Fire Pulse. PLCK is available for handling as much as 4MHz. Drive Current of P-line is 400mA. Data of P1P4 is shifted to PDATAO, that of P5P8 shifted to PDATA1, that of P9-P12 shifted to PDATA2, and that of P13-P16 shifted to PDATA3.
3-15
CIRCUIT DESCRIPTION
3-3-2-9 SYNCHRONOUS SERIAL INTERFACE part

As the part interfacing with THUNDERBOLT ASIC, it consists of /TBCS,TBCLK,TBDO. In sending SERIAL DATA of 13 BIT to Thunderbolt ASIC, meaning of each bit is as follows. BIT 1 is the bit to do On/Off VPH(+11.82V), BIT [2:7] is the bit for driving MOTOR 1, BIT [8:13] is the bit to drive MOTOR 2. MOTORs are available for being used as STEPPER MOTOR and DC MOTOR respectively.
3-3-2-10 MOTOR control part (DIR, PWM, LFPHA,LFPHB, LFIA[0:1], LFIB[0:1])

S3C46MOX(Jupiter3) is arranged to support one Step motor and one DC motor. This system does not use the Motor control part provided by S3C46MOX(Jupiter3).
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13
STEPPER MOTOR VPH_ENABLE MOTOR1_CURR_I1_PHASEB MOTOR1_CURR_I0_PHASEB MOTOR1_DIR_PH_B MOTOR1_CURR_I1_PHASEA MOTOR1_CURR_I0_PHASEA MOTOR1_DIR_PH_A MOTOR2_CURR_I1_PHASEB MOTOR2_CURR_I0_PHASEB MOTOR2_DIR_PH_B MOTOR2_CURR_I1_PHASEA MOTOR2_CURR_I0_PHASEA MOTOR2_DIR_PH_A
DC MOTOR VPH_ENABLE Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. MOTOR1_DIRECTION Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. Not used in this mode. MOTOR2_DIRECTION
Tcs-sclk Tcs-sclk
/ TBCS
Data Latcked on the rising edge of SCLK
TBCLK
Tdsu Tdhd
bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13
MSB
SDI stays at last value
TBDO
bit 1
LSB
bit 2
bit 3
bit 4
bit 5
time
< Figure 12 SYNCHRONOUS SERIAL INTERFACE TIMING DIAGRAM >
3-16
CIRCUIT DESCRIPTION
3-3-2-11 GENERAL PURPOSE I/O PORT of S3C46MOX(Jupiter3)

1. J3 Assigned GCS Ports
2. J3 Assigned GPI Ports
3-17
CIRCUIT DESCRIPTION
3. J3 Assigned GPO
3-18
CIRCUIT DESCRIPTION
3-3-3 RESET circuit

This system is configured with PRIMARY RESET(/POR) of Power Reset, Reset by WATCH DOG TIMER, external PRIMARY RESET, and SECOND RESET(/_F_POR) which was done AND. PRIMARY RESET SYSTEM is used for resetting MAIN CONTROLLER(U15) when System Power is authorized, and SECOND RESET resets FLASH MEMORY(U7). Figure 15 below is BLOCK DIAGRAM related to the reset of entire system. When +3.3V reaches 3.1V so that system may operate, POWER MONITOR(U13) moves to High(+3.3V) after maintaining low(OV) in the degree of 50mS-200mS output while monitoring it. This Reset signal is input into MFP CONTROLLER(S3C46MOX(Jupiter3 : U15) right away, and MFP CONTROLLER becomes awake. And it releases /F_POR after MCLK 1 clock.
3-3-3-1 POWER MONITOR ( U13 )

Since +3.3V power supplied to XC61FN3112MR is unstable, when it becomes 3.1V(3.038V~3.162V), it is checked as the POWER FAILURE. And the output terminal of XC61FN3112MRF becomes LOW(0V),it is applied to S3C46MOX(Jupiter3)(U15), and RESET(LOW ACTIVE) is operated When S3C46MOX(Jupiter3) Reset is cancelled, FLASH MEMORY connected to /F_POR of S3C46MOX(Jupiter3) is Reset together. Output terminal of XC61FN3112MRF is pulled up 100K in the structure of Open drain.
3-3-3-2 WATCH DOG OUTPUT (/F_POR)

Since WATCH DOG TIMER, which is Programmable Counter in S3C46MOX(Jupiter3) is set as disable for INITIAL STATE, it shall be set as Disable so that it wont operate, and after it is initialized for operation, it shall be reused by setting it Enable. When Watch Dog Reset occurs, it is about 10mS depending on the value set at the initial stage. And Counter value of Watch Dog Timer is changed by the program. Reset signal (/F_POR,UI5-106) shall be generated, and entire system shall be Reset and initialized.
< Figure 13. POWER RESET BLOCK DIAGRAM >
3-19
CIRCUIT DESCRIPTION
3-4 MEMORY
3-4-1 General Information
The memories of this system are 1MB of Flash Memory (U7), 8MB of SDRAM (U8), and 8MB of SDRAM (U27).
3-5 Image processing part (U21)

3-5-1 General description
Image Processor OA-980(U21) is mainly configured with On-chip Controller(8bit), Scanner Interface Section(PI), Image Processing Section(IP), Memory Interface Section(MI), JBIG Comp & Decomp Section, Rotate and Inkjet Engine Section, Printer Interface Section(PO), 1284 Parallel Port Interfaced and Host Interface Section(HI). (See Figure 14 )
3-4-2 Construction of the Memory

The Flash Memory and SDRAM are selected by each Chip Select (/ROM_CS, /SCS1, /SD_RAS, and /SD_CAS), and data accesses with Half Word unit.
3-5-1-1 Physical 3-4-3 Memory Backup and Self Refresh 3-4-3-1 Self Refresh Mode
It is a Mode for maintaining the stored data at SDRAM when Set Main Power is not supplying for a long time as the case of the Battery back up. When POR (U15-46) is low, set the S3C46MOX (U15)/RAS(U8-18), /CAS(U817), CS(U8-19), and CLKE(U8-37) to LOW, and support /WE(U8-16) to HIGH to operate the Self Refresh. At this moment, the consumption of the electronic current is remarkably reduced (1mA). The CLKE has to be maintained as LOW at Self Refresh Mode, and all the input signals including Clock is ignored at this point. For an escape from the Self Refresh Mode, the Clock must be supported normally, and CLKE must be changed to HIGH.
Core 8bit Microcontroller Process 0.35U CMOS Drive power /frequency 3.3V 75MHz Package 208pin QFP Design OASIS
3-5-1-2 Features & Functions

10bit scanning interface : Supports CIS and CCD interface. Needs external ADC(up to 16bit). Image processing Section : Full quality RGB to CMYK or 6 color conversion Photo/Text detect allows mixed documents. Arbitrary image scaling using true interpolation. Automatic contrast and brightness correction. Error diffusion or programmable dither arrays. JBIG compression block : JBIG/MH/MR/MMR Comp. & Decomp. Inkjet engine format : Rotates data to suit the Lexmark engine format Printer Interface section : Supports a single byte DMA with 150MHz clock speed. Microcontroller interface part : 8bit multiplexed bus acts as address and data bus General purpose input and output port : 30 GPIO pins.
3-4-3-2 Memory Backup Circuit

U1, U2, and U3 (DRAM I/F Circuit) supply the /RAS and /CAS signals (DRAM Control signal) via Invert signal (U31) of /F_POR and Gate (U1-1, U1-2), and control the Enable signal (SD_CKE) by /F_POR (Power on Reset). It means that DRAM Control Signal might not be affected before /F_POR is released, that is, the power is instable. BACKUP Power Circuit (R12, R13, Q8, R17, C31, D2, R21, C30) converts the main power and Backup power by /F_POR signal. Q2 supplies proper amount of the electronic current (hFE=120, 300mA) from the main power to operate SDRAM, and it is driven by Switching TR Q8 which is controlled by /F_POR signal. Backup in a short period of electricity failure is guaranteed by using electrolysis CAP (1F/5.5V:C17) with Backup power. Serious resistance of R16 is converted to the main power, so it never interrupts the main power by given a limit of current when C17 is charged. C31 helps to minimize the power drop in case of power change. D2 and R21 are supplied to RTC Power (U15-87) via VB2 for RTC Backup.
3-20
CIRCUIT DESCRIPTION
3-5-2 OA-980 Description by functions 3-5-2-1 Clock Control Section

Internal drive frequency operates classified into two parts. Almost all On-chip Controller(8bit) Module drives by Main_clock, and Printer Interface Section(PO) only drives by Base_clock. Main_clock and Base_clock may be set with frequency each desires by receiving Clock supplied from outside by PLL Logic. At present, system Main_clock and Base_clock are each set in 48MHz, and may be checked at SDRAM_CLK of SDRAM(U27). Clock supplied from outside does not use separate crystal, but 48MHz is supplied by IP_CLK, CLK_Out of Jupiter3(U15). The one which pulled up Main_EXT(pin46) and Base_EXT(pin43) is the Option using internal PLL, and, at the time of Pull-up, it does not use internal PLL, but just use Clock supplied to Main_CLK(pin45) and Base_CLK(pin42) as Main_clock and Base_clock.
1. Memory Map
0x0000 .... 0x00ff 0x0100 .... 0xfbff 0xfc00 .... 0xffff Boot ROM SDRAM program store and SDRAM stack HW registers
2. Power On/Off Reset

Power On Reset Depending on the signal state of Reset_L(pin35), OA980 may be reset in the manner of hardware. Reset is on at Low state and, at High state, Reset is Off. Accordingly, in order for OA-980 to operate normally, after the System initialization, the /IP_RST of Jupiter3(U15-31) shall be converted to High state. In order for safe Hardware Reset to be accomplished, it should be maintained in Low state for more than 1000 Main_clock(10uS). Power Off Reset PWR_down(pin107), for SDRAM(U27) to advance to the Self Refresh Mode Reset_L(pin35) at the Power Safe Mode, shall advance to the Reset Mode earlier than the minimum of 1uS. This System does not use it.
3-5-2-2 Internal Microcontroller

8bit RISC Microcontroller is built-in, and Address area which Micro-controller control is 64kbyte. At the same time when cache is built in for control of more efficient SDRAM, it possesses Hook function, namely the internal Boot ROM 256byte required for self-initialization function, too.
3. Hook function : Self-initialization function

In case self ROM is connected to OA-980 as in Figure (15), although the execution file is downloaded to SDRAM, the execution file is initialized by receiving download from Memory. This execution file is the ROM File supporting so that all functions of Image processing related to OA-980 as well as register setting value required for initialization(Copy, PC scan, MultiMediaCard Print) may operate normally.
<Figure 14. OA-980 Block Diagram>
3-21
CIRCUIT DESCRIPTION
0=H@M=HA 4AIAJ 0ECD
* J 4 ? A?JE
?DA? I B 4
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4 )BJA H 5 BJM= HA 4AIAJ =@L= ?A J FHAF=H=JE @A J BE A BH @ M =@ ANA?KJE , M =@ A NA?KJE BH BE A 5,4 ) 7 %
KFEJAH !
, M BH
=@ JDA ANA?KJE . =ID A
BE A J 5,4)
7 %
HO 7' B KFEJAH !
1 EJE= E A @ M =@A@
) '& >O JDA ANA?KJE 5,4) @A
BE A
7 % D=LA EJ J
A JAH E JDA FAH=JE
4 A=@O
<Figure 15. Boot Code Flow Diagram>
3-22
CIRCUIT DESCRIPTION
3-5-2-3 Host Interface Section (HI : Jupiter3 interface section)
Unlike the existing DuoIP sequence, OA-980 exchanges Command and data with Jupiter 3 in the Multiplexed 8bit Bus(data & address) mode. Namely, it does not receive Address and Data simultaneously, but receive data after receiving Address first using Data Bus of Jupiter3. HI Section also supports the data movement in the DMA mode. Accordingly, when transmitting large capacity of Image data(RGB data of MultiMedCard), it uses the DMA mode.
1. Multiplexed 8bit Bus(data & address) mode

once Jupiter3 may not support Multiplexed 8bit Bus(data & address) mode used by OA-980, it configured a circuit additionally so that mutual Interface may be possible by making required signal using two NOR GATE(UR16) and one OR Gate(U40). As REG_ADDR_VAL(pin27) signal is the signal for OA-980 to play a role of informing that value input into 8bit of OA980 Bus is not Data but Address value, when ADDR(10) is High and /IP_CS, /WR Low, High shall be generated as shown in the circuit diagram. See figure (16). At this time, since /WR_L(pin31), the Write signal of OA-980, should be maintained in High, the signal shall be generated in case actual Write is accomplished with one OR Gate(U18), namely, only when ADDR(10) is Low, When REG_ADDR_VAL (pin27) is High, input the Address value of OA-980, and when Low, from the standpoint of Jupiter3, it may Read or Write One Byte Data using two Cycles by Reading or Writing relevant Data of (to) Address.
<Figure 16. Hi Block Timing diagram(1)>
3-23
CIRCUIT DESCRIPTION
3-5-2-4 Scanner Interface Section(PI)

2. DMA mode
DMA mode is the method of Reading or Writing Data in Block unit by activating two DMA Channels of OA-980 respectively. When A8 or A9 is Low and when /IP_CS is Low, GDMA of Jupiter3 Reads or Writes in Memory to Memory mode, as the appropriate DMA Channel is activated. See Figure (17). Of course, it performs required DMA register setting in Multiplexed 8bit Bus(data & address) mode before DMA is accomplished. It directly controls 16bit ADC and 600dpi color CCD connected to CCD, processes Shading and Gamma correction, the basic course required for Image process of RGB 12bit(8+4bit) data transferred from ADC, then performs the function of storing the data in SDRAM of OA-980 through MI Block.
<Figure 17. Hi Block Timing diagram(2)>
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CIRCUIT DESCRIPTION
3-5-2-5 Image Processing Section(IP)

After performing color compensating required for the System for RGB digital data input, it conducts the role of converting to CMYK data printable. IP Block consists of four Modules mainly. - Photo text detect - Zoom and dpi adjust - Color space conversion - Half toning and loss less JPEG
3-5-2-8 Rotate and Inkjet Engine Section

After Image CMYK Data which ended all image processing is converted to Format so that Inkjet Printer Engine may print, it plays the role of saving them on the external SDRAM(U27). The Data stored in the external SDRAM(U27) is transferred to Head Control Part of Jupiter3 through MI and HI Block of OA-980 by DMA of Jupiter3, and then printed by Spitfire.
3-5-2-9 Printer Interface Section(PO)

When the Image process required for PC Scan (See Fig. 19) is completed, OA-980 requests that /IP_REQ signal in PO_Block should take the Scan Image Data from the External DMA Block of Jupiter3(U15). The External DMA Block of Jupiter3(U15) generates not only /IP_ACK signal to bring Data by Byte as the unit but also /RD signal to bring the Data. The External DMA Block of Jupiter3(U15) stores the Data in SDRAM(U9) and then restore /IP_ACK as "High" to receive a next Data/. As DMA Timing properties between Jupiter and OA-980 do not match, /IP_ACK0 is separately created to prevent BUS collision by using one OR-Gate(U18-3) so that OA-980 may use the BUS only in /RD in the way of inputting the /ACK signal into OA-980 only when /RD is actually produced, while Jupiter3 may use in /WR, as shown in the Timing of Fig. 18. That is, since OA-980 sends Data to BUS during /ACK signal section, BUS collision occurs between DMA of Jupiter3 and /WR section, where /RD, /WR are all carried out during /ACK.
3-5-2-6 Memory Interface Section(MI)

MI Block consists of four Channels, located between external SDRAM(U27) and blocks inside OA-980, and is controlled so that the flow of all data may be accomplished more efficiently.
3-5-2-7 JBIG Comp & Decomp Section

By condensing Image data processed at Blocks into JBIG algorithm and save them in external SDRAM(U27), it shall have Memory domain used more efficiently. Naturally, even when moving Image data which was condensed to JBIG, to other block, it is conveyed to Image data freed from condensation.
<Figure 18. PO Block DMA Timing Diagram>
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CIRCUIT DESCRIPTION
3-5-3 Copy Data Flow for OA-980
3-26
CIRCUIT DESCRIPTION
3-5-4 OA-980 I/O PORT
3-27
CIRCUIT DESCRIPTION
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CIRCUIT DESCRIPTION
3-6 CCD MODULE and ADC Part

3-6-1 CCD Module General Description
CCD Module has the structure transferring RGB data to be converted into the digital signal through ADC on the basis of the level of analog signal to OA-980, the Image Processor, which divides the signals reflected by emitting light to document into R, G, B data according to each frequency. The voltage used in the CCD Module are 11.75V for analog signal of RGB, 5V as input for CCD and other elements. The input part of CCD Module consists of CCD_TG, CCD_CLK1,CCD_CLK2 and CCD_RS, the output of OA-980(U21), CCD_TG controls the scan line, which is set variously according to copy mode, color and mono, and scan resolution. CCD_CLK1 and CCD_CLK2 are clocks by each pixel, CD_RS is reset signal of each pixel. Since the pixel of 1/2 cycle of CCD_CLK1 and CCD_CLK2 is sampled, color signal sends RGB data to output for 1/2 cycle, and controls the pixel of 1/2 cycle for mono. Therefore, the output signal from the CCD Module classifies the signals received by RGB channel according to each frequency band and uses each video signal(CN1) as the input data of ADC(U16).
TG, CLK,RS to be used are as follows.
Color Copy CCD_TG CCD_CLK1,CCD_CLK2 CCD_RS 5mS 1.6uS 800uS
< TG, CLK,RS >
Mono Copy 2.5mS 800uS 400uS
< TG, CLK,RS >
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CIRCUIT DESCRIPTION
3-6-2 ADC
Description ADC(U16) is the input data that change the analog signal of RGB to the digital signal of 16bit (8bit + 8bit) so that it may be used as the input of OA-980(U21), image processor, while VSMP(_ADC_VSMP) is used as a sampling signal for each pixel of RGB. That is, it controls the signal for one pixel like CLK1,CLK2 of CCD and its maximum sampling rate is of color 2MHz mono 4MHz. MCLK(ADC_CLK) is CLK for the signal of VSMP, the relation between MCLK and VSMP is as follows.
Color VSMP ADC_CLK VSMP:MCLK 800ns(1.25MHz) 133ns(7.5MHz) 1:6 Mono 400ns(2.5MHz) 133ns(7.5MHz) 1:3
The relations among SCK(ADC_SCK), SDI(ADC_SDI) and SEN(ADC_SEN) are equivalent to the control bit for register setting to mode, output signal appears in 8bit unit from OP0 to OP7, and 5V/3.3V will be used as the power source.
16.5 MCLK PERIODS
ADC_CLK VSMP
OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11)
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<Figure 20. Color mode MCLK, VSMP>
16.5 MCLK PERIODS
ADC_CLK VSMP
OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11)
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<Figure 20-1. Color mode MCLK, VSMP>
3-30
CIRCUIT DESCRIPTION
3-7 THUNDERBOLT ASIC description

3-7-1 Entire description
THUNDERBOLT ASIC is configured with SERIAL INTERFACE INPUT PORT interfacing Main controller, 2 DC-DC Converter Controllers, Power On Reset Generation Circuit, and Motor drive part.
3-7-2 THUNDERBOLT FUNCTION DESCRIPTION 3-7-2-1 SERIAL INTERFACE INPUT PORT

To MAIN CONTROLLER(S3C46MOX(Jupiter3)), /TBCS,TBCLK,TBDO are connected with MAIN CONTROLLER (S3C46MOX (Jupiter3)), and see the figure for Timing.
Tcs-sclk Tcs-sclk
/ TBCS
Data Latcked on the rising edge of SCLK
TBCLK
Tdsu Tdhd
bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13
MSB
SDI stays at last value
TBDO
bit 1
LSB
bit 2
bit 3
bit 4
bit 5
time
< Figure 21. SERIAL INTERFACE INPUT Timing Diagram >
Parameter Fclk Tclh Tcll Tcs-sclk Tsclk-cs Tdsu Tdhd Trd Tfd Trc Tfc
Description Serial clock frequency SCLK high width SCLK low width Delay nCS falling to first SCLK rising Delay last SCLK rising edge to nCS rising Data valid to SCLK set up time Data hold time SDI rise time SDI fall time SCLK rise time SCLK fall time
Min 125 125 250 250 125 125 5 5 5 5
Typ 2.5 200 200 800 400 200 200
Max 4 20 20 20 20
Units MHz nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec
< Figure 21-1. SERIAL INTERFACE INPUT Timing Specification >
3-31
CIRCUIT DESCRIPTION
3-7-2-2 DC-DC Converter Controller

This System uses VCC by converting it to +5V, and +3.3V, the power source of the system, is obtained from the +5V converted by using REGULATOR IC to use. VPH is used as the head power by converting it to +11.82V.
< Figure 22. DC-DC Converter Controller Diagram>
3-7-2-3 Power On Reset Generation Circuit

This System does not use Power On Reset Generation Circuit.
3-7-2-4 Motor drive part

This System uses DC Motor for CR(Carriage Return) MOTOR, and Stepper motor for LF(Line Feed) motor. CR(Carriage Return) MOTOR drive circuit description
1 CR MOTOR specification
CR MOTOR performs reciprocating movement of CARRIAGE from side to side so that INK CARTRIDGE may print on the paper. MOTOR TYPE : PM DC MOTOR declination Drive voltage : +30VDC Winding line resistance : 12 2 Driver IC : Thunderbolt
2. CR MOTOR drive
2-1. DC Motor operation DC Motor drive uses positive phase terminal(+) and anti-phase terminal(-) bound together respectively using 2nd Motor Driver(MD2) of Thunderbolt ASIC inside, and controls two-way operation of DC motor, by receiving input of "DIR_DCM," 7th bit among "PWM"(DC-motor Pulse Width Modulation) signal, output of Jupiter-III, and 13Bit Serial Port Inputs("TBDO" Signal) coming into Thunderbolt ASIC transmitted from Jupiter-III. This Driver is driven by VBULK power source(+30V), and on terms of Motor Stall not being generated, it is designed to supply 750mA current, and 2.4A current to output terminal for maximum length of 100ms.
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CIRCUIT DESCRIPTION
2-2. Driver Spec. 1) Absolute Maximum Rating Name Vout Iout Description DC Motor Driver Output Voltage DC Motor Driver Output Current Condition Min Max 42 2.4 Units Volts A
2) DC Specification Name I peak I out Description Peak DC Motor Driver Output Current DC Motor Driver Sustaining Current Condition Not Stalled On Time=100ms 1.6 Min Max 0.75A 2.4 Units Volts A
3) AC/Transient Specifications Name fPWM Description PWM frequency Condition Ta = 25C Min 19 Nom 20 Max 21 Units KHz
4) Truth Table DIR_DCM 0 0 1 1 PWM 0 1 0 1 #NAME? On Off On Off #NAME? Off On Off Off #NAME? On On On Off #NAME? Off Off Off On
3. LF(Line Feed) MOTOR drive circuit description

3-1. LF MOTOR MOTOR TYPE : 2-2 Bi-polar Stepper Motor Drive Voltage : +30V Spherical line resistance : 5 7% Driver IC : Thunderbolt 3-2. LF Motor Operation LF Motor(Stepper Motor) drive uses the first Motor Driver(MD1) in Thunderbolt ASIC, and Drive Pulse is output from 4 terminals of A+, A-, B+,and B-. two H letter type Drivers. Drive Pulse controls size and flow direction of current(A+ => A- or A- => A+) according to bit7-bit No.13 signals among 13Bit Serial Port Inputs("TBDO" Signal) coming into Thunderbolt ASIC transmitted from Jupiter-III. This Driver is driven by VBULK power source (+30V), and on terms of motor stall not being generated, it is designed to supply current of 600mA, maximum 700A current to each phase of motor.
3-33
CIRCUIT DESCRIPTION
3-3. Driver Spec. 1) Absolute Maximum Rating Name V out I out Description DC Motor Driver Output Voltage DC Motor Driver Output Current Condition Min Max 42 0.7 Units Volts A
2) DC Specification Name I peak Description Peak DC Motor Driver Output Current Condition Not Stalled Min Max 0.6A Units Volts
3-34
CIRCUIT DESCRIPTION
OPE 3-8 Basic concept

3-8-1 Overview
OPE BOARD is separated from the Main Board functionally, and operates entire Micom(HT48C5A-000Z) in the Board. OPE and Main exchange mutual information using UART(universal asynchronous receiver/transmitter) channel. Also, Resetting of OPE is designed to control at the Main. Micom in OPE performs key-scanning and LCD, LED display control, and senses document detect, Scan position and so on. When information is generated from OPE(key touch, sensor level change, etc.), it sends specific code coping with the situation to Main, and the Main operates system by analyzing this code. If the Main tries to display data on OPE, the Main sends data to OPE via UART line on the basis of the format specified, and OPE displays it to LCD. This system does not apply document detect and SCAN position.
3-8-2 UART
OPE and MAIN exchange information mutually by using asynchronous communication mode(UART), and in full duplex. Band rate is 9600bps, and uses 7.37MHz resonator as oscillating element. It engages in communication with 8bit data without parity bit. UART line has two lines for Tx and Rx, and the default level is in the 'high' state. For communication, the start bit(low level) is transmitted before 8bit data. When the data transmission(8bit) is completed, the high state is maintained as the stop bit(high level) is transmitted. Data is transmitted from LSB(DO), and MSB(D7) is transmitted lastly.
3-9 UART operation

3-9-1 UART communication
1) UART TX FORMAT
Codes for change of KEY, TOUCH, SENSOR LEVEL and so on are transmitted in single code without PRE/POST DATA, and OK or Error messages to check if communication is performed properly are also transmitted in single code. Provided that, in case the Main requested a certain value(LCD, other register) particularly, data requested is transmitted followed by sending Post Data('EOH') first.
2) UART RX FORMAT
Data being received will be arranged to be received according to the following specified format to know what data they are.
a) b) Type of data received Number of data (n+1) received after. ---------c) DATA(N) ---------d) Check sum(1)
D0 start bit
D1
D2
D3
D4
D5
D6
D7 stop bit
data 8bit (D0 ~ D7)
DATA are received in the sequence of A,B,C, and D, and the Check sum to check if the transmission is made properly will be found by doing XOR data from A to C.
3-35
CIRCUIT DESCRIPTION
3-9-2 UART communication DATA 1) UART transmission DATA(received by the Main side)
Types key data Status ON OFF SCAN POSITION sensor ON OFF DOC. detector sensor ON OFF For initial use of initial OPE UART communication OK ERR LCD interface of OPE OK ERR Self initial generation of OPE Send data requested by the Main DATA 11H~ 88H af H a5 H a4 H a1 H a0 H ee H b0 H c0 H df H d0 H e2 H e0 H LCD data keeps status quo Data types:LCD, other(Note 3) When failed in the interface once & when succeeded first(Note 2) PORT PB-5 PORT PB3 used port PORT PC0~PORT PC7 Level L H H L L H After power on, generated only once (Note 2) Check if the scan cover is opened. SCX-1150F not applied Remarks
(Note)
1. After this, keep waiting until there is response from the Main. 2. The case of longer time(longer than 10ms) elapsed longer than waiting time required for Interface is regarded as fail 3. After this code went out, then data requested it goes out.
KEY MATRIX
(1_H) (_1H) (_2H) (_3H) (_4H) (_5H) (_6H) (_7H) (_8H) Quality Zoom Rate Copy_black Setup Enter CANCEL Receive Mode RESERVED (2_H) Copy Page Special Copy Copy_Color Vol_Left Vol_Right Contrast Search/Delete RESERVED (3_H) 1 4 7 * Resolution FAX Forw Redial/Pause Ink Save (4_H) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED (5_H) 2 5 8 0 FAX_Black FAX_Color OHD Paper Save (6_H) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED (7_H) 3 6 9 # M8 M9 M10 Toll Save (8_H) M1 M2 M3 M4 M5 M6 M7 Scan to
<SCX-1150F OPE BD KEY MATRIX>
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CIRCUIT DESCRIPTION
2) Received DATA(transmitted by MAIN)

1. DATA TYPE
DATA types a1 H a2 H a3 H a4 H b1 H Meaning LCD DISPLAY DATA(FULL LINE) LCD DISPLAY DATA(1'ST LINE) LCD DISPLAY DATA(2'ST LINE) LED DATA Change of LCD types Remarks
2. NO. OF DATA
In case DATA is N BYTE, N+1
3. DATA
In case DATA TYPE is LCD DATA, it is configured with ASCII CODE to be displayed. In case DATA TYPE is LED DATA, it is 1 BYTE. LED DATA BIT ASSIGNMENT: DATA BIT LED NO. BIT 0 LED 0 BIT 1 LED 1 BIT 2 LED 2 BIT 3 LED 3 BIT 4 LED 4 BIT 5 LED 5 BIT 6 LED 6 BIT 7 LED 7
4. CHECK SUM
The value done XOR all of them from DATA TYPE to DATA.
5. Change of LCD types

<2 LINE * Change to 16 character LCD> DATA TYPE NO. OF DATA DATA CHECK SUM : b1 H :2 : 26 H : b1h XOR 2 XOR 16h = a5 h
<1 LINE * Change to 16 character LCD> DATA TYPE NO. OF DATA DATA CHECK SUM DEFAULT : b1 H :2 : 26 H : b1h XOR 2 XOR 26h = 95 h : 2 LINE 16 Character LCD
In case the MAIN does not change the LCD types, it is the Default LCD state of OPE MICOM. * SCX-1150F uses 1 LINE LCD.
3-37
CIRCUIT DESCRIPTION
3-10 I/O PORT configuration and use usage

It has 32 I/O Ports, and 24 Ports of them are arranged to decide I/O direction with Software Control, and the rest 8 Ports are arranged to be used for Input or Output only. All of I/O Ports are classified into four Blocks according to the characteristics of I/O Control, and each Block consists of 8 Ports. Type PA X PB X PC X PD X I/O Control Byte Control Byte Control Byte Control Byte Control I/O direction I/O => Output In : 4, Out : 4 I/O => Input I/O => Output USE LED Control UART, LCD, Sensor Key Input LCD Data, Key Scan Remarks
1) Assignment of Port PAX -. PA0 -. PA1 -. PA2 -. PA3 -. PA4 -. PA5 -. PA6 -. PA7 : RESERVED : LED 1 : RESERVED : RESERVED : RESERVED : RESERVED : RESERVED : RESERVED
2) Assignment of port PBX -. PB0(Output) -. PB1(Output) -. PB2(Output) -. PB3(Input) -. PB4(Input) -. PB5(Input) -. PB6(Output) -. PB7(Input) : LCD Enable : LCD R/W : LCD RS : GND : Unused (Pull-up) : GND : UART TXD in Main UART : UART RXD from Main UART
3-38
CIRCUIT DESCRIPTION
3-11 FAX Transceiver

3-11-1 General Information
- This circuit treats the Transmit signal of modem and between LIU and modem.
3-11-2. Modem(U19)
- FM336 is a Single Chip Fax Modem. It functions as a modem, DTMF Detection, and DTMF signal function. The main
ports of this modem are as follows. TXA 1, 2 (PIN 28, 29) is a sending output port from modem, and RIN (PIN32) is a receiving input port. /POR (PIN34) is a signal from OA-980 (U21), which initializes the modem without system power off. D0~D7 (PIN87~95) are Data Bus. RS0~RS4 (PIN 96,97,2,3,4) are Register Selection signals inside of modem and define the Modes. /CS (PIN5) is a Modem Chip Selection signal. /RD (PIN 7) is a control signal for reading, and /WR (PIN6) is a control signal for writing. IRQ (PIN79) is a Modem Interrupt Output signal. The speed of FM336 is MAX. 33.6K bps.
3-11-3. Sending
- This circuit treats a sending output of Analog signal from modem (U19, FM 336). The output signal by each mode is outputted the Differential TX signal from modem TXA1, 2(PIN28, 29), and the Differential TX signal goes to telephone line via Matching Transformer (600:600, T2) LIUBd.
3-11-4. Receiving
- The analog signal via Matching Transformer (600:600, T2) of LIU Bd is directly transmitted to Receiving input RIN
(PIN32) of modem.
TXA1 MODEM FM336 (U19) RIN TXA2 Matching Transformer(T2) FAX
MAIN PBA
LIU PBA
< Fax Transceiver >
3-39
CIRCUIT DESCRIPTION
3-11-5. FM336 FEATURES

2-wire half - duplex fax modem modes with send and receive data rates up to 33600 bps. - V.34, V.17, V.29, V.27 ter, and V.21 channel 2 - Short train option in V.17 and V.27 ter 2-wire full - duplex data modem modes - V.21, V.23 (75 bps TX/1200 bps RX or 1200 bps TX/ 75 bps RX) PSTN session starting - V.8 signaling HDLC support at all speeds - Flag generation, 0 bit stuffing, ITU CRC - 16 or CRC - 32 calculation and generation - Flag detection, 0 bit deletion, ITU CRC - 16 or CRC - 32 check sum error detection - FSK flag pattern detection during high speed receiving Tone modes and features - Programmable single or dual tone generation - DTMF receive - Tone detection with three programmable tone detectors Serial synchronous data Parallel synchronous data Automatic Rate Adaptation (ARA) in V.34 Half-Duplex TTL and CMOS compatible DTE interface - ITU-T V.24 (EIA/TIA-232-E) (data/control) - Microprocessor bus (data/configuration/control) Receive dynamic range: 0 dBm to 43 dBm for V.17, V.33, V.29, V.27terand V.21, 9 dBm to 43 dBm for V.34 half-duplex Programmable RLSD turn-on and turn-off thresholds Programmable transmit level: 0 to -15 dBm Adjustable speaker output to monitor received signal DMA support interrupt lines Two 16-byte FIFO data buffers for burst data transfer with extension up to 255 bytes NRZI encoding/decoding Diagnostic capability +3.3V operation with +5V tolerant inputs +5V analog signal interface Typical power consumption:- Sleep mode: 20 mW - Normal mode: 250 mWa 100-pin PQFP package
3-40
CIRCUIT DESCRIPTION
3-11-6. Signaling Rates, and Data Rates
3-41
CIRCUIT DESCRIPTION
3-11-7. Modem Functions Interface Signals
3-42
CIRCUIT DESCRIPTION
3-11-8. FM336 Pin Signals

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1. RESERVED RS2 RS3 RS4 /CS /WR /RD /RDCLK /RLSD TDCLK TXD /CTS VDD1 RESERVED RESERVED VSS NC /RESET SR4OUT NC SR4IN CLK_OUT EYESYNC EYECLK MAVSS MAVDD SPKR TXA2 TXA1 VREF VC RIN MAVSS /POR RESERVED RESERVED /TALK VDD RESERVED RESERVED NC M_CNTRL_SIN M_CLKIN M_TXSIN M_SCK M_RXOUT M_STROBE RESERVED OH VDD IA IA IA IA IA IA OA OA OA IA OA PWR GND OA OA IA OA OA OA GND PWR O(DF) O(DD) O(DD) MI MI I(DA) AGND IA O(DD) PWR IA IA IA IA IA IA O(DD) PWR HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface DTE Serial Interface DTE Serial Interface DTE Serial Interface DTE Serial Interface DTE Serial Interface NC Modem Interconnect Modem Interconnect NC Modem Interconnect Modem Interconnect Diagnostic Signal Diagnostic Signal Telephone Line Interface Telephone Line Interface Telephone Line Interface Modem Interconnect Modem Interconnect Te lephone Line Interface Modem Interconnect Telephone Line Interface NC Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Modem Interconnect Telephone Line Interface 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RESERVED VSUB VSS NC NC Sleep VDD1 RESERVED RESERVED NC SR1IO VCORE VDD1 XTCLK VSS RESERVED RXD /DTR VDD1 IA_SLEEP VGG YCLK XCLK EYEXY /DSR /RI RINGD /RTS IRQ VSS GPO0 RESERVED RESERVED VDD1 XTALI/CLKIN XTALO D0 D1 D2 D3 D4 VDD1 D5 D6 D7 RS0 RS1 PLL_VDD VSS PLL_GND GND GND MI PWR MI PWR PWR IA GND OA IA PWR MI PWR OA OA OA OA OA IA IA OA GND MI PWR I O IA/OB IA/OB IA/OB IA/OB IA/OB PWR IA/OB IA/OB IA/OB IA/OB IA/OB PWR GND GND NC NC Modem Interconnect NC Modem Interconnect DTE Serial Interface DTE Serial Interface DTE Serial Interface Modem Interconnect Overhead Signal Overhead Signal Diagnostic Signal DTE Serial Interface Telephone Line Interface Te lephone Line Interface DTE Serial Interface HOST Interface Modem Interconnect Overhead Signal Overhead Signal HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface HOST Interface -
2. 3.
I/O types: MI = Modem interconnect. IA, IB = Digital input. OA, OB = Digital output. I(DA) = Analog input. O(DD), O(DF) = Analog output. NC = No external connection required. RESERVED = No external connection allowed. Interface Legend: HOST = Modem Control Unit (Host) DTE = Data Terminal Equipment
3-43
CIRCUIT DESCRIPTION
3-11-9. FM336 Signals Definitions
TXA1, TXA2 RIN RINGD
O(DD) O(DA) IA
/TALK
O(DD)
OH
O(DD)
/RI
OA
Transm it Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other. Each output can drive a 300 load. Recei ve Analog. RIN is a single-ended receive data input from the telephone line interface or an optional external hybrid circuit. Ring Detect. The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz. The frequency detection range may be changed by the host in DSP RAM. The circuit driving RINGD should be a 4N35 optoisolator or equivalent. The circuit driving RINGD should not respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detected ring signals are reflected on the /RI output signal as well as the RI bit. Relay B Contro l. The /TALK open collector output can directly drive a +5V reed relay coil with a minimum resistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. A clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be used to drive heavier loads (electro-mechanical relays). /TALK is controlled by host setting/resetting of the RB bit. In a typical application, /TALK is connected to the normally closed Tal k/Data relay (/TALK). In this case, /TALK active opens the relay to disconnect the handset from the telephone line. Relay A Cont rol. The OH open collector output can directly drive a +5V reed relay coil with a minimum resistance of 360 ohms (13.9 mA max. @ 5.0V) and a must-operate voltage no greater than 4.0 VDC. A clamp diode, such as a 1N4148, should be installed across the relay coil. An external transistor can be used to drive heavier loads (electro-mechanical relays). OH is controlled by host setting/resetting of the RA bit. In a typical application, OH is connected to the normally open Off-Hook relay (OHRC). In this case, OH active closes the relay to connect the modem to the telephone line. Alternatively, in a typical application, OH is connected to the normally open Caller ID relay (CALLID). When the modem detects a Calling Number Delivery (CND) message, the OH output is asserted to close the CALLID relay in order to AC couple the CND information to the modem RIN input (without closing the offhook relay and allowing loop current flow which would indicate an off-hook condition). Ring Indicat or. /RI output follows the ringing signal present on the line with a low level (0 V) during the ON time, and a high level (+3.3 V) during the OFF time coincident with the ringing signal. The RI status bit reflects the state of the /RI output. Three signals provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye pattern is a display of received baseband constellation. By observing this constellation, common line disturbances can usually be identified. Serial Eye Pattern X/Y Output. EYEXY is a serial output containing two 11-bit diagnostic words (EYEX and EYEY) for display on the oscilloscope X axis (EYEX) and Y axis (EYEY). EYEX is the first word clocked out; EYEY follows. Each word has 8-bits of significance. EYEXY is clocked by the rising edge of EYECLK. This serial digital data must be converted to parallel digital form by a serial-to-parallel converter, and then to analog form by two digital-to-analog (D/A) converters. Serial Eye Pattern Clock. EYECLK is a 336 kHz output clock for use by the serial-to-parallel converters. The low-to-high transitions of RDCLK coincide with the low-to-high transitions of EYECLK. EYECLK, therefore, can be used as a receiver multiplexer clock. Serial Eye Pattern Strobe. EYESYNC is a strobe for loading the D/A converters. Speaker Analog Output. The SPKR output reflects the received analog input signal. The SPKR on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speaker is turned off, the SPKR output is clamped to the voltage at the VC pin. The SPKR output can drive an impedance as low as 300 ohms. In a typical application, the SPKR output is an input to an external LM386 audio power amplifier.
EYEXY
OA
EYECLK
OA
EYESYNC SPKR
OA O(DF)
3-44
CIRCUIT DESCRIPTION
FM336 Signals Definitions (Contd)
3-45
CIRCUIT DESCRIPTION
3-46
CIRCUIT DESCRIPTION
3-47
CIRCUIT DESCRIPTION
3-12 LIU PBA

3-12-1 Background of Line Connection Part
This LIU is designed for the standards (FCC, CTR 21 etc.) of America and Europe where dont allow the Handset, and the line interface is applied for sending/receiving 33.6k bps. However, contact by 33.6k bps allows just for using FM336 modem of Connexant Co., and provisions is given as below for some countries, require the special function. - Greater Britain: 3,4,8, (#3, #4: TIP, Ring, #8:Shunt) - United States and some other countries: 3,4 (TIP, Ring) United States and some other countries, where apply CTR21 (Common Technical Requirements), are using Modular Jack #3, #4, and the Modular Jack Harness is designed for joint use of America and Europe counties.
3-12-2 Functions
3-12-2-1 DC Conditions
The normal conducting rage of LIU is 12mA-90mA. Because no more than 60mA current cannot flow in terminal by applying the CTR21 standard, no more than 60mA DC flows in the Current intercept circuit when the current, which flows via Bridge Diode (BD1) and Q2, is connected to LINE_A, LINE_B, and LINE_C. It means an entire line current, flows through LIU, isnt over 60mA. - CTR21 standard: 12mA-60mA - United States and other countries standard: 12mA-90mA The characters of DC are defined as bellows with voltage of the Line input from the Gate input part of Q1 and R20, which is connected to the Source of Q1. -VDCR=VLI + ILINEXR20 (VDCR: Tip-Ring DC voltage), ILNE: Line current VLI: Line Input voltage, VLI=BVD1+VCE (Q2)+VDS (Q1) In this part, a voltage drop is not considered to Q3 (2SA 1156), R12, R11, etc. at the moment of forming DC loop with applying CTR21 standard. The DC resistance of terminal is about 70W higher when applying CTR21 standard than applying America standard. Not only CML1 (Relay), but also U6 (PC817) must be turned on for forming a DC Loop. The base of Q6 (KSC945) must be controlled by /DP terminal, and U6 must be turned on to flow the current in Q1,Q2,and R20 via the bridge diode (BD1) at the same time the CML_1 When the base of the Q4 gets the line voltage from DTR terminal, Q3 is turned on and flows to Q2 via R11 by applying the CTR21 standard. When the line current is more than 60mA, Q5 is turned on, but Q3 and Q4 are turned off. The most of current is wasted at R12 (1kW, 2W), so it cant flow more than 60mA. The 1% of tolerance resistance must be use for R11 under the condition of turning on the Q5.
3-12-2-2AC Conditions
AC Impedance of the LIU is basically 600ohm, and it is possible to make it as complex impedance by using C36, R47, and R48. - United States: vertical impedance 600W (30%) CTR21: vertical impedance 270ohm + 750ohm//150nF (more than 1- 4dB)
3-12-2-3 MF Dialing
3-48
CIRCUIT DESCRIPTION
DTMF dialing is controlled by modem, and sends the signal at the suitable level and with on-off time according to the national spec of each country. - Freq. Tolerances: 1.5% High Group: 1209, 1336, 1477, 1633 Hz Low Group: 697, 770, 852, 941 Hz
3-12-2-4 DP Dialing
The DP Dialing controls the DP signals from the main via /DP terminal. When the signal goes to America, the DP signal is adjusted to 40:60 of M/B (Make/Break ratio), and when the signal goes to Europe, the DP signal is adjusted to 33:66 of M/B. The DP signal is made by U6 (PC817), and the current, flows in the base of Q2 by Coupler, controls on/off function. The DC current in telephone line is controlled by the on/off of Q2, and as a result, the DP Dial signal is created. -CTR21 doesnt have a telephone function but line connection (#3, #4). It has no DP conditions and is suitable to the standard if the terminal does do only DTMF Dial.
3-12-2-5 Ringer
Ring Signal from the Line (TIP, Ring) goes to U9 (PC814) via C5, R3, ZD1, and ZD2. U9 detects the signal and outputs it to Main BD. C5 is the Ringer Capacitor and normally 1UF/250V is used. R3 is a resistance to control the AC current, and by controlling the R3, the REN value is adjusted to higher or lower.
3-49
SCHEMATIC DIAGRAMS
4. Schematic Diagrams
4-1 Main Circuit Diagram (1/8)
SHEET 2 CONNETOR PART CONN.SCH
SHEET 6 IMAGE PROCESSING PART SCANIP.SCH SHEET 7 MODEM PART MODEM.SCH
SHEET 3 CONTROLLER PART

SAMSUNG ELECTRONICS CO., LTD. ALL RIGHTS RESERVED
JUPITER.SCH
C
SHEET 4 MEMORY PART MEM.SCH

D
SHEET 8 PARALLEL PORT PART PARA.SCH

D
SHEET 5 DRIVER PART DRIV.SCH

ED. DATE 1 2 3
SIGN
A R P .
C H E C K
E N G .
D W G .
SCX-1150F Main Board REV 0.2

1/8
REF NO
SEC
DIAGRAM
4-1
SCHEMATIC DIAGRAMS
Main Circuit Diagram (2/8)
11.75V
30V
3.3V
5V
R8 5.1K
CN1-26 CN1-25 CN1-24 CN1-23 CN1-22 CN1-21 CN1-20 CN1-19 CN1-18 CN1-17 CN1-16 CN1-15 CN1-14 CN1-13 CN1-12 CN1-11 CN1-10 CN1-9 CN1-8 CN1-7 CN1-6 CN1-5 CN1-4 CN1-3 CN1-2 CN1-1
CHY CHX _SF_POR ACLK AGATE LDCS LATCHCTL PCLK PDATA3 PDATA2 PDATA1 PDATA0 PLOAD PENABLE PH_ID1 PH_ID2 OK2PRT C1 220pF C7 220pF 3.3V
30V C205 100nF 5V C67 100uF 16V L11 600ohm BEDA L5 L6 L12
600ohm BEDA
PULLUP
5VA BD6
600ohm BEDA
CN11-1 CN11-2 CN11-3 CN11-4
C66 100nF
C49 100nF
R43 10K
C50 330uF 50V
R155 1.5K R154 10K DGND R144 R152 C204 22pF C203 22pF C209 100nF R153 10K BD13 BD11 BD12 BD10 L9
0ohm
0,5% C119 100nF C118 100uF 16V
USB20-4W2100 CN8-1 CN8-2 CN8-3 CN8-4
BD7 GND30 DGND
0,5%
0 0
AGND
L10 0
DGND
FGND
GND12 GND30 DGND
30V 5V
5V
5V
R149 47K
R147 47K
R148 47K
CN7-1 5V
1 2 3 4 5
DIN15 OPE_TXDD _OPE_RES OPE_RXD CN16-1 CN16-2 CN16-3 CN16-4 CN16-5 CN16-6 CN16-7 CN16-8 CN16-9 CN16-10 CN16-11 CN16-12 CN16-13 CN16-14 CN16-15
CN14-1 CN14-2 CN14-3 CN14-4 CN14-5 CN14-6 CN14-7 CN14-8 CN14-9 CN14-10 CN14-11 CN14-12 CN14-13 CN14-14 CN14-15 CN14-16 CN14-17 CN14-18 CN14-19 CN14-20 CN14-21 CN14-22 CN14-23 CN14-24 CN14-25 CN14-26 CN14-27 CN14-28 CN14-29 CN14-30 CN14-31 CN14-32 CN14-33 CN14-34 CN14-35 CN14-36
_STB CD(0:7)
R207 47K
OPE_MAGIC C97 100nF C80 100pF C81 100pF C82 100pF
DGND _ACK BUSY PE SLCT _AUTOFD
DGND
ADF_PHA ADF_IA0 ADF_IA1 ADF_PHB ADF_IB0 ADF_IB1 _ADF_DET _D_DET _D_SCAN REG1_SEN
L7 5V L8 DGNDFGND
600ohm BEDA
R209 0 C336 100pF C208 100nF DGND
R136 47K
R138 47K
5V
11.75VA
GND30
DGND
CN9-1 3711-002815 DGND _INIT _ERROR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LIU C182 100nF C181 100pF C194 100pF (UNUSED) DGND AGND DGND AGND AGND 5V 3.3V E_DP MODEM_RX MODEM_TX1 MODEM_TX2 REMOTE R137 R135 DP 1K 1K _HOOK_OFF _RING_DET CN12-1 CN12-2 R145 100 R146 4.7K
C
3.3V SPK_OUT+ SPK_OUTCN13-1 CN13-2
COVER_OPEN CN3-1 CN3-2 CN3-3 5045-03A 3711-000198|scon_pin3_2.5mm
_SLCTIN C337 100pF DGND DGND DGND C338 100pF
RECALL Q5 3 2SC2812L6-TA 2 C B E R126 2K TP230 1 R125 3K _CML_ON
C197 100nF
CR_NA CR_A
DGND
D
INV_POWER 11.75V R45 22K C3 100uF 25V R44 22 HOME 5V
Q4 3 2SC2812L6-TA 2
1 TP77 R123 2K
R124 3K
LF_B LF_NA LF_A LF_NB
CN4-4 CN4-3 CN4-2 CN4-1 5045-04A 3711-000225
R24 100 1/8W
R23 47K _P_PICKUP CN6-5 CN6-4 CN6-3 CN6-2 CN6-1
C58 220pF
AGND 100nF C33 U5 RPI-441C1 DGND R378 0 11.75V Q7 KSA1203_YTF CCD_TG CCD_CLK1 INV_POWER DGND
SCAN_A SCAN_NA SCAN_B SCAN_NB
5V
DGND
5V
5V
5V
5V
CN5-24 CN5-23 CN5-22 CN5-21 CN5-20 CN5-19 CN5-18 CN5-17 CN5-16 CN5-15 CN5-14 CN5-13 CN5-12 CN5-11 CN5-10 CN5-9 CN5-8 CN5-7 CN5-6 CN5-5 CN5-4 CN5-3 CN5-2 CN5-1 FPC_24 CCD AGND
R25 10K
R28 10K
R33 10K
R38 10K
U6
TP365
C95 C98 C96 R37
10nF 10nF 10nF 0
VOUT_G VOUT_R VOUT_B 100 R36
CCD_CLK2 CCD_RS
C334 100nF R377 10K DGND
C333 100nF TP364
OPE_TXD
R375 680 TP363
ED. DATE SIGN
R35 R30 R26
0 0 0
100 100 100
R34 R29 R27 _OPE_RES OPE_TXDD
_OPE_RST
47pF
47pF
47pF
47pF
LAMP_ON
TP78
D8 RB420D T147 TP367 R373 4.7K
R366 TP366 1K
3 2
Q1 2SC2812L6-TA
CD74HCT244M DGND DGND DGND DGND
A R P .
C H E C K
E N G .
D W G .
GND12
DGND DGND DGND DGND
C32
C35
C38
C39
REF NO
SEC
CONNECTION
2/8
4-2
SCHEMATIC DIAGRAMS
4
3.3V
BD4
600ohm BEDA
3.3V VB2
A
C109 100nF
3.3V 1 C64 100nF U11 LF25CDT I0 OUT GND 2 3 C65 1uF 50V C99 100nF C113 100nF C77 100nF C91 100nF C111 100nF 2.5V
C76 100uF 16V
C92 100nF
C88 100nF
C87 100nF
C110 100nF
C78 100nF
3.3V U13 XC61FN3112MR
R77 100K
A
_POR
TP3
DGND PLLGND 3.3V DGND C79 100nF
C90 10nF
DGND DGND DGND DGND PLLGND R101 4.7K 3.3V
DATA(0:15)
R76 R100
0 0
_POR _F_POR _IP_INT _MODEM_IRQ PH_ID1 _ROM_CS _IP_CS _MODEM_CS _GPIO_CS 245DIR _WR _RD _SCAS _SRAS _SCS0 _SCS1 R95
C220 1nF
R3 4.7K
3.3V
R208 R90 R91
100 100 100 100 100 100 100 100 100 100 100 100 100 100
DGND BD14 CIM21J121NES U37 FS781BZB
C125
22pF
R71 R83 R86 R85 R93 ADDR(0:19) R55 R56 R50 R59 R51 R60
X1 SD16150J7-10.000M R107 100 C219 22pF DGND R204 3.3K C217 0.68nF
C216 100nF
DGND DGND 100
DGND IPCLK
U15 S3C46MOX
A20 A21 A22 _OPE_RST _IP_RST
R61 R11
100 100
SCLK SCKE DQM0 DQM1 C70 100pF DGND
C93 820pF
C89 820pF
3.3V
DGND
PD(0:7)
R58 R57 R73
100 100 100 RA1 100 1/16W RA2 100 1/16W _TRST TDI TCK TDO TMS RA5 1/16W RA4 1/16W RA3 1/16W ACLK AGATE LATCHCTL PCLK PDATA3 PDATA2 PDATA1 PDATA0 PENABLE PLOAD LDCS KEYCLICK TBCLK TBDO _TBCS 4.7K R64 4.7K R78 4.7K R65 4.7K R62 4.7K R63 3.3V
R75 R74 R94 R92
4.7K 4.7K 4.7K 4.7K
C
DGND
_P_SLCTIN _P_STB _P_INIT _P_AUTOFD _P_ERROR P_SLCT P_PE P_BUSY _P_ACK USB_DP USB_DM PULLUP VBUS C215 1nF DGND DGND
D
3.3V
C218 22pF
R102 10M X3 0.32768MHz C112 22pF R89 100
R84 4.7K
R88 4.7K
R80 R72 R87 DGND
600ohm BEDA
100 100
OK2PRT OPE_RXD OPE_TXD PH_ID2 _IP_REQ _IP_ACK _P_PICKUP COVER_OPEN PWM CHYY CHXX
ED. DATE
SIGN
A R P .
C H E C K
E N G .
D W G .
REF NO
SEC
CONTROLLER
3/8
4-3
SCHEMATIC DIAGRAMS
ADDR(1:19)
U7 1107-001302 R41 0
DATA(0:15) ADDR(1:12) U8 K4S641632D-TC75 DATA(0:15)
A
3.3V
VB
A20
R32
0 C37 100nF
_SD_RAS _SD_CAS A21 A22 _SCS0 _WR DQM0 DQM1
_ROM_CS _RD _WR R42 0
DGND _F_POR
C53 100nF
C69 100nF
C52 100nF
C51 100nF
C55 100nF
C68 100nF
C57 100nF
SCLK SD_CKE
B
DGND DGND
3.3V
3.3V
C18 100nF
C4 100nF
U1-3 MC74VHC32DR2 R9 10K C6 1nF R10 10K
U2-4 74VHC08MX
U2-3 74VHC08MX DGND SD_CKE DGND
_F_POR
C9 1nF
C8 100pF
C10 100pF
U3-1 74VHC27
_SD_RAS U1-1 MC74VHC32DR2
DGND DGND DGND DGND DGND
_SRAS
3.3V
VB D2 MMSD914T1 R22 0 R21 200 (UNUSED)
VB2 _SD_CAS _SCAS U1-2 MC74VHC32DR2
Q2 KSA1182-Y R17 R13 180K R12 68K R16 200 1.5K
Q8 2SC2812L6-TA
VB
C5 100nF
D
DGND 5.5V,5V C31 16V 10uF C30 16V 10uF CHX DGND CHXX R371 100K DGND DGND DGND U2-2 74VHC08MX CHY CHYY U1-4 MC74VHC32DR2 U2-1 74VHC08MX
ED. DATE
DGND
SIGN
A R P .
C H E C K
E N G .
D W G .

4/8
REF NO
SEC
MEMORY
4-4
SCHEMATIC DIAGRAMS
1
5V
2
30VA
TBDO TBCLK _TBCS
C85 100nF
C84 100nF 3.3V GND30 DGND
C15 22pF
C16 22pF
A
SCAN_IA0 SCAN_IA1 SCAN_PHA R82 R68 R69 100 100 100
A
11.75V DGND ZD1 1N4743A L1 D1 SS26 150uH R15 12K
2007-007004 0403-000150 JB27-00001A
R388 0 R387 0 R4 R6 0
C71 22pF 30VB
R20 1K
C26 100nF
C14 47nF
2203-000989
C27 100nF
C28 220uF 50V

2401-000880
5V U14 TEA3718S GND30 R54 2.7K C83 820pF R66 56K C86 820pF BD5 CIB32P600NES SCAN_A SCAN_NA SCAN_B SCAN_NB GND30 R70 10K 5V 30VA GND30 C75 22pF DGND C62 100nF C61 100nF C36 47nF C22 47nF C73 22pF C59 22pF C74 22pF 30VB PWM C23 47nF C13 47nF R67 1K C29 22uF50V C25 10nF
DGND GND30 R7 500ohm

2103-001041
GND30 3 R14 3K
2007-000842
GND12 5V
U4 17E0201
GND30 D3 SS26
0402-001212
L2
150uH C24 47nF R19 2K ZD2 1N4735A

0403-000141
JB27-00001A
R18 2K
2007-000669
C40 100nF
C41 470uF 16V

2401-001363
R389
R79 0.5
GND30
GND30
R39 0
2007-000669
DGND R31 R5 0.68 0.68 C34 1nF GND30 C20 1nF C21 1nF
2203-000440
LF_A GND30 LF_NA LF_B LF_NB C19 1nF
GND30
DGND
2007-007845|R6432_RES
DGND SCAN_IB0 SCAN_IB1 SCAN_PHB R48 R47 R49 100 100 100
GND30
GND30
CR_A CR_NA
GND30
C72 22pF
C11 22pF GND30 GND30
C12 22pF
2203-000626
U10 TEA3718S GND30
GND30
R53
1K 3.3V
C
C60 820pF R46 56K C63 820pF
BD3 CIB32P600NES
C
5V 5V
R52 0.5 C152 100nF U22 C74LCX245FT-ELP DGND C108 100nF _HOOK_OFF DATA(0:3) DATA(0:7) U17 MM74HCT273WM R81 10K
GND30
TONE_CTL 3.3V _RING_DET DP _CML_ON RECALL C121 100nF TX_CTL RX_CTL
D
_GPIO_CS 30VA 30V 30VB
_SPK_CTL DGND E_DP
_RD U18-1 MC74VHC32DR2
DGND
BD1
120 ohm BEDA
BD2
0,5%
DGND
DGND
DGND
_WR U18-2 MC74VHC32DR2
ED. DATE
01.08.06
SIGN
A R P .
C H E C K
E N G .
D W G .

5/8
REF NO
SEC
DRIVER
4-5
SCHEMATIC DIAGRAMS
3.3V
BD8 600ohm BEDA
C139 100nF
C142 100nF C164 100nF C153 100nF
C130 100nF C140 100nF
C163 100nF C178 100nF
C162 100nF C165 100nF
C128 100nF C151 100nF
C129 10uF 16V
C143 10uF 16V
C180 10uF 16V
C176 10uF 16V
DGND
3.3V
R206 4.7K HOME REG1_SEN _ADF_DET VOL_00 VOL_10 VOL_20
DGND
R134 4.7K
BASEEXT R119 0 SDRAMDATA(0:15)
MAINEXT R120 0
DGND
DGND
ADC_SDI ADC_SEN ADC_SCK LAMP_ON _D_DET _D_SCAN _SF_POR _MODEM_RST ADF_PHA ADF_PHB ADF_IA0 ADF_IA1 ADF_IB0 ADF_IB1 SCAN_PHA SCAN_PHB SCAN_IA0 SCAN_IA1 SCAN_IB0 SCAN_IB1 ADDR(9:8) R205 100 R115 R117 100 100 RA6 100 1/16W U27 K4S641632C SDRAMDATA(0:15)
3.3V
DATA(0:7) U3-3 74VHC27 ADDR(10) _IP_CS _WR U3-2 74VHC27 DGND
U21 OA-980
R374 33 DGND 3.3V TP457 TP460 TP458 TP459 R128 4.7K C131 100nF DGND
C179 100nF C201 100nF C196 100nF C193 100nF C202 100nF C200 100nF C177 100nF
C198 10uF 16V
C
R116 4.7K _IP_INT _IP_RST
3.3V
3.3V
5V
5VA
10uF C116 100nF U16 WM8192
C107 10uF 16V
C127 10uF 16V C106 100nF C115 100nF
TP450 3.3V BASEEXT MAINEXT R118 1K
DATA(0:7) DGND
DGND
AGND
DGND VOUT_R VOUT_G VOUT_B
IPCLK
R98
100 _IP_ACK0 _IP_REQ DGND 1TP33 1TP232 1TP231 1TP31 1TP32 1TP233 1TP237 1TP238 1TP269 1TP236 1TP234 1TP235 1TP25 1TP29 1TP30 1TP268 1TP28 1TP26 1TP27 AGND R97 47K 3.3V C105 100nF
ADC_CLK _ADC_VSMP ADC_SCK ADC_SDI ADC_SEN
C102 10nF CCD_TG _ADC_VSMP ADC_CLK CCD_RS CCD_CLK2 CCD_CLK1 C94 100nF C103 100nF
R104 4.7K
C104 1000nF
DGND
R105 4.7K
C114 100nF
DGND
DGND MC74VHC32DR2
AGND
ADDR(10)
ED. DATE
_WR_L
01.08.06
_WR U18-3 MC74VHC32DR2 _IP_ACK _IP_ACK0 _RD U18-4
SIGN
A R P .
C H E C K
E N G .
D W G .

6/8
REF NO
SEC
IMAGE PROCESS
4-6
SCHEMATIC DIAGRAMS
A
C175 1nF +3.0V R132 91K
5V
MODEM_TX2 MODEM_TX1 C174 100nF R133 47K R131 330K C188 100nF TX
L4 C149 100nF C155 100nF C150 22uF 16V
10uH C157 100nF C134 100nF MODEM_RX KA358D-T/F U25-2 +3.0V C189 R143 11.75VA 1nF 130K
AGND
DGND
5V
D4 MMSD914T1
U23-2 MC14053BD RX
C173 100nF U25-1
+3.0V
3.3V C183 R372 10K R114 10K R121 10K 100nF C185 100nF R140
KA358D-T/F
3K
AGND C184 100nF R139 120K REMOTE
C138 22uF 16V C135 1nF
C137 100nF C147 100nF
C146 100nF C133 100nF
C136 100nF C145 100nF
RX_CTL DGND C144 1nF AGND C186 1nF +3.0V
DATA(0:7) DGND
R142 DGND 3.3V U23-3 MC14053BD ADDR(0:4) R109 10K C187 100nF R141 47K U24-2
300K
KA358D-T/F
R130
120K
C171
100nF
RX
Q3 2SC2812L6-TA _MODEM_IRQ R112 10K R113 10K +3.0V 5V _RD _WR _MODEM_CS U19 FM336R6719-12
TX
TX_CTL C154 1nF
DGND _MODEM_RST
D6 MMSD914T1
DGND
330K
150K
1M
1M
R157
R163
R162
R160
R156
R158
R161
R164
330K
47K
R122 4.7K
C148 100nF
C
5V
DGND
DGND
R110 100 X2 28.224MHz
C206 100nF
AGND C122 27pF C123 27pF R159 4.7K C199 100nF TONE_OUT
VOL_0
DGND AGND
DGND 5V
VOL_1
VOL_2
D
5V C213 R166 5V C210 1nF 11.75V BD9 CIM21J121NES C156 22uF 25V C169 100nF TONE_OUT C214 KEYCLICK R379 1M C132 100nF 100nF R167 47K C211 1uF C212 1uF AGND TONE_CTL D7 MMSD914T1 C166 1nF +3.0V DGND 11.75VA U23-4 MC14053BD DGND SPK_OUT+ AGND SPK_OUTAGND AGND AGND AGND 1nF 150K _SPK_CTL 11.75VA U24-1 KA358D-T/F C170 100nF R165 10K 11.75VA U23-1 MC14053BD +3.0V
R127 24K
C172 100nF
R129 8.2K C167 10uF 16V C168 100nF
U34 MC34119DR2
ED. DATE
KEYTONE DGND DGND
01.08.06
SIGN
A R P .
C H E C K
E N G .
D W G .

7/8
REF NO
SEC
MODEM
4-7
SCHEMATIC DIAGRAMS
5V 5V
B
_STB DGND CD(0:7) CD(0) CD(1) CD(2) CD(3) CD(4) CD(5) CD(6) CD(7)
5V C195 100nF C207 100nF C190 100nF
3.3V U26 TC74LVX4245MTCX
PD(0:7) DGND PD(0) PD(1) PD(2) PD(3) PD(4) PD(5) PD(6) PD(7) 3.3V
HIC1 SUPER1284
245DIR
3.3V
C191 100nF
C192 100nF
U33
C
_ACK BUSY PE SLCT
39
RA7
DGND _P_ACK P_BUSY P_PE P_SLCT _P_ERROR VOL_00 VOL_10 VOL_20
VOL_0 VOL_1 VOL_2
_P_STB RA8 _AUTOFD _SLCTIN _ERROR _INIT 39 _P_AUTOFD _P_SLCTIN _P_INIT DGND
TC74LVX4245MTCX
DGND
ED. DATE
01.08.06
SIGN
A R P .
C H E C K
E N G .
D W G .

8/8
REF NO
SEC
PARALLEL PORT PART
4-8
SCHEMATIC DIAGRAMS
4-2 ADFCircuit Diagram
510
0.5
0.5
SCX-1150F ADF
4-9
SCHEMATIC DIAGRAMS
4-3 SMPS Circuit Diagram
Magic-V3 POWER SUPPLY(100-240Vac)

F1
AC250V T 2A TNR1
LF1 SQH0350
10D471K
DSC10D9
2KBP06M
BD1
NT1
C7=PC630V103 B1=BEAD R2=1/4W180K C3=222
T1 EE2525W D4=SR204
C13=10V1000uF
KA78R33
+3.3V0.8A
10D561K
C1=224
C2=104
IL1 PE
C5=400V120uF
R3=1/4W/180K
48t =550uH
2t
C15=1KV102 R21=1/4W22
R18=2W2.2K
R1=1W560K
C14=16V47uF
R-30190
U2 2 3
CH1 CON1-1
3 X
C4=222
CON1-2 GND
R19=1/4W/180K
Q2=FQU2N60
9
3t
ZD5=27V R20=1/4W68K
10 Q1
C6=1KV331
D1=1N4148 C8=103 R10=330 R11=180 D2=1N4148 D5=ER502 B2=BEAD CH3 CON1-3 +30V1.3A SSP5N80A
2 7
R14=6.8K R12=1K R15=6.8KF
R13=510
ZD1=9.1V
D3=1N4148
R5=47K
R7=3.3KF
1 2
PC1
PC123B C10=1uF
C12=50V47uF/KMG
PC1=PC123B
ZD2=4.3VB
R8=330
4 3
Q3=C1008-Y
R17=1W0.42(MINI)
R4=1W0.42(MINI)
R6=510
C9=103
Q4=C1008
ZD3=5.6V
R16=1.8KF
R9=33
C11=50V470uF/KMG
Title Size B
Date:
MAGIC POWER SUPPLY CIRCUIT DIAGRAM (Magic-V3)

Document Number {Doc}
Friday, July 20, 2001
ZD4=1W36V
CON1-4 GND
12t
3t
Rev 01 Sheet 1 of 1
4-10
SCHEMATIC DIAGRAMS
4-4 LIU Circuit Diagram
6 line_A R12 1K, 2W R11 12 line_C
R21 220
2SA1156-M Q7
5V
L1-6 A
(WHT)
3 2
U7 PC817C 4
5V
10, 1%,0.25W Q5 BC547B 3 A R10 100 0.25W
D11 1N914
3
L1-2
AGND (BLK)
2
Q8 KSC945-Y 3 1 15K 2
R22 12K RECALL D10 1N914 (unused) C1 33nF/250V (unused) L1 4.2mH
Q3 2SA1156-M
1
Q4 MPSA45 *
*
B L1-3 (BRW)
ARS4
R23
R13 180K, 1/4W GND5
5V line_B Q6 KSC945-Y D8 1N914 R15 12K D9 1N914
FLT1 60uH ARS1 5 VAR3 ARS2 VAR4 FGND VAR5 G6S-2-Y 9 10 L1-4 (RED) ARS3 FLT2 60uH C L1-5
(ORG)
GND5
JP3 4 3 8
JP7
L2 (unused) 4.2mH 3
BD1 W06G 2 line_B line_C line_A 1
3 120K 1
DP
15K R16 5V GND5 R49 2.74K, 1% C3 1uF 100V R44 220 R51 1K,1%
(unused) C16 33nF/250V
GND5 MODEM_RX P10 R48 150 MODEM_TxA1
AGND
4 2SA1156-M Q2
CML_1
unused
T3 4 U6 PC817C 1 ZD4 MTZ4.7B ZD3 MTZ4.7B 82107 C36 68nF
R5 82
U2
1
R4 82
R8 100
D1 BAT47
5V U10 LCA190 5V VAR1 V82ZA2 (unused) C15 150pF 3 Q1 VN2410M 2 JP5 3 2 1 2 100-1016 600:600 3 T2 4
MODEM_TxA2
5V
VAR2
2 PC814
VR61BTP
3 GND5
1
* U3
7 3
JP11 INSTPAR
R9 100
D2 BAT47
C34 15nF D
_HOOK2
D4 1N914
D13 1N4148 R50
R1 56K
5V GND5 MA91000045S
(unused) FLT3 60uH JP19
5V 1 R20 33,1W ZD2 1N4746A ZD1 1N4746A 5V R45 10K D6 1N914 _RING D7 1N914 E GND5 5V U9 PC814 MODEM_RX MODEM_TxA1 MODEM_TxA2 REMOTE _CML1 _HOOK2 _RING DP RECALL _E_DP
R46 D12 1N4148
_E_DP
D5 1N914 GND5 L2-3

(BLU)
C4 50V 0.47uF
R2 200K R3 15K
T1
5 7
ZD6 MTZ4.7B C7 1nF R7 30K
C5 1uF
GND5
AGND
4 E
SJ3030K
8 ZD5 MTZ4.7B 12V C14 0.47uF 50V
L2-5
(YEL)
C9 15nF/400V
L2-4
(GRN)
GND12
P1 35303-0850 1 2 3 4 5 6 7 8 9 10 11 12 13 14 35303-1450 GND5 GND12 GND5 Changed by: Date Changed: 6
GND5
REMOTE
12V 5V G6S-2-Y 1 CML_1 12 _CML1 12V
D3 1N4148
C13 10uF 50V
C10 100nF
C12 10uF 50V
C11 100nF
P2 P2 P2 P2 P2 P2 P2 P2
1 2 3 4 5 6 7 8
L1-5 L1-4 L1-3 L1-2 L1-6 L2-3 L2-4 L2-5
GND12 Engineer: Drawn by: R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Time Changed: QA CHK: 6:33:26 pm 7 REV: 01 Drawing Number: 01 8 TITLE: COMPANY NAME Address City
F Size: A3
SCX-1150F LIU
8 1 6 A TL Page: 01
4-11
SCHEMATIC DIAGRAMS
4-5 OPE Circuit Diagram
CN2-4
CN2-2
CN2-5
CN2-1 CN2-3
OPE_POW
CN1-4 CN1-5 CN1-6 CN1-7 CN1-8 CN1-9 CN1-10 CN1-11 CN1-12 CN1-13 CN1-14
CN1-3
CN1-2
CN1-1
OPE_POW
TITLE:
SCX-1150F OPE Board
4-12
This manual is made and described centering around circuit diagram and circuit description needed in the repair center in the form of appendix.
Samsung Electronics Digital Printing CS Group

Copyright (c) 2001. 10

Samsung SCX 1150 MFP Service Manual

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Samsung SCX 1150 MFP Service Manual

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Repair Manual

MODEM CLOCK 28.224MHz

MONO CARTRI DGE

PRINT HEAD(2PEN) 600DPI DOUBLE

HEIGHT ENCORDER SENSOR

IEEE 1284 TIMERS

CARRIAGE RETURN MOTOR

FLASH (8Mbit) SDRA M (64Mbit)

MOTOR 48MHz /REQ /ACK

COVER OPEN SENSOR

( 30V, 3. 3V) SDRAM (64Mbit)

IMAGE PROCESSOR OA-980

ADF STEPPER MOTOR DRIVER

Refer to the Schematic diagram(See page 4-2)

Repair Manual Samsung Electronics

3-1. GENERAL DESCRIPTION

3-2. MEMORY MAP

<Figure 1. S3C46MOX(Jupiter3) MEMORY MAP>

Repair Manual Samsung Electronics

3-3-2 S3C46MOX(Jupiter3) FUNCTION DESCRIPTION

3-3-2-2 DATA and ADDRESS BUS CONTROL 1. /RD & /WR

2. CHIP SELECT (/ROMCS, /IP_CS,/MED_CS,/SCS0,/SCS1)

Repair Manual Samsung Electronics

MODEM CLOCK 28.224MHz

MONO CARTRI DGE

PRINT HEAD(2PEN) 600DPI DOUBLE

HEIGHT ENCORDER SENSOR DERASTERIZER

PAPER EXIT SENSOR

IEEE 1284 TIMERS

CARRIAGE RETURN MOTOR

FLASH (8Mbit) SDRA M (64Mbit)

<Figure 2. Block Diagram of Main Part>

COVER OPEN SENSOR

IMAGE PROCESSOR OA-980

ADF STEPPER MOTOR DRIVER

<Figure 3. Flash Memory Read Timing>

<Figure 4. Flash Memory Write Timing>

Repair Manual Samsung Electronics

<Figure 5. SDRAM Read Timing>

Repair Manual Samsung Electronics

<Figure 6. SDRAM Write Timing>

Repair Manual Samsung Electronics

<Figure 7. SDRAM Write Timing>

Repair Manual Samsung Electronics

<Figure 8. SDRAM auto Refresh Timing>

Repair Manual Samsung Electronics

<Figure 9. SDRAM Self Refresh Timing>

Repair Manual Samsung Electronics

Repair Manual Samsung Electronics

3-3-2-3 EXTERNAL DMA part

3-3-2-6 PARALLEL PORT INTERFACE division

3-3-2-4 DRAM control part

3-3-2-5 RTC (REAL TIME CLOCK) part

Repair Manual Samsung Electronics

<Figure 10. Compatibility Hardware Handshaking Timing>

<Figure 10-1. ECP Hardware Handshaking Timing (forward)>

Repair Manual Samsung Electronics

<Figure 10-2. ECP Hardware Handshaking Timing (reverse)>

Repair Manual Samsung Electronics

3-3-2-7 USB INTERFACE PART

D< Figure 10-3. USB Signal Line DIAGRAM >

Repair Manual Samsung Electronics

3-3-2-8 HEAD control part

0=H@M=HA 4AIAJ 0ECD

4 )BJA H 5 BJM= HA 4AIAJ =@L= ?A J FHAF=H=JE @A J BE A BH @ M =@ ANA?KJE , M =@ A NA?KJE BH BE A 5,4 ) 7 %

) '& >O JDA ANA?KJE 5,4) @A