EE 261

James Morizio
1
MOS Transistor Theory
So far, we have viewed a MOS transistor as an
ideal switch (digital operation)
Reality: less than ideal
EE 261
James Morizio
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EE 261
James Morizio
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Introduction
So far, we have treated transistors as ideal
switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
Also explore what a degraded level really means
EE 261
James Morizio
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MOS Transistor Theory
Study conducting channel between source and drain
Modulated by voltage applied to the gate (voltage-
controlled device)
nMOS transistor: majority carriers are electrons
(greater mobility), p-substrate doped (positively doped)
pMOS transistor: majority carriers are holes (less
mobility), n-substrate (negatively doped)
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James Morizio
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Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s
V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence V
ds
0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
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James Morizio
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Gate Biasing
p-substrate
n
+
n
+
Source
Gate
Drain
Channel
+ -
E
SiO
2
V
SS
(Gnd)
V
gs
=0: no current flows from
source to drain (insulated by
two reverse biased pn
junctions
V
gs
>0: electric field created
across substrate
Electrons accumulate under gate: region changes from p-type
to n-type
Conduction path between source and drain
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James Morizio
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nMOS Device Behavior
V
gs
<< V
t
Polysilicon gate p-substrate
Accumulation
mode
Enhancement-mode transistor: Conducts when gate bias
V
gs
> V
t
Depletion-mode transistor: Conducts when gate bias is zero
V
gs
= V
t
Depletion mode
Depletion region
Oxide insulator
V
gs
> V
t
Inversion mode
Depletion region
Inversion
Region
(n-type)
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James Morizio
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nMOS Cutoff
No channel
I
ds
= 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
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James Morizio
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nMOS Linear
Channel forms
Current flows from d to s
e
-
from s to d
I
ds
increases with V
ds
Similar to linear resistor
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
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James Morizio
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nMOS Saturation
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
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James Morizio
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I-V Characteristics
In linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
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James Morizio
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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
=
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
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James Morizio
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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
= CV
C =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
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James Morizio
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Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
=
ox
WL/t
ox
= C
ox
WL
V =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
EE 261
James Morizio
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Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
=
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
C
ox
=
ox
/ t
ox
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James Morizio
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Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v =
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James Morizio
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Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E =
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James Morizio
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Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t =
EE 261
James Morizio
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Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = V
ds
/L
Time for carrier to cross channel:
t = L / v
EE 261
James Morizio
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nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
ds
I =
EE 261
James Morizio
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nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ds
Q
I
t
=
=
EE 261
James Morizio
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nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V

=
| |
=
|
\ .
| |
=
|
\ .
ox
=
W
C
L

EE 261
James Morizio
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nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
ds
I =
EE 261
James Morizio
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nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
2
dsat
ds gs t dsat
V
I V V V
| |
=
|
\ .
EE 261
James Morizio
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nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V

| |
=
|
\ .
=
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James Morizio
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nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

| |
= <
|
\ .

>

Shockley 1
st
order transistor models
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James Morizio
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Current-Voltage Relations
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James Morizio
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Current-Voltage Relations
k
n
: transconductance of transistor
W : width-to-length ratio
L
As W increases, more carriers available to conduct current
As L increases, V
ds
diminishes in effect (more voltage
drop). Takes longer to push carriers across the transistor,
reducing current flow
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James Morizio
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Example
For a 0.6 m process
From AMI Semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L

| |
| |
= = =
| |

\ .
\ .
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
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James Morizio
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pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same
current
In this class, assume
n
/
p
= 2 to 3
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James Morizio
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Capacitance
Any two conductors separated by an insulator
have capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is associated
with source/drain diffusion
EE 261
James Morizio
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Gate Capacitance
Approximate channel as connected to source
C
gs
=
ox
WL/t
ox
= C
ox
WL = C
permicron
W
C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9
0
)
polysilicon
gate
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James Morizio
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The Gate Capacitance
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James Morizio
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Diffusion Capacitance
C
sb
, C
db
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to C
g
for contacted diff
C
g
for uncontacted
Varies with process
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James Morizio
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Diffusion Capacitance
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James Morizio
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Parasitic Resistances
W
L
D
Drain
Drain
contact
Polysilicon gate
D
S
G
R
S
R
D
V
GS,eff
R
S
= (L
S
/W)R + R
C
R
D
= (L
D
/W)R + R
C
R
C
: contact resistance
R : sheet resistance per square
of drain-source diffusion
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James Morizio
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Body Effect
Many MOS devices on a common substrate
Substrate voltage of all devices are normally equal
But several devices may be connected in series
Increase in source-to-substrate voltage as we proceed vertically
along the chain
d1
d2
s1
s2
V
12
V
11
g1
g2
V
sb1
= 0
V
sb2
= 0
Net effect: slight increase
in threshold voltage V
t
,
V
t2
>V
t1
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James Morizio
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Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing V
DD
V
DD
V
DD
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James Morizio
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Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing V
DD
V
g
= V
DD
If V
s
> V
DD
-V
t
, V
gs
< V
t
Hence transistor would turn itself off
nMOS pass transistors pull no higher than V
DD
-V
tn
Called a degraded 1
Approach degraded value slowly (low I
ds
)
pMOS pass transistors pull no lower than V
tp
V
DD
V
DD
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James Morizio
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Pass Transistor Ckts
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
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James Morizio
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Pass Transistor Ckts
V
DD
V
DD
V
s
= V
DD
-V
tn
V
SS
V
s
= |V
tp
|
V
DD
V
DD
-V
tn
V
DD
-V
tn
V
DD
-V
tn
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
-V
tn
V
DD
-2V
tn
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James Morizio
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Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace I
ds
(V
ds
, V
gs
) with effective resistance R
I
ds
= V
ds
/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay
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James Morizio
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RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
k g
s
d
g
s
d
kC
kC
kC
R/k
k g
s
d
g
s
d
kC
kC
kC
2R/k
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James Morizio
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RC Values
Capacitance
C = C
g
= C
s
= C
d
= 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent
EE 261
James Morizio
45
Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change
EE 261
James Morizio
46
Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor
current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change
EE 261
James Morizio
47
DC Response
DC Response: V
out
vs. V
in
for a gate
Ex: Inverter
When V
in
= 0 -> V
out
= V
DD
When V
in
= V
DD
-> V
out
= 0
In between, V
out
depends on
transistor size and current
By KCL, must settle such that
I
dsn
= |I
dsp
|
We could solve equations
But graphical solution gives more insight
I
dsn
I
dsp
V
out
V
DD
V
in
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James Morizio
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Transistor Operation
Current depends on region of transistor behavior
For what V
in
and V
out
are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
EE 261
James Morizio
49
nMOS Operation
V
gsn
>
V
dsn
>
V
gsn
>
V
dsn
<
V
gsn
<
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
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James Morizio
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nMOS Operation
V
gsn
> V
tn
V
dsn
> V
gsn
V
tn
V
gsn
> V
tn
V
dsn
< V
gsn
V
tn
V
gsn
< V
tn
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
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James Morizio
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nMOS Operation
V
gsn
> V
tn
V
dsn
> V
gsn
V
tn
V
gsn
> V
tn
V
dsn
< V
gsn
V
tn
V
gsn
< V
tn
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
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James Morizio
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nMOS Operation
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
V
tn
V
out
> V
in
- V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
< V
gsn
V
tn
V
out
< V
in
- V
tn
V
gsn
< V
tn
V
in
< V
tn
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
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James Morizio
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pMOS Operation
V
gsp
<
V
dsp
<
V
gsp
<
V
dsp
>
V
gsp
>
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
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James Morizio
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pMOS Operation
V
gsp
< V
tp
V
dsp
< V
gsp
V
tp
V
gsp
< V
tp
V
dsp
> V
gsp
V
tp
V
gsp
> V
tp
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
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James Morizio
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pMOS Operation
V
gsp
< V
tp
V
dsp
< V
gsp
V
tp
V
gsp
< V
tp
V
dsp
> V
gsp
V
tp
V
gsp
> V
tp
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0
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James Morizio
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pMOS Operation
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
V
tp
V
out
< V
in
- V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
V
tp
V
out
> V
in
- V
tp
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0
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James Morizio
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I-V Characteristics
Make pMOS wider than nMOS such that
n
=
p
V
gsn5
V
gsn4
V
gsn3
V
gsn2
V
gsn1
V
gsp5
V
gsp4
V
gsp3
V
gsp2
V
gsp1
V
DD
-V
DD
V
dsn
-V
dsp
-I
dsp
I
dsn
0
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James Morizio
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DC Transfer Curve
Transcribe points onto V
in
vs. V
out
plot
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
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James Morizio
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Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
E
D
C
B
A
pMOS nMOS Region
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James Morizio
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Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp Cutoff Linear E
Saturation Linear D
Saturation Saturation C
Linear Saturation B
Linear Cutoff A
pMOS nMOS Region
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James Morizio
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Beta Ratio
If
p
/
n
1, switching point will move from V
DD
/2
Called skewed gate
Other gates: collapse into equivalent inverter
V
out
0
V
in
V
DD
V
DD
0.5
1
2
10
p
n

=
0.1
p
n

=
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James Morizio
62
Noise Margins
How much noise can a gate input see before it
does not recognize the input?
Indeterminate
Region
NM
L
NM
H
Input Characteristics Output Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
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Logic Levels
To maximize noise margins, select logic levels at
V
DD
V
in
V
out
V
DD

p
/
n
> 1
V
in
V
out
0
EE 261
James Morizio
64
Logic Levels
To maximize noise margins, select logic levels at
unity gain point of DC transfer characteristic
V
DD
V
in
V
out
V
OH
V
DD
V
OL
V
IL
V
IH
V
tn
Unity Gain Points
Slope = -1
V
DD
-
|V
tp
|

p
/
n
> 1
V
in
V
out
0
EE 261
James Morizio
65