Course Outline

((EE EE6205 6205) VLSI Design ) VLSI Design

By Dr. Yaseer A. Durrani
Dept. of Electronics Engineering
University of Engineering & Technology, Taxila
Course Outline
1 Introduction to VLSI
1 Back End
IC Fabrication Process
1 Front End
CMOS Circuits Layout
MOS Transistor Theory
2
Static & Dynamic Logic Circuits
VLSI Embedded Systems
Reference Books
1 VLSI Design, H.C. M. Glesner
1 VLSI Design Circuit Methodology, Liming Xiu
1 The VLSI Handbook, Wai-Kai Chen
1 Digital Design & Fabrication, V. G. Oklobdzija
1 Modern VLSI Deisgn, Wayne Wolf
1 CMOS VLSI Design 3
rd
Ed., Weste & Harris
3
Grading policy
1 Assignments 08%
1 Quizzes 12%
1 Mid 20%
1 Course Project/Case Studies 20%
1 Final 40%
4
Introduction to VLSI Design
(EE6205) VLSI Design (EE6205) VLSI Design
By Dr. Yaseer A. Durrani
Dept. of Electronics Engineering
University of Engineering & Technology, Taxila
5
Outline
1 What is a VLSI Circuit?
1 VLSI Challenges
1 Major Approaches in VLSI
ASIC, FPFA, PLD, PLA, PAL etc.
1 Levels of Abstraction
1 System on Chip Design
6
1 System on Chip Design
1 Low Power Designs
What is a VLSI Circuit?
1 Very Large Scale Integrated Circuit
1 Process of integration of millions of transistors in a single chip
1 VLSI design involves all aspects of creating in IC
Integration of (mathematical expression) dx
Integration of (Transistors and complex logic gates)
7
1 VLSI design process is classified into 2 categories
Front End: Performs all aspects of design before
handing design over foundry for manufacture in
GDSII (graphical design system II) format
Back End: IC manufacturer (foundry) handles most
Back End tasks that are Mask generation, Wafer
processing, Testing, Delivery of samples, Final
mass production
What is a VLSI Circuit?
1 Many disciplines have contributed in VLSI design:
Solid-State Physics
Material Science
Lithography & Fabrication
Device Modeling
Circuit Design & Layout
Architecture
Algorithms
CAD Tools
8
CAD Tools
Why VLSI?
1 Integration improves the design
Lower parasitic = higher speed
Lower power consumption
Physically smaller
1 Integration reduces manufacturing cost - (almost) no manual assembly
Era Date Complexity
(Number of logic blocks/chip)
9
Single Transistor 1959 Less than 1
Unit Logic (one gate) 1960 1
Multi-function 1962 2-4
Complex Function 1964 5-20
Medium Scale Integration 1967 20-200
Large Scale Integration 1972 200-2000
Very Large Scale Integration 1978 2000-20000
Ultra Large Scale Integration 1989 20000-?
Giga Scale Integration Future
1 Technology scaling doubled the number of devices in an IC
(processors, FPGAs, , etc) every 2-3 years
1 Scaling also provided devices with reduced delay 1 frequency
doubling (with aggressive pipelining) 1increased power density
1 Increases in clock frequency slowed down (or stopped); available
devices are used to create multi-processor (multi-core) processors
Why VLSI?
10
Technology Trends
1 Processor
Logic capacity increases ~ 30% per year
Clock frequency increases ~ 20% per year
Cost per function decreases ~20% per year
1 Memory
DRAM capacity: increases ~ 60% per year
(4x every 3 years)
Speed: increases ~ 10% per year
11
Cost per bit: decreases ~25% per year
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Logic trans/cm
2
6.2M 18M 39M 84M 180M 390M
Cost/trans (mc) 1.735 .580 .255 .110 .049 .022
#pads/chip 1867 2553 3492 4776 6532 8935
Clock (MHz) 1250 2100 3500 6000 10000 16900
Chip size (mm
2
) 340 430 520 620 750 900
Wiring levels 6-7 7 7-8 8-9 9 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5
High-perf pow (W) 90 130 160 170 175 183

Productivity Gap
Productivity
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)
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10,000
100,000
1,000,000
10,000,000
58% / Yr. compound
complexity growth rate
12
gap
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7
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2
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21% / Yr. compound
productivity growth rate
VLSI Design Challenge
1 Goal: Circuit design with increasing complexity with shorter times
1 Medium of implementation: VLSI gives designer to control over almost
everything:
Architecture, Logic Design, Speed, Area, Power,
1 Densities are increasing, costs decreasing with each passing year
13
How to partition a
complex SoC design into
manageable blocks?
How to analyze &
How to check entire
design for localized
voltage drops?
How to calculate & fix
timing in presence of
VLSI Chip Design Issues
14
reduce chip power
consumption?
How to ensure reliability
against electromigration
& hot electron effects?
timing in presence of
crosstalk and noise?
How to guarantee
manufacturability by
correct layout?
Source: Design Aids for Low Power, Jan M. Rabaey
IC Products
1 Processors
CPU, DSP, Controllers
1 Memory chips
RAM, ROM, EEPROM
1 Analog
Mobile communication,
audio/video processing
1 Programmable
CPLD, PLA, PAL, FPGA
Medical
Point of Service
Home Automation
Wearable
Network sensors
Secondary displays
15
CPLD, PLA, PAL, FPGA
1 Embedded systems
Used in cars, factories
Network cards
1 System-on-Chip (SoC)
Distributed systems
Entertainment
Thin Client
PND
Consumer Robotics
Portable media
Industrial Automation
Telematics
Thin Client
Printed Circuit Board (PCB)
16
16
IC Design Alternatives
Standard Components
Application Specific ICs
Fixed Application
Application by
Programming
Semi
Custom
Silicon
Compilation
Full
Custom
Major Approaches in VLSI Design
17
Compilation Custom
Logic Families
Hardware
Programming
(MASK)
Software
Programming
TTL/CMOS
PLA
ROM
Microprocessor
EPROM,EEPROM
PLD
Major Approaches in VLSI Design
18
Application-Specific Standard Product (ASSP)
Standard IC
(off the shelf)
ASIC
(User-Specified)
SSI/MSI LSI/VLSI Semi-custom Full-custom
User-programmable
Standard Digital/Analog Standard
Major Approaches in VLSI Design
19
User-programmable
PLDs FPGAs
Standard
Library cells
Digital/Analog
Mixed Signal
Standard
ASICs
All Masks
Density
Peifoimance
Ilexibility
Design time
Manufactuiing time
Cost - low volume
Cost - high volume
123456 123456
Veiy High
Veiy High
Veiy High
Veiy Long
Veiy High
Low
Medium
17889AB37C
High
High
High
High
Low
Shoit
Medium
DE7CF237C
Low
High
High
High
Shoit
Shoit
Medium
DE7FE7C
Low
High
Low
Veiy Shoit
Veiy Shoit
Medium- Low
Medium- Low
1 IC that customized for a particular use, rather than intended for general-
purpose use
1 Modern ASICs often include entire uP, Memory including ROM, RAM,
EEPROM, flash memory, Digital voice recorder etc.
1 ASIC has grown from 5,000 gates to over 100 million
1 Properties:
Custom design, labor intensive, high volume opportunities, Standard
parts for quick time to market applications, Economics of design,
Application-Specific Integrated Circuit (ASIC)
parts for quick time to market applications, Economics of design,
Fast prototyping
1 CAD Tools:
System-level design: Concept to VHDL/C
Physical design: VHDL/C to silicon
Timing closure (Monterey, Magma, Synopsys, Cadence, Avant!)
1 Design Strategies:
Hierarchy, Regularity, Modularity, Locality
20
Application Specific Standard Product (ASSP)
1 IC that implements a specific function that appeals to a wide market
1 It combine a collection of functions & designed by or for one customer
1 ASSPs are used in all industries, from automotive to communications
1 Examples: Video and/or audio encoding and/or decoding
21
Types of ASIC
1 Full-Custom ASICs:
Custom-made from scratch for a specific application
Their ultimate purpose is decided by the designer
All the photolithographic layers of IC are already fully defined, leaving no
room for modification during manufacturing
1 Semi-Custom ASICs:
Partly customized to perform different functions within the field of their
general area of application
Designers allowed some modification during manufacturing, although the
masks for diffused layers are already fully defined
1 Platform ASICs:
Designed & produced from defined set of methodologies, intellectual
properties & well-defined design of silicon that shortens the design cycle and
minimizes development costs
Made from predefined platform slices, where each slice is a
premanufactured device, platform logic or entire system
Premanufactured material reduces development costs
22
Full Custom Design
Comp
Via
Metal2
I/O Pad
Macro Cell
1 Engineers design manually some or all cells, circuits or layouts
1 Circuits are highly optimized for speed, area, or power
1 Design style is only suitable for very high performance circuitries
23
A/D
PLA I/O
RAM
Metal1
Metal2
Glue Logic
(Standard
Cell Design)
Macro Cell
Design
1 Users can select a desired platform based on their needs
1 Offers high performance with characteristics of both ASIC & FPGA
1 Verification costs can be significantly lower than ASIC because major functions
on platform might be preverified
1 ASIC performance is better than platformed ASIC and it is better than FPGA
1 Platform ASIC trades the high performance of ASIC with shorter time to market
& lower development cost. The platform ASIC approach is gaining momentum
due to its relatively lower cost as compared to an ASIC. But for very large
volume products, its unit cost could be higher than ASIC
Platform/Structured Design
volume products, its unit cost could be higher than ASIC
1 Pre-designing processors like ARM or MIPs processors, clock, power
distribution & test structures
24
1 Group of transistor & interconnect that provides Boolean logic function
(AND, OR, XOR, XNOR, buffer, inverter, flip-flop or latch)
1 Utilization of functional blocks to achieve very high gate density and
good electrical performance
1 Standard-cell design fits b/w Gate Array & Full Custom design
1 Cell-based methodology makes it possible for one designer to focus on
high-level (logical function) aspect of digital design, while another
designer focuses on the implementation (physical) aspect
Standard-Cell Design
designer focuses on the implementation (physical) aspect
25
Standard Cell Design
D C C B
A C C
Cell
Metal1
Metal2
GND VDD
Cell library
26
A C C
D C D B
B C C C
C D
A B
Cell library
Standard Cell Library
1 Collection of Standard-Cells: These cells are realized as fixed-height, variable-
width full-custom cells, which enables them to be placed in rows, easing the
process of automated digital layout. The cells are typically optimized full-
custom layouts, which minimize delays and area
1 Typical library contains two main components:
Library Database - Consists of layout, schematic, symbol, abstract, and
other logical or simulation views
Timing Abstract - Generally in Liberty format, to provide functional
definitions, timing, power, and noise information for each cell
27
definitions, timing, power, and noise information for each cell
1 Standard-cell library contain additional components:
Full layout of the cells
Spice models of the cells
Verilog/VHDL models
Parasitic Extraction model
DRC/LVS rule decks
Behavioral model
Timing & Testing model
Circuit Schematic
Wire-load & Routing model
Physical
Design
Technology
Mapping
Synthesis
IC Design Steps
Specifications
High-level
Description
Functional
Description
28
Packaging
Fabri-
cation
Placed
& Routed
Design
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
Gate-level
Design
Logic
Description