Sie sind auf Seite 1von 15

Last (family) name: _________________________ First (given) name: _________________________ Student I.D.

#: _____________________________ Circle section: Kim Hu

Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals

Final Exam
Sunday, December 15, 10:05-12:05 PM

1. 2. 3. 4. 5. 6. 7.

Closed book examination. No calculator, hand-held computer or portable computer allowed. Five points penalty if you fail to enter name, ID# , or instructor selection. Answer must be entered into specified boxes if provided. You must show your work to receive full or partial credit for your answers. No one shall leave room during last 5 minutes of the examination. Upon announcement of the end of the exam, stop writing on the exam paper immediately. Pass the exam to isles to be picked up by a TA. The instructor will announce when to leave the room. 8. Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 14 Academic misconduct procedures.

Instructions:

F02, ECE/CS 352 Quiz #3

Problem 1 2 3 4 5 6 7 8 Total

Points 10 10 10 10 15 5 20 15 100

Score

Flip-Flop Excitation Tables JK Flip-Flop Q(t+1) J 0 0 1 1 0 X 1 X D Flip-Flop Q(t) Q(t+1) 0 0 0 1 1 0 1 1 SR Flip-Flop Q(t+1) S 0 0 1 1 0 0 1 X

Q(t) 0 0 1 1

K X X 1 0

Q(t) 0 0 1 1

R X 0 1 0

D 0 1 0 1

T Flip-Flop Q(t) Q(t+1) 0 0 0 1 1 0 1 1

T 0 1 1 0

ECE/CS 352 Final Fall 2002

1. (10 points) 2-level implementation and logic minimization (a) (5 points) Implement the following Boolean functions in 2-level NOR-NOR logic. F(a, b, c, d) = m(1, 3, 5, 7, 9, 12, 15). Minimize your logic and draw the logic schematic. Assume complements of the input Boolean variables are available. Answer: To find NOR-NOR implementation, we need to find F (a, b, c, d ) in SOP format, which is F (a, b, c, d ) = a d + b d + a b c + a b d . Then we find F(a, b, c, d) by finding a dual of F (a, b, c, d ) , the complementing each literals.
F (a, b, c, d ) = (a + d ) (b + d ) (a + b + d ) (a + b + c)

ECE/CS 352 Final Fall 2002

(b) (5 points) Consider the Boolean function below: F(a, b, c, d) = M (1, 4, 5, 6, 9, 10). Find ALL the prime implicants of function f(a, b, c, d) using the tabular method. Answers without work will not receive any credit!

ECE/CS 352 Final Fall 2002

2. (10 points) Radix and Diminished-Radix arithmetic Compute the following using specified method (number of bits n = 6). If an overflow occurs, indicate how you have determined the overflow condition. You must show your work to receive full credit (show carries or borrows on top of minuends whenever possible). (a) (4 points) Compute the following using a signed 1s complement arithmetic (number of bits n = 6).

101101 001001

(b) (4 points) Compute the following using an unsigned 2s complement arithmetic (number of bits n = 6).

001101 011001

(c) (2 points) Compute the following using 9s complement arithmetic. Two numbers given below are decimal numbers.

27310 76810

ECE/CS 352 Final Fall 2002

3. (10 points) ALU A 4-bit multi-function register operates according to a function table where S1, S0 are two mode selection inputs.

Full Adder S1 Ai X Sum Y Cout Bi S0 Ci Cin Fi Ci+1

The schematic above is an ALU bit slice which can perform both arithmetic and logic operations by choosing appropriate control signals C0, S0 and S1 where C0 is a Ci for the least significant bit. . Let F = Fn1F1F0 to be the output, A = An1A1A0 and B = Bn1B1B0. Complete the function table below for output F. For each function, clearly indicate whether the function is an arithmetic operation (A) or a logical operation (L). Answer: S1 S0 0 0 1 1 0 1 0 1 C0 = 0
A B , (L)

C0 = 1

A B , (L)

ECE/CS 352 Final Fall 2002

4. (10 points) Sequential circuits and timing analysis The clock (CLK) signal is connected to following two sequential circuits with output Y.

A Y B

CLK

The clock (CLK) signal is connected to a sequential circuit with output Y. Complete the timing diagram given below. Assume that the gate delays are negligible.

CLK

A B Y

ECE/CS 352 Final Fall 2002

5. (15 points) State diagram, state table and synchronous circuit design The state diagram shown below is for a synchronous sequential circuit with unknown function. This sequential circuit has two state variables S1(t) and S0(t), and an input C. State variables S1(t) and S0(t) are to be implemented with SR flip-flops.

C=0/Z=0

C=0/Z=0

C=1/Z=1

11
C=1/Z=0

00
C=1/Z=0

10
C=1/Z=0 C=0/Z=0
(a) (5 points) Complete the state table below.

01

C=0/Z=0

C 0 0 0 0 1 1 1 1

S1(t) S0(t) S1(t+1) S0(t+1) 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1

S1S S1R S0s S0R

ECE/CS 352 Final Fall 2002

(b) (4 points) Express the result in a minimized SOP standard format.

S1S = S1R = S0S = S0R =


(c) (3 points) A set-dominant SR flip-flop is a special type of SR flip-flop such that when both inputs S and R are set to logic 1, the output of the FF becomes logic 1 in the next clock cycle. Suppose you are to use a pair of set-dominant SR flip-flops to implement the circuit. Would this change your implementation/design? Answer: (circle only one) Yes or No If Yes, list all implementation/design changes. If No, show why it would not change your implementation. You must show your work to get credit.

(d) (3 points) A reset-dominant SR flip-flop is a special type of SR flip-flop such that when both inputs S and R are set to logic 1, the output of the FF becomes logic 0 in the next clock cycle. Suppose you are to use a pair of reset-dominant SR flip-flops to implement the circuit. Would this change your implementation/design? Answer: (circle only one) Yes or No If Yes, list all implementation/design changes. If No, show why it would not change your implementation. You must show your work to get credit.

ECE/CS 352 Final Fall 2002

6. (5 points) Memory organization (a) (3 points) How many address lines and how many data lines a 128K 8 SRAM chip has?

Answer: Number of address lines =

Number of data lines =

(b) (2 points) How many 64K 8 SRAM chips are required to build a 128K 32 SRAM subsystem?

Answer:

chips

ECE/CS 352 Final Fall 2002

10

7. (20 points) Programmable Devices and Hazard. Following is a programmed Programmable Logic Array implementing three functions F(A, B, C), G(A, B, C) and H(A, B, C). For the remaining of this problem, we will focus only on F(A, B, C). Warning: There will be NO partial credit given for this problem.
A

(a) (4 points) Draw a Karnaugh map corresponding to the function F(A, B, C) and show all product terms used for implementing function F(A, B, C).

A\BC 0 1

00

01

11

10

(b) (4 points) Redraw a Karnaugh map corresponding the function F(A, B, C) and indicate all single input change static-1 hazard.

A\BC 0 1
ECE/CS 352 Final Fall 2002

00

01

11

10

11

(c) (4 points) A multiple input change logic hazard may occur. Identify all of them by filling the blanks of the table below.
Input before a multiple input change Input after a multiple input change

(d) (3 points) Suppose you are to use the fewest number of additional product terms (AND gates) to be ORed to the function F to eliminate all logical hazards. List the function F below using a SOP standard notation. Hint: List the original product terms used first, then list the additional product terms required to eliminate the static-1 logic hazard.

Answer:

F(A, B, C) =

ECE/CS 352 Final Fall 2002

12

(e) (5 points) Implement the function Z (a, b, c) = a b c + a b c + a b c + a b c using Programmable Array Logic below. Be sure to label all inputs and clearly indicate the output Z.

ECE/CS 352 Final Fall 2002

13

8. (15 points) Below is an ASM chart of certain controller. Assume R0 and R1 are 8-bit registers.

IDLE R0 R0+1

ST0

0 R1 0

WORK R0 0

ST1 R1 R1+1

(a) (5 points) Find the response for the ASM chart above to the following sequence of inputs (assume that the initial state is ST0).

S: 1 C: 0 State: ST0 R0 R1 0 0

1 0

1 0

0 1

0 1

0 1

0 1

0 1

1 0

ECE/CS 352 Final Fall 2002

14

(b) (10 points) Implement this ASM chart using one-state-per-state method. Using positive edge triggered flip-flops, AND, OR, NOT gates. Simplify the design to use as few logic gates as possible.

ECE/CS 352 Final Fall 2002

15