Quiz Solution

Pipelining

Question 1

You have the task of pipelining a combinational circuit consisting entirely of 2-input NAND gates with 1ns propagation delay by adding registers having tS=1ns, tH=1 ns, tPD=2 ns. he propagation delay of the original combinational circuit is 20 ns. A. !ssuming you add the minimum number of registers to pipeline the circuit for ma"imal throughput, what is the latency of the resulting pipelined circuit# tP$ of %&ns when built from 1ns components, we have input'output path involving %& components. o get ma"imal throughput, place each component in its own pipeline stage for a total of %& stages. (ach stage re)uires tP$,*(+ , tP$,-!-$ , tS,*(+ . % , 1 , 1 . /ns to do its 0ob. So the latency of the circuit pipelined for ma"imal throughput is %&"/ . 1&ns.

B. !ssume that the registers have tS.1ns, t2.& ns, tP$.% ns, and you add the minimum number of registers to pipeline the circuit for ma"imal throughput, what is the latency of the resulting pipelined circuit# (ach stage re)uires tP$,*(+ , tP$,-!-$ , tS,*(+ . % , 1 , 1 . /ns to do its 0ob. So the latency of the circuit pipelined for ma"imal throughput is %&"/ . 1&ns.

Question %

4f the registers labeled 3 and + are removed, describe the resulting circuit5s behavior.

*emoving 3 and + combines the last two pipeline stages into a single pipeline stage. he latency improves to 24ns and the throughput stays 1/8ns.

4f the pipeline registers in the given circuit were all replaced with non'ideal pipeline registers having propagation delays of % ns, set'up times of 1 ns, and hold times of & ns, what would be the ma"imum throughput achievable with the supplied si" combinational modules#

he clock period would be set by the delay of the pipeline stage containing the 616 module7 t !" = tPD#$%& ' 8 ' tS#$%& = 11ns. So the throughput would be 1/11ns.

4f the pipeline registers in the given circuit were all replaced with non'ideal pipeline registers having propagation delays of % ns, set'up times of 1 ns, and hold times of & ns, how long before the system clock must the input " be set'up to assure that the pipeline registers ! and 8 work properly#

tS#( = ) ' tS#$%& = 8ns.

Suppose that a second output, g9":, is desired from the given circuit. 4t provides the partial result present at the output of the pipeline register labeled ;. 4f we wish the outputs f9": and g9": to correspond to the same input after each clock, how many new pipeline registers should be added to the circuit shown#