Reg. No.

Question Paper Code :

M.E./M.Tech. DEGREE EXAMINATION, JANUARY 2011. First Semester Applied Electronics

(Common to VLSI Design)

248102 ADVANCED DIGITAL SYSTEM DESIGN (Regulation 2010)

1. 2. 3. 4. 5. 6. 7. 8.

Compare and contrast the features of Mealy and Moore state machines. State the rules for state assignment.

Name the two types of asynchronous sequential circuits. What is a static hazard? Give an example.

What are the two common types of faults that occur in digital circuits? What is a primitive D-cube? Draw the schematic of a configuration memory cell of Xilinx 4000 FPGA.

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9. 10.

State the difference between PLA and PAL. Write a VHDL code for a 2 1 multiplexer using data flow modeling.

What are named and positional associations in structural modeling?

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Answer ALL questions.

PART A (10 2 = 20 marks)

Time : Three hours

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Maximum : 100 marks

PART B (5 16 = 80 marks) 11. (a) (i) (ii) Design a Moore based serial adder.

Reduce the following state table using partitioning method and implication chart. Present State a b c d e f g h Next State X=0 X=1 c d h b e f c c f e g g b a g f

Present Output X=0 0 0 0 0 0 0 0 X=1 0 0

(b)

(i) (ii)

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Or Or 2

What is an ASM chart? What are the basic building blocks of ASM chart? (6) Convert the following state graph to its equivalent SM chart.

z a , zb , z c are the Moore outputs. and z1 , z 2 are the Mealy outputs.

Also implement the state graph using T Flipflops. 12. (a)

1
0 (10) (16)

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Design an asynchronous sequential circuit that has two inputs x 2 and x1 and one output z when x1 = 0 , the output z is 0. The first change in x 2 that occurs while x1 is 1 will cause output z to be 1. The output z will remain 1 until x1 returns to 0.

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(6) (10) 0 0 1 1 1

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(b)

(i) (ii)

Give the hazard-free realisation for the following Boolean function. (6) Show that the following state table has essential hazards. PS NS X=0 X=1 A B C D Z

B C D A

0 0 0 1

13.

(a)

line a s-a-0, line a s-a-1, line f s-a-1, line w s-a-1.

(b) 14. (a)

Discuss in detail about the D algorithm with suitable example.

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Or Or 3

Explain the path sensitization method. Derive the test vectors to detect the following stuck-at-faults in the given circuit : (16)

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Design a sequential BCD to excess-3 code converter using Mealy Model. Also implement the circuit using a suitable sequential PAL (Reproduce only the required portion of the sequential PAL) (16)

(b)

(i)

With simplified block diagram, explain the CLB architecture of Xilinx 4000 FPGA. (8) Explain the features of Xilinx 4000 series I/O block. (8)

(ii)

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(10) (16)

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15.

(a)

(i) (ii)

What is a generate statement? Write the VHDL code for a 4-bit parallel adder using generate statement. (10) Give the VHDL code example for the synthesis of a CASE statement. (6) Or

(b)

Design a 4 4 binary multiplier and write the VHDL code using behavioral model. (16)

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1
4

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