De Course File 2013-14

Year : II COURSE DESCRIPTION Global Institute Technology, Jaipur
(Approved by AICTE and Affiliated to RTU, Kota)
Digital Electronics
Sem : III
1. 2. 3.
Name of the Faculty Designation Department
: : :
Rishabh Sharma Asst. Professor Electronics & Communication Engineering Lecture: 3hrs/week
External Marks: 80 Internal Marks: 20 Total Marks: 100
1. Program Educational Objective (PEO):

The department to fulfill its Mission has following specific educational objectives: PEO 1: Core competence and Successful career The Graduate shall able to use modern techniques, innovate, design, simulate, develop, and test hardware components by pursuing successful careers in Indian and multinational companies, PSUs as Team Leaders, Managers, Consultants or as entrepreneurs and also to pursue higher education. PEO 2: Lifelong learning The students are provided with an academic environment to become aware of excellence, leadership and the life-long learning needed for a successful professional career. PEO#3: Professionalism The Graduates of the program shall have professional and ethical attitude, communication skills, multidisciplinary approach and competence to relate engineering issues to broader social perspective.
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2. Program Outcomes (PO):

All Electronics and Communication Engineering graduates shall demonstrate:
(a). An ability to apply knowledge of mathematics, science, and engineering to electronics and communication engineering problems. (b). An ability to design and conduct experiments, and to analyze and interpret gathered data. (c). An ability to develop and/or design a system or system components to meet desired specifications, performance, and capabilities (d). An ability to function on and/or develop leadership in multi-disciplinary teams (e). An ability to identify, formulates, and solves electronics and communication engineering problems. (f). An understanding of professional and ethical responsibility (g). An ability for effective communication and an ability to function individually as well as part of a team (h). An ability to understand and correctly interpret the impact of engineering solutions in a social/global context. (i). An ability to engage in life-long learning to follow developments in electronics and communication engineering. (j). A knowledge and understanding of contemporary issues and recognition of the need for quality. (k). An ability to skillfully use modern engineering tools and techniques necessary for engineering design, analysis and applications. (l). An ability to pinpoint and define engineering problems in the fields of electronics & communication engineering and able to resolve them through analytical thinking in their own or related fields.
(m). Graduates will exhibit research and problem-solving skills to support lifelong personal and
professional development and able to face competitive exams like GATE, IES, ISRO, BSNL (JTO), DRDO, DMRC etc.
3. Course Objectives:
A. Core Competence: To provide basic understanding and working of digital electronic circuits and logics along with their applications to the students. B. Lifelong learning: To Student will be able purse study in advanced digital electronics, Logic Family, Number System.TTL Family.
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C. Professionalism: To prepare students for understanding working principals of modern logical devices used in various industries.
4. Course Objective contribution to Programme Outcomes:

Sr.no Course Objective 1 2 3 Core Competence Lifelong learning Professionalism Mapping with Programme Outcomes a B c d e f g h i j k l m
5. Course prerequisite:
Practical knowledge of Logic Gates Practical knowledge of Combinational Circuits and sequential circuits. Basics of EDC.
6. Course description This course will be taught using the top-down approach. Topics covered include introduction to digital electronics and comparison with analog electronics, number system and codes for basic understanding of digital coding system. Boolean algebra and digital logic gates to simplify Boolean expression. Ability to understand working function of switching circuits, in modern digital systems. Minimization techniques come under combination systems. Basic memory elements like Latches, flip-flops, counters and registers are sequential systems.
7. Course Syllabus:
UNIT 1: NUMBER SYSTEMS, BASIC LOGIC GATES & BOOLEAN ALGEBRA: Binary Arithmetic & Radix representation of different numbers. Sign & magnitude representation, Fixed point representation, complement notation, various codes & arithmetic in different codes & their inter conversion. Features of logic algebra, postulates of Boolean algebra. Theorems of Boolean algebra. Boolean function. Derived logic gates: Exclusive-OR, NAND, NOR gates, their block diagrams and truth tables. Logic diagrams from Boolean expressions and vice-versa. Converting logic diagrams to universal -3-
logic. Positive, negative and mixed logic. Logic gate conversion.
UNIT 2: DIGITAL LOGIC GATE CHARACTERISTICS: TTL logic gate characteristics. Theory & operation of TTL NAND gate circuitry. Open collector TTL. Three state output logic. TTL subfamilies. MOS & CMOS logic families. Realization of logic gates in RTL, DTL, ECL, C-MOS & MOSFET. Interfacing logic families to one another.
UNIT 3: MINIMIZATION TECHNIQUES: Minterm, Maxterm, Karnaugh Map, K map upto 4 variables. Simplification of logic functions with K-map, conversion of truth tables in POS and SOP form. Incomplete specified functions. Variable mapping. Quinn-Mc Klusky minimization techniques.
UNIT 4: COMBINATIONAL SYSTEMS: Combinational logic circuit design, half and full adder, subtractor. Binary serial and parallel adders. BCD adder. Binary multiplier . Decoder: Binary to
Graydecoder, BCD to decimal, BCD to 7-segment decoder. Multiplexer, demultiplexer, encoder. Octal to binary, BCD to excess-3 encoder. Diode switching matrix. Design of logic circuits by multiplexers, encoders, decoders and demultiplexers.
UNIT 5: SEQUENTIAL SYSTEMS: Latches, flip-flops, R-S, D, J-K, Master Slave flip flops. Conversion of flip-flops. Counters: Asynchronous (ripple), synchronous and synchronous decade counter, Modulus counter, skipping state counter, counter design. Ring counter. Counter applications. Registers : buffer register, shift register.
8. Important Topics Covered:

Karnaugh Map State diagram of Flip-flops Digital ICs
9. References:
Digital Electronics: Principles And Integrated Circuits by Anil K. Maini, Wiley India Pvt Ltd 1st edition. Digital Electronics: Principles And Applications (With CD) by Tokheim Tata Mcgraw Hill Education Private Limited 6th edition. -4-
10. Topics beyond the syllabus:

Five (5) variable K-Map and Tabular Method. IIL Digital Logic Family Analog to Digital Convertor Johnsons counter Memories
11. Interaction Methods:

Class room teaching, Black Board Teaching, Power slide Presentation. Interactive Interaction - Group Discussion, Quiz Indirect Interaction- Problem Solving Independent Interaction- Assignment Questions
12. Course outcomes:

At the end of the course a student will: 1. have the basic knowledge of logic gates, Universal logic gates and Karnaugh Map.
2. have the knowledge and use of modern upcoming technologies like digital logic families and Flip
flops & register.
13. Additional Seminar/Workshop/Industrial Tour:

N/A
14. Assessment of Outcomes:

University Assessment 1. Mid-Term Test #1 (10%) 2. Mid-Term Test #2 (10%) 3. Unit Test 4. Class Test 5. University End Semester Examination (80%) Remedial Actions Taken (For Weak Students) 1. Weekly Assessments 2. Extra Classes 3. Counseling Signature of faculty
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Year : II CLASS TIME TABLE Digital Electronics Global Institute Technology, Jaipur
Sem : III
1. 2. 3.
: : :
Rishabh Sharma Asst. Professor Electronics & Communication Engineering
DAY
I 7:50 -8:45 M-III (RM)

CAS(VR)T1 MIII (AJ)T2
II 8:45 -9:40 SOFT SKILLS
III 9:40-10:35
IV 10:35 -11:30
V 11:30 -12:25
LUNCH 12:25 1:05
VI 1:05 -2:00 DSA (NJ)
MON
TUE
WED
EPM-R.C. (SW) EPM (SW) EPM (SW)
THUR
Elc.W/s /MJG/G1 EDC(PS)T1 CP Lab-I/MS/G2 CA(VR)T2 EDC Lab/PS/G3 CP Lab-I/MS/G1 EPM M-III EDC Lab/PS/G2 (SW) (RM) DE Lab/DV/G3 EDC Lab/PS/G1 CAS EDC DE Lab/DV/G2 (VR) (PS) Elc.W/s /MJG/G3 DE Lab/DV/G1 Project Lab Elc.W/s /MJG/G2 (AJ) CP Lab-I/MS/G3 EDC (PS) CAS (VR) DSA -R.C. (NJ) BE (NS)
B R E A K
DSA (NJ) M-III (RM)
CAS - R.C. (VR) DE -R.C. (RS)
FRI
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Year : II CLASS TIME TABLE Digital Electronics Global Institute Technology, Jaipur
Sem : III
DAY
I 7:50 -8:45 M-III (RM)

CAS(VR)T1 MIII (AJ)T2
II 8:45 -9:40 SOFT SKILLS
III 9:40-10:35
IV 10:35 -11:30
V 11:30 -12:25
LUNCH 12:25 1:05
VI 1:05 -2
MON
TUE
WED
EPM-R.C. (SW) EPM (SW) EPM (SW)
THUR
Elc.W/s /MJG/G1 EDC(PS)T1 CP Lab-I/MS/G2 CA(VR)T2 EDC Lab/PS/G3 CP Lab-I/MS/G1 EPM M-III EDC Lab/PS/G2 (SW) (RM) DE Lab/DV/G3 EDC Lab/PS/G1 CAS EDC DE Lab/DV/G2 (VR) (PS) Elc.W/s /MJG/G3 DE Lab/DV/G1 Project Lab Elc.W/s /MJG/G2 (AJ) CP Lab-I/MS/G3 EDC (PS) CAS (VR) DSA -R.C. (NJ) BE (NS)
DSA (NJ
B R E A K
DSA (NJ
M-I (RM
CAS (VR
FRI
DE -R (RS
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Year : II Year TFTT (Tentative Frame Time Table) Subject: Digital Electronics Global Institute Of Technology, Jaipur
Sem : III Sem
1. 2. 3.
: Rishabh Sharma : Asst. Professor : Electronics & Communication Engineering
The Schedule for the Course / Subject is:

Lecture Date as per TFTT/Course Date of completion Plan Total students present in the class 25 31
S.NO. Unit Name of the Unit and Topic Binary Arithmetic & Radix representation of different numbers Sign & magnitude representation, Fixed point representation, complement notation various codes & arithmetic in different codes & their inter conversion Features of logic algebra, postulates of Boolean algebra. Theorems of Boolean algebra. Boolean function Derived logic gates: Exclusive-OR, NAND, NOR gates, their block diagrams and truth tables Positive, negative and mixed logic Logic gate conversion. Logic diagrams from Boolean expressions and vica-versa. Converting logic diagrams to universal logic
No.of Hrs.
1 2 3 4 5 6 7 8 9 10 1
6/8/2013 7/8/2013 13/8/2013 14/8/2013 17/8/2013 20/8/2013 21/8/2013 22/8/2013 24/8/2013 27/8/2013 28/8/2013 29/8/2013 31/8/2013 3/9/2013 4/9/2013 5/9/2013 7/9/2013 10/9/2013
6/8/2013 13/8/2013 14/8/2013 17/8/2013 21/8/2013 24/8/2013 27/8/2013 28/8/2013 29/8/2013 31/8/2013 3/9/2013 4/9/2013 5/9/2013 7/9/2013 10/9/2013 11/8/2013 12/9/2013
10
37 37 39
53 31 33 49 46 31 32 50 46 48 40 29
Remedial class ASSIGNMENT-1 & CLASS TEST-1

11 12 13 14 15 16 3 Minterm, Maxterm Karnaugh Map, K map upto 4 variables Simplification of logic functions with K-map, conversion of truth tables in POS and SOP form Incomplete specified functions. Variable mapping Quinn-Mc Klusky minimization
18/9/2013
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17
techniques
Remedial class ASSIGNMENT-2 & CLASS TEST-2 PPT-1 ON K MAP

18 19 20 21 22 23 24 4 Combinational Logic Circuit Design,half and full adder,Subtractor Binary serial and parallel adders. BCD adder. Binary multiplier Decoder: Binary to Gray decoder, BCD to decimal, BCD to 7-segment decoder Multiplexer, demultiplexer, encoder. Octal to binary, BCD to excess-3 encoder Design of logic circuits by multiplexers, encoders, decoders and demultiplexers Diode switching matrix
11/9/2013 14/9/2013 17/9/2013 21/9/2013 10/9/2013 24/9/2013 25/9/2013 26/9/2013 28/9/2013 31/9/2013 3/10/2013 5/10/2013 8/10/2013 26/9/2013 28/9/2013 31/9/2013 3/10/2013 5/10/2013 8/10/2013 9/10/2013 12/10/2013 15/10/2013 12/10/2013 15/10/2013 17/10/2013 19/10/2013 22/10/2013 23/10/2013 31/10/2013 2/11/2013 5/11/2013
19/9/2013 1/10/2013 5/10/2013 9/10/2013 18/9/2013 10/10/2013 12/10/2013 15/10/2013

7
37
32 29 44
42 41 40 44 30
16/10/2013 16/10/2013 17/10/2013 17/10/2013 30/10/2013 15/10/2013 16/10/2013 16/10/2013 17/10/2013

7 31 31 46 46 30 31

25 26 27 28 29 30 31 5 Latches, flip-flops, R-S, D, J-K flip flop Master Slave flip flops. Conversions of flip-flops Counters : Asynchronous (ripple), synchronous and synchronous decade counter Modulus counter, skipping state counter counter design. Ring counter Registers: buffer register, shift register
31 46
44 30 30
17/10/2013 30/10/2013 30/10/2013 31/10/2013 31/10/2013 31/10/2013

42

32 33 34 35 36 37 2 TTL logic gate characteristics. Theory & operation of TTL NAND gate circuitry Open collector TTL. Three state output logic. TTL subfamilies. MOS & CMOS logic families Realization of logic gates in RTL, DTL, ECL, C-MOS & MOSFET Interfacing logic families to one another
31/10/2013
42
2/11/2013 5/11/2013 6/11/2013 7/11/2013 8/11/2013 10/11/2013 12/11/2013
40 38 20 25 26 42 10
Remedial class ASSIGNMENT-5 & CLASS TEST-5 PPT-2 ON logic families
Total No. of Instruction Periods available for the course: 37 Hours / Periods
Signature of Faculty
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Year : II Year COURSE SCHEDULE Global Institute Of Technology, Jaipur

(Unit Wise) UNIT - I Ankit Sharma Asst. Professor E I & C Engineering Topics / Sub Topics Reference (Text Book, Journal.) Page No.to
Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 1 to 6 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 7 to 19 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 20 to 32, 39,40 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 41 to 44 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 77 to 81, 87-94 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 82, 83 & 95 to 98 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 100 to 101
Sem : III Sem
1. 2. 3. S.No. 1 2
Name of the Faculty Designation Department Date

06/08/13
: : :
No. of Periods
1
08/08/13
Difference between Analog and Digital systems, Types of Number systems & their Conversion Binary Arithmetic,Radix representation of different numbers.Sign & magnitude representation, Fixed point representation, complement notation Various codes, & arithmetic in different codes & their inter conversion, Features of logic algebra, Postulates of Boolean algebra Theorems of Boolean algebra, Demorgans Theorem & its Proof Simplification of Boolean functions, Basic Logic gates, Derived logic gates: ExclusiveOR, Ex- NOR their block diagrams and truth tables. Universal Logic gates: NAND & NOR gates with their block diagrams & truth tables,Logic diagrams from Boolean expressions and viceversa, Positive, negative and mixed logic Converting logic diagrams to universal logic, Logic gate conversion.
09/08/13
13/08/13
16/08/13
23/08/13
25/08/13
Signature of Faculty Date
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Year : II Year COURSE SCHEDULE (Unit Wise) Global Institute of Technology, Jaipur
UNIT - II Rishabh Sharma Asst. Professor
Sem : III Sem
1. 2. 3. S.No. 1 2 3 4 5 6

29/08/13
: : :
Electronics & Communication Engineering Topics / Sub Topics Reference (Text Book, Journal.) Page No.to
Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 114 to 117 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 118 to 119 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 119 to 120, 139 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 121 to 138 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 140 to 144 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 145 to 148, 151 to 155
No. of Periods
1
Digital IC Terminology, Characteristics of Digital Ics BJT, RTL, DCTL, RCTL
30/08/13
03/09/13
DTL & Modified DTL, HTL, IIL
05/09/13
TTL, ECL MOSFET LOGIC, Construction & Operation of MOSFET CMOS Logic & Interfacing of TTL & CMOS
06/09/13 07/09/13
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Year : II Year COURSE SCHEDULE Global Institute Of Technology, Jaipur

(Unit Wise) UNIT - III Sem : III Sem
1. 2. 3. S.No. 1
Name of the Faculty Designation Department Date No. of Periods

1
: : :
Rishabh Sharma Asst. Professor Electronics & Communication Engineering Topics / Sub Topics Reference (Text Book, Journal.) Page No.to
Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 50 to 55 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 56 to 59 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 59 to 65 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 65 to 72 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 65 to 72
29/08/13
SOP & POS Form, Conversion of Logic Expression to Standard SOP or POS form. Concept of Minterm & Maxterm, conversion of truth tables in POS and SOP form Karnaugh Map, K map upto 4 variables
30/08/13
03/09/13
Simplification of logic functions with K-map.
05/09/13
Incomplete specified functions. Variable mapping.
06/09/13 07/09/13
Quinn-Mc Klusky minimization techniques & problems based on this topic
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Year : II Year COURSE SCHEDULE (Unit Wise) UNIT - IV
Global Institute of Technology, Jaipur

(Approved by AICTE a nd Affiliated to RTU, Kota)
Sem : III Sem
1. 2. 3. S.No. 1 2 3 4 5 6 7 8 9

12/09/13
: : :
Rishabh Sharma Asst. Professor Electronics & Communication Engineering Topics / Sub Topics Reference (Text Book, Journal.) Page No.to
Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 161 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 161 to 165 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No.165 to 167, 175 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 168 to 170,178 to 180 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 181 to 183, 188 to 194 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 195 to 204 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 205 to 210 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 220 to 225 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 211 to 213
No. of Periods
1
Steps to design Combinational circuits (with examples) , Code conversion Combinational logic circuit design, half and full adder. Half Subtractor & Full subtractor, Binary Serial Adder Binary parallel adders, BCD Adder Binary Multiplier & Multiplexers
13/09/13
14/09/13
19/09/13 20/09/13
21/09/13
Multiplexers& Demultiplexers
01/10/13
Decoder: Binary to Gray decoder, BCD to decimal Encoder. Octal to binary, BCD to excess-3 encoder. BCD to 7-segment decoder, matrix Diode switching
03/10/13
04/10/13
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Year : II Year COURSE SCHEDULE (Unit Wise) UNIT - V Rishabh Sharma Asst. Professor Electronics & Communication Engineering Topics / Sub Topics
Difference between combinational cicuits & sequential circuits, working principle of flip-flops (bistable multivibrator) Latches, flip-flops, R-S(Clock Based & without Clock), D Flip Flop J-K, T & Master Slave Flip Flop,
Global Institute Of Technology, Jaipur

Sem : III Sem
1. 2. 3. S.No.
1

10/10/2013
: : :
No. of Periods
1
Reference (Text Book, Journal.) Page No.to

Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 253 to 254 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 255 to 264 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 265 to 276 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 277 to 288 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 293 to 335 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 293 to 335 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 345 to 357, 336-339 Digital Circuits and Design (S.Salivahanan,S.Arivazhangan) Page No. 345 to 357
11/10/2013
12/10/2013
15/10/2013 17/10/13 18/10/13 19/10/13
Realization of one flip flop using other flip flops Counters (Asynchronous & Synchronous Decade Counter), Modulus Counter, skipping State Counter, UP/DOWN Counter, Counter Design with problems Shift Register Counter:Ring Counter, Johnson Counter & Counter Applications Registers( Shift Registers, bufferr Registers)
5, 6 7
22/10/13
29/10/13
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Year : II Year Global Institute of Technology, Jaipur

LECTURE PLAN Sem : III Sem Date: 6/8/2013
1. 2. 3.
Subject Lesson No. Title
: Digital Electronics : 1
Subject Code: 3CS5 Duration of Lesson: 55 Min
: NUMBER SYSTEMS, BASIC LOGIC GATES & BOOLEAN ALGEBRA
Topic: Binary Arithmetic & S.NO. numbers 1.
Radix representation of different
Time Allotted
Introduction: It is imperative to understand that the type of numeration

system used to represent numbers has no impact upon the outcome of any Arithmetical function (addition, subtraction, multiplication, division, roots, powers, or logarithms).
2.
Division Of The Topic: 1. Explanation of number system 2. Radix representation 40
3.
Conclusion: There are four type of number system namely binary, Decimal, Octal and Hexadecimal. One can convert from one base to another.
4.
Question/Answer/ Review: Explain the different types of number system. 5
Level of Difficulty (for faculty):
Tough
Moderate
Easy
Teaching Aids: Chalk, Black Board, Marker, Projector & PPT Teaching Points: Lecture delivered Reference Readings: S. Salivahanan, S. Arivazhangan", Vikas publications, Fifteenth Edition, 2008
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1. 2. 3. S.NO. 1.
: Digital Electronics : 2 :
NUMBER SYSTEMS, BASIC LOGIC GATES & BOOLEAN ALGEBRA
Topic: - Sign & magnitude representation, Fixed point representation, complement notation Introduction: : It is imperative to understand that the type of numeration
system used to represent numbers has no impact upon the outcome of any Arithmetical function (addition, subtraction, multiplication, division, roots, powers, or logarithms).
Time Allotted
2.
Division Of The Topic: 1. 2. 3. 4. Explanation Sign representation Fixed point representation Complement Notation
40
3.
Conclusion: The number is represented in two ways sign and unsigned. They may we represented as fixed point also.
4.
Question/Answer/ Review: Explain the complement notation. 5
Tough
Moderate
Easy
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1. 2. 3.
Topic: - Various codes & arithmetic in different codes & their inter S.NO. conversion 1. Introduction: There are different codes in digital electronics. The coding is used for safe transmission of data.
Time Allotted
5 2. Division Of The Topic: 1. 2. 3. 4. Explanation Different type of codes Arithmetics Conversion
40
3.
Conclusion: The codes are weighted codes non weighted codes, hamming code etc
4.
Question/Answer/ Review: Explain the weighted and non weighted codes. 5
Tough
Moderate
Easy
Teaching Aids: Chalk, Black Board, Marker, Projector & PPT Teaching Points: Lecture delivered Reference Readings: " S. Salivahanan, S. Arivazhangan", Vikas publications, Fifteenth Edition, 2008
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1. 2. 3. S.NO. 1.
: Digital Electronics : 4&5 :
Topic: - Features of logic algebra, postulates of Boolean algebra. Theorems of Boolean algebra. Boolean function Introduction: Features of logic algebra, postulates of Boolean algebra. Theorems of Boolean algebra. Boolean function. Division Of The Topic: 1. Explanation 2. Postulates of Boolean algebra 3. Theorems of Boolean algebra
Time Allotted
2.
40
3.
Conclusion: Different postulates and d morgans threorem is learned. 5
4.
Question/Answer/ Review: Explain the d morgans theorem. 5
Tough
Moderate
Easy
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1. 2. 3. S.NO. 1.
Topic: - Derived logic gates: Exclusive-OR, NAND, NOR gates, their block diagrams and truth tables Introduction: There are two universal gates NAND and NOR and any Basic and Advanced Gate can be derived from these universal gates. Division Of The Topic: 1. Explanation 2. symbol 3. truth tables for Ex OR and Ex NOR
Time Allotted
2.
40
3.
Conclusion: There are two derived gates Ex-OR and Ex- NOR. 5
4.
Question/Answer/ Review: Explain the truth table of Ex- OR and Ex-NOR Gate? 5
Tough
Moderate
Easy
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1. 2. 3.
S.NO. Topic: - Positive, negative and mixed logic. 1. Introduction: In digital electronics high and low values of input and output is assigned to 0 and 1 based on that there are three type of logic . Division Of The Topic: 1. Explanation 2. Block Diagrams
Time Allotted
2.
40
3.
Conclusion: There are three type of logics namely Positive, negative and mixed logic.
4.
Question/Answer/ Review: Explain Mixed Logic. 5
Tough
Moderate
Easy
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1. 2. 3.
: NUMBER SYSTEMS, BASIC LOGIC GATES & BOOLEAN ALGEBRA
S.NO. Topic: - Logic gate conversion. 1. Introduction: There are two universal gates NAND and NOR and any Basic and Advanced Gate can be derived from these universal gates. Division Of The Topic: 1. Explanation 2. Block Diagrams
Time Allotted
2.
40
3.
Conclusion: All the basic gates and derived gates are obtained from the universal gates.
4.
Question/Answer/ Review: Obtain the derived gate from the universal gates. 5
Tough
Moderate
Easy
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1. 2. 3.
: Digital Electronics : 9 & 10 :
S.NO. 1.
2.
Topic: - Logic diagrams from Boolean expressions and vice-versa. Converting logic diagrams to universal logic Introduction: The Boolean expression is converted into the logic diagram and logic diagram is converted into the Boolean expression. The logic diagram can be implemented using basic gates then it may be converted using universal gates. Division Of The Topic: 1. 2. 3. 4. Explanation Block Diagrams Conversion Problems
Time Allotted
40
3.
Conclusion: Logic diagrams from Boolean expressions and vice-versa is done and converted into to universal logic.
4.
Question/Answer/ Review: Explain the conversion of basic gate logic diagram to universal logic diagram. 5
Tough
Moderate
Easy
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LECTURE PLAN Sem : III Sem Date:24/8/2013
1. 2. 3. S.NO. 1.
: DIGITAL LOGIC GATE CHARACTERISTIC Time Allotted
2.
Topic: - TTL logic gate characteristics. Theory & operation of TTL NAND gate circuitry Introduction: For the fabrication of digital ICs we have different technologies. For each family we are defining the Fan In, Fan Out, PD, Power consumption etc. using each logic family the universal gate is implemented and working is explained. Division Of The Topic:
1. Explanation 2. Block Diagrams 3. Working
40
3.
Conclusion: NAND Gate implemented using TTL. 5
4.
Question/Answer/ Review: Explain the working of TTL NAND gate. 5
Tough
Moderate
Easy
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1. 2. 3.
DIGITAL LOGIC GATE CHARACTERISTIC
S.NO. Topic: - Open collector TTL. Three state output logic 1. Introduction: For the fabrication of digital ICs we have different technologies. For each family we are defining the Fan In, Fan Out, PD, Power consumption etc. using each logic family the universal gate is implemented and working is explained Division Of The Topic:
1. Explanation
Time Allotted
2.
2. Block Diagrams 3. working
40
3.
Conclusion: Three type of TTL logic namely Open Collector, Tri State and general.
4.
Question/Answer/ Review: Explain open collector TTL NAND Gate.? 5
Tough
Moderate
Easy
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1. 2. 3.
S.NO. 1.
Topic: - TTL subfamilies. MOS & CMOS logic families Introduction: For the fabrication of digital ICs we have different technologies. For each family we are defining the Fan In, Fan Out, PD, Power consumption etc. using each logic family the universal gate is implemented and working is explained Division Of The Topic:
1. Explanation 2. Block Diagrams 3. Working of MOS and CMOS logic Family.
Time Allotted
2.
40
3.
Conclusion: Different type of MOS and CMOS technologies has learned .
4.
Question/Answer/ Review: Compare CMOS and TTL. 5
Tough
Moderate
Easy
- 25 -

1. 2. 3.
S.NO. 1.
Topic: - Realization of logic gates in RTL, DTL, ECL, C-MOS & MOSFET Introduction: For the fabrication of digital ICs we have different technologies. For each family we are defining the Fan In, Fan Out, PD, Power consumption etc. using each logic family the universal gate is implemented and working is explained. Division Of The Topic
1. Explanation 2. Implementation
Time Allotted
2.
40
3. Block Diagrams 3. Conclusion: Logic gates in different logic families. Question/Answer/ Review: Compare DTL, RTL, ECL and CMOS. 5
4.
Tough
Moderate
Easy
- 26 -

1. 2. 3.
S.NO. 1.
Topic: - Interfacing logic families to one another Introduction: For the fabrication of digital ICs we have different technologies. For each family we are defining the Fan In, Fan Out, PD, Power consumption etc. using each logic family the universal gate is implemented and working is explained Division Of The Topic: 1.Explanation
Time Allotted
2.
40 2.Block Diagram 3. Interfacing Conclusion: Interfacing The TTL to CMOS And CMOS to TTL is explained.
3.
4.
Question/Answer/ Review: Explain the TTL to CMOS interfacing. 5
Tough
Moderate
Easy
- 27 -

1. 2. 3.
MINIMIZATION TECHNIQUES
S.NO. 1.
Topic: - Min term, Max term Introduction: There are different technique for the reduction of Boolean expression namely K Map and Quine Mc Clusky Method. There are two terms defined Min term and Max term. Division Of The Topic:
1. Min Term 2. Max Term
Time Allotted
2.
40
3.
Conclusion: Two Boolean terms are defined Min Term and Max Term.
4.
Question/Answer/ Review: Define min term and max term? 5
Tough
Moderate
Easy
- 28 -

1. 2. 3.
S.NO. 1.
Topic: - Karnaugh Map, K map up to 4 variables Introduction: There are different technique for the reduction of Boolean expression namely K Map and Quine Mc Clusky Method. There are two terms defined Min term and Max term. Division Of The Topic:
1. Derivation of 4 variable K Map 2. Method 3. Problems
Time Allotted
2.
40
3.
Conclusion: Boolean expression is solved using K Map. Question/Answer/ Review: Explain the rules to solve K Map
4.
Tough
Moderate
Easy
- 29 -

1. 2. 3. S.NO. 1.
Topic: - Simplification of logic functions with K-map, conversion of truth tables in POS and SOP form Introduction: There are different technique for the reduction of Boolean expression namely K Map and Quine Mc Clusky Method. There are two terms defined Min term and Max term Division Of The Topic: 1.Explanation 2.K Map 3.Block Diagrams 4. SOP & POS
Time Allotted
2.
40
3.
Conclusion: Simplification using K Map and truth table for SOP and POS 5
4.
Question/Answer/ Review: Explain the Conversion of truth tables in SOP Form? 5
Tough
Moderate
Easy
- 30 -

1. 2. 3.
S.NO. Topic: - Incomplete specified functions. Variable mapping 1. Introduction: There are different technique for the reduction of Boolean expression namely K Map and Quine Mc Clusky Method. There are two terms defined Min term and Max term Division Of The Topic: 1.Explanation 2.Plotting of K Map For ISF 3. Diagrams 3. Conclusion: K Map for incomplete specified function is explained. The variables are plotted on the K Map. Question/Answer/ Review:
Time Allotted
2.
40
4.
5 Explain the Variable Mapping. Level of Difficulty (for faculty): Tough Moderate Easy
- 31 -

1. 2. 3.

S.NO. Topic: - Quinn-Mc Klusky minimization techniques 1. Introduction: There are different technique for the reduction of Boolean expression namely K Map and Quine Mc Clusky Method. There are two terms defined Min term and Max term Division Of The Topic: 1. Explanation 2. Derivation 3. Problems 3. Conclusion: The method of solving the Boolean function is explained.
Time Allotted
2.
40
4.
Question/Answer/ Review: Simplify the expressions:

(i) (ii) Y= m(3, 6, 7,8,10,12,14,17,19,20,21,24,25,27,28) using K-Map. f(w,x,y,z)= m(1,3,4,5,9,10,11)+ (6,8)
Tough
Moderate
Easy
- 32 -

LECTURE PLAN Sem : III Sem Date:
1. 2. 3.
COMBINATIONAL SYSTEMS
S.NO. Topic: - Combinational logic circuit design 1. Introduction: In Combinational circuits (like arithmetic circuits, multiplexers, encoders & decoders), the output depends only on the input values at that time. The basic building blocks of arithmetic unit is half-adder, full adder and these circuits perform operations at speed less than 1s. Division Of The Topic: 1. Steps to design the combinational circuits 2. Examples 3. Implementing the circuit using basic logic gates 3. Conclusion: Students are now able to understand what a combinational circuit actually means and by designing the circuit of staircase system they are aware of its practical application. Question/Answer/ Review: Design a combinational circuit for converting binary number into gray number. Level of Difficulty (for faculty): Tough Moderate Easy
Time Allotted
2.
40
4.
- 33 -

LECTURE PLAN Sem : III Sem Date: 26,28/9/2013
1. 2. 3.
: Digital Electronics : 2 4 & 25 :
COMBINATIONAL SYSTEMS Time Allotted
S.NO. Topic: - half adder and full adder 1. Introduction: The simplest combinational circuit that performs the arithmetic addition of two binary digits is known as half adder. Whereas a full adder is a combinational circuit that performs the arithmetic sum of three input bits and produces a sum output and a carry output. Division Of The Topic: 1. Difference between half adder & full adder. 2. Realization of half adder & full adder covering:
(i) Truth table (ii) K-Map (iii) Designing of Half adder & full adder using basic logic gates
2.
40
3.
Conclusion: Circuit for Half adder & full adders were designed & the verified the circuit by considering few examples of addition. Question/Answer/ Review:
1. Implement the circuit of full adder using half adders. 2. Implement the circuit of half adder using NAND gate only.
4.
Tough
Moderate
Easy
- 34 -

1. 2. 3.
S.NO. Topic: - Half subtractor and Full subtractor 1. Introduction: Half subtractor is a combinational circuit that performs the subtraction of two binary bits. Whereas a full subtractor is a combinational circuit that performs the subtraction involving three bits. Division Of The Topic: 1. Difference between half subtractor and Full subtractor. 2. Realization of half subtractor and Full subtractor covering: Truth table K-Map (iii) Designing of Half subtractor and Full subtractor using basic logic gates 3. Conclusion: Circuit for half subtractor and Full subtractor were designed & the verified the circuit by considering few examples of subtraction. Question/Answer/ Review: 1. Implement the circuit of full subtractor using half subtractors. 2. Implement the circuit of half subtractor using NAND gate only. Level of Difficulty (for faculty): Tough Moderate Easy (i) (ii)
2.
40
4.
- 35 -

1. 2. 3.
: Digital Electronics : 27 : COMBINATIONAL SYSTEMS
S.NO. Topic: - Binary serial and parallel adders 1. Introduction: Parallel adder performs the addition of all the bits of two given no.s (augend and addend) simultaneously. Parallel adder is also known as ripple adder. Whereas in serial adder, the addition operation is carried out bit by bit. Serial adder has simpler circuitory but low speed of operation when compared with parallel adder. Division Of The Topic: 1. Circuit Diagram of Parallel Adder & Serial adder 2. Explanation of these adders with example 3. IC-7483-a 4 bit binary adder & Cascading of ICs(2 7483 ICs) to perform 4 bit addition. 3. Conclusion:
Time Allotted
2.
40
4.
Question/Answer/ Review: Realize the circuit of serial and parallel subtractor. 5
Tough
Moderate
Easy
Year : II Year
- 36 -

1. 2. 3.
S.NO. Topic: - BCD adder and Binary multiplier 1. Introduction: A circuits that adds two BCD digits in parallel and produces a sum digit which is also in BCD.A BCD adder also includes the correction logic circuit in its internal construction. A multiplier performs the multiplication operation. Division Of The Topic: a) BCD Adder 1. Truth Table 2. K-Map 3. Realization of K-Map b) Multiplier 4. Multipliers using partial product addition & shifting and 5. Parallel Multipliers Conclusion: Concept of BCD Adder and Multiplier is studied.
Time Allotted
2.
40
3.
4.
Question/Answer/ Review: Design a binary multiplier that multiplies a 4-bit number B = B3B2B1B0 by a 3 bit number A = A2A1A0 to form the product C = C6C5C4C3C2C1C0.
Tough
Moderate
Easy
Year : II Year
- 37 -

LECTURE PLAN
Date: 15/10/2013
Sem : III Sem
1. 2. 3.
Subject : Digital Electronics Lesson No. Title : 28
: COMBINATIONAL SYSTEMS
S.NO. 1.
Topic: - Multiplexer & Demultiplexer ; Design of logic circuits by Multiplexers

Introduction: - The term multiplex means many into one. A digital multiplexer is a combinational circuit that selects one digital information from several sources and transmits the selected information onto a single output line. A multiplexer is also called a data selector. Demultiplexer (also called as Data distributors) which means many into one. Division Of The Topic: a) Multiplexer i. 1 to 4 Multiplexer ii. 1 to 8 Multiplexer b) Demultiplexer i. 4 to 1 Demultiplexer ii. 8 to 1 Demultiplexer c) Applications of Multiplexer: Data routing, Logic function generator, Control sequence, Parallel to Serial Converter. d) Realisation of higher order multiplexers/demultiplexers using lower order multiplexers/demultiplexers respectively. e) Design of Boolean expressions by multiplexers & vice cersa(using Type 0, Type 1 & Type 2 method). f) Realisation of arithmetic circuits using multiplexers.
Time Allotted
2.
40
3.
4.
Conclusion: The use for multiplexers is cost savings by connecting a multiplexer and a demultiplexer (or demux) together over a single channel (by connecting the multiplexer's single output to the demultiplexer's single input). Multiplexers can also be used as components of programmable logic devices. Question/Answer/ Review:
5 5
Tough
Moderate
Easy
Teaching Aids: Chalk, Black Board, Marker, Projector & PPT Teaching Points: Lecture delivered
Reference Readings: S. Salivahanan, S. Arivazhangan", Vikas publications, Fifteenth Edition, 2008 Year : II Year
- 38 -

1. 2. 3.
S.NO. 1.
Topic: - Decoder: Binary to Gray decoder, BCD to 7-segment

decoder
Time Allotted
Introduction: A decoder can take the form of a multiple-input, multipleoutput logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2n, binary-coded decimal decoders.
2.
Division of the Topic: 1) Binary to Gray Code Decoder.

a) Truth Table b) Solve K-map c) Design the combinational circuit.
2) BCD to 7-segment Decoder

40
3.
Conclusion:
It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. A decoder that contains enable inputs is also known as a decoderdemultiplexer. Thus, we have a 4-to-16 decoder produced by adding a 4th input shared among both decoders, producing 16 outputs.
4.
Question/Answer/ Review:
Design a combinational circuit or decoder that converts BCD number to decimal number.
Tough
Moderate
Easy
Year : II Year
- 39 -

LECTURE PLAN
Sem : III Sem
Date: 19/10/2013
1. 2. 3. S.NO. 1.
Topic: - ; Encoder: Octal to binary, BCD to excess-3 encoder; Diode switching matrix Introduction :- Encoder: In encoders, the number of input lines are lesser than the no. of outputs. And these encoders convert one form of code into another form. Hence, an encoder is a combinational circuit that performs opposite to a decoder. Converter: In converter, the number of input lines is equal to the number of output lines. Diode Switching Matrix:It is an encoder that has been designed using the array matrix of wires. Some of the wires are connected to the diode on the circuit design. Division Of The Topic: 1) Octal to Binary Encoder
2.
40
3.
Conclusion:
An encoder is a device, circuit, transducer, software program, algorithm or person that converts information from one format or code to another, for the purposes of standardization, speed, secrecy, security, or compressions.
4.
Design a combinational circuit/encoder for BCD to excess-3 conversion.
Tough
Moderate
Easy
Year : II Year - 40 -

1. 2. 3.
: Digital Electronics : 31 : SEQUENTIAL SYSTEMS
S.NO. Topic: - Latches & flip-flops 1. Introduction: In digital circuit theory, sequential logic is a type of logic
circuit whose output depends not only on the present value of its input signals but on the past history of its inputs. This is in contrast to combinational logic, whose output is a function of only the present input. Flip flop is a single bit storage device & it is a building block of sequential circuit.
Time Allotted
2.
Division Of The Topic:

1. 2. 3. 4. Introduction to Sequential circuits. Difference between Sequential & Combinational circuits. Difference between flip-flops and latches. Working principle of flip-flops( Bistable multivibrator).
40
3.
Conclusion:
Sequential logic is used to construct finite state machines, a basic building block in all digital circuitry, as well as memory circuits and other devices.
4.
Q. Define Sequential circuit . Write two properties of any sequential circuit. Q.Tabulate the difference between combinational circuits and sequential circuits.
Tough
Moderate
Easy
Year : II Year
- 41 -

1. 2. 3.
S.NO. Topic: - R-S & D- flip flop. 1. Introduction: A flip-flop or latch is a circuit that has two stable
states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.
Time Allotted
2.
Division Of The Topic:

1. 2. 3. 4. 5. 6. Logic circuit diagram Truth table Ps/ns state table Exitatation table or characteristic table Characteristic equation State diagram
40
3.
Conclusion: R-S flip- flop is fundamental flip-flop that can be implement in every flip-flop. D flip-flop is the delay flip-flop used where we need some delay in any sequential cuircuit. Question/Answer/ Review: Draw and explain the logic diagram of R-S and D flip flop with their characteristic equation and state diagram.
4.
Tough
Moderate
Easy
Year : II Year
- 42 -

1. 2. 3.
S.NO. Topic: - J-K, Master Slave flip- flops 1. Introduction: The J-K flip flop avoid the problem of forbidden state that occur in R-S flip flop. J-K flip-flop are connected in feedback patterns. Master-slave flip-flop are used to remove race around condition occur in J-K flip-flop.in this two J-K flip-flop are connected back to back or series. Division Of The Topic:
1. 2. 3. 4. 5. 6. Logic circuit diagram Truth table Ps/ns state table Exitatation table or characteristic table Characteristic equation State diagram
Time Allotted
2.
40
3.
Conclusion: J-K flip-flop used to design different types of counters. Master-slave flip-flop are used to remove race around condition. Question/Answer/ Review: Q1.Draw and explain the logic diagram of clocked J-K flip-flop with their characteristic equation and state diagram. Q2.Draw and explain the logic diagram of Master-slave flip-flop
4.
Tough
Moderate
Easy
Year : II Year
- 43 -

1. 2. 3.
S.NO. 1.
Topic: - Conversions of flip-flops, Counters : Asynchronous (ripple), synchronous and synchronous decade counter Introduction: To implement any type of flip-flops we first draw logic diagram then exitatation table or characteristic table Characteristic equation using k- map. Division Of The Topic: 1. 2. 3. 4. 5. Logic circuit diagram Ps/ns state table Exitatation table or characteristic table Characteristic equation using k- map Final logic diagram of desire circuit.
Time Allotted
2.
40
3.
Conclusion: We can implement any type of flip-flop using Conversions of flipflops. In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Question/Answer/ Review: Q1. Design T flip-flop using J-K and S-R flip-flop. Q2. Design D flip-flop using S-R flip-flop. Q3. Design BCD counter. Tough Moderate Easy
4.
Year : II Year
- 44 -

1. 2. 3.
S.NO. 1.
Topic: - Modulus counter, skipping state counter, counter design. Ring counter, Counter applications. Introduction: The number of unique states that a counter may have
before the sequence repeats itself is the modulus of the counter. Example, Modulus 10 would have the counter with states 0-9 and then reset to zero. A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the state one while others are in their zero states.
Time Allotted
2.
Discusion Of The Topic:

1.Logic Diagram 2.Truth table 3. Working
40
3.
Conclusion: Modulus counter are used where we need fixed no. of state. Skipping counter are used where we want to skip some particular state which is not required. Question/Answer/ Review: Q1. Design mod-10 counter. Q2. Design skipping counter. Tough Moderate Easy
4.

LECTURE PLAN Sem : III Sem - 45 -
Date: 8,10/11/2013
1. 2. 3.
: Digital Electronics : 36 & 37 : SEQUENTIAL SYSTEMS
S.NO. Topic: - Registers: buffer register, shift register. 1. Introduction: Registers are normally measured by the number of bits they can hold, for example, an "8-bit register" or a "32-bit register".In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain. Discusion Of The Topic: 1.logic diagram 2.Truth table 3. working
Time Allotted
2.
40
3.
Conclusion:
One of the most common uses of a shift register is to convert between serial and parallel interfaces. Shift registers can be used as simple delay circuits.
4.
Question/Answer/ Review: Q1. Explain the working of parallel input serial output shift register. Q2. Explain the working of buffer register
Tough
Moderate
Easy
Year : II Year
- 46 -
Global Jaipur
Institute Of Technology,
ASSIGNMENT SHEET-I Digital electronics
Sem : III Sem
1. 2. 3.
: : :
Date: 29/8/12 Time:
This assignment sheet corresponds to Unit No. I (Number Systems, Basic Logic Gates & Boolean Algebra)
Q1(a). Perform BCD Addition on (4)10 & (7)10. (b). (247.36)8 = ( ? )2 = ( ? )16 Q2. Prove: [(AB) + (A) + (AB)] = 0.
- 47 -
Year : II Year ASSIGNMENT SHEET-II Digital electronics

Sem : III Sem
1. 2. 3.
: : :
Rishabh Sharma Asst. Professor Electronics & Communication Engineering Date: 17/09/12 Time:
This assignment sheet corresponds to Unit No.III (Minimization techniques) Q6. Convert the following Boolean function into canonical SOP form (a) F(A,B,C,D)=A+BC+ABD+ABCD (b) F(W,X,Y,Z)= XZ+WXY+WXZ+WXZ
Q7. Use multiple function minimization to obtain the simplest set of sop expression for p sub cubes of following function and explain the combined complexity in total literal terms F1 (A,B,C)= F2 (A,B,C)= F3 (A,B,C)=
- 48 -
Year : II Year ASSIGNMENT SHEET-III Digital electronics Sem : III Sem

1. 2. 3.
: : :
This assignment sheet corresponds to Unit No.IV (Combinational Systems)
Q8. Design a combinational circuit to generate a parity bit for digit coded in BCD code. The circuit should also have an additional output that produces an error signal of no BCD input to the circuit. Realise the circuit using NAND-NAND logic. Q9. Write down the short note on diode switching matrix. Q10. Design a combinational circuit which generates output if4 bit input contains even numbers otherwise the output is zero.
- 49 -
Year : II Year ASSIGNMENT SHEET-IV Digital electronics

Sem : III Sem
1. 2. 3.
: : :
Rishabh Sharma Asst. Professor Electronics & Communication Engineering Date :3/11/2013
This assignment sheet corresponds to Unit No. V (Sequential circuits) Q11. Explain the steps involved in realization of one flip flop from another flip flop. Q12. What is shift register? Explain its types and also explain the ring counter. Q13. Design a sequential circuit having one input and one output using the J K flip flop. State diagram is given below 0/0 001 1/1 1/0 100 0/0 0/0 1/1 1/1 010 0/0 01 1 0/1
00 0
- 50 -
Q14. Give the pulse train sequence which will be generated by shift register circuit shown in figure. Assume initial state of circuit is 1111.
Cp
Serial in parallel out Shift register D3 D2 D1 D0
Q15. What is counter explain synchronous and asynchronous counter and also explain modulus counter and design MOD 5 counter.
- 51 -
Year : II Year ASSIGNMENT SHEET-V Digital electronics

Sem : III Sem
1. 2. 3.
: : :
Rishabh Sharma Asst. Professor Electronics & Communication Engineering Date 12/11/2013.
This assignment sheet corresponds to Unit No. II (Digital Logic Gates & Caharacteristics) Q3. Explain the working of CMOS NOT gate and NAND gate. Q4. Describe RTL and DTL logic families and explain following properties of digital logic families (a) Figure of merit (b) Noise immunity (c) Fan in and fan out (d) Saturation delay time Q5. Explain the TTL logic family in detail and also compare TTL logic family with MOS family.
- 52 -
Year : II Year Unit Test I Digital electronics

Sem : III Sem
1. 2. 3.
: : :
Date: 29/08/12 Time:
This Unit Test corresponds to Unit No. I (Number Systems, Basic Logic Gates & Boolean Algebra)
Q1(a). Perform BCD Addition on (4)10 & (7)10. (b). (247.36)8 = ( ? )2 = ( ? )16 Q2. Prove: [(AB) + (A) + (AB)] = 0.
- 53 -
Year : II Year Unit Test II Digital electronics Sem : III Sem

1. 2. 3.
: : :
This Unit Test corresponds to Unit No.III (Minimization techniques) Q1. Solve using K-map: F(A,B,C,D) = m (1,5,6,12,13,14) + d (2,4) Q2. Implement the following expression using NAND gate only: Y = AD + ADB + ADC
- 54 -
Year : II Year Unit Test III Digital electronics Rishabh Sharma Asst. Professor Electronics & Communication Engineering Date: 05/10/12 Time: This Unit Test corresponds to Unit No.IV (Combinational Systems) Sem : III Sem

1. 2. 3.
: : :
Q1. Implement the following Boolean function using 8:1 MUX: F(A,B,C,D) = ABCD + ABCD + ABCD + ABCD + ABCD. Q2. Implement the full subtarctor using 4:1 MUX. Q3. Design full adder using 3:8 line decoder. Q4. Impelemnt the following gates with 3 input MUX, assuming that implemented & uncomplemented variables are available. (a) 3 input EX-OR gate. (b) 3 input EX-NOR gate.
- 55 -
Year : II Year Unit Test - IV Global Institute Of Technology, Jaipur

Sem : III Sem Rishabh Sharma Asst. Professor Electronics & Communication Engineering Date :3/11/2013
1. 2. 3.
: : :
This Unit Test corresponds to Unit No. V (Sequential circuits) Q1. Draw the circuit diagram of JK F/F. Also define Race-Around Condition. Realize JK F/F using SR F/F. Q2. Design a Gray code counter.
- 56 -
Year : II Year Unit Test - V Global Institute Of Technology, Jaipur

Sem : III Sem Rishabh Sharma Asst. Professor Electronics & Communication Engineering Date :11/11/2013
1. 2. 3.
: : :
This Unit Test corresponds to Unit No. II (Digital Logic Gates & Caharacteristics) Q1. What are the different types of logic families? Give a comparison of different families with regards to speed, power dissipation, noise margin, fan-out and fan-in. Q2. Define the characteristics of Digital ICs.
Year : II Year Question Bank - 57 -
Digital Electronics Global Of Technology, Jaipur

Institute
Sem : III Sem
1. 2. 3.
: : :
UNIT I Number System: Q1. Perform the following functions:(i) (56.1A)H = X8 = X2 = X10 = XG
(ii) Add the given numbers in binary:

(a) (25)10 + (10)10 (b) (10.5)10 + (7.5)10
(iii) Perform addition on the given numbers using 2s complement system:

(a) (b) (c) (d) (29)10 + (19)10 (39)10 + (-22)10 (-47)10 + (29)10 (-32)10 + (-44)10
(iv) Perform subtraction on the given numbers using 2s complement system: (a) (28)10 - (19)10 (b) (39)10 - (-21)10 (c) (19)10 - (-43)10 (d) (-57)10 - (-33)10
(v) Perform BCD subtraction on given numbers:

(a) (835)10 - (274)10 (b) (274)10 - (835)10 (vi) Write short notes on codes alongwith their properties. (vii) Subtract the given numbers: (a) (32)8 (15)8 (b) (4A.15)16 (11.27)16
(viii) Construct a seven bit hamming code with four bit data 1101. (ix) A seven bit hamming code is received as 1000110. Is the received code correct? If not, what is the correct code?
- 58 -
(x) Perform the given operation:

(a) Add (168)10 & (234)10 using Xs-3 code. (b) Subtract (168)10 from (234)10 using Xs-3 code. (xi) Find the value of base/radix for a given number system: (a) (1000)x = [(11)2]3 (b) (41/3) = 13.
Boolean algebra: Q2. Prove the following:

(a) *(AB)+ (A) + (AB)+ = 0. (b) A*B+C,AB + AC-+=AB. (c) *(A+B)(A)(A+B)+=1.
Q3. Simplify the following expressions using Boolean laws:

(a) Y = f (A, B, C) = m (0, 2, 4, 6, 7). Realize the circuit using Nand Gate only. Q4. Prove consensus thorem. Take an example or Boolean expression using consensus theorm. Q5. Impelment all the basic logic gates & derived logic gates using universal gates(NAND & NOR) only. Q6. Realize the following expressions: (a) Y= AD + AD(B + C) using NAND gate only. (b) Y= AD + AD(B + C) using NOR gate only.
Unit No. II (Logic families) Q1. Define the following IC parameters: a) Voltage & current parameters b) Fan-in & Fan-out c) Noise Margin d) Propagation Delay e) Power dissipation f) Figure of merit g) Operating Temperature Q2. Draw and explain the working of TTL Nand Gate for the following three configurations: a) Totem Pole output b) Open Collector output alongwith their applications c) Tri State Device Q3. Draw & explain CMOS as a) Inverter/ Not Gate - 59 -
b) Nand Gate c) Nor Gate Also give reason that why the CMOS network is known as Ratio less Circuit. Q4. Compare the characteristics of RTL, ECL, TTL, ECL & CMOS logic families. Describe the interfacing of CMOS & TTL logic families.
Unit No.III (Minimization techniques) Q.1 Solve the following expressions using K- map:(a) Y = BD + ABC + ACD + ACD + ABC. (b) f (A,B,C,D) = m (1, 5, 6, 12, 13, 14) + d(2, 4). (c) Y = m (1, 5, 7, 13, 14, 15, 17, 18, 21, 22, 25, 29) + d (6, 9, 19, 23, 30). (d) f (A,B,C,D) = M (0, 2, 5, 7, 8, 10) + d(2, 4).Implement the simplified function using NAND/NAND form. Q2. Minimize using Quine McCluskey Method/ Tabular Method: (a) Y= f (A, B, C, D) = m (0, 1, 4, 5, 9, 11, 13, 15). (b) Y = f(A, B, C, D) = m (0, 1, 4, 5, 10, 11, 14, 15). (c) Y= f (A, B, C, D) = m (0, 1, 4, 8, 14, 15) + d (5, 9, 13). (d) Y = f(A, B, C, D) = M (4, 5, 6, 9, 11, 12, 13, 14). Q3. Explain positive, negative and mixed logics. Q4. Convert the following given SOP expression into POS form:(a) Y = m (0, 1, 3, 7). (b)Y = m (4, 6, 8, 10, 11, 12, 14, 15).
Unit No. IV (Combinational Systems) Q1. Explain the working of 4 bit carry look ahead adder. What are its advantages? Q2. Implement the following mentioned four Boolean function using three half adder circuits: D=A B C F = ABC+ABC G = ABC+ (A+B) C H = ABC Q3. Design a parity generator for
(i) (ii) Even parity Odd parity
Use gates for realization of the circuit. Also explain the working of parity checker circuit.
Q4. Implement the following functions using MUX: - 60 -
(i) (ii)
F = m (0, 1, 2, 3, 4, 10, 11, 14, 15) using MUX having 3 select line. F(A, B, C, D) = ABCD + ABCD + ABCD + ABCD + ABCD
Q5. What is the difference between decoder & demultiplexer. Construct a 5 x 32 decoder using four 3 x 8 decoder with enable and a 2 x 4 decoder. Draw a block diagram. Q6. Design a combinational circuit with 4 inputs that represents a decimal digit in BCD and 4 outputs that produces 9s compliment of the input digit. The unused combination can be treated as dont care conditions.
Unit No. V (Sequential circuits) Q1. Differentiate between: 1) Bistable circuit, Latch & flip flop. 2) Synchronous and asynchronous sequential circuits (Also mention the drawbacks of Asynchronous counter). Q2. What is Race Around condition in JK flip-flop & how it can be eliminated? Q3. Draw a logic diagram of Clocked SR flip-flop and obtain its characterstic equation. Q4. Draw & explain the working of M/S (Master Slave) flip flop. Also draw the circuit of M/S using NAND gates only. Q5. Realize JK flip flop using SR, D & T flip flops. Q6. How many flip flops are required to make a shift register using to store the following data:
(i) (ii) (25)10 (A6)16
Q7. Draw & explain the following registers:

(i) (ii) (iii) Serial in Parallel out Parallel in parallel out Johnson Counter
Q8. Write short note on the application of Flip flops & shift registers. Q9. Design a 3 bit synchronous UP/DOWN Counter using T flip flop. Q10. Draw the diagram of a 4 bit binary ripple counter using flip flops that triggers on the positive edge.
- 61 -
Q11. Determine the next state for each of the six unused states in the BCD ripple counter.Is the counter self starting? Q12. Design the following counters:
1) Counter which goes through the states 0, 2, 4, 5, 0 using T flip flops. 2) Mod- 5 Synchronous Counter using JK flip flop. 3) 3-bit gray code Synchronous counter.
Year : II Year Model Question Paper Global Institute Of Technology, Jaipur

Subject: Digital Electronics
Sem : III Sem
UNIT I Q1. (i) Perform the following conversion:(iii) (2598.675)10 = X16 (iv) (v) (vi) (vii) (56.1A)H = X8 (110110111)2 = X8 = X10 (7777)8 = X10 (47.23)10 = X8 - 62 -
(viii)
(2035)8 = X16
(ix) (1001011.10101)2 = X8 = X10 (x) (113.15)8 = X10 (ii) Implement the EX-OR and EX-NOR gates using NAND gates and NOR Gates. (iii) Perform the following operation (a ) (756)8 (637)8 + (725)16. OR (i) Subtract the following:(b) (45600)8 (13271)8 (c) (10110101)2 (10101010)2 Using 2s complement (d) (429)10 (546)10 using BCD Subtraction. (e) (212)10 (169)10 using 1s complement. (f) (33)10 (57)10 using 2s complement.
(g) (68)10 (31)10 using BCD Subtraction. (h) 01100 -00011 using 2s complement
(i) 3570-2100 using 9s complement
(ii) Implement the following expression:(a) Y = (A+BC) (B+C'A) using NAND gates only
(b) f (A,B,C,D) = (A+B+C)(A+C)(C+D) using NOR gates only (c) Y = A'D + AD'(B + C') using NAND gates only
UNIT II
Q2. (i) Define the following1) 2) 3) 4) Fan-in & Fan-out Noise Margin Propagation Delay RTL
- 63 -
OR
(ii)
Draw and explain the working of DTL.
(iii) Write short note on CMOS families
Unit III
Q3. (i) Minimize the Boolean expression using K- map:(a) f(A,B,C,D) = m (0,4,6,7,8,9,10,13) (b) f =m (0,2,3,4,6,8,10,11,12,13,14) + d(1,15) (c) f = m (0,2,6,10,11,12,13) + d(3,4,5,14,15) (ii) Express the following Boolean function in the product of maxterm:F = xy + x'z OR
(i) Prove that:(a) (b) [AB'(C + BD) + A'B']C = B'C (AB + AC)' + A'B'C = A'+B'C'
(ii) Minimize the Boolean expression using laws of Boolean algebra: AB'C + B + BD' + ABD' + A'C
Unit IV
Q4. (i) Write short notes on shift registers. (ii) Implement the following function with a MUX using type-1 methodF(A,B,C,D) = m (0,1,3,4,8,9,15) OR
(i) Write short note on1) Level Triggering 2) Edge Triggering (ii) Design a full Adder using two half Adders. - 64 -
(iii) Design BCD to Excess-3 encoder.
UNIT V
5. (i) Realize the D flip flop using JK flip-flop.
(ii) Differentiate between synchronous and asynchronous sequential circuits. (iii) what is Race Around condition in JK flip-flop?
OR
(i) Differentiate b/w a) Combinational & Sequential Circuits. b) Flip-flop and Latch. (ii) Draw a logic diagram of Clocked SR flip-flop and obtain its characterstic equation.
Year : II Year MID TERM I Question Paper Global Institute Of Technology, Jaipur
Sem : III Sem
Duration: 1 Hr.
Maximum Marks:20
All questions carry equal marks. Duration: 1 Hr. Unit -1

Q1(a). A information code of 4 bit 1010 is transmitted using 7 bit hamming codes & received as 1011110 .locate the parity bit in transmitted code also write the algorithm for error detection & correction . [RTUECE -2011] 6M Q1(b).What number of range represented in : [RTU2008] (i) 8 bit sign magnitude form (ii) 8 bit unsigned magnitude form (iii) 8 bit BCD (iv) 8 bit 2s complement representation 2M
Maximum Marks: 20
Unit -3
Q.2 Minimize the following expression using variable enter Map [3 variables]
- 65 -
F=(ABCD+ABCD+ABCD+ABCD+ABCD) Also realize the minimum function using universal logic . [RTU ECE-2012] OR Q.2 Minimize the following switching function using Quine Mc Cluskey method f(A,B,C,D)= (1,3,4,5,9,10,11)+d(6,8 )[RTU2008]
8M
8M
UNIT -4
Q.3 Realize Full Adder using Half Adder & realize it using universal logic. [RTU2008] OR Q.3 Explain 4 bit parallel Adder / Subtractor 4M 4M
Year : II Year MID TERM II Question Paper Global Institute Of Technology, Jaipur
Sem : III Sem
Duration: 1 Hr.
Maximum Marks:20
Note: Attempt all the Question UNIT-4 Q.1 Design a BCD to Seven segment display (only K- map with functions)? OR Q.1 Design a binary to octal decoder? 8 8
Q.2 Implement 16:1 order MUX using 4:1 MUX?
UNIT-5 Q.3 Q.3 Discuss race around problem in J K flip flop & its solution (triggering method)? 8 OR Discuss race around problem in J K flip flop & its solution (Master Slave configuration)? 8
Signature of Head of the Department
Signature of Faculty
- 66 -
Date
Date
Year : II Year

Performance of Students in Mid Term Exams
Sem : III Sem
Max. Marks:- 20 S. No. Roll No.

12EGJEC001 12EGJEC002 12EGJEC003 12EGJEC004 12EGJEC005 12EGJEC006 12EGJEC007 12EGJEC008 12EGJEC009 12EGJEC010 12EGJEC011 12EGJEC012
Student Name ABHAY SINGH DHAKAR ABHISHEK BHARDWAJ AKANKSHA SHARMA ALEKH KUMAR AMAN KUMAR NAYAK AMAN MATHUR AMAN SINGHVI AMIT KUMAR AMIT SIKHWAL ANAND KUMAR ANIL KUMAR SHARMA ANJANA BALAGOPALAN - 67 -
1ST Term 13 9 16 2 15 9 4 14 10 5 9 17
2ND Term
Average/ best one
12EGJEC013 12EGJEC014 12EGJEC015 12EGJEC016 12EGJEC017 12EGJEC018 12EGJEC019 12EGJEC020 12EGJEC021 12EGJEC022 12EGJEC023 12EGJEC024 12EGJEC025 12EGJEC026 12EGJEC027 12EGJEC028 12EGJEC029 12EGJEC030 12EGJEC031 12EGJEC032 12EGJEC033 12EGJEC034 12EGJEC035 12EGJEC036 12EGJEC037 12EGJEC038 12EGJEC039 12EGJEC040 12EGJEC041 12EGJEC042 12EGJEC043 12EGJEC044
ANKIT ANKIT BANSAL ANKIT GUPTA ANKITA AGARWAL ANKITA SHUKLA ANKUSH MANDA ANSHIKA ANSHU SAHU ANURAG MALVIYA APOORV GUPTA ASHUTOSH GUPTA ASTHA DANGI AYUSHI SAXENA BALRAM YOGI BHAVYA KUMARI CHETAN SINGH KARMSOT CHIRAG KANTHER DEEKSHA GUPTA DEEPAK GOYAL DEEPAK JANGID DEEPAK KANKAR DEEPANK CHAUDHARY DEEPESH YADAV DEVILAL DHAKA DHARMENDRA KUMAR DILIP NIRWAN DIPENDRA SINGH DIVYA LADHA DIVYBHAN SINGH SISODIA GAURAV CHAWLA GAURAV VIJAY GAUTAM BHATHEJA - 68 -
AB 17 14 AB 15 8 15 AB 10 10 0 15 5 10 12 8 8 AB 10 4 13 16 8 AB 3 3 4 10 11 8 6 8
12EGJEC045 12EGJEC046 12EGJEC047 12EGJEC048 12EGJEC049 12EGJEC050 12EGJEC051 12EGJEC052 12EGJEC053 12EGJEC054 12EGJEC055 12EGJEC056 12EGJEC057 12EGJEC058 12EGJEC059 12EGJEC060 12EGJEC061 12EGJEC062 12EGJEC063
HARSH SHARMA HARSHITA AGRAWAL HRIDYANAND JATIN KUMAR KHATRI KAPIL SINGHAL KARTIKEY TIWARI KHYATI KABRA KULDEEP KULDEEP KACHAWA KUMAR MANDEEP KUMARI ANAMIKA KUNAL SWAMI MADHURIMA MITTAL MAHAK SINGHVI MAITRAIYEE GAUTAM MANEESH MAKHIJA MANISH JANGID MAYANK GOTHWAL MOHIT KUMAR SHARMA
8 10 AB 3 8 10 16 8 AB AB 11 8 8 10 16 AB 13 8 2
Signature of Faculty Date :-
Year :II Global Institute of Technology, Jaipur (Approved by AICTE and Affiliated to RTU, Kota) PERFORMANCE OF ASSIGNMENT Digital Elelctronics Sem :III
- 69 -
S. No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Grades Roll No. Student Name #1

12EGJEC001 12EGJEC002 12EGJEC003 12EGJEC004 12EGJEC005 12EGJEC006 12EGJEC007 12EGJEC008 12EGJEC009 12EGJEC010 12EGJEC011 12EGJEC012 12EGJEC013 12EGJEC014 12EGJEC015 12EGJEC016 12EGJEC017 12EGJEC018 12EGJEC019 12EGJEC020 12EGJEC021 12EGJEC022 12EGJEC023 12EGJEC024 12EGJEC025 12EGJEC026 12EGJEC027 12EGJEC028
Average #2 A B B A B B A A A+ A B A B B B A A A A A A A A B A A A A+ #3 A B B A B B A A A+ A B A B B A A A B A A A A A B A A A A+ #4 A A B A B B A A A+ A B A A B B A A B A A A A A A A B A B #5 A A A A B B B A A+ A B A A A A A A A A A A A A A A A A A+ A B B A B B A A A A B A A B B A A A A A A A A B A A A A A B A A A B A A A A B A A A B A A A A A A A A B A A A A+
ABHAY SINGH DHAKAR ABHISHEK BHARDWAJ AKANKSHA SHARMA ALEKH KUMAR AMAN KUMAR NAYAK AMAN MATHUR AMAN SINGHVI AMIT KUMAR AMIT SIKHWAL ANAND KUMAR ANIL KUMAR SHARMA ANJANA BALAGOPALAN ANKIT ANKIT BANSAL ANKIT GUPTA ANKITA AGARWAL ANKITA SHUKLA ANKUSH MANDA ANSHIKA ANSHU SAHU ANURAG MALVIYA APOORV GUPTA ASHUTOSH GUPTA ASTHA DANGI AYUSHI SAXENA BALRAM YOGI BHAVYA KUMARI CHETAN SINGH KARMSOT - 70 -
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
12EGJEC029 12EGJEC030 12EGJEC031 12EGJEC032 12EGJEC033 12EGJEC034 12EGJEC035 12EGJEC036 12EGJEC037 12EGJEC038 12EGJEC039 12EGJEC040 12EGJEC041 12EGJEC042 12EGJEC043 12EGJEC044 12EGJEC045 12EGJEC046 12EGJEC047 12EGJEC048 12EGJEC049 12EGJEC050 12EGJEC051 12EGJEC052 12EGJEC053 12EGJEC054 12EGJEC055 12EGJEC056 12EGJEC057 12EGJEC058 12EGJEC059
CHIRAG KANTHER DEEKSHA GUPTA DEEPAK GOYAL DEEPAK JANGID DEEPAK KANKAR DEEPANK CHAUDHARY DEEPESH YADAV DEVILAL DHAKA DHARMENDRA KUMAR DILIP NIRWAN DIPENDRA SINGH DIVYA LADHA DIVYBHAN SINGH SISODIA GAURAV CHAWLA GAURAV VIJAY GAUTAM BHATHEJA HARSH SHARMA HARSHITA AGRAWAL HRIDYANAND JATIN KUMAR KHATRI KAPIL SINGHAL KARTIKEY TIWARI KHYATI KABRA KULDEEP KULDEEP KACHAWA KUMAR MANDEEP KUMARI ANAMIKA KUNAL SWAMI MADHURIMA MITTAL MAHAK SINGHVI MAITRAIYEE GAUTAM - 71 -
A A A A A A A B B A B A A A A A A A A -B B B A A B A+ A+ A A A
A B A A A A B B B A B A B A A B A A A B A A A A B B A+ A A A
A B A A A A B B B A A A B A A B A A A B A A A B A A A+ A A A
A A B B A A B B A A B A A A A A A B A B B A A A A A A+ A A A
A A A A A A A B A A A A A A A A A A A B B A A A A A A A A A
A A A A A A B B B A B A A A A A A A A B B A A A A A A+ A A A
60 61 62
12EGJEC060 12EGJEC061 12EGJEC062 12EGJEC063
MANEESH MAKHIJA MANISH JANGID MAYANK GOTHWAL MOHIT KUMAR SHARMA
B B B
A B A
A A A
A A A
A A A
A A A
- 72 -
Year :II Global Institute of Technology, Jaipur (Approved by AICTE and Affiliated to RTU, Kota) PERFORMANCE OF UNIT TEST Digital Electronics Sem :III
S. No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Grades Roll No. Student Name #1

12EGJEC001 12EGJEC002 12EGJEC003 12EGJEC004 12EGJEC005 12EGJEC006 12EGJEC007 12EGJEC008 12EGJEC009 12EGJEC010 12EGJEC011 12EGJEC012 12EGJEC013 12EGJEC014 12EGJEC015 12EGJEC016 12EGJEC017 12EGJEC018 12EGJEC019 12EGJEC020 12EGJEC021 12EGJEC022 12EGJEC023
Average #2 A B B A B B A A A A B A B B B A A A A A B A A #3 A B B A B B A A A A B A B B A A A B A A B A A #4 A B B A B B A A A A B A B B B B A B A A B A A #5 A B A A B B B A A A B A B A A A A A A A B A A A B B A B B A A A A B A B B B A A A A A B A A A B A A A B A A A A B A A A B A A A A A A A A
ABHAY SINGH DHAKAR ABHISHEK BHARDWAJ AKANKSHA SHARMA ALEKH KUMAR AMAN KUMAR NAYAK AMAN MATHUR AMAN SINGHVI AMIT KUMAR AMIT SIKHWAL ANAND KUMAR ANIL KUMAR SHARMA ANJANA BALAGOPALAN ANKIT ANKIT BANSAL ANKIT GUPTA ANKITA AGARWAL ANKITA SHUKLA ANKUSH MANDA ANSHIKA ANSHU SAHU ANURAG MALVIYA APOORV GUPTA ASHUTOSH GUPTA - 73 -
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
12EGJEC024 12EGJEC025 12EGJEC026 12EGJEC027 12EGJEC028 12EGJEC029 12EGJEC030 12EGJEC031 12EGJEC032 12EGJEC033 12EGJEC034 12EGJEC035 12EGJEC036 12EGJEC037 12EGJEC038 12EGJEC039 12EGJEC040 12EGJEC041 12EGJEC042 12EGJEC043 12EGJEC044 12EGJEC045 12EGJEC046 12EGJEC047 12EGJEC048 12EGJEC049 12EGJEC050 12EGJEC051 12EGJEC052 12EGJEC053 12EGJEC054
ASTHA DANGI AYUSHI SAXENA BALRAM YOGI BHAVYA KUMARI CHETAN SINGH KARMSOT CHIRAG KANTHER DEEKSHA GUPTA DEEPAK GOYAL DEEPAK JANGID DEEPAK KANKAR DEEPANK CHAUDHARY DEEPESH YADAV DEVILAL DHAKA DHARMENDRA KUMAR DILIP NIRWAN DIPENDRA SINGH DIVYA LADHA DIVYBHAN SINGH SISODIA GAURAV CHAWLA GAURAV VIJAY GAUTAM BHATHEJA HARSH SHARMA HARSHITA AGRAWAL HRIDYANAND JATIN KUMAR KHATRI KAPIL SINGHAL KARTIKEY TIWARI KHYATI KABRA KULDEEP KULDEEP KACHAWA KUMAR MANDEEP - 74 -
B A A A A A A A A A A A B B A B A A A A A A A A -B B B A A B
B A A A A A B A A A A B B B A B A B A A B A A A B A A A A B
B A A A A A B A A A A B B B A A A B A A B A A A B A A A B A
A A B A A+ A A B B A A B B A A B A A A A A A B A B B A A A A
A A A A A+ A A A A A A A B A A A A A A A A A A A B B A A A A
B A A A A A A A A A A B B B A B A A A A A A A A B B A A A A
55 56 57 58 59 60 61 62 63
12EGJEC055 12EGJEC056 12EGJEC057 12EGJEC058 12EGJEC059 12EGJEC060 12EGJEC061 12EGJEC062 12EGJEC063
KUMARI ANAMIKA KUNAL SWAMI MADHURIMA MITTAL MAHAK SINGHVI MAITRAIYEE GAUTAM MANEESH MAKHIJA MANISH JANGID MAYANK GOTHWAL MOHIT KUMAR SHARMA
A+ A+ A A A B B B A
B A+ A A+ A A B A B
A A+ B A A A A A B
A A+ A A A A B A A
A A+ B A+ A A B A A
A A+ A A A A B A A
- 75 -

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Year : II COURSE DESCRIPTION Global Institute Technology, Jaipur

(Approved by AICTE and Affiliated to RTU, Kota)

Name of the Faculty Designation Department

External Marks: 80 Internal Marks: 20 Total Marks: 100

1. Program Educational Objective (PEO):

2. Program Outcomes (PO):

4. Course Objective contribution to Programme Outcomes:

logic. Positive, negative and mixed logic. Logic gate conversion.

8. Important Topics Covered:

10. Topics beyond the syllabus:

11. Interaction Methods:

12. Course outcomes:

13. Additional Seminar/Workshop/Industrial Tour:

14. Assessment of Outcomes:

Name of the Faculty Designation Department

Rishabh Sharma Asst. Professor Electronics & Communication Engineering

I 7:50 -8:45 M-III (RM)

II 8:45 -9:40 SOFT SKILLS

LUNCH 12:25 1:05

VI 1:05 -2:00 DSA (NJ)

EPM-R.C. (SW) EPM (SW) EPM (SW)

DSA (NJ) M-III (RM)

CAS - R.C. (VR) DE -R.C. (RS)

I 7:50 -8:45 M-III (RM)

II 8:45 -9:40 SOFT SKILLS

LUNCH 12:25 1:05

EPM-R.C. (SW) EPM (SW) EPM (SW)

Sem : III Sem

Name of the Faculty Designation Department

: Rishabh Sharma : Asst. Professor : Electronics & Communication Engineering

The Schedule for the Course / Subject is:

Remedial class ASSIGNMENT-1 & CLASS TEST-1

Remedial class ASSIGNMENT-2 & CLASS TEST-2 PPT-1 ON K MAP

19/9/2013 1/10/2013 5/10/2013 9/10/2013 18/9/2013 10/10/2013 12/10/2013 15/10/2013

16/10/2013 16/10/2013 17/10/2013 17/10/2013 30/10/2013 15/10/2013 16/10/2013 16/10/2013 17/10/2013

Remedial class ASSIGNMENT-3 & CLASS TEST-3

17/10/2013 30/10/2013 30/10/2013 31/10/2013 31/10/2013 31/10/2013

Remedial class ASSIGNMENT-4 & CLASS TEST-4

2/11/2013 5/11/2013 6/11/2013 7/11/2013 8/11/2013 10/11/2013 12/11/2013

Remedial class ASSIGNMENT-5 & CLASS TEST-5 PPT-2 ON logic families

Year : II Year COURSE SCHEDULE Global Institute Of Technology, Jaipur

Sem : III Sem

Name of the Faculty Designation Department Date

Signature of Faculty Date

UNIT - II Rishabh Sharma Asst. Professor

Sem : III Sem

Name of the Faculty Designation Department Date

Digital IC Terminology, Characteristics of Digital Ics BJT, RTL, DCTL, RCTL

DTL & Modified DTL, HTL, IIL

Signature of Faculty Date

Year : II Year COURSE SCHEDULE Global Institute Of Technology, Jaipur

(Unit Wise) UNIT - III Sem : III Sem

Name of the Faculty Designation Department Date No. of Periods

Simplification of logic functions with K-map.

Incomplete specified functions. Variable mapping.

Quinn-Mc Klusky minimization techniques & problems based on this topic

Signature of Faculty Date

Year : II Year COURSE SCHEDULE (Unit Wise) UNIT - IV

Global Institute of Technology, Jaipur

Sem : III Sem

Name of the Faculty Designation Department Date

Signature of Faculty Date

Global Institute Of Technology, Jaipur

Sem : III Sem