Lecture 5, Transistor matching and good

layout techniques
26-Mar-13
Lecture 5, Transistor matching and good
layout techniques, http://avlsi.ini.uzh.ch 1
Transistor mismatch & Layout techniques
1. Transistor mismatch its causes
and how to estimate its magnitude
2. Layout techniques for good
matching
3. Layout techniques to minimize
parasitic effects
Neuromorphic Engineering 2
Spring
Delbruck/Indiveri/Liu
Part 1: Device Matching
(especially transistor matching)
0 0.5 1
10
-15
10
-10
10
-5
gate voltage (V)
d
r
a
i
n

c
u
r
r
e
n
t

(
A
)
1 transistor
The hard problem transistor mismatch
1. Transistor gain and
exponential I-V
relationship are very
useful
0 0.5 1
10
-15
10
-10
10
-5
gate voltage (V)
d
r
a
i
n

c
u
r
r
e
n
t

(
A
)
300 transistors
The hard problem transistor mismatch
2. But - transistor current
matching is terrible
Mead &Hoeneison, 1972
3. But capacitors depend on tightly-controlled
oxide and can match 100x better
1. Transistor gain and
exponential I-V
relationship are very
useful
Transistor matching data
From Brad Minch, formerly Cornell, now at Olin Tech
Teresa Serrano-Gotarredona, Bernabe Linares-Barranco
Inst. of Microelectronics, Sevilla, Spain
Statistical rule for matching
(aka Pelgroms rule)
( )
X
A
X
WL
o
A
=
Zero order rule:
(X is some quantity like V
T
)
1. The variance goes as 1/area, i.e., o goes as
1/dimension
2. Only applies for local, identically-drawn neighbors.
3. There are many refinements to account for spatial
locality, large scale effects (tilt), etc.
4. Statistical transistor models try to model individual
parameter variations, e.g. V
T
, |, k, W/L
Lecture 5, Transistor matching and good
layout techniques
26-Mar-13
Lecture 5, Transistor matching and good
layout techniques, http://avlsi.ini.uzh.ch 2
Small transistors Big mismatch
J SSC, 39:1, 2004 p157-168 Gyvez, Tuinhout,
(Inter-die)
1. All devices follow
area rule
2. Caps match 1-2
decades better
than FETs
3. pfets match worse
than nfets (usually)
Notes: Gradient and
border effects are
removed here. I
0

exp(-V
T
) and VT
has normal
distribution
Cheng, Roy, Asenov ESSCIRC 2003
Dominant cause of FET mismatch is random
dopant fluctuation
Magnitude of V
T
mismatch
A
VT
is reported to be ~1 mV*um per nm
oxide thickness (J SSC, 39:1, 2004 p157-
168)
Example: 0.35um process with T
ox
=7nm,
A
VT
=7mV*um.
FET with W=L=2um
(With =0.2um, this is 10/10 ),
o(V
T
)=7mV*um/sqrt(2um*2um)=3.5mV
Minch measured value is 2.4mV
( ) , what is ?
T
T
V
T V
A
V A
WL
o =
Weak inversion mismatch
To zero order, weak inversion mismatch goes as
It is reported that weak inversion (sometimes) has
additional mismatch not accounted for by o(V
T
)
( ) ( )
(log ) exp
T ds
ds
ds T
V I
I
I U
o o
o
| |
= =
|
\ .
( )
T
V o
(log )
ds
I o
Serrano-Gotarredeno, Linares-Barranco 2000
Mismatch is almost constant in weak inversion
0.35u process
I
ds
I
ds
Lecture 5, Transistor matching and good
layout techniques
26-Mar-13
Lecture 5, Transistor matching and good
layout techniques, http://avlsi.ini.uzh.ch 3
Mismatch process scaling
1. From 1.2u to 0.35u, FETs with same dim have same
mismatch. (not true for deeper submicron, gets worse).
2. Cap matching depends on absolute size.
I
0
I
0
Reducing mismatch by design
Objectives:
Good event-threshold uniformity
Fast response under wide illumination range
AlogI
A
random variation
Part 2: Layout for good device
matching
Use unit devices: e.g. for capacitor matching
e.g. 3:1 capacitor
ratio
Not
very
precise
Much better
(if you can
afford it)
Put devices as nearby as possible E.g. Matching resistors
Lecture 5, Transistor matching and good
layout techniques
26-Mar-13
Lecture 5, Transistor matching and good
layout techniques, http://avlsi.ini.uzh.ch 4
Use same orientation: e.g.
diff pair/current mirror
better
Even better:
1. Use dummy devices on ends
2. Use common centroid
Use common-centroid to cancel
gradients: e.g. diff pair with common
centroid transistors
Surroundings affect matching
Minchet al. ISCAS 1996
Relative
capacitance
Use dummy devices to create identical
local surroundings
Checklist of Matching Techniques
1. Same dimensions
2. Same structure (do not match nFETs with
pFETs)
3. As large as possible
4. Close to one another
5. Same orientation
6. Laid out in a common-centroid arrangement
7. Surrounding circuits should be similar
8. Same temperature
Part 2: General layout techniques
Lecture 5, Transistor matching and good
layout techniques
26-Mar-13
Lecture 5, Transistor matching and good
layout techniques, http://avlsi.ini.uzh.ch 5
Layout Techniques for Good Performance
Every node has a parasitic capacitance and
resistance
Layout of mixed analog and digital circuits
should be carefully planned to minimize parasitic
effects and undesirable coupling
Digital circuits should have their own power
supply lines.
Digital ground should not be connected to
the substrate!
Latchup: avoid it by using lots of substrate
and well contacts
Shielding from substrate noise
Digital circuit
Analog circuit
Never connect digital ground to the substrate
V=LdI/dt noise on digital ground yanks around local
substrate. This can move backgate on analog FETs,
severely affecting them.
Shielding from minority carriers Papers about transistor mismatch
1. Lakshmikumar, K.R. Hadaway, R.A. Copeland, M.A. Characterisationandmodelingof mismatchinMOS
transistorsfor precisionanalogdesign, IEEE J. Solid-State Circuits 1986, 21:6, p1057-1066
2. M. J . M. Pelgrom, A. C. J . Duinmaiger, andA. P. G. Welbers, Matchingpropertiesof MOS transistorsfor
precisionanalogdesign, IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
3. AleksandraPavasovi, AndreasG. AndreouandCharlesR. Westgate, Characterizationof subthresholdMOS
mismatchintransistorsfor VLSI systems, AnalogInt. CircuitsandSignal Processing, 1994, 6:1, p75-85
4. Forti, F. Wright, M.E. Measurement of MOS current mismatchintheweak inversionregion, IEEE J. Solid-
State Circuits 1994, 29:2, p138-142
5. T. Mizuno, J . Okamura, A. Toriumi, "Experimental Studyof ThresholdVoltageFluctuationduetostatistical
variationof channel dopant number inMOSFETs," IEEE Trans. ElectronDevices, vol. ED-41, pp. 2216-2221,
1994.
6. TeresaSerrano-GotarredonaandBernabLinares-Barranco, "A New5-Parameter MOS Transistor Mismatch
Model," IEEE Electron Device Letters, vol. 21, No. 1, pp. 37-39. J anuary2000. (PDF 144K, 3pages)
7. TeresaSerrano-GotarredonaandBernabLinares-Barranco, "Systematic Width-and-LengthDependent CMOS
Transistor MismatchCharacterizationandSimulation," Analog Integrated Circuits and Signal Processing,
Kluwer Academic Publishers, December 1999. (PDF 1.4M, 26pages)
8. T. Serrano-GotarredonaandB. Linares-Barranco, "A 5-ParametersMismatchModel for Short Channel MOS
Transistors," Proceedings of the 1999 European Solid State Circuits Conference (ESSCIRC99), pp. 440-443,
1999. (PDF 266K, 4pages)
9. Thematchingof small capacitorsfor analogVLSI, Minchet. Al. ISCAS 1996p239-241