Lecture on

VHDL
Dr. K. G. Sharma
FET, MITS University
Dr. K. G. Sharma
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What is VHDL?
VHSIC
Hardware
Description
Language
VHSIC Very High Speed Integrated Circuit
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Developed in the early 1980s
Method of describing electronic systems for the American
Department of Defense
Use for digital design only
Synthesis tools used to create and optimize the
implementation
Limitations of VHDL
Digital only, not analogyet
Completely dependent upon synthesis tools
Not much control on physical hardware layout
Introduction
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VLSI Design Cycle
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Design Styles
Full Custom Gate Array Standard Cell FPGA
Cell size Variable Fixed height Fixed Fixed
Cell type Variable Variable Fixed Programmable
Cell Placement Variable Variable Fixed Fixed
Interconnection Variable Variable Variable Programmable
Area Compact Compact to
Moderate
Moderate Large
Performance High High to
Moderate
Moderate Low
Fabrication layers All All Routing layer None
Various design styles are used in order to reduce the complexity of
physical design and to give high yield and quick time-to-market
designs.
Different design styles are
Full Custom
Gate Array
Standard Cell
FPGA
Comparison of design styles
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Levels of Abstraction in Digital Design
Each level of abstraction defines how much
detail about the design is specified in its
description.
Behavioral level uses VHDL to describe
function of a design, without specifying the
architecture of registers
Contains as much timing information as a
designer requires to represent the function
Register Transfer Language VHDL used to
define every register in the design
Still contains architectural information
Logic level deals with the interconnection of
logic gates and registers
Layout information and analog effects are
ignored
Deals with function, architecture, and
technology
Layout is the lowest level of abstraction.
Specifies the actual layout of the design on
silicon, and may also specify detailed timing
information or analog effects.
VHDL uses a simulation cycle to model the stimulus and
response nature of digital hardware.
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VHDL Simulation Cycle
Concurrency VHDL is able to describe activity that
happens in parallel
Hierarchy the ability to describe the structure. Also,
the ability to mix descriptions of structure with
descriptions of behavior
Sequential VHDL has statements that execute on after
the other in sequence, such as a traditional software
language like C
Time VHDL allows us to model time
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VHDL Language Concepts
Contains a package or a collection of packages
Resource Libraries
Standard Package
IEEE developed packages
Altera Component packages
Any library of design units that are referenced in a design
Working Library
Library into which the unit is being compiled
LIBRARY ieee;
Contains the following packages:
std_logic_1164 (std_logic types & related functions)
std_logic_arith (arithmetic functions
std_logic_signed (signed arithmetic functions)
std_logic_unsigned (unsigned arithmetic functions)
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Libraries
LIBRARY <any_name>;
USE <any_name>.<package_name>.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
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Libraries in VHDL
VHDL provides two different types of execution:
sequential and concurrent.
Different types of execution are useful for
modeling of real hardware.
Supports various levels of abstraction.
Sequential statements view hardware from a
programmer approach.
Concurrent statements are order-independent and
asynchronous.
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Sequential vs Concurrent Statements
The main VHDL building block. An entity declaration
describes the interface of the component.
Describes the interface to a hierarchical block without defining
behavior.
Equivalent to a symbol in a schematic design.
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Entity
d0
d1
f
s
2-to-1 Multiplexer
ENTITY mux2to1 is
PORT( d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux2to1;
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Entity
d0
d1
f
s
2-to-1 Multiplexer
ENTITY mux2to1 is
PORT( d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux2to1;
PORT declaration establishes the interface of the object to
the outside world.
Three parts of the PORT declaration
Name
Any identifier that is not a reserved word.
Mode
In, Out, Inout, Buffer
Data type
Any declared or predefined datatype.
Sample PORT declaration syntax:
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Port Declaration
Architecture declarations describe the operation of the
component.
Many architectures may exist for one entity, but only one may
be active at a time.
An architecture is similar to a schematic of the component.
The internal details of an entity are specified by an architecture
body using any of the following modeling styles:
1. As a set of interconnected components (to represent structure),
2. As a set of concurrent assignment statements (to represent
dataflow),
3. As a set of sequential assignment statements (to represent behavior),
4. Any combination of the above three (Mixed).
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Architecture
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Structural Style of Modeling
Architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X, Y: in BIT; Z: out BIT);
end component;
component AND2
port (L, M: in BIT; N: out BIT);
end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
architecture behav of reg4 is
begin
storage : process is
variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
begin
if en = '1' and clk = '1' then
stored_d0 := d0;
stored_d1 := d1;
stored_d2 := d2;
stored_d3 := d3;
end if;
q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns;
q2 <= stored_d2 after 5 ns;
q3 <= stored_d3 after 5 ns;
wait on d0, d1, d2, d3, en, clk;
end process storage;
end architecture behav
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Behavioral Style of Modeling
Architecture dataflow of sop is
begin
-- Begin parallel statements
g <= e or f; -- Statement a
e <= a and b; -- Statement b
f <= c and d; -- Statement c
end dataflow_machine;
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Dataflow Style of Modeling
Entities can be pieced together to form larger structures
The interconnection of the entities and their architectures
describe the hierarchy
A good example is the construction of a 4-to-1 mux from
two 2-to-1 muxes being used as components.
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Hierarchy
d0
d1
f
d2
d3
s0 s1
ENTITY mux4to1 IS
PORT(w0, w1, w2, w3, sel0, sel1 :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux4to1;
ARCHITECTURE structure OF mux4to1 IS
SIGNAL I1, I2 :STD_LOGIC;
COMPONENT mux2to1
PORT(d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END COMPONENT;
BEGIN
u1:mux2to1 PORT MAP(w0, w1, sel0, I1);
u2:mux2to1 PORT MAP(w2, w3, sel0, I2);
u3:mux2to1 PORT MAP(I1, I2, sel1, f);
END structure;
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Hierarchy
Aprocess is a region of VHDL code that executes SEQUENTIALLY.
Exists inside the architecture
Multiple processes execute with each other concurrently
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Processes
ENTITY orgate IS
PORT (a,b : in bit;
z : out bit);
END orgate;
ARCHITECTURE Behavior OR orgate IS
BEGIN
or_func: PROCESS (a,b)
BEGIN
IF (a='1' OR b='1') THEN
z <= '1';
ELSE
z <= '0';
END IF;
END PROCESS or_func;
END Behavior
A package contains a collection of definitions that may be
referenced by many designs at the same time
Usage is similar to that of a component
Separate design file that exists outside of the other design
units seen thus far, such as entities and architectures
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Packages
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT (d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux2to1;
ARCHITECTURE LogicFunc OF mux2to1 IS
BEGIN
f <= (d0 AND (NOT s)) OR (d1 AND s);
END LogicFunc;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mux2to1_package IS
COMPONENT mux2to1
PORT (d0, d1, s :IN STD_LOGIC;
f :OUT STD_LOGIC);
END COMPONENT;
END mux2to1_package;
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Packages
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.mux2to1_package.all;
ENTITY mux4to1 IS
PORT(w0, w1, w2, w3, sel0, sel1 :IN STD_LOGIC;
f :OUT STD_LOGIC);
END mux4to1;
ARCHITECTURE structure OF mux4to1 IS
SIGNAL I1, I2:STD_LOGIC;
BEGIN
u1:mux2to1 PORT MAP(w0, w1, sel0, I1);
u2:mux2to1 PORT MAP(w2, w3, sel0, I2);
u3:mux2to1 PORT MAP(I1, I2, sel1, f);
END structure;
Thank You