Lecture on

Verilog
Dr. K. G. Sharma
ECE Department
FET, MITS University
Developed by Gateway Design Automation (1980)
Later acquired by Cadence Design(1989) who made it public in 1990
Became a standardized in 1995 by IEEE (Std 1364) regulated by
Open Verilog International (OVI)
Verilog is:
Ahardware design language (HDL)
Tool for specifying hardware circuits
Syntactically, a lot like C or Java
An alternative to VHDL (and more widely used)
Dr. K. G. Sharma
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What is Verilog?
Easy to learn and use
Relatively new and uses syntax of C programming
(VHDL is older of the two and inherits the characteristics of ADAand Pascal)
Functional verification of the design can be done early in
the design cycle
Model digital logic circuits
Behavioral level modeling
RTL level modeling
Gate level modeling
Mixed level modeling
Dr. K. G. Sharma
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Overview of Verilog as HDL
Model Digital logic circuits
Behavioral level modeling
RTL level modeling
Gate level modeling
Mixed level modeling
Simulate and verify digital logic circuits
In simulating we can write-
Test Benches
Bus-Functional models
Observability
Full Timing simulation
Synthesize digital logic circuits
Basics of RTL coding
Combinational circuits
Sequential circuits
Dr. K. G. Sharma
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What can we do with Verilog
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Design Process
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Synthesis and HDLs
Hardware description language (HDL) is a convenient, device independent
representation of digital logic.
A module is the basic
building block in Verilog.
It can specify any system
of almost any complexity.
Regardless of its
complexity, module
specification always has
the same structure.
Verilog designs consist of
interconnected modules.
A module can be an
element or collection of
lower level design blocks.
A simple module with
combinational logic might
look like this:
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Verilog: The Module
Out = sel a + sel b
2-to-1 multiplexer with inverted output
Basic type: bit vector
Values: 0, 1, X (don't care), Z (high impedance)
Connect things together with: wire
Single wire:
wire my_wire;
Array of wires
wire[7:0] my_wire;
Why not wire[0:7]?
For procedural assignments, we'll use reg
Again, can either have a single reg or an array
reg[3:0] accum; // 4 bit reg
reg is not necessarily a hardware register
Dr. K. G. Sharma
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Data Types in Verilog
Avoid using %, **, and / because you'll run into problems
when trying to synthesis
Dr. K. G. Sharma
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Verilog RTL Operators
Each circuit can be specified in several ways, according
to designer needs
Structural style Using primitives and lower level module
instantiation.
Dataflow style Specifying output signal in terms of input signal
transformations.
Behavioral style Specifying algorithmically the expected
behavior of the circuit.
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Coding Styles in Verilog
The circuit is specified in terms of instantiations of lower level components (in this case
logic gates, which are Verilog primitives) connected with internal signals. The translation
of such a specification into a physical circuit is straightforward.
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Structural Style
This style is similar to logical equations, although in general it is not limited to logical
values only. The specification is comprised of expressions made up of input signals and
assigned to outputs. In most cases, such an approach can be quite easily translated into a
structure and then implemented.
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Dataflow Style
It specifies the circuit in terms of its expected behavior. It is closest to a natural language
description of the circuit functionality, but also the most difficult to synthesize.
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Behavioral Style
Let's design a 1 bit full adder
module FA( input a, b, cin, output s, cout);
assign s = a ^ b ^ c;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
Ok, but what if we want more than 1 bit FA?
Dr. K. G. Sharma
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A simple example (comb. circuit)
We can use 1 bit FA to build a 4 bit full adder
module 4bitFA( input [3:0] A, B, input cin,
output [3:0] S, output cout);
wire c0, c1, c2;
FAfa0(A[0],B[0],cin,S[0],c0); // implicit binding
FAfa1(.a(A[1]), .b(B[1]), .cin(c0), .s(S[1]), .cout(c1)); // explicit binding
FAfa2(A[2],B[2],c1,S[2],c2);
FAfa3(A[3],B[3],c2,S[3],cout);
endmodule
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A 4-bit Full Adder
Along with the different coding styles, Verilog also
supports switch level modeling.
Verilog provides various constructs to model switch-level
circuits. Digital circuits at MOS-transistor level are
described using these elements.
MOS Switches Two types of MOS switches can be
defined with the keywords, nmos and pmos
nmos n1 (out, data, control);
pmos p1 (out, data, control);
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Switch Level Modeling
CMOS Switches CMOS switches are declared with the
keyword cmos
cmos c1 (out, data, ncontrol, pcontrol);
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Switch Level Modeling
//Define your own NOR gate
module my_nor (out, a, b);
output out;
input a, b;
//Internal wires
wire c;
// set up power and ground lines
supply1 pwr; // pwr is connected to Vdd power supply
supply0 gnd; // gnd is connected to Vss (ground)
//instantiate pmos switches
pmos (c, pwr, b);
pmos (out, c, a);
//instantiate nmos switches
nmos (out, gnd, a);
nmos (out, gnd, b);
endmodule
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Example of switch level modeling
These languages have taken designers from low
level detail to much higher level of abstraction.
In 2000 VHDL International (VI) & Open verilog
International (OVI) merged into Accellera.
Simulation & synthesis are the two main kinds of
tools which operate on the VHDL & Verilog
languages.
They are not a toolset or methodology they are
each a different language.
However toolsets and methodologies are essential for
their effective use.
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VHDL and Verilog
Similarities.
Verilog and VHDL are Hardware Description languages that are used
to write programs for electronic chips.
VHDL is a strongly typed language. VHDL does not allow the
intermixing, or operation of variables, with different classes. Verilog
uses weak typing, which is the opposite of a strongly typed language.
Verilog is case sensitive and on the other hand, VHDL is not case
sensitive.
Verilog is easier to learn than VHDL due to the popularity of the C
programming language.
VHDL has the advantage of having a lot more constructs that aid in
high-level modeling. Verilog has no concept of packages, and all
programming must be done with the simple data types.
Verilog lacks the library management of software programming
languages. This means that Verilog will not allow programmers to put
needed modules in separate files that are called during compilation.
Large projects on Verilog might end up in a large, and difficult to
trace, file.
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VHDL and Verilog
Differences.
Thank You