CSW 353

(Assembly Language)

Computer Architecture
Dr. Salma Hamdy
10/30/2013

s.hamdy@cis.asu.edu.eg

Computer System Architecture

Chapter 1: Digital Logic Circuits Chapter 2: Digital Components Chapter 3: Data Representation Chapter 4: Register Transfer and Microoperations Chapter 5: Basic Computer Organization Chapter 6: Programming the Basic Computer Chapter 7: Microporgammed Control

Chapter 12: Memory Organization

Chapter 8: CPU

Chapter 11: I/O Organization

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1. 2. 3. 4.

Instruction Codes Computer Registers Computer Instructions Timing and Control

Basic Computer Organization and Design - I

Ch5. Introduces the basic computer and shows its operation can be specified with register transfer statements.

1. Instruction Codes
The general-purpose computer is capable of executing various microoperations, and can be instructed as to what specific sequence of operations it must perform. The user of a computer can control the process by means of a program (set of instructions that specify the operations, operands, and the sequence by which processing has to occur.
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1. Instruction Codes (cont.)

Instructions and data are stored in memory.
Memory
Read instruction

Control register
Interpret binary code of instruction. Execute it by issuing a sequence of microoperations.

Every computer has its own unique instruction set. The most important property of a general-purpose computer is the ability to store and execute instructions (stored program concept).
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1. Instruction Codes (cont.)

Instruction: group of bits that instruct the computer to perform a specific operation. Its most basic part is the operation part, which is the group of bits that define such operations as add, subtract, shift, etc. Size of operation part depends on the total number of operations available in the computer ( distinct operations require an operation part of bits). operation part
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instruction

1. Instruction Codes (cont.)

Executing an instruction by control unit:
Receives instruction from memory. Interprets its operation code (opcode) bits. Issues a sequence of control signals to initiate microoperations in internal computer registers.

Operations vs. microoperation. Operation code = macrooperation.

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1. Instruction Codes (cont.)

e.g. A computer with 64 distinct operations has an instruction set with a 6-bit operation code. One of them can be ADD operation with code 110010. When the control interprets this code, it issues control signals to read operand from memory and add it to a processor register.

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1. Instruction Codes (cont.)

Operation must be performed on some data stored in memory. An instruction code therefore must include not only the operation, but also the registers or memory words where the operands are stored, as well as the register or memory word where the result is to be stored.
information opcode about data instruction
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Specify: - Memory word by address. - Processor register by bits to select one among .
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1. Instruction Codes (cont.)

Instruction code formats are invented by the designer who specify the architecture of the computer. In our basic computer design, we will adopt the following stored program organization:
One processor register (accumulator ). Two-part instruction code. Address is where to find operand. Operation is performed on operand and content of processor register.
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1. Instruction Codes (cont.)

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1. Instruction Codes (cont.)

Effective Address Address of operand in a computational instruction. Target address in a branch-type instruction. Addressing modes: When the second part of instruction code specifies An operand immediate. Address of operand direct. Address of a memory word that stores the address of operand indirect. One bit in the instruction code is used to distinguish between direct and indirect. 10/30/2013 12

1. Instruction Codes (cont.)

Indirect access mode bit

Direct Indirect Memory references Effective address 0 1 457 1 2 1350

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2. Computer Registers
Instructions are normally stored in consecutive memory locations and executed sequentially one at a time starting from a specific address.
Counter to calculate address of next instruction. Register for holding memory addresses. Register to store instruction read from memory. Register to manipulate data.
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2. Computer Registers (cont.)

Basic computer registers and memory and their functions.

branching
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2. Computer Registers (cont.)

Basic computer registers and memory and their functions.

How to connect all of them?

branching
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2. Computer Registers (cont.)

Common Bus System
Bus size. Selecting output on bus. Receiving data from bus. Memory read/write. Varying register size. Controls.

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2. Computer Registers (cont.)

Registers Design

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2. Computer Registers (cont.)

Registers Design Binary counter with parallel load and synchronous clear.

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2. Computer Registers (cont.)

Registers Design

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2. Computer Registers (cont.)

Registers Design Register with parallel load.

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2. Computer Registers (cont.)

Memory Design Address is specified by , eliminating the need for address bus. Content of any register can be specified from memory for a write operation. Any register can receive data from memory after a read operation except .
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2. Computer Registers (cont.)

AC
Its 16 inputs come from adder logic circuit. This circuit has three sets of inputs.

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2. Computer Registers (cont.)

Clock Single pulse to ,

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3. Computer Instructions
Basic Computer Instruction Format Memory-reference instruction. Register-reference instruction. Input-output instruction.

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3. Computer Instructions (cont.)

Basic Computer Instruction Format

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3. Computer Instructions (cont.)

Ho many instructions can this computer be designed to perform? 3-bit opcode only 7 memory instructions? 12 bits in register and input-output more! e.g. AND memory word in address 000000001100 to . (AND opcode: 000) Instruction: 0 000 000000001100
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3. Computer Instructions (cont.)

Ho many instructions can this computer be designed to perform? 3-bit opcode only 7 memory instructions? 12 bits in register and input-output more! e.g. AND memory word in address 000000001100 to . (AND opcode: 000) Instruction: 0 000 000000001100 Hexadecimal: 0 0 0 C
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3. Computer Instructions (cont.)

ISZ opcode: 110 Instruction: 0 110 0000 0000 0101 Hexadecimal: 6 0 0 5 Instruction: 1 110 0000 0000 1100 Hexadecimal: E 0 0 C Memory Reference Instructions =0 first hex digit ranges from 0 to 6. =1 first hex digit ranges from 8 to E.
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3. Computer Instructions (cont.)

Register Reference Instructions Instruction: 0 111 0000 0000 0101 Hexadecimal: 7 0 0 5 Instruction: 0 111 0000 0000 1100 Hexadecimal: 7 0 0 C First hex digit is always 7.
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3. Computer Instructions (cont.)

Input-Output Instructions Instruction: 1 111 0000 0000 0101 Hexadecimal: F 0 0 5 Instruction: 1 111 0000 0000 1100 Hexadecimal: F 0 0 C First hex digit is always F.
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3. Computer Instructions (cont.)

Instruction Set Completeness
Arithmetic, logic, shift, moving data, control, input output.

Efficiency.
e.g. multiplication, XOR must be programmed in the basic computer (Ch6).

Commercial computers
Ch8.
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4. Timing and Control

Timing of all registers and flip-flops is controlled by a master clock generator. But the clock doesnt change the state of a register unless the register is enabled by a control signal generated in a control unit. Hardwired control vs. microprogrammed control (ch7). For now, we will design a hardwired control unit.
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4. Timing and Control (cont.)

The control unit that supervises the operations in a digital system would normally consists of timing signals that determine the time sequence in which the operations are executed must know operation. The timing sequence in the control unit can be easily generated by means of counters or shift registers.
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4. Timing and Control (cont.)

Simple Examples 1. Word-time Generation for Serial Operation The control unit in a serial operation must generate a word-time that stays on for a number of pulses equal to the number of bits in the shift register. This word-time signal can be generated by means of a counter that counts the required number of pulses.
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4. Timing and Control (cont.)

1. Word-time Generation for Serial Operation If the word-time signal must stay on for eight clock pulses
To shift register

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Notice that the flip-flops are negative-edge-triggered

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4. Timing and Control (cont.)

2. Timing-Signals Generation for Parallel Mode The control units in systems the operate in parallel mode must generate timing signals that stay on for only one clock pulse, but these timing signals must be distinguished from each other. These signals can be generated by a circular shift register, or a counter with a decoder.
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4. Timing and Control (cont.)

2. Timing-Signals Generation for Parallel Mode Ring Counter: circular shift register with one flipflop set to one at a time.
initial value 1000

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Notice that the flip-flops are negative-edge-triggered

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4. Timing and Control (cont.)

2. Timing-Signals Generation for Parallel Mode Counter that goes through distinct states, with
decoder to decode the states.

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4. Timing and Control (cont.)

2. Timing-Signals Generation for Parallel Mode The timing signals when enabled by the clock pulse, can be used to generate multiple-phase clock pulses. ANDing with produces a clock pulse at 1/4th the frequency of the master-clock pulses.

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4. Timing and Control (cont.)

Basic Computer Control Unit Two decoders Sequence counter Control logic gates

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4. Timing and Control (cont.)

Basic Computer Control Unit Counter can be incremented or cleared. Example Suppose we want the timing sequence , , , , then at , is cleared if is active. In register-transfer logic statement: :
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4. Timing and Control (cont.)

Basic Computer Control Unit Initially, is cleared triggering only registers whose control inputs are connected to . increments with every cycle resulting the sequence:

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4. Timing and Control (cont.)

Basic Computer Control Unit : How?

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4. Timing and Control (cont.)

Basic Computer Control Unit A memory read/write cycle will be initiated with the rising edge of a timing signal. It will be assumed that the memory cycle time is less than the clock cycle time (so that
read/write will finish before the next rising edge, and that edge will be used to load memory word into a register).

Most commercial computer provide wait cycles in the processor.

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5. Instruction Cycle
A program (sequence of instructions) residing in memory is executed by going through a cycle for each instruction, which in turn, is divided into a sequence of subcycles or phases.

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5. Instruction Cycle (cont.)

In the basic computer, each instruction goes through these phases:
1. Fetch instruction from memory. 2. Decode the instruction. 3. Read the effective address if needed. 4. Execute the instruction.

Upon completing step 4, control goes back to step 1 and so on until a HALT instruction is encountered.
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5. Instruction Cycle (cont.)

Fetch and Decode What happens? The microoperations can be specified by the following register-transfer statements:

How are these implemented?

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5. Instruction Cycle (cont.)

Fetch and Decode

Remember, SC increments after each clock pulse. To produce the sequence , , ,

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5. Instruction Cycle (cont.)

Determining the Type of Instruction During . Control unit examines opcode and Decoder output distinguished memory-reference instructions from the other two types.

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5. Instruction Cycle (cont.)

Instruction Cycle (Initial configuration)

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5. Instruction Cycle (cont.)

Instruction Cycle (Initial configuration) ?

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5. Instruction Cycle (cont.)

Instruction Cycle (Initial configuration)

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5. Instruction Cycle (cont.)

Register-Reference Instructions = and = , at clock transition (0-11) specify one of 12 instructions. Let the bits of be . . Let the Boolean relation = . Since the control function is distinguished by one of the bits in (0-11), then all control functions can be simply denoted by .
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5. Instruction Cycle (cont.)

Register-Reference Instructions Example: CLA Hex. 7 8 0 0 Binary 0 111 1000 000 000 Control function that initiates microoperations for this instruction is: =
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the

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5. Instruction Cycle (cont.)

Register-Reference Instructions ??

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5. Instruction Cycle (cont.)

Register-Reference Instructions is cleared after the execution of each instruction initiating (fetch) that causes a new cycle. After a HALT, the start flip-flip must be set manually.

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Selected Problems
To be selected!

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Next Lecture
Continuation of Basic Computer Organization and Design.

Assignment
- Reading: Chapter 5: sections 1-5.

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References
- Digital Design, 4th ed, M. Morris Mano, Prentice Hall, 2006. -http://microcom.kut.ac.kr/ ch05 - God bless Google and Wiki!

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