Code: 9A10504

B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

LINEAR & DIGITAL IC APPLICATIONS

(Common to E.Con.E, EIE & ECC)
Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) Briefly explain the op-amp block diagram and mention ideal op-amp specifications. (b) Determine the output of a differential amplifier when both differential and common mode signals are applied. Ad = 92.3, Ac = -0.237. Input signals ( Volts) (i) V1 = 10 sin . V2 = -10 sin (ii) V1 =210 sin . V2 = 190 sin (a) (i) Draw the circuit for V-I converter and derive the equation for its output current. (ii) Design an inverting adder to give an output voltage V0= -(0.1 V1 + 0.5V2 + 10V3). (b) A non-inverting amplifier has R1 = 95 K and R2 = 5 K. The op-amp has a unity gain frequency of 1.2 MHz. What is the closed loop bandwidth? What is the closed loop gain at 600 KHz? (a) Indicate the function of each pin of 555 chip. (b) Design a 555 astable multi vibrator to operate at 10 KHz with 40% duty cycle. (a) Explain about the different CMOS logic families. (b) Discuss about the CMOS dynamic electrical behavior. (a) Compare TTL and ECL. (b) Write the specifications of CMOS 40XX series. (a) Write the description about the following terms related to HDL. (i) Functions and procedures. (ii) Data types. (iii) Constants. (b) Explain the structural design elements with an example. (a) Design 3X8 decoder and write VHDL code using behavioral design. (b) Design 8 bit ALU and write VHDL code. (a) Write the comparisons between Latches and flip-flops. (b) Explain the synchronous design methodology. Max. Marks: 70

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Code: 9A10504

B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

LINEAR & DIGITAL IC APPLICATIONS

(Common to E.Con.E, EIE & ECC)
Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) Explain the following terms related to op-amp (i) Slew rate. (ii) CMRR. (iii) PSRR. (iv) Input off set current. (b) Mention features of IC741 and calculate the common mode gain Ac if Ad = 105 and CMRR = 60 dB. (a) Draw the op-amp antilog amplifier and drive an expression for its output voltage. (b) Design the Schmitt trigger circuit using an op-amp to set UTP = 4 V. LTP = -2 V, supply voltages = 15 V are available. Sketch the hysteresis loop. (a) What are the modes of operating a 55 timer? Explain. (b) Explain the IC 565 frequency multiplier. (a) Design the Logic function f(A, B, C) = (A(B + C) + AB) using CMOS logic. (b) Explain the CMOS steady state electrical behavior. (a) Discuss about comparison of various BIPOLAR logic families. (b) Explain the specifications of ICS with standard 74XX series. (a) Explain the various design styles used in VHDL. (b) Discuss about the simulation and synthesis used in VHDL. (a) Design 4-bit comparator and write VHDL code. (b) Explain about the combinational multiplier. (a) Design 8-bit shift register and write VHDL code. (b) Explain about the PLDs. Max. Marks: 70

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Code: 9A10504

B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

LINEAR & DIGITAL IC APPLICATIONS

(Common to E.Con.E, EIE & ECC)
Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) Compare the practical and ideal specifications of IC741. (b) Define thermal drift. What is the need for frequency compensation? (a) (i) Draw the circuit for I-V converter and derive the equation for its output voltage. (ii) Describe the principle of operation of precision half wave rectifier with waveforms. (b) Explain the operation of log amplifier using op-amp. (a) Explain how a 555 timer in astable mode can be used for FSK generation. (b) Design a PLL circuit using 565 IC to get free running frequency is 4.5 KHz, lock range is 2 KHz and capture range is 100 Hz. Assume supply voltages are available. And also draw the circuit diagram. (a) Compare HC, HCT, VHC and VHCT CMOS logic families with the help of output specifications with from 4.5 to 5.5 V. (b) Design the Logic function f(A, B, C) = (AB(BC) + AC) using CMOS logic and also explain its operation. (a) Which is the fastest non-saturated logic gate? Draw the circuit and explain its functions. (b) Explain low voltage CMOS logic and ECL. (a) Design the logic circuit and write a data-flow style VHDL program for the following functions: F(A, B, C, D) = A, B, C, D (1, 4, 5, 7, 12, 14, 15) + d(3, 11). (b) Explain the use of packages. Give the syntax and structure of a package in VHDL. (a) Design 4-bit parallel adder and write VHDL code also. (b) Explain the Decimal-to-BCD encoder and draw the logic diagram. (a) Explain with neat sketch how four bits 1110 are serially entered into the shift register. (b) Explain about PLA devices. Max. Marks: 70

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Code: 9A10504

B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14

LINEAR & DIGITAL IC APPLICATIONS

(Common to E.Con.E, EIE & ECC)
Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) Draw and explain the equivalent circuit of an operational amplifier. Give its features. (b) What are the DC and AC characteristics of an operational amplifier? Explain any one of them in each category. (a) Design an inverting adder to give an output voltage V0 = - (0.1 V1 + 0.5V2 + 10V3). (b) What is an instrumentation amplifier? List any three applications of the instrumentation amplifier. (a) Explain frequency translation and FM detection applications of PLL. (b) (i) Draw the block schematic of PLL and explain the operation of each block. (ii) Derive an expression for capture range of PLL. (a) Explain about the CMOS dynamic electrical behavior. (b) Design the EX-OR gate using CMOS logic and also explain its operation. (a) Explain the concept and implementation of ECL logic family. (b) Design TTL three state NAND gate and explain the operation with the help of functional table. (a) Explain the difference between function and procedure supported by VHDL with suitable examples. (b) (i) Explain data-flow design elements of VHDL. (ii) Write a VHDL program to detect prime number of a 8-bit input. (a) Using two 74X138 decoders design a 4 to 16 decoder. (b) Explain about 1x4 de-multiplexer and write VHDL program for this de-multiplexer. (a) Design and draw the circuit diagram of decade counter and explain its operation. (b) Differentiate between ROM and RAM and give their applications. Max. Marks: 70

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