EMIF03-SIM02F2

3 LINE EMI FILTER INCLUDING ESD PROTECTION

IPAD

MAIN PRODUCT APPLICATIONS: EMI filtering and ESD protection for: SIM Interface (Subscriber Identify Module) UIM Interface (Universal Identify Module) DESCRIPTION The EMIF03-SIM02F2 is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF03 flip chip packaging means the package size is equal to the die size. This filter includes an ESD protection circuitry which prevents the device from destruction when subjected to ESD surges up 15kV. BENEFITS EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Lead free package Very low PCB space consuming: 1.42mm x 1.42mm Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reducing of parasitic elements through integration & wafer level packaging. COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 Level 4 on external & Vcc pins: 15kV(air discharge) 8kV (contact discharge) Level 1 on internal pins: 2kV (air discharge) 2kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3 Figure 2: Configuration
VCC 100 RST in R1 47 CLK in R2 100 Data in R3 Data ext CLK ext RST ext

Flip-Chip (8 Bumps)

Table 1: Order Code Part Number EMIF03-SIM02F2

Marking GJ

Figure 1: Pin Configuration (Ball side)

3
RST in

2
RST ext

1 A
CLK ext

CLK in

Gnd

B C

Data in

VCC

Data ext

Cline = 20pF max.

GND

TM: IPAD is a trademark of STMicroelectronics.

September 2005

REV. 5

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Table 2: Absolute Ratings (limiting values) Symbol Parameter and test conditions Internal pins (A3, B3, C3): ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge External pins (A2, B1, C2, C1): ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge Maximum junction temperature Operating temperature range Storage temperature range Value 2 2 15 8 125 - 40 to + 85 - 55 to + 150 C C C Unit

VPP

kV

Tj Top Tstg

Table 3: Electrical Characteristics (Tamb = 25C) Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM Rd R1 , R3 R2 Cline Tolerance 20% Tolerance 20% @ 0V Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between Input & Output Input capacitance per line Test conditions IR = 1 mA VRM = 3V 1.5 100 47 20 Min. 6 Typ. Max. 20 0.2 Unit V A pF
IPP VCL VBR VRM IRM IR VF V IF I

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Figure 3: S21 (dB) attenuation measurement (A2-A3 line)

EMIF03-SIM02F2_FREQ-MEAS_PM428 Aplac 7.70 User: ST Microelectronics Sep 22 2004 0.00

Figure 4: S21 (dB) attenuation measurement (B1-B3 line)

EMIF03-SIM02F2_FREQ-MEAS_PM428 Aplac 7.70 User: ST Microelectronics Sep 22 2004 0.00

dB

dB

-10.00

-10.00

-20.00

-20.00

-30.00

-30.00

-40.00 100.0k 1.0M A2/A3 Line 10.0M f/Hz 100.0M 1.0G

-40.00 100.0k 1.0M B1/B3 line 10.0M f/Hz 100.0M 1.0G

Figure 5: S21 (dB) attenuation measurement (C1-C3 line)

EMIF03-SIM02F2_FREQ-MEAS_PM428 Aplac 7.70 User: ST Microelectronics Sep 22 2004 0.00

Figure 6: Analog crosstalk measurements

EMIF03-SIM02F2_FREQ-MEAS_PM428 Aplac 7.70 User: ST Microelectronics Sep 22 2004 0.00 dB -10.00

dB

-20.00
-10.00

-30.00 -40.00
-20.00

-50.00 -60.00 -70.00

-30.00

-80.00 -90.00
-40.00 100.0k 1.0M C1/C3 line 10.0M f/Hz 100.0M 1.0G

-100.00 100.0k 1.0M Xtalk A2/B3 10.0M f/Hz 100.0M 1.0G

Figure 7: Voltages when IEC61000-4-2 (+15 kV air discharge) applied to external pin

Figure 8: Voltages when IEC61000-4-2 (-15 kV air discharge) applied to external pin

Vexternal : 10V/d

Vexternal : 5V/d

Vinternal : 10V/d
100ns/d

Vinternal : 5V/d

100ns/d

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Figure 9: Line capacitance versus reverse applied voltage (typical)

C(pF)
20. 00 16. 00 12. 00 8. 00 4. 00

VR(V)
0. 00 0 1 2 3 4 5

Figure 10: Aplac model

Lbump Rbump a2 Cbump Rsub bulk Lbump Rbump b3 Cbump Rsub bulk LbumpRbump c1 Rsub Cbump bulk Dext1 0.25 0.28 Dext2 Dext1 0.25 Bulk Dint1 Dint2 0.29 0.31 0.29 Dint1 bulk Rsub Cbump Rsub Cbump bulk 100 Rbump Lbump c3 Rsub Cbump bulk 47 Rbump Lbump b1 100 Rbump Lbump a3

Lbump Ls 100m Rbump a2 Lgnd Port1 50 Cgnd Rgnd Port2 50 a3 100m Ls

Figure 11: Aplac parameters

Ls 950pH Rs 150m Cext1 15pF Cint1 4.5pF Cext2 14pF Cint2 4pF Rbump 20m Lbump 50pH Cbump 0.15pF Rgnd 500m Lgnd 50pH Cgnd 0.15pF Rsub 100m Model Dint1 BV=15 CJO=Cint1 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.001m VJ=0.6 TT=50n Model Dext1 BV=15 CJO=Cext1 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.001m VJ=0.6 TT=50n Model Dint2 BV=15 CJO=Cint2 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.001m VJ=0.6 TT=50n Model Dext2 BV=15 CJO=Cext2 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.001m VJ=0.6 TT=50n

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EMIF03-SIM02F2
Figure 12: Ordering Information Scheme

EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip x = 1: 500m, Bump = 315m = 2: Leadfree Pitch = 500m, Bump = 315m = 3: Leadfree Pitch = 400m, Bump = 250m

yy

xxx zz

Fx

Figure 13: FLIP-CHIP Package Mechanical Data

500m 50 650m 65 315m 50

500m 50

1.42mm 50m

Figure 14: Foot print recommendations

Figure 15: Marking

1.42mm 50m

365
Dot, ST logo xx = marking z = packaging location yww = datecode (y = year ww = week)

240

365

Copper pad Diameter : 250m recommended , 300m max

Solder stencil opening : 330m

Solder mask opening recommendation : 340m min for 315m copper pad diameter

x x z y ww

40

220

All dimensions in m

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EMIF03-SIM02F2
Figure 16: FLIP-CHIP Tape and Reel Specification
Dot identifying Pin A1 location 4 +/- 0.1 1.5 +/- 0.1

1.75 +/- 0.1 3.5 +/- 0.1

0.73 +/- 0.05

All dimensions in mm

Table 4: Ordering Information Ordering code EMIF03-SIM02F2 Marking GJ Package Flip-Chip Weight 2.9 mg Base qty 5000 Delivery mode Tape & reel 7

Note: More informations are available in the application notes: AN1235: Flip-Chip: Package description and recommendations for use AN1751: "EMI Filters: Recommendations and measurements"

8 +/- 0.3

ST E

ST E

ST E

xxz yww

User direction of unreeling

xxz yww

xxz yww

4 +/- 0.1

Table 5: Revision History Date 08-Oct-2004 20-Oct-2004 25-Mar-2005 Revision 1 2 3 First issue. Minor layout update. Figure 1 on page 1: pin configuration definitions changed from RST out, CLK out and Data out to RST ext, CLK ext and Data ext. Titles in Figures 7 and 8 changed - No technical data changed out changed to ext in Figure 2. Description of Changes

13-Jun-2005 12-Sep-2005

4 5

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com

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