IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30,31,2012

588

BIST USING GENETIC ALGORITHM FOR ERROR DETECTION AND CORRECTION

Fahmitha Banu.M Electronics and Communication Engineering Oxford Engineering College Trichy, India Poornima.N Electronics and Communication Engineering Oxford Engineering College Trichy, India
a low peak power

Abstract

This

paper

presents

consumption BIST based on genetic algorithm (GA) is applied for viterbi decoder error detection and correction, denoted by GAlTPGEDC. This method aims at reducing the changes m-I test vectors are between successive test pattern. Here

excessive power dissipation, and results in delay penalty into the design .To lower the power in test mode, many techniques have been proposed to reduce the switching

activities of test pattern. For LFSR based test pattern

generator (TPG), Guiller proposed a modified clock scheme for liner feedback shift register (LFSR), so that only half of the D flip-flops works during each test period, thus only half of the test pattern can be switched .DS-LFSR is proposed in , in which there's d times clock frequency between slow LFSR and normal LFSR, and test pattern generated by original LFSR is rearranged to reduce the switch frequency. LP-TPG techniques can efficiently reduce the average power compared to traditional pseudo random BIST circuits, but sometimes

inserted between two successive n-bit generated by linear feedback shift registers (LFSR), where m and elements of group were optimized by GA. Thus the switching activities of test vectors are greatly reduced in test mode without compromising fault coverage. The proposed structure has the advantages of low test. Experiments conducted on ISCAS'89 benchmark circuits demonstrate that proposed scheme gives better fault coverage and with viterbi decoder error detection and correction was performed with a large reduction in power dissipation during testing.

Keywords

Low power consumption design, GA, BIST,

lead to fault coverage reduction. Single input change sequence technique is a better low power approach which greatly decreases the transitions of inputs to reduce the internal switching activities. The combination of LFSR and scan shift registers is used to generate random single input change sequences. A pseudo single input change sequence technique is proposed by adding an extra cyclic shift register and XOR gates, so that 2n-l single input change test vectors can be inserted between two neighbor vectors generated by LFSR, n is the length of LFSR. Thus average power is reduced. The drawback of this methodology is that the test vectors' switching activities will still be very large if the test clock frequency is very high since the seed changes every 2n clock period. In this paper comparison of ITPG and GAITPG was made which reduce the power consumption. A method of them, which was denoted by inserted test pattern generator (ITPG) [4], i.e. the BIST TPG was based on a linear feedback shifted register (LFSR), leading to pseudo single-input-change test set to reduce the number of weighted switching activity (WSA) at inputs of the circuit under test (CUT).

TPG, LFSR, weighted switching activity (WSA)

LINTRODUCTION Power conswnption in test mode is usually higher than that in normal mode, and it has been shown that power consumption during test mode is as high as 200% of the power consumed in the normal mode [1] .In general, the test power issues include excess average and excess peak power. The excess average power consumption will result in high accumulated heat, and the excess peak power consumption can cause some reliability problems or even damage the circuit under test. The main reason is that the circuit under test has much more switching activities. Thus special care must be taken to ensure that the power rating of circuits is not exceeded during test application. A number of techniques to control power consumption in test mode have been presented in the literature. These include test scheduling algorithms under power constraints, techniques for minimizing power during scan testing, and low-power built in self-test (BIST). Embedded logic blocks used in VLSI chips usually have low controllability and observability. BIST structures are well-suited for testing such blocks. Also, the use of efficientBIST structures allows at-speed testing can provide very high fault coverage and bring down the cost of testing [2]. BIST also supports test reuse and protects intellectual property [31. Because of well known characteristic, BIST has been widely studied and applied. However, there are some major drawbacks for this BIST whose architecture is based on the linear feedback shift register (LFSR). One is that the BIST circuit introduces more switching activities in the circuit under test during test than that during normal operation. That can cause

Fig. 1 Structure of ITPG

ISBN: 978-81-909042-2-3 2012 IEEE

IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30,31,2012

589

mutation probability was set to 0.05, and crossover For an n-bit cycle shifted register (CSR), only after performing one cycle (which equals 2n CLK cycles) and returning to all-zero state can the LFSR generate the next pattern. The outputs of LFSR maintain current value during the cycle of CSR, at the same time, the n-bit outputs of LFSR perform XOR operation with the n-bit outputs of CSR one by one, to produce the vectors inserted in two successive patterns from the LFSR. Although the pattern and successive inserted vectors are correlative, the next pattern generated by LFSR is
Calculate Fitness Value Initialize The Population

probability was set to 0.8.

Start

random, leading to a pseudo single input change, which reduces the peak power consumption. A low peak power consumption BIST TPG based on genetic algorithm (GA), which is denoted by GAITPG, has been proposed [5]. It aimed at the reduction of the changes between successive test patterns and adopts the test-per-clock structure. As shown in fig.2

Select And Save Optimize Individual

CrossoverfMutation

Calculate Fitness Value, then appraising it

ml eLK

I "',':-I
'
t""

ur S R

Obtain Optimize solution

End

Fig.3 Procedural Flow Chart of GA After mutating and inverting fitness value is calculated again and power is checked. If low power is Fig. 2 Structure of GAITPGEDC This paper presents an improved performance of GAITPGEDC, followed by a compare of reduction of power consumption with other low power BIST TPG design, as indicated by figure 1. III. ERROR DETECTION AND CORRECTION The general idea for achieving error detection II. OPTIMIZING PROCESS BASED ON GA As showed in fig.2 (m-I) vectors are inserted between two successive n-bit pseudorandom test patterns generated by the original LFSR and moreover the transition density of test patterns is lowered availably. In order to minimize the power conswnption, m and the element of a group are needed to be optimized by GA, as described in figure 3. The evolutionary process includes chromosome encoding, roulette selection, one-point crossover, mutations and inversions. By calculating and modifying, and correction is to add some redundancy (i.e., some extra data) to a message, which receivers can use to check consistency of the delivered message, and to recover data determined to be erroneous. Error-detection and correction schemes can be either systematic or non systematic: In a systematic scheme, the transmitter sends the original data, and attaches a fixed number of check obtained then optimized solution is obtained and it is included in population. If low power is not achieved again then fitness evaluation is done again to rebuild the population again and the process is carried out again to generate the optimize solution.

bits (or parity data), which are derived from the data bits
by some deterministic algorithm. If only error detection is required, a receiver can simply apply the same algorithm to the received data bits and compare its output with the received check bits; if the values do not match, an error has occurred at some point during the transmission. In a

ISBN: 978-81-909042-2-3 2012 IEEE

IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30,31,2012

590

system that uses a non-systematic code, the original message is transformed into an encoded message that has at least as many bits as the original message. Error correction may generally be realized in two different ways: Automatic repeat request (ARQ) (sometimes also referred to as backward error correction): This is an error control technique whereby an error detection scheme is combined with requests for retransmission of erroneous data. Every block of data received is checked using the error detection code used, and if the check fails, retransmission of the data is requested - this may be done repeatedly, until the data can be verified. Forward error correction (FEC): The sender encodes the data using an error-correcting code (ECC) prior to transmission. The additional information (redundancy) added by the code is used by the receiver to recover the original data. In general, the reconstructed data is what is deemed the "most likely " original data. The purpose of FEC is to improve the capacity of

GAITPGEDC is the same with the original LFSR, and next to measure the total power, and to correct the errors occur in viterbi decoder.

A.Simulation on stuck-at fault coverage

The stuck-at fault coverage can be made between the ITPG and the GAITPGEDC, under the condition that their test length is equal, as shown in table 1. For most of the ISCAS'85 benchmark circuits, both stuck-at fault coverage obtained by the two schemes are very similar and for viterbi decoder using GAITPGEDC high fault coverage is obtained.
B. Simulation on power consumption

Analogically,

VHDL

codes

were

used

to

simulate the test generation process, which includes the original ITPG, the inserted TPG shown in figure 1 and the GAITPG. Then test set were obtained and applied to the CUT: some ISCAS'85 benchmark circuits and viterbi decoder. In the experiment, WSA was used to evaluate the energy/power consumption of the circuit [6]. That is to say, as defmed in reference [6], WSA is usually used for evaluating total power consumption, while consumption. Table 1. Simulation result of fault coverage.

channel by adding some carefully designed redundant information to the data being transmitted through the channel. The process of adding this redundant information is known as channel coding. Convolution coding and block coding are two major form of channel coding. FEC processing in a receiver may be applied to a digital bit stream or in the demodulation of a digitally modulated carrier. For the latter, FEC is an integral part of the initial analog-to-digital conversion in the receiver. The Viterbi decoder implements a soft-decision algorithm to demodulate digital data from an analog signal corrupted by noise. Many FEC coders can also generate a bit-error rate (BER) signal which can be used as feedback to fine tune the analog receiving electronics. Block codes work on fixed-size blocks (packets) of bits or symbols of predetermined size. Practical block codes can generally be decoded in polynomial time to their block length. Convolution codes work on bit or symbol streams of arbitrary length. They are most often decoded with the Viterbi algorithm, though other with algorithms are sometimes used. Viterbi decoding allows asymptotically optimal decoding efficiency increasing constraint length of the convolution code, but at the expense of exponentially increasing complexity. A convolution code can be turned into a block code, if desired, by "tail-biting ".

WSAa for

average power consumption and WSAp for peak power

Fault Coverage(FC)% Circuits ITPG GAITPGEDC

C432 C439 C880 C3540

99 98 99 96

97 99 99 97

Viterbi Decoder IV. EXPERIMENT RESULT VHDL codes were used to perform the

87

93

simulations one by one on the original LFSR, the inserted TPG (as described in figure 1) and the GAITPGEDC, and experiments were performed on some ISCAS'85 benchmark circuits and viterbi decoder. The goal of the experiments is first to make sure that the stuck-at fault coverage keeps the same when the test length of the

With the same test length, a comparison of the weighted switching activity can be made between the GAITPGEDC and the ITPG, as reported in table 2. Table 2 shows that the power consumption obtained by GAITPGEDC is much higher than that by the ITPG for the viterbi decoder circuit and correct the error with reduced switching activity.

ISBN: 978-81-909042-2-3 2012 IEEE

IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30,31,2012

591

5. E. M. Tan, S. D. Song, and W. K. Shi, "Power Reduction in BIST Design Based on Genetic Algorithm and Vector-Inserted TPG". Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments. Xi'an, 2007, VoI.IV. 4-533-537. 6. X. D. Zhang, W. L. Shan, and K. Roy. "Low-power

Table 2. Comparison of power conswnption

between ITPG and GAITPG

weighted random pattern testing". IEEE Transactions on

CAD o flCs and Systems, 2000,19(11): 1389-1398.

Circ uit
Viterbi Decoder

ITPG(mw)
14

GAITPGEDC(mw)
9

IV.CONCLUSION As showed in table 2, GAITPGEDC can highly reduce the weighted switching activity (WSA), during BIST application, that is, all the total power/energy, the average power and the peak power consumption are highly reduced. Experimental results based on ISCAS'85 benchmark circuits and viterbi decoder for error detection and correction show that about 26% to 64% reductions in the nwnber of the WSAp are attained, additionally, approximate 50% to 90% reductions of the WSA and the WSAa achieved, without A consumption comparison between losing of the stuck-at of fault power was coverage. reduction and GAITPGEDC ITPG

reported, to demonstrate that GAITPGEDC is much more efficient in the reduction of peak power conswnption when the pattern is applied to viterbi decoder for error detection and correction.

V.REFERENCES
I.Y. Zorian, "A distributed BIST control scheme for

complex VLSI devices," Proc. 11th IEEE VLSI Test Symp., Atlantic City, New Jersy, pp.4-9, Apr. 1993. 2. I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis, "An efficient built-in self test method for robust path delay fault testing," Journal of Electronic Testing: Theory and Applications, vol.8, no.2, pp.2 I 9-222, Apr. 1996. 3. A. Chandra and K. Chakrabarty, "Frequency-directed run-length (FDR) codes with application to system-on-a chip test data compression," 19th IEEE Proc. VLSI Test Symp., CA, pp.42-47, May 2001. 4. R. H. He, X. W. Li, and Y. Z. Gong, "A low power BIST TPG design". Proceedings of the 5th international conference on ASIC, 2003. 1136-1139, vol. 2.

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ISBN: 978-81-909042-2-3 2012 IEEE