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Freescale Semiconductor Data Sheet: Technical Data

Document Number: KL25P80M48SF0 Rev. 3, 9/19/2012

KL25 Sub-Family Data Sheet

KL25P80M48SF0

Supports the following: MKL25Z32VFM4, MKL25Z64VFM4, MKL25Z128VFM4, MKL25Z32VFT4, MKL25Z64VFT4, MKL25Z128VFT4, MKL25Z32VLH4, MKL25Z64VLH4, MKL25Z128VLH4, MKL25Z32VLK4, MKL25Z64VLK4, and MKL25Z128VLK4
Features Operating Characteristics Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V Temperature range (ambient): -40 to 105C Performance Up to 48 MHz ARM Cortex-M0+ core Memories and memory interfaces Up to 128 KB program flash memory Up to 16 KB RAM Clocks 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator Multi-purpose clock source System peripherals Nine low-power modes to provide power optimization based on application requirements 4-channel DMA controller, supporting up to 63 request sources COP Software watchdog Low-leakage wakeup unit SWD interface and Micro Trace buffer Bit Manipulation Engine (BME) Security and integrity modules 80-bit unique identification (ID) number per chip Human-machine interface Low-power hardware touch sensor interface (TSI) General-purpose input/output Analog modules 16-bit SAR ADC 12-bit DAC Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Timers Six channel Timer/PWM (TPM) Two 2-channel Timer/PWM (TPM) Periodic interrupt timers 16-bit low-power timer (LPTMR) Real-time clock Communication interfaces USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator Two 8-bit SPI modules Two I2C modules One low power UART module Two UART modules

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2012 Freescale Semiconductor, Inc.

Table of Contents
1 Ordering parts...........................................................................3 1.1 Determining valid orderable parts......................................3 2 Part identification......................................................................3 2.1 Description.........................................................................3 2.2 Format...............................................................................3 2.3 Fields.................................................................................3 2.4 Example............................................................................4 3 Terminology and guidelines......................................................4 3.1 Definition: Operating requirement......................................4 3.2 Definition: Operating behavior...........................................4 3.3 Definition: Attribute............................................................5 3.4 Definition: Rating...............................................................5 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating requirements......................................................................6 3.7 Guidelines for ratings and operating requirements............7 3.8 Definition: Typical value.....................................................7 3.9 Typical Value Conditions...................................................8 4 Ratings......................................................................................8 4.1 Thermal handling ratings...................................................8 4.2 Moisture handling ratings..................................................9 4.3 ESD handling ratings.........................................................9 4.4 Voltage and current operating ratings...............................9 5 General.....................................................................................9 5.1 AC electrical characteristics..............................................10 5.2 Nonswitching electrical specifications...............................10 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Voltage and current operating requirements.........10 LVD and POR operating requirements.................11 Voltage and current operating behaviors..............12 Power mode transition operating behaviors..........13 Power consumption operating behaviors..............13 EMC radiated emissions operating behaviors.......20 Designing with radiated emissions in mind...........21 Capacitance attributes..........................................21 5.3.1 5.3.2 Device clock specifications...................................21 General Switching Specifications..........................22 5.4 Thermal specifications.......................................................22 5.4.1 5.4.2 Thermal operating requirements...........................22 Thermal attributes.................................................22

6 Peripheral operating requirements and behaviors....................23 6.1 Core modules....................................................................23 6.1.1 SWD Electricals ...................................................23

6.2 System modules................................................................25 6.3 Clock modules...................................................................25 6.3.1 6.3.2 MCG specifications...............................................25 Oscillator electrical specifications.........................27

6.4 Memories and memory interfaces.....................................29 6.4.1 Flash electrical specifications................................29

6.5 Security and integrity modules..........................................30 6.6 Analog...............................................................................31 6.6.1 6.6.2 6.6.3 ADC electrical specifications.................................31 CMP and 6-bit DAC electrical specifications.........35 12-bit DAC electrical characteristics.....................36

6.7 Timers................................................................................39 6.8 Communication interfaces.................................................39 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 USB electrical specifications.................................39 USB VREG electrical specifications......................39 SPI switching specifications..................................40 I2C.........................................................................44 UART....................................................................44

6.9 Human-machine interfaces (HMI)......................................45 6.9.1 TSI electrical specifications...................................45

7 Dimensions...............................................................................45 7.1 Obtaining package dimensions.........................................45 8 Pinout........................................................................................45 8.1 KL25 Signal Multiplexing and Pin Assignments................45 8.2 KL25 Pinouts.....................................................................48 9 Revision History........................................................................52

5.3 Switching specifications.....................................................21

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Ordering parts

1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PKL25 and MKL25

2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format
Part numbers for this device have the following format: Q KL## A FFF R T PP CC N

2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid):
Field Q KL## A FFF Qualification status Kinetis family Key attribute Program flash memory size Description Values M = Fully qualified, general market flow P = Prequalification KL25 Z = Cortex-M0+ 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB

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Terminology and guidelines Field R T PP Silicon revision Temperature range (C) Package identifier Description Values (Blank) = Main A = Revision after main V = 40 to 105 FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm)

CC N

Maximum CPU frequency (MHz) Packaging type

4 = 48 MHz R = Tape and reel (Blank) = Trays

2.4 Example
This is an example part number: MKL25Z64VLK4

3 Terminology and guidelines


3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed:
Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit

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Terminology and guidelines

3.2 Definition: Operating behavior


An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements:
Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. A Unit

3.3 Definition: Attribute


An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example
This is an example of an attribute:
Symbol CIN_D Description Input capacitance: digital pins Min. 7 Max. pF Unit

3.4 Definition: Rating


A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: Operating ratings apply during operation of the chip. Handling ratings apply when the chip is not powered.

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Terminology and guidelines

3.4.1 Example
This is an example of an operating rating:
Symbol VDD Description 1.0 V core supply voltage 0.3 Min. 1.2 Max. V Unit

3.5 Result of exceeding a rating


40 Failures in time (ppm) 30

20

The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.

10

0 Operating rating Measured characteristic

3.6 Relationship between ratings and operating requirements


tin gr a g tin ( n. mi ) tin gr e ir qu e n me t (m in. ) ir qu e n me t (m ax .) g tin (m ax .) tin gr e tin gr a

ra pe

ra pe

ra pe

ra pe

Fatal range
Expected permanent failure

Degraded operating range


- No permanent failure - Possible decreased life - Possible incorrect operation

Normal operating range


- No permanent failure - Correct operation

Degraded operating range


- No permanent failure - Possible decreased life - Possible incorrect operation

Fatal range
Expected permanent failure

Operating (power on)


in. ) lin g ing rat ax .)

n Ha

dli

ng

ng ati

(m

(m

Ha

nd

Fatal range
Expected permanent failure

Handling range
No permanent failure

Fatal range
Expected permanent failure

Handling (power off)

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Terminology and guidelines

3.7 Guidelines for ratings and operating requirements


Follow these guidelines for ratings and operating requirements: Never exceed any of the chips ratings. During normal operation, dont exceed any of the chips operating requirements. If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8 Definition: Typical value


A typical value is a specified value for a technical characteristic that: Lies within the range of values specified by the operating behavior Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.

3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. 70 Typ. 130 Max. A Unit

3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions:

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Ratings
5000 4500 4000 3500 IDD_STOP (A) 3000 2500 2000 1500 1000 500 0 0.90 0.95 1.00 VDD (V) 1.05 1.10 TJ 150 C 105 C 25 C 40 C

3.9 Typical Value Conditions


Typical values assume you meet the following conditions (or other conditions as specified):
Symbol TA VDD Description Ambient temperature 3.3 V supply voltage 25 3.3 Value C V Unit

4 Ratings
4.1 Thermal handling ratings
Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Min. 55 Max. 150 260 Unit C C Notes 1 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

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General

4.2 Moisture handling ratings


Symbol MSL Description Moisture sensitivity level Min. Max. 3 Unit Notes 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings


Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 105C Min. -2000 -500 -100 Max. +2000 +500 +100 Unit V V mA Notes 1 2

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4.4 Voltage and current operating ratings


Symbol VDD IDD VDIO VAIO ID VDDA VUSB_DP VUSB_DM VREGIN Description Digital supply voltage Digital supply current Digital pin input voltage (except RESET) Analog pins1and RESET pin input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage USB_DP input voltage USB_DM input voltage USB regulator input Min. 0.3 0.3 0.3 25 VDD 0.3 0.3 0.3 0.3 Max. 3.8 120 3.6 VDD + 0.3 25 VDD + 0.3 3.63 3.63 6.0 Unit V mA V V mA V V V V

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General
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General

5.1 AC electrical characteristics


Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure.

Figure 1. Input signal measurement reference

All digital I/O switching characteristics, unless otherwise specified, assumes: 1. output pins have CL=30pF loads, are slew rate disabled, and are normal drive strength

5.2 Nonswitching electrical specifications


5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol VDD VDDA Description Supply voltage Analog supply voltage Min. 1.71 1.71 0.1 0.1 0.7 VDD 0.75 VDD Max. 3.6 3.6 0.1 0.1 Unit V V V V V V Notes

VDD VDDA VDD-to-VDDA differential voltage VSS VSSA VSS-to-VSSA differential voltage VIH Input high voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V VIL Input low voltage 2.7 V VDD 3.6 V 1.7 V VDD 2.7 V

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0.35 VDD 0.3 VDD

V V

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General

Table 1. Voltage and current operating requirements (continued)


Symbol VHYS IICDIO Description Input hysteresis Digital pin negative DC injection current single pin VIN < VSS-0.3V IICAIO Analog2 pin DC injection current single pin VIN < VSS-0.3V (Negative current injection) VIN > VDD+0.3V (Positive current injection) IICcont Contiguous pin DC injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins Negative current injection Positive current injection VRAM VDD voltage required to retain RAM mA -5 +5 -5 mA 3 Min. 0.06 VDD Max. Unit V 1 Notes

-25 1.2

+25

mA

1. All digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.

5.2.2 LVD and POR operating requirements


Table 2. VDD supply LVD and POR operating requirements
Symbol VPOR VLVDH Description Falling VDD POR detect voltage Falling low-voltage detect threshold high range (LVDV=01) Low-voltage warning thresholds high range VLVW1H VLVW2H VLVW3H VLVW4H VHYSH VLVDL Level 1 falling (LVWV=00) Level 2 falling (LVWV=01) Level 3 falling (LVWV=10) Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis high range Falling low-voltage detect threshold low range (LVDV=00) 2.62 2.72 2.82 2.92 1.54 2.70 2.80 2.90 3.00 60 1.60 2.78 2.88 2.98 3.08 1.66 V V V V mV V Min. 0.8 2.48 Typ. 1.1 2.56 Max. 1.5 2.64 Unit V V 1 Notes

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General

Table 2. VDD supply LVD and POR operating requirements (continued)


Symbol VLVW1L VLVW2L VLVW3L VLVW4L VHYSL VBG tLPO Description Low-voltage warning thresholds low range Level 1 falling (LVWV=00) Level 2 falling (LVWV=01) Level 3 falling (LVWV=10) Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis low range Bandgap voltage reference Internal low power oscillator period factory trimmed 1.74 1.84 1.94 2.04 0.97 900 1.80 1.90 2.00 2.10 40 1.00 1000 1.86 1.96 2.06 2.16 1.03 1100 V V V V mV V s Min. Typ. Max. Unit Notes 1

1. Rising thresholds are falling threshold + hysteresis voltage

5.2.3 Voltage and current operating behaviors


Table 3. Voltage and current operating behaviors
Symbol VOH Description Output high voltage Normal drive pad 2.7 V VDD 3.6 V, IOH = -5 mA 1.71 V VDD 2.7 V, IOH = -1.5 mA VOH Output high voltage High drive pad 2.7 V VDD 3.6 V, IOH = -18 mA 1.71 V VDD 2.7 V, IOH = -6 mA IOHT VOL Output high current total for all ports Output low voltage Normal drive pad 2.7 V VDD 3.6 V, IOL = 5 mA 1.71 V VDD 2.7 V, IOL = 1.5 mA VOL Output low voltage High drive pad 2.7 V VDD 3.6 V, IOL = 18 mA 1.71 V VDD 2.7 V, IOL = 6 mA IOLT IIN IIN IIN IOZ Output low current total for all ports Input leakage current (per pin) for full temperature range Input leakage current (per pin) at 25 C Input leakage current (total all pins) for full temperature range Hi-Z (off-state) leakage current (per pin) 0.5 0.5 100 1 0.025 65 1 V V mA A A A A 2 2 2 0.5 0.5 V V 1 VDD 0.5 VDD 0.5 100 V V mA 1 VDD 0.5 VDD 0.5 V V 1 Min. Max. Unit Notes 1

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General

Table 3. Voltage and current operating behaviors (continued)


Symbol RPU RPD Description Internal pullup resistors Internal pulldown resistors Min. 20 20 Max. 50 50 Unit k k Notes 3 4

1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD = 3.6 V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 4. Measured at VDD supply voltage = VDD min and Vinput = VDD

5.2.4 Power mode transition operating behaviors


All specifications except tPOR and VLLSxRUN recovery times in the following table assume this clock configuration: CPU and system clocks = 48 MHz Bus and flash clock = 24 MHz FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. VLLS0 RUN VLLS1 RUN VLLS3 RUN LLS RUN VLPS RUN STOP RUN 4 4.4 s 4 4.4 s 4 4.6 s 42 53 s 93 115 s 95 115 s Min. Typ. Max. 300 Unit s Notes

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General

5.2.5 Power consumption operating behaviors


Table 5. Power consumption operating behaviors
Symbol IDDA Description Analog supply current Min. Typ. Max. See note Unit mA Notes 1 2 6.4 mA

IDD_RUNCO_ Run mode current in compute operation - 48 MHz core / 24 MHz flash/ bus disabled, LPTMR CM running using 4MHz internal reference clock, CoreMark benchmark code executing from flash at 3.0 V IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash at 3.0 V IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash at 3.0 V at 25 C at 125 C IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V

3 4.1 5.2 mA 3 5.1 6.3 mA 3, 4,

6.4 6.8

7.8 8.3

mA mA 3

3.7

5.0

mA

IDD_WAIT

3 2.9 4.2 mA

IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus at 3.0 V IDD_VLPRCO Very low power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0 V IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash at 3.0 V

3 2.5 3.7 mA

5 188 570 A

5 224 613 A

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General

Table 5. Power consumption operating behaviors (continued)


Symbol IDD_VLPR Description Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash at 3.0 V Very low power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled at 3.0 V Stop mode current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_VLPS Very-low-power stop mode current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_LLS Low leakage stop mode current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0V at 25C at 50C at 70C at 85C at 105C 0.7 1.3 2.3 5.1 13 1.4 13 14 17 25 A 1.4 2.5 5.1 9.2 21 3.2 19 21 26 38 A 1.9 3.6 6.5 13 30 3.7 39 43 49 69 A 4.4 10 20 37 81 16 35 50 112 201 A 345 357 392 438 551 490 827 869 927 1065 A Min. Typ. 300 Max. 745 Unit A Notes 5, 4

IDD_VLPW

135

496

IDD_STOP

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General

Table 5. Power consumption operating behaviors (continued)


Symbol IDD_VLLS0 Description Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C IDD_VLLS0 Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) at 3.0 V at 25 C at 50 C at 70 C at 85 C at 105 C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for time. 3. MCG configured for FEI mode. 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. 6. No brownout 6 176 760 2120 4500 12130 860 3577 11660 18450 22441 nA Min. Typ. 381 956 2370 4800 12410 Max. 943 11760 13260 15700 23480 Unit nA Notes

Table 6. Low power mode peripheral adders typical value


Symbol IIREFSTEN4MHz Description -40 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. External 4MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 56 25 56 Temperature (C) 50 56 70 56 85 56 105 56 A Unit

IIREFSTEN32KHz

52

52

52

52

52

52

IEREFSTEN4MHz

206

228

237

245

251

258

uA

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General

Table 6. Low power mode peripheral adders typical value (continued)


Symbol IEREFSTEN32KHz Description -40 External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. VLLS1 VLLS3 LLS VLPS STOP ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. MCGIRCLK (4MHz internal reference clock) OSCERCLK (4MHz external crystal) ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. MCGIRCLK (4MHz internal reference clock) OSCERCLK (4MHz external crystal) IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 86 235 45 86 256 45 86 265 45 86 274 45 86 280 45 86 287 45 A 66 214 66 237 66 246 66 254 66 260 66 268 A 22 22 22 22 22 22 A 25 Temperature (C) 50 70 85 105 Unit

440 440 490 510 510

490 490 490 560 560

540 540 540 560 560

560 560 560 560 560

570 570 570 610 610

580 580 680 680 680 nA

IRTC

432

357

388

475

532

810

nA

IUART

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General

Table 6. Low power mode peripheral adders typical value (continued)


Symbol IADC Description -40 ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 366 25 366 Temperature (C) 50 366 70 366 85 366 105 366 A Unit

5.2.5.1

Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions: MCG in FBE for run mode, and BLPE for VLPR mode USB regulator disabled No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA

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General

Run Mode Current Vs Core Frequency


Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
8.00E-03

7.00E-03

6.00E-03

Current Consumption on VDD(A)

5.00E-03

All Peripheral CLK Gates

4.00E-03

All Off

All On
3.00E-03

2.00E-03

1.00E-03

000.00E+00 '1-1 1 '1-1 2 '1-1 3 '1-1 4 '1-1 6 '1-1 12 '1-1 24 '1-2 48

CLK Ratio Flash-Core Core Freq (MHz)

Figure 2. Run mode supply current vs. core frequency

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General

VLPR Mode Current Vs Core Frequency


Temperature = 25, V DD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE

400.00E-06

350.00E-06

Current Consumption on VDD (A)

300.00E-06

250.00E-06

All Peripheral CLK Gates


200.00E-06

All Off All On

150.00E-06

100.00E-06

50.00E-06

000.00E+00
'1-1 '1-2 '1-2 '1-4

CLK Ratio Flash-Core Core Freq (MHz)

Figure 3. VLPR mode current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors


Table 7. EMC radiated emissions operating behaviors for 64-pin LQFP package
Symbol VRE1 VRE2 VRE3 VRE4 VRE_IEC Description Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 IEC level Frequency band (MHz) 0.1550 50150 150500 5001000 0.151000 Typ. 13 15 12 7 M Unit dBV dBV dBV dBV 2, 3 Notes 1, 2

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range.

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20 Freescale Semiconductor, Inc.

General 2. VDD = 3.3 V, TA = 25 C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated EmissionsTEM Cell and Wideband TEM Cell Method

5.2.7 Designing with radiated emissions in mind


To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for EMC design.

5.2.8 Capacitance attributes


Table 8. Capacitance attributes
Symbol CIN_A CIN_D Description Input capacitance: analog pins Input capacitance: digital pins Min. Max. 7 7 Unit pF pF

5.3 Switching specifications


5.3.1 Device clock specifications
Symbol fSYS fBUS fFLASH fSYS_USB fLPTMR fSYS fBUS fFLASH fLPTMR fERCLK fLPTMR_pin Description Normal run mode System and core clock Bus clock Flash clock System and core clock when Full Speed USB in operation LPTMR clock VLPR System and core clock Bus clock Flash clock LPTMR clock External reference clock LPTMR clock mode1 Table continues on the next page... 4 1 1 24 16 24 MHz MHz MHz MHz MHz MHz 20 48 24 24 24 MHz MHz MHz MHz MHz Min. Max. Unit Notes

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Freescale Semiconductor, Inc. 21

General Symbol
K

Description

Min.

Max. 16 16 8 8

Unit MHz MHz MHz MHz

Notes

fLPTMR_ERCL LPTMR external reference clock fosc_hi_2 fTPM fUART0 Oscillator crystal or resonator frequency high frequency mode (high range) (MCG_C2[RANGE]=1x) TPM asynchronous clock UART0 asynchronous clock

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module.

5.3.2 General Switching Specifications


These general purpose specifications apply to all signals configured for GPIO, UART, and I2C signals.
Symbol Description GPIO pin interrupt pulse width (digital glitch filter disabled) Synchronous path External RESET and NMI pin interrupt pulse width Asynchronous path GPIO pin interrupt pulse width Asynchronous path Port rise and fall time 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 36 ns Min. 1.5 100 16 Max. Unit Bus clock cycles ns ns Notes 1 2
2

5.4 Thermal specifications


5.4.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol TJ TA Description Die junction temperature Ambient temperature Min. 40 40 Max. 125 105 Unit C C

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22 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

5.4.2 Thermal attributes


Table 10. Thermal attributes
Board type Single-layer (1S) Symbol RJA Description Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to board Thermal resistance, junction to case Thermal characterization parameter, junction to package top outside center (natural convection) 80 LQFP 70 64 LQFP 71 48 QFN 84 32 QFN 92 Unit C/W Notes 1

Four-layer (2s2p)

RJA

53

52

28

33

C/W

Single-layer (1S)

RJMA

59

69

75

C/W

Four-layer (2s2p)

RJMA

46

22

27

C/W

RJB RJC JT

34 15 0.6

34 20 5

10 2.0 5.0

12 1.8 8

C/W C/W C/W

2 3 4

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental ConditionsForced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors


6.1 Core modules
6.1.1 SWD Electricals
Table 11. SWD full voltage range electricals
Symbol Description Operating voltage Table continues on the next page... Min. 1.71 Max. 3.6 Unit V

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Freescale Semiconductor, Inc. 23

Peripheral operating requirements and behaviors

Table 11. SWD full voltage range electricals (continued)


Symbol J1 Description SWD_CLK frequency of operation Serial wire debug J2 J3 SWD_CLK cycle period SWD_CLK clock pulse width Serial wire debug J4 J9 J10 J11 J12 SWD_CLK rise and fall times SWD_DIO input data setup time to SWD_CLK rise SWD_DIO input data hold time after SWD_CLK rise SWD_CLK high to SWD_DIO data valid SWD_CLK high to SWD_DIO high-Z 20 10 0 5 3 32 ns ns ns ns ns ns 0 1/J1 25 MHz ns Min. Max. Unit

J2 J3 J3

SWD_CLK (input)

J4

J4

Figure 4. Serial wire clock input timing

SWD_CLK
J9 J10

SWD_DIO
J11

Input data valid

SWD_DIO
J12

Output data valid

SWD_DIO
J11

SWD_DIO

Output data valid

Figure 5. Serial wire data timing

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24 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.2 System modules


There are no specifications necessary for the device's system modules.

6.3 Clock modules


6.3.1 MCG specifications
Table 12. MCG specifications
Symbol fints_ft fints_t Description Internal reference frequency (slow clock) factory trimmed at nominal VDD and 25 C Internal reference frequency (slow clock) user trimmed Min. 31.25 Typ. 32.768 0.3 Max. 39.0625 0.6 Unit kHz kHz %fdco 1 Notes

fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature using SCTRIM and SCFTRIM fdco_t fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0 - 70 C Internal reference frequency (fast clock) factory trimmed at nominal VDD and 25 C Frequency deviation of internal reference clock (fast clock) over temperature and voltage --factory trimmed at nominal VDD and 25 C Internal reference frequency (fast clock) user trimmed at nominal VDD and 25 C Loss of external clock minimum frequency RANGE = 00 Loss of external clock minimum frequency RANGE = 01, 10, or 11 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 640 ffll_ref Mid range (DRS = 01) 1280 ffll_ref

+0.5/-0.7 0.4

3 1.5

%fdco %fdco

1, 2 1, 2

fintf_ft fintf_ft

4 +1/-2

MHz %fintf_ft 2

fintf_t floc_low floc_high

3 (3/5) x fints_t (16/5) x fints_t 31.25 20 40

MHz kHz kHz

20.97 41.94

39.0625 25 48

kHz MHz MHz 3, 4

Table continues on the next page...

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Freescale Semiconductor, Inc. 25

Peripheral operating requirements and behaviors

Table 12. MCG specifications (continued)


Symbol Description Low range (DRS = 00) 732 ffll_ref Mid range (DRS = 01) 1464 ffll_ref Jcyc_fll tfll_acquire fvco Ipll FLL period jitter fVCO = 48 MHz FLL target frequency acquisition time PLL VCO operating frequency PLL operating current PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) PLL operating current PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) PLL reference frequency range PLL period jitter (RMS) fvco = 48 MHz fvco = 100 MHz Jacc_pll PLL accumulated jitter over 1s (RMS) fvco = 48 MHz fvco = 100 MHz Dlock Dunl tpll_lock Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time 1.49 4.47 1350 600 2.98 5.97 150 + 1075(1/ fpll_ref) 10-6 ps ps % % s 11 120 50 ps ps 10 48.0 1060 100 MHz A 9 1 ms 8 180 ps 7 47.97 MHz Min. Typ. 23.99 Max. Unit MHz Notes 5, 6 fdco_t_DMX32 DCO output frequency

Ipll

2.0

600

4.0

A MHz

fpll_ref Jcyc_pll

10

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

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26 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.3.2 Oscillator electrical specifications


This section provides the electrical characteristics of the module. 6.3.2.1
Symbol VDD IDDOSC

Oscillator DC electrical specifications


Description Supply voltage Supply current low-power mode (HGO=0) 32 kHz 4 MHz 8 MHz (RANGE=01) 16 MHz 24 MHz 32 MHz Min. 1.71

Table 13. Oscillator DC electrical specifications


Typ. 500 200 300 950 1.2 1.5 Max. 3.6 Unit V 1 nA A A A mA mA 1 25 400 500 2.5 3 4 10 1 M M M M A A A mA mA mA 2, 3 2, 3 2, 4 Notes

IDDOSC

Supply current high gain mode (HGO=1) 32 kHz 4 MHz 8 MHz (RANGE=01) 16 MHz 24 MHz 32 MHz

Cx Cy RF

EXTAL load capacitance XTAL load capacitance Feedback resistor low-frequency, low-power mode (HGO=0) Feedback resistor low-frequency, high-gain mode (HGO=1) Feedback resistor high-frequency, low-power mode (HGO=0) Feedback resistor high-frequency, high-gain mode (HGO=1)

Table continues on the next page...

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Freescale Semiconductor, Inc. 27

Peripheral operating requirements and behaviors

Table 13. Oscillator DC electrical specifications (continued)


Symbol RS Description Series resistor low-frequency, low-power mode (HGO=0) Series resistor low-frequency, high-gain mode (HGO=1) Series resistor high-frequency, low-power mode (HGO=0) Series resistor high-frequency, high-gain mode (HGO=1) Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (HGO=1) 0 0.6 k V Min. Typ. 200 Max. Unit k k k Notes

VDD

0.6

VDD

1. VDD=3.3 V, Temperature =25 C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used.. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.

6.3.2.2
Symbol fosc_lo fosc_hi_1

Oscillator frequency specifications


Description Oscillator crystal or resonator frequency low frequency mode (MCG_C2[RANGE]=00) Oscillator crystal or resonator frequency high frequency mode (low range) (MCG_C2[RANGE]=01) Oscillator crystal or resonator frequency high frequency mode (high range) (MCG_C2[RANGE]=1x) Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Min. 32 3

Table 14. Oscillator frequency specifications


Typ. Max. 40 8 Unit kHz MHz Notes

fosc_hi_2

32

MHz

fec_extal tdc_extal

40

50

48 60

MHz %

1, 2

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 14. Oscillator frequency specifications (continued)


Symbol tcst Description Crystal startup time 32 kHz low-frequency, low-power mode (HGO=0) Crystal startup time 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) Min. Typ. 750 250 0.6 Max. Unit ms ms ms Notes 3, 4

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. 2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set.

6.4 Memories and memory interfaces


6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module. 6.4.1.1 Flash timing specifications program and erase

The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead.
Table 15. NVM program/erase timing specifications
Symbol thvpgm4 thversscr thversall Description Longword Program high-voltage time Sector Erase high-voltage time Erase All high-voltage time Min. Typ. 7.5 13 52 Max. 18 113 452 Unit s ms ms 1 1 Notes

1. Maximum time based on expectations at cycling end-of-life.

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Freescale Semiconductor, Inc. 29

Peripheral operating requirements and behaviors

6.4.1.2
Symbol trd1sec1k tpgmchk trdrsrc tpgm4 tersscr trd1all trdonce tpgmonce tersall tvfykey

Flash timing specifications commands


Description Read 1s Section execution time (flash sector) Program Check execution time Read Resource execution time Program Longword execution time Erase Flash Sector execution time Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Min.

Table 16. Flash command timing specifications


Typ. 65 14 65 62 Max. 60 45 30 145 114 1.8 25 500 30 Unit s s s s ms ms s s ms s 2 1 1 2 Notes 1 1 1

1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.

6.4.1.3
Symbol IDD_PGM IDD_ERS

Flash high voltage current behaviors


Description Average current adder during high voltage flash programming operation Average current adder during high voltage flash erase operation Min.

Table 17. Flash high voltage current behaviors


Typ. 2.5 1.5 Max. 6.0 4.0 Unit mA mA

6.4.1.4
Symbol

Reliability specifications
Description

Table 18. NVM reliability specifications


Min. Program Flash 5 20 10 K Typ.1 50 100 50 K Max. Unit years years cycles 2 Notes

tnvmretp10k Data retention after up to 10 K cycles tnvmretp1k nnvmcycp Data retention after up to 1 K cycles Cycling endurance

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40C Tj 125C.

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30 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.5 Security and integrity modules


There are no specifications necessary for the device's security and integrity modules.

6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 19 and Table 20 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1
Symbol VDDA VDDA VSSA VREFH VREFL VADIN CADIN

16-bit ADC operating conditions


Description Supply voltage Supply voltage Ground voltage ADC reference voltage high ADC reference voltage low Input voltage Input capacitance 16-bit mode 8-/10-/12-bit modes Conditions Absolute Delta to VDD (VDD-VDDA) Delta to VSS (VSS - VSSA)

Table 19. 16-bit ADC operating conditions


Min. 1.71 -100 -100 1.13 VSSA VREFL 13-/12-bit modes fADCK < 4 MHz 13-bit mode 16-bit mode 13 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time Table continues on the next page... 20.000 818.330 Ksps 1.0 2.0 5 18.0 12.0 k MHz MHz 5 5 6 Typ.1 0 0 VDDA VSSA 8 4 2 Max. 3.6 +100 +100 VDDA VSSA VREFH 10 5 5 k 4 Unit V mV mV V V V pF 2 2 3 3 Notes

RADIN RAS

Input resistance Analog source resistance

fADCK fADCK Crate

ADC conversion clock frequency ADC conversion clock frequency ADC conversion rate

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Peripheral operating requirements and behaviors

Table 19. 16-bit ADC operating conditions (continued)


Symbol Crate Description ADC conversion rate Conditions 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best results. The results in this data sheet were derived from a system which has < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1ns. 5. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT

Min. 37.037

Typ.1

Max. 461.467

Unit Ksps

Notes 6

Z ADIN
SIMPLIFIED CHANNEL SELECT CIRCUIT

Z AS R AS V ADIN V AS C AS

Pad leakage due to input protection

R ADIN

ADC SAR ENGINE

R ADIN INPUT PIN

R ADIN

INPUT PIN

R ADIN C ADIN

INPUT PIN

Figure 6. ADC input impedance equivalency diagram

6.6.1.2
Symbol IDDA_ADC

Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)


Description Supply current Conditions1 Min. 0.215 Table continues on the next page... Typ.2 Max. 1.7 Unit mA Notes 3

16-bit ADC electrical characteristics

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Peripheral operating requirements and behaviors

Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description ADC asynchronous clock source Conditions1 ADLPC = 1, ADHSC = 0 ADLPC = 1, ADHSC = 1 ADLPC = 0, ADHSC = 0 ADLPC = 0, ADHSC = 1 Sample Time TUE Total unadjusted error Differential nonlinearity Min. 1.2 2.4 3.0 4.4 Typ.2 2.4 4.0 5.2 6.2 Max. 3.9 6.1 7.3 9.5 Unit MHz MHz MHz MHz LSB4 Notes tADACK = 1/ fADACK

fADACK

See Reference Manual chapter for sample times 12-bit modes <12-bit modes 12-bit modes <12-bit modes 4 1.4 0.7 0.2 1.0 0.5 -4 -1.4 -1 to 0 -5.4 -1.8 0.5 6 12.8 11.9 14.5 13.8 bits bits LSB4 LSB4 VADIN = VDDA 5 -2.7 to +1.9 -0.7 to +0.5 <12-bit modes 12-bit modes <12-bit modes LSB4 5 6.8 2.1 -1.1 to +1.9 -0.3 to 0.5 12-bit modes LSB4 5 5

DNL

INL

Integral nonlinearity

EFS

Full-scale error

EQ

Quantization error

16-bit modes 13-bit modes

ENOB

Effective number 16-bit differential mode of bits Avg = 32 Avg = 4 16-bit single-ended mode Avg = 32 Avg = 4

12.2 11.4

13.9 13.1 6.02 ENOB + 1.76

bits bits dB 7

SINAD THD

Signal-to-noise plus distortion Total harmonic distortion

See ENOB 16-bit differential mode Avg = 32 16-bit single-ended mode Avg = 32

94 -85

dB dB 7

SFDR

Spurious free dynamic range

16-bit differential mode Avg = 32 16-bit single-ended mode Avg = 32 82 78 95 90 dB dB

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 20. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol EIL Description Input leakage error Conditions1 Min. Typ.2 IIn RAS Max. Unit mV Notes IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope VTEMP25 Temp sensor voltage Across the full temperature range of the device 25 C 1.715 719 mV/C mV

1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode

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Peripheral operating requirements and behaviors

Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

6.6.2 CMP and 6-bit DAC electrical specifications


Table 21. Comparator and 6-bit DAC electrical specifications
Symbol VDD IDDHS IDDLS VAIN VAIO VH Description Supply voltage Supply current, high-speed mode (EN = 1, PMODE = 1) Supply current, low-speed mode (EN = 1, PMODE = 0) Analog input voltage Analog input offset voltage Analog comparator hysteresis1 VDD 0.5 20 80 5 10 20 30 50 250 0.5 200 600 mV mV mV mV V V ns ns CR0[HYSTCTR] = 00 CR0[HYSTCTR] = 01 CR0[HYSTCTR] = 10 CR0[HYSTCTR] = 11 VCMPOh VCMPOl tDHS tDLS Output high Output low Propagation delay, high-speed mode (EN = 1, PMODE = 1) Propagation delay, low-speed mode (EN = 1, PMODE = 0) Min. 1.71 VSS Typ. Max. 3.6 200 20 VDD 20 Unit V A A V mV

Table continues on the next page...

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Freescale Semiconductor, Inc. 35

Peripheral operating requirements and behaviors

Table 21. Comparator and 6-bit DAC electrical specifications (continued)


Symbol IDAC6b INL DNL Description Analog comparator initialization delay2 6-bit DAC current adder (enabled) 6-bit DAC integral non-linearity 6-bit DAC differential non-linearity Min. 0.5 0.3 Typ. 7 Max. 40 0.5 0.3 Unit s A LSB3 LSB

1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD 0.7 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64
CMP Hysteresis vs Vinn
90.00E-03

80.00E-03

70.00E-03

60.00E-03 CMP Hysteresis (V)

50.00E-03

HYSTCTR S etting
0 1

40.00E-03

2 3

30.00E-03

20.00E-03

10.00E-03

000.00E+00 0.1 0.4 0.7 1 1.3 1.6 Vinn (V) 1.9 2.2 2.5 2.8 3.1

Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)


CMP Hysteresis vs Vinn
180.00E-03

160.00E-03

140.00E-03

120.00E-03

CMP Hysteresis (V)

100.00E-03

HYS TCTR S etting


0 1 2 3

80.00E-03

60.00E-03

40.00E-03

20.00E-03

000.00E+00 0.1 -20.00E-03 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1

Vinn (V)

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

6.6.3 12-bit DAC electrical characteristics

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36 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.6.3.1
Symbol VDDA VDACR TA CL IL

12-bit DAC operating requirements


Desciption Supply voltage Reference voltage Temperature Output load capacitance Output load current

Table 22. 12-bit DAC operating requirements


Min. 1.71 1.13 Max. 3.6 3.6 Unit V V C pF mA 2 1 Notes

Operating temperature range of the device 100 1

1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT) 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

6.6.3.2
Symbol
P

12-bit DAC operating behaviors


Description Min. VDACR 100 60

Table 23. 12-bit DAC operating behaviors


Typ. 100 15 0.7 0.4 0.1 3.7 0.000421 Max. 250 900 200 30 1 100 VDACR 8 1 1 0.8 0.6 90 250 Unit A A s s s mV mV LSB LSB LSB %FSR %FSR dB V/C %FSR/C 6 2 3 4 5 5 1 1 1 Notes

IDDA_DACL Supply current low-power mode IDDA_DACH Supply current high-speed mode
P

tDACLP tDACHP

Full-scale settling time (0x080 to 0xF7F) low-power mode Full-scale settling time (0x080 to 0xF7F) high-power mode

tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) low-power mode and high-speed mode Vdacoutl Vdacouth INL DNL DNL DAC output voltage range low high-speed mode, no load, DAC set to 0x000 DAC output voltage range high highspeed mode, no load, DAC set to 0xFFF Integral non-linearity error high speed mode Differential non-linearity error VDACR > 2 V Differential non-linearity error VDACR = VREF_OUT Gain error Power supply rejection ratio, VDDA 2.4 V Temperature coefficient offset voltage Temperature coefficient gain error Output resistance load = 3 k

VOFFSET Offset error EG PSRR TCO TGE Rop

Table continues on the next page...

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 37

Peripheral operating requirements and behaviors

Table 23. 12-bit DAC operating behaviors (continued)


Symbol SR Description Slew rate -80h F7Fh 80h High power (SPHP) Low power (SPLP) BW 3dB bandwidth High power (SPHP) Low power (SPLP) 550 40 1.2 0.05 1.7 0.12 kHz Min. Typ. Max. Unit V/s Notes

1. 2. 3. 4. 5. 6.

Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR 100 mV The DNL is measured for 0 + 100 mV to VDACR 100 mV The DNL is measured for 0 + 100 mV to VDACR 100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device

Figure 11. Typical INL error vs. digital code

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


38 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Figure 12. Offset at half scale vs. temperature

6.7 Timers
See General switching specifications.

6.8 Communication interfaces


6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 39

Peripheral operating requirements and behaviors

6.8.2 USB VREG electrical specifications


Table 24. USB VREG electrical specifications
Symbol VREGIN IDDon IDDstby IDDoff Description Input supply voltage Quiescent current Run mode, load current equal zero, input supply (VREGIN) > 3.6 V Quiescent current Standby mode, load current equal zero Quiescent current Shutdown mode VREGIN = 5.0 V and temperature=25C Across operating voltage and temperature ILOADrun ILOADstby VReg33out Maximum load current Run mode Maximum load current Standby mode Regulator output voltage Input supply (VREGIN) > 3.6 V Run mode Standby mode VReg33out COUT ESR ILIM Regulator output voltage Input supply (VREGIN) < 3.6 V, pass-through mode External output capacitor External output capacitor equivalent series resistance Short circuit current 3 2.1 2.1 1.76 1 3.3 2.8 2.2 290 3.6 3.6 3.6 8.16 100 V V V F m mA 2 650 4 120 1 nA A mA mA Min. 2.7 Typ.1 120 1.1 Max. 5.5 186 10 Unit V A A Notes

1. Typical values assume VREGIN = 5.0 V, Temp = 25 C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

6.8.3 SPI switching specifications


The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 25. SPI master mode timing on slew rate disabled pads
Num. 1 Symbol fop Description Frequency of operation Min. fperiph/2048 Max. fperiph/2 Unit Hz Note 1

Table continues on the next page...

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


40 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 25. SPI master mode timing on slew rate disabled pads (continued)
Num. 2 3 4 5 6 7 8 9 10 11 Symbol tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 25 ns Min. 2 x tperiph 1/2 1/2 tperiph - 30 16 0 0 Max. 2048 x tperiph 1024 x tperiph 10 tperiph - 25 Unit ns tSPSCK tSPSCK ns ns ns ns ns ns Note 2

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph

Table 26. SPI master mode timing on slew rate enabled pads
Num. 1 2 3 4 5 6 7 8 9 10 11 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI tv tHO tRI tFI tRO tFO Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 36 ns Min. fperiph/2048 2 x tperiph 1/2 1/2 tperiph - 30 96 0 0 Max. fperiph/2 2048 x tperiph 1024 x tperiph 52 tperiph - 25 Unit Hz ns tSPSCK tSPSCK ns ns ns ns ns ns Note 1 2

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 41

Peripheral operating requirements and behaviors SS1 (OUTPUT) 3


SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT)

2 5 5

10

11

10

11

6 MISO (INPUT)

7 MSB IN2 BIT 6 . . . 1 8 LSB IN 9 LSB OUT

MOSI (OUTPUT)

MSB OUT2

BIT 6 . . . 1

1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 13. SPI master mode timing (CPHA = 0)


SS1 (OUTPUT) 2
SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT)

10

11

10

11

6 MISO (INPUT)

7 MSB IN2 BIT 6 . . . 1


9

LSB IN

8 MOSI 2 (OUTPUT)PORT DATA MASTER MSB OUT


1.If configured as output

BIT 6 . . . 1

MASTER LSB OUT

PORT DATA

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 14. SPI master mode timing (CPHA = 1) Table 27. SPI slave mode timing on slew rate disabled pads
Num. 1 2 3 4 5 Symbol fop tSPSCK tLead tLag tWSPSCK Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Min. 0 4 x tperiph 1 1 tperiph - 30 Max. fperiph/4 Unit Hz ns tperiph tperiph ns Note 1 2

Table continues on the next page...

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


42 Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 27. SPI slave mode timing on slew rate disabled pads (continued)
Num. 6 7 8 9 10 11 12 13 Symbol tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1. 2. 3. 4. Description Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 25 ns Min. 2 7 0 Max. tperiph tperiph 22 tperiph - 25 Unit ns ns ns ns ns ns ns Note 3 4

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state

Table 28. SPI slave mode timing on slew rate enabled pads
Num. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol fop tSPSCK tLead tLag tWSPSCK tSU tHI ta tdis tv tHO tRI tFI tRO tFO 1. 2. 3. 4. Description Frequency of operation SPSCK period Enable lead time Enable lag time Clock (SPSCK) high or low time Data setup time (inputs) Data hold time (inputs) Slave access time Slave MISO disable time Data valid (after SPSCK edge) Data hold time (outputs) Rise time input Fall time input Rise time output Fall time output 36 ns Min. 0 4 x tperiph 1 1 tperiph - 30 2 7 0 Max. fperiph/4 tperiph tperiph 122 tperiph - 25 Unit Hz ns tperiph tperiph ns ns ns ns ns ns ns ns Note 1 2 3 4

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 43

Peripheral operating requirements and behaviors

SS (INPUT) 2 12 13 4

SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT)

12

13 9

8 MISO (OUTPUT) see note 6 MOSI (INPUT) NOTE: Not defined! SLAVE MSB 7 MSB IN

10 BIT 6 . . . 1

11

11 SEE NOTE

SLAVE LSB OUT

BIT 6 . . . 1

LSB IN

Figure 15. SPI slave mode timing (CPHA = 0)


SS (INPUT) 2
SPSCK (CPOL = 0) (INPUT) SPSCK (CPOL = 1) (INPUT)

4 12 13

12

13

10 MISO (OUTPUT) MOSI (INPUT) NOTE: Not defined! see note 8 SLAVE 6 MSB IN MSB OUT 7

11 BIT 6 . . . 1 SLAVE LSB OUT

BIT 6 . . . 1

LSB IN

Figure 16. SPI slave mode timing (CPHA = 1)

6.8.4 I2C
See General switching specifications.

6.8.5 UART
See General switching specifications.
KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
44 Freescale Semiconductor, Inc.

Dimensions

6.9 Human-machine interfaces (HMI)


6.9.1 TSI electrical specifications
Table 29. TSI electrical specifications
Symbol TSI_RUNF TSI_RUNV TSI_EN TSI_DIS TSI_TEN TSI_CREF TSI_DVOLT Description Fixed power consumption in run mode Variable power consumption in run mode (depends on oscillator's current selection) Power consumption in enable mode Power consumption in disable mode TSI analog enable time TSI reference capacitor Voltage variation of VP & VM around nominal values Min. 1.0 0.19 Type 100 100 1.2 66 1.0 Max 128 1.03 Unit A A A A s pF V

7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. To find a package drawing, go to www.freescale.com and perform a keyword search for the drawings document number:
If you want the drawing for this package 32-pin QFN 48-pin QFN 64-pin LQFP 80-pin LQFP Then use this document number 98ASA00473D 98ASA00466D 98ASS23234W 98ASS23174W

8 Pinout

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 45

Pinout

8.1 KL25 Signal Multiplexing and Pin Assignments


The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
80 64 LQFP LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 48 QFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 QFN 1 2 3 4 5 6 7 8 9 Pin Name PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA PTE29 PTE30 Default DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED VDD VSS USB0_DP USB0_DM VOUT33 VREGIN ADC0_DP0/ ADC0_SE0 ADC0_DM0/ ADC0_SE4a ADC0_DP3/ ADC0_SE3 ADC0_DM3/ ADC0_SE7a VDDA VREFH VREFL VSSA CMP0_IN5/ ADC0_SE4b DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DISABLED DISABLED DISABLED SWD_CLK DISABLED DISABLED SWD_DIO NMI_b DISABLED TSI0_CH1 TSI0_CH2 TSI0_CH3 TSI0_CH4 TSI0_CH5 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN ADC0_DP0/ ADC0_SE0 ADC0_DM0/ ADC0_SE4a ADC0_DP3/ ADC0_SE3 ADC0_DM3/ ADC0_SE7a VDDA VREFH VREFL VSSA CMP0_IN5/ ADC0_SE4b DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE29 PTE30 TPM0_CH2 TPM0_CH3 TPM_CLKIN0 TPM_CLKIN1 PTE20 PTE21 PTE22 PTE23 TPM1_CH0 TPM1_CH1 TPM2_CH0 TPM2_CH1 UART0_TX UART0_RX UART2_TX UART2_RX ALT0 ALT1 PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 SPI1_MOSI SPI1_SCK SPI1_MISO SPI1_PCS0 SPI1_MOSI ALT2 ALT3 UART1_TX UART1_RX ALT4 ALT5 ALT6 I2C1_SDA I2C1_SCL ALT7

RTC_CLKOUT CMP0_OUT SPI1_MISO

23 24 25 26 27 28 29 30 31

19 20 21 22 23 24 25 26 27

15 16 17 18 19 20 21

10 11 12 13 14

PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5

PTE31 PTE24 PTE25 PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 UART0_RX UART0_TX I2C1_SCL I2C1_SDA USB_CLKIN

TPM0_CH4 TPM0_CH0 TPM0_CH1 TPM0_CH5 TPM2_CH0 TPM2_CH1 TPM0_CH0 TPM0_CH1 TPM0_CH2 SWD_DIO NMI_b I2C0_SCL I2C0_SDA SWD_CLK

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


46 Freescale Semiconductor, Inc.

Pinout 80 64 LQFP LQFP 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 48 QFN 22 23 24 25 26 27 28 29 30 31 32 33 34 32 QFN 15 16 17 18 19 20 21 22 Pin Name PTA12 PTA13 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 PTA19 RESET_b PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB8 PTB9 PTB10 PTB11 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 VSS VDD PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 Default DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED VDD VSS EXTAL0 XTAL0 RESET_b ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 DISABLED DISABLED DISABLED DISABLED TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 DISABLED VSS VDD DISABLED DISABLED CMP0_IN0 CMP0_IN0 VSS VDD PTC4/ LLWU_P8 PTC5/ LLWU_P9 PTC6/ LLWU_P10 SPI0_PCS0 SPI0_SCK SPI0_MOSI UART1_TX LPTMR0_ ALT2 EXTRG_IN SPI0_MISO TPM0_CH3 CMP0_OUT TSI0_CH9 TSI0_CH10 TSI0_CH11 TSI0_CH12 ADC0_SE14/ TSI0_CH13 ADC0_SE15/ TSI0_CH14 ADC0_SE11/ TSI0_CH15 ADC0_SE8/ TSI0_CH0 ADC0_SE9/ TSI0_CH6 ADC0_SE12/ TSI0_CH7 ADC0_SE13/ TSI0_CH8 VDD VSS EXTAL0 XTAL0 PTA18 PTA19 PTA20 PTB0/ LLWU_P5 PTB1 PTB2 PTB3 PTB8 PTB9 PTB10 PTB11 PTB16 PTB17 PTB18 PTB19 PTC0 PTC1/ LLWU_P6/ RTC_CLKIN PTC2 PTC3/ LLWU_P7 I2C1_SCL SPI1_PCS0 SPI1_SCK SPI1_MOSI SPI1_MISO UART0_RX UART0_TX TPM2_CH0 TPM2_CH1 EXTRG_IN TPM0_CH0 CMP0_OUT TPM_CLKIN0 TPM_CLKIN1 SPI1_MISO SPI1_MOSI I2C0_SCL I2C0_SDA I2C0_SCL I2C0_SDA TPM1_CH0 TPM1_CH1 TPM2_CH0 TPM2_CH1 EXTRG_IN UART1_RX UART1_TX TPM_CLKIN0 TPM_CLKIN1 LPTMR0_ ALT1 ALT0 ALT1 PTA12 PTA13 PTA14 PTA15 PTA16 PTA17 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO ALT2 ALT3 TPM1_CH0 TPM1_CH1 UART0_TX UART0_RX SPI0_MISO SPI0_MOSI ALT4 ALT5 ALT6 ALT7

57 58 59 60 61 62 63

45 46 47 48 49 50 51

35 36 37 38 39

23 24 25 26 27

I2C1_SDA UART1_RX

TPM0_CH1 TPM0_CH2 CLKOUT

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 47

Pinout 80 64 LQFP LQFP 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 52 53 54 55 56 57 58 59 60 61 62 63 64 48 QFN 40 41 42 43 44 45 46 47 48 32 QFN 28 29 30 31 32 Pin Name PTC7 PTC8 PTC9 PTC10 PTC11 PTC12 PTC13 PTC16 PTC17 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 Default CMP0_IN1 CMP0_IN2 CMP0_IN3 DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED DISABLED ADC0_SE5b DISABLED DISABLED DISABLED ADC0_SE6b ADC0_SE7b DISABLED ADC0_SE6b ADC0_SE7b ADC0_SE5b ALT0 CMP0_IN1 CMP0_IN2 CMP0_IN3 ALT1 PTC7 PTC8 PTC9 PTC10 PTC11 PTC12 PTC13 PTC16 PTC17 PTD0 PTD1 PTD2 PTD3 PTD4/ LLWU_P14 PTD5 PTD6/ LLWU_P15 PTD7 SPI0_PCS0 SPI0_SCK SPI0_MOSI SPI0_MISO SPI1_PCS0 SPI1_SCK SPI1_MOSI SPI1_MISO UART2_RX UART2_TX UART2_RX UART2_TX UART0_RX UART0_TX TPM0_CH0 TPM0_CH1 TPM0_CH2 TPM0_CH3 TPM0_CH4 TPM0_CH5 SPI1_MISO SPI1_MOSI SPI0_MISO SPI0_MOSI ALT2 SPI0_MISO I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA TPM_CLKIN0 TPM_CLKIN1 TPM0_CH4 TPM0_CH5 ALT3 ALT4 ALT5 SPI0_MOSI ALT6 ALT7

8.2 KL25 Pinouts


The below figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section.

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


48 Freescale Semiconductor, Inc.

Pinout

PTD6/LLWU_P15

PTD4/LLWU_P14

PTC6/LLWU_P10

PTC12

PTC13

PTC11

PTC10

PTD2

PTD7

PTD5

PTD3

PTD1

PTC9

PTC8

PTD0

71

PTC7

PTC5/LLWU_P9 62

PTC17

79

75

72

69

80

78

76

68

70

67

66

65

64

77

74

PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 25 26 28 29 31 23 24 27 32 35 30 36 33 34 37 38 39 40

73

63

61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

PTC4/LLWU_P8

PTC16

VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB19 PTB18 PTB17 PTB16 PTB11 PTB10 PTB9 PTB8 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19

PTE29

PTE30

PTE25

PTA0

PTA3

PTA5

PTE31

PTE24

PTA12

PTA15

PTA16

PTA13

PTA14

Figure 17. KL25 80-pin LQFP pinout diagram

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 49

PTA17

PTA18

PTA1

PTA2

PTA4

VDD

VSS

Pinout

PTD6/LLWU_P15

PTD4/LLWU_P14

PTC6/LLWU_P10

PTD0

PTC9

PTD7

PTC8

61

62

59

55

52

51

PTC5/LLWU_P9 50

PTC11

PTD3

PTD1

58

64

60

57

56

54

PTE0 PTE1 VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 PTE22 PTE23 VDDA VREFH VREFL VSSA

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 25 26 23 24 27 28 29 31 17 18 19 20 30

63

53

49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

PTC4/LLWU_P8

PTC10

PTD5

PTD2

PTC7

VDD VSS PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB19 PTB18 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19

PTE30

PTE31

PTE29

PTE24

PTE25

PTA0

PTA3

PTA12

PTA13

PTA4

VSS

Figure 18. KL25 64-pin LQFP pinout diagram

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


50 Freescale Semiconductor, Inc.

PTA18

PTA1

PTA2

PTA5

VDD

Pinout

PTD6/LLWU_P15

PTD4/LLWU_P14

PTC6/LLWU_P10

PTC5/LLWU_P9
38

48

46

45

47

44

43

42

41

40

39

37

PTC4/LLWU_P8

PTD7

PTD5

PTD3

PTD2

PTD1

PTD0

PTC7

VDD VSS USB0_DP USB0_DM VOUT33 VREGIN PTE20 PTE21 VDDA VREFH VREFL VSSA

1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 13 14 15 16 17 18 19 20 24

36 35 34 33 32 31 30 29 28 27 26 25

PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTC0 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0/LLWU_P5 RESET_b PTA19

PTE24

PTE25

PTA1

PTA2

PTE29

PTE30

PTA0

PTA3

PTA4

VDD

Figure 19. KL25 48-pin QFN pinout diagram

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


Freescale Semiconductor, Inc. 51

PTA18

VSS

Revision History

PTD6/LLWU_P15

PTD4/LLWU_P14

PTC6/LLWU_P10

PTC5/LLWU_P9
26

32

31

29

30

28

27

25

PTC4/LLWU_P8

PTD7

PTD5

PTC7

PTE0 VSS USB0_DP USB0_DM VOUT33 VREGIN VDDA VSSA

1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9

24 23 22 21 20 19 18 17

PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTB1 PTB0/LLWU_P5 RESET_b PTA19 PTA18

PTA1

PTA2

PTE30

VDD

PTA0

PTA3

Figure 20. KL25 32-pin QFN pinout diagram

9 Revision History
The following table provides a revision history for this document.
Table 30. Revision History
Rev. No. 1 2 3 Date 7/2012 9/2012 9/2012 Substantial Changes Initial NDA release. Completed all the TBDs, initial public release. Updated Signal Multiplexing and Pin Assignments table to add UART2 signals.

KL25 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.


52 Freescale Semiconductor, Inc.

PTA4

VSS

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Document Number: KL25P80M48SF0 Rev. 3, 9/19/2012