Ee101 Jfet 1

EE101: JFET operation and characteristics
M. B. Patil
mbpatil@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay
M. B. Patil, IIT Bombay
Field-eect transistors
Gate
Source
Drain
Gate
Source
Drain
* A Field-Eect Transistor (FET) has a gate (G) terminal which controls the current ow between the other two terminals, viz., source (S) and drain (D).
Gate
Source
Drain
* A Field-Eect Transistor (FET) has a gate (G) terminal which controls the current ow between the other two terminals, viz., source (S) and drain (D). * In simple terms, a FET can be thought of as a resistance connected between S and D, which is a function of the gate voltage VG .
Gate
Source
Drain
* A Field-Eect Transistor (FET) has a gate (G) terminal which controls the current ow between the other two terminals, viz., source (S) and drain (D). * In simple terms, a FET can be thought of as a resistance connected between S and D, which is a function of the gate voltage VG . * The mechanism of gate control varies in dierent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT.
Gate
Source
Drain
* A Field-Eect Transistor (FET) has a gate (G) terminal which controls the current ow between the other two terminals, viz., source (S) and drain (D). * In simple terms, a FET can be thought of as a resistance connected between S and D, which is a function of the gate voltage VG . * The mechanism of gate control varies in dierent types of FETs, e.g., JFET, MESFET, MOSFET, HEMT. * FETs can be used for analog and digital applications. In each case, the fact that the gate is used to control current ow between S and D plays a crucial role.
Junction Field-eect transistors (JFET)

G
2a
Gate S
p+ n Si
D
L G (Not drawn to scale. Typically, L 2a.)

Crosssectional view Source Drain G
Z L
S 3D view
2a
p+ n Si
D
Simplified structure

G
2a
Gate S
p+ n Si
D

Z L
S 3D view
2a
p+ n Si
D
* The n-type region between the top and bottom p + regions oers a resistance to current ow. The resistance depends on VG .

G
2a
Gate S
p+ n Si
D

Z L
S 3D view
2a
p+ n Si
D
* The n-type region between the top and bottom p + regions oers a resistance to current ow. The resistance depends on VG . * We will rst consider the case, VD = VS = 0 V .
JFET with VS = VD = 0 V
neutral depleted
p+ W h
D S
0V
0V
0V
0V
0V
0V
VG = 0 V
VG = 1 V
VG = 2 V
neutral depleted
p+ W h
D S
0V
0V
0V
0V
0V
0V
VG = 0 V
VG = 1 V
VG = 2 V
* The bias across the p -n junction is (VG VS ), i.e., VG , since VS = VD = 0 V .
neutral depleted
p+ W h
D S
0V
0V
0V
0V
0V
0V
VG = 0 V
VG = 1 V
VG = 2 V
* The bias across the p -n junction is (VG VS ), i.e., VG , since VS = VD = 0 V . * As the reverse bias across the junction is increased (by making VG more negative), the depletion region widens, and the resistance oered by the n-region increases.
neutral depleted
p+ W h
D S
0V
0V
0V
0V
0V
0V
VG = 0 V
VG = 1 V
VG = 2 V
* The bias across the p -n junction is (VG VS ), i.e., VG , since VS = VD = 0 V . * As the reverse bias across the junction is increased (by making VG more negative), the depletion region widens, and the resistance oered by the n-region increases. * When the reverse bias becomes large enough, the depletion region consumes the entire n-region. The corresponding VG is called the pinch-o voltage.
JFET: pinch-o voltage
neutral depleted S
p+ W h
D
0V
0V
neutral depleted S
p+ W h
D
0V
0V
* VP = VG for which h = 0, i.e., W = a.
neutral depleted S
p+ W h
D
0V
0V
* VP = VG for which h = 0, i.e., W = a. s 2 (Vbi V ) * For a p + -n junction, W = , where Vbi is the built-in potential of q Nd the junction.
neutral depleted S
p+ W h
D
0V
0V
* VP = VG for which h = 0, i.e., W = a. s 2 (Vbi V ) * For a p + -n junction, W = , where Vbi is the built-in potential of q Nd the junction. s 2 (Vbi V ) * For pinch-o, W = a = q Nd q Nd a 2 . VP = Vbi 2
neutral depleted S
p+ W h
D
0V
0V
neutral depleted S
p+ W h
D
0V
0V
s * For pinch-o, W = a =
2 (Vbi V ) q Nd a 2 VP = Vbi . q Nd 2
neutral depleted S
p+ W h
D
0V
0V
* Example: Nd = 2 1015 cm3 , a = 1.5 m, Vbi = 0.8 V .
neutral depleted S
p+ W h
D
0V
0V
* Example: Nd = 2 1015 cm3 , a = 1.5 m, Vbi = 0.8 V . W = 0.8 (1.6 1019 Coul)(2 1015 cm3 )((1.5 104 )2 cm2 ) 2 11.7 8.85 1014 F /cm
= 0.8 3.48 2.7 V .
neutral depleted S
p+ W h
D
0V
0V
* Example: Nd = 2 1015 cm3 , a = 1.5 m, Vbi = 0.8 V . W = 0.8 (1.6 1019 Coul)(2 1015 cm3 )((1.5 104 )2 cm2 ) 2 11.7 8.85 1014 F /cm
= 0.8 3.48 2.7 V . If a gate voltage VG = 2.7 V is applied, the n-channel gets pinched o, and the device resistance becomes very large.
JFET with VG = constant, VD = 0 V
neutral depleted
p+ W h
D S
W h
0V
0V
0V
VD = 0 V
VD = 0.05 V
V (x)
VD = 1 V 1V
0V
neutral depleted
p+ W h
D S
W h
0V
0V
0V
VD = 0 V
VD = 0.05 V
V (x)
VD = 1 V 1V
0V
* Consider an n-JFET with VG constant (and not in pinch-o mode).
neutral depleted
p+ W h
D S
W h
0V
0V
0V
VD = 0 V
VD = 0.05 V
V (x)
VD = 1 V 1V
0V
* Consider an n-JFET with VG constant (and not in pinch-o mode). If a positive VD is applied, the potential V (x ) inside the channel from S to D (along the dashed line) increases from 0 V to VD .
neutral depleted
p+ W h
D S
W h
0V
0V
0V
VD = 0 V
VD = 0.05 V
V (x)
VD = 1 V 1V
0V
* Consider an n-JFET with VG constant (and not in pinch-o mode). If a positive VD is applied, the potential V (x ) inside the channel from S to D (along the dashed line) increases from 0 V to VD . Note that W and h are now functions of x such that, W (x ) + h(x ) = a.
neutral depleted
p+ W h
D S
W h
0V
0V
0V
VD = 0 V
VD = 0.05 V
V (x)
VD = 1 V 1V
0V
* Consider an n-JFET with VG constant (and not in pinch-o mode). If a positive VD is applied, the potential V (x ) inside the channel from S to D (along the dashed line) increases from 0 V to VD . Note that W and h are now functions of x such that, W (x ) + h(x ) = a. * Since the p -n junction bias at a given x is (VG V (x )), the drain end of the channel has a larger reverse bias than the source end.
neutral depleted
p+ W h
D S
W h
0V
0V
0V
VD = 0 V
VD = 0.05 V
V (x)
VD = 1 V 1V
0V
* Consider an n-JFET with VG constant (and not in pinch-o mode). If a positive VD is applied, the potential V (x ) inside the channel from S to D (along the dashed line) increases from 0 V to VD . Note that W and h are now functions of x such that, W (x ) + h(x ) = a. * Since the p -n junction bias at a given x is (VG V (x )), the drain end of the channel has a larger reverse bias than the source end. the depletion region is wider at the drain.
JFET: derivation of ID equation

y
G
a x
W h
Area = 2 h Z
D
2h
0V
Z
G
VD x
0V

y
G
a x
W h
Area = 2 h Z
D
2h
0V
Z
G
VD x
0V
Consider a slice of the device. The current density at any point in the neutral region is assumed to be in the x direction, and given by, dn dV Jn = q n nE + qDn q n nE = q n Nd , dx dx

y
G
a x
W h
Area = 2 h Z
D
2h
0V
Z
G
VD x
0V
Consider a slice of the device. The current density at any point in the neutral region is assumed to be in the x direction, and given by, dn dV Jn = q n nE + qDn q n nE = q n Nd , dx dx dn where we have neglected the diusion current, since n Nd = 0. dx

y
G
a x
W h
Area = 2 h Z
D
2h
0V
Z
G
VD x
0V
Consider a slice of the device. The current density at any point in the neutral region is assumed to be in the x direction, and given by, dn dV Jn = q n nE + qDn q n nE = q n Nd , dx dx dn where we have neglected the diusion current, since n Nd = 0. dx Note that only the neutral part of the n-Si conducts since there are no carriers in the depletion regions.

y
G
a x
W h
Area = 2 h Z
D
2h
0V
Z
G
VD x
0V
Consider a slice of the device. The current density at any point in the neutral region is assumed to be in the x direction, and given by, dn dV Jn = q n nE + qDn q n nE = q n Nd , dx dx dn where we have neglected the diusion current, since n Nd = 0. dx Note that only the neutral part of the n-Si conducts since there are no carriers in the depletion regions. At a given x, the current ID is obtained by integrating Jn over the area of the neutral channel region (see gure on the right). Since Jn is constant over this area,

y
G
a x
W h
Area = 2 h Z
D
2h
0V
Z
G
VD x
0V
Consider a slice of the device. The current density at any point in the neutral region is assumed to be in the x direction, and given by, dn dV Jn = q n nE + qDn q n nE = q n Nd , dx dx dn where we have neglected the diusion current, since n Nd = 0. dx Note that only the neutral part of the n-Si conducts since there are no carriers in the depletion regions. At a given x, the current ID is obtained by integrating Jn over the area of the neutral channel region (see gure on the right). Since Jn is constant over this area, ZZ dV dV W ID ( x ) = Jn dx dz = 2hZ q n Nd = 2qZ n Nd a 1 , dx dx a where we have used h = a W , i.e., h = a(1 W /a).

y
G
a x
W h
0V
ID (x ) = 2 q Z n Nd a
dV dx
W 1 . a

y
G
a x
W h
0V
dV dx
W 1 . a
Since ID (x ) is constant from x = 0 to x = L, we get, s ! Z L Z V q D 2 1 ID dx = ID L = 2qZ n Nd a Vbi (VG V ) dV , 2 qNd a 0 0 where we have used, for the depletion width W , s 2 W (x ) = [Vbi (VG V )] . qNd

y
G
a x
W h
0V
dV dx
W 1 . a
Since ID (x ) is constant from x = 0 to x = L, we get, s ! Z L Z V q D 2 1 ID dx = ID L = 2qZ n Nd a Vbi (VG V ) dV , 2 qNd a 0 0 where we have used, for the depletion width W , s 2 W (x ) = [Vbi (VG V )] . qNd qNd a2 Evaluating the integral and using Vbi VP = , we get (do this!) 2 ( " 3/2 #) 2 VD + Vbi VG Vbi VG 3/2 ID = G0 VD (Vbi VP ) , 3 Vbi VP Vbi VP where G0 = 2qZ n Nd a/L.

y
G
a x
W h
0V
dV dx
W 1 . a
Since ID (x ) is constant from x = 0 to x = L, we get, s ! Z L Z V q D 2 1 ID dx = ID L = 2qZ n Nd a Vbi (VG V ) dV , 2 qNd a 0 0 where we have used, for the depletion width W , s 2 W (x ) = [Vbi (VG V )] . qNd qNd a2 Evaluating the integral and using Vbi VP = , we get (do this!) 2 ( " 3/2 #) 2 VD + Vbi VG Vbi VG 3/2 ID = G0 VD (Vbi VP ) , 3 Vbi VP Vbi VP where G0 = 2qZ n Nd a/L. Note that G0 is the channel conductance if there was no depletion, i.e., if h(x ) = a throughout the channel.
Special case: VD 0 V
y
G neutral depleted G
p+ W h
D
a x
W h
0V
0V
VD 0 V
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #)
y
p+ W h
D
a x
W h
0V
0V
VD 0 V
ID = G 0
#) Vbi VG 3/2 VD + Vbi VG 3/2 Vbi VP Vbi VP 2 1 /2 3 1 /2 G0 VD (Vbi VP ) VD (Vbi VG ) (using Taylors series) 3 2 ( VD 2 (Vbi VP ) 3 "
y
p+ W h
D
a x
W h
0V
0V
VD 0 V
ID = G 0
#) Vbi VG 3/2 VD + Vbi VG 3/2 Vbi VP Vbi VP 2 1 /2 3 1 /2 G0 VD (Vbi VP ) VD (Vbi VG ) (using Taylors series) 3 2 ( ) Vbi VG 1/2 = G0 VD 1 . Vbi VP ( VD 2 (Vbi VP ) 3 "
y
p+ W h
D
a x
W h
0V
0V
VD 0 V
ID = G 0
#) Vbi VG 3/2 VD + Vbi VG 3/2 Vbi VP Vbi VP 2 1 /2 3 1 /2 G0 VD (Vbi VP ) VD (Vbi VG ) (using Taylors series) 3 2 ( ) Vbi VG 1/2 = G0 VD 1 . Vbi VP ( VD 2 (Vbi VP ) 3 " 2 2 1 /2 1 /2 (Vbi VG ) , and a = (Vbi VP ) , we get qNd qNd
Since W =
y
p+ W h
D
a x
W h
0V
0V
VD 0 V
ID = G 0
2 2 1 /2 1 /2 (Vbi VG ) , and a = (Vbi VP ) , we get qNd qNd W ID = G 0 V D 1 . a Since W =
y
p+ W h
D
a x
W h
0V
0V
VD 0 V
ID = G 0
2 2 1 /2 1 /2 (Vbi VG ) , and a = (Vbi VP ) , we get qNd qNd W ID = G 0 V D 1 . a This simply shows that the channel conductance reduces linearly with W (as seen before the Since W = VS = VS = 0 V condition), and for VG = VP (i.e., W = a), the conductance becomes zero.
JFET: pinch-o near drain

200
G 150
V G =0 V ID (A) W h
a x
0V
100
50 G 0
VG =1 V VG =2 V
VD (Volts)
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .

200
G 150
V G =0 V ID (A) W h
a x
0V
100
50 G 0
VG =1 V VG =2 V
VD (Volts)
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
For a given VG , ID reaches a maximum at VD = VG VP (show this by dierentiating the above equation).

200
G 150
V G =0 V ID (A) W h
a x
0V
100
50 G 0
VG =1 V VG =2 V
VD (Volts)
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
For a given VG , ID reaches a maximum at VD = VG VP (show this by dierentiating the above equation). At this value of VD , the bias across the p -n junction at the drain end is VG VD = VP .

200
G 150
V G =0 V ID (A) W h
a x
0V
100
50 G 0
VG =1 V VG =2 V
VD (Volts)
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
For a given VG , ID reaches a maximum at VD = VG VP (show this by dierentiating the above equation). At this value of VD , the bias across the p -n junction at the drain end is VG VD = VP . In other words, the drain end of the channel has just reached pinch-o.

200
G 150
V G =0 V ID (A) W h
a x
0V
100
50 G 0
VG =1 V VG =2 V
VD (Volts)
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
G
D pinchoff
0V
G

200
G 150
V G =0 V ID (A) W h
a x
0V
100
50 G 0
VG =1 V VG =2 V
VD (Volts)
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
G
D pinchoff
0V
What happens if VD is increased further?

JFET: saturation
G G G G
0V
0V
0V
0V
A VD 0 V
sat B V D < VD ID
sat C VD = VD
sat D V D > VD
C B
A
sat = V V VD G P VD
Consider a xed VG with VD varying from 0 V to a value beyond condition C.
JFET: saturation
G G G G
0V
0V
0V
0V
A VD 0 V
sat B V D < VD ID
sat C VD = VD
sat D V D > VD
C B
A
sat = V V VD G P VD

sat , a short high-eld region develops near the drain end, and the In this situation, i.e., VD > VD sat excess voltage, VD VD drops across this region.
JFET: saturation
G G G G
0V
0V
0V
0V
A VD 0 V
sat B V D < VD ID
sat C VD = VD
sat D V D > VD
C B
A
sat = V V VD G P VD

Because the high-led region is conned to a very small distance, the conditions in the device are almost identical in C and D.
JFET: saturation
G G G G
0V
0V
0V
0V
A VD 0 V
sat B V D < VD ID
sat C VD = VD
sat D V D > VD
C B
A
sat = V V VD G P VD

Because the high-led region is conned to a very small distance, the conditions in the device are almost identical in C and D. The current in case D is almost the same as that for case C.
JFET: saturation
G G G G
0V
0V
0V
0V
A VD 0 V
sat B V D < VD ID
sat C VD = VD
sat D V D > VD
C B
A
sat = V V VD G P VD

Because the high-led region is conned to a very small distance, the conditions in the device are almost identical in C and D. The current in case D is almost the same as that for case C.
sat The region VD > VD is therefore called the saturation region.
JFET: example
An n-channel silicon JFET has the following parameters (at T = 300 K ): a = 1.5 m, L = 5 m, Z = 50 m, Nd = 2 1015 cm3 , Vbi = 0.8 V , n = 300 cm2 /V -sec. (a) What is the pinch-o voltage? (b) Write a program to generate ID -VD characteristics for VG = 0 V , 0.5 V , 1 V , 1.5 V , 2 V .
sat (c) For each of the above VG values, compute VD , and show it on the ID -VD plot. The part of sat an ID -VD corresponding to VD < VD is called the linear region, and that corresponding sat to VD > VD is called the saturation region.
JFET: example
An n-channel silicon JFET has the following parameters (at T = 300 K ): a = 1.5 m, L = 5 m, Z = 50 m, Nd = 2 1015 cm3 , Vbi = 0.8 V , n = 300 cm2 /V -sec. (a) What is the pinch-o voltage? (b) Write a program to generate ID -VD characteristics for VG = 0 V , 0.5 V , 1 V , 1.5 V , 2 V .
sat (c) For each of the above VG values, compute VD , and show it on the ID -VD plot. The part of sat an ID -VD corresponding to VD < VD is called the linear region, and that corresponding sat to VD > VD is called the saturation region.
Answer: (a) VP = 2.68 V . (b)

200 linear saturation
V G =0 V
150
ID (A)
0.5 V
100
1 V
50
1.5 V 2 V
1 2 3 4 5
VD (Volts)
JFET: simplied model for saturation
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
sat At saturtation, VD = VG VP , giving ( " #) Vbi VG 3/2 2 sat . ID = G0 VD (Vbi VP ) 1 3 Vbi VP
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .
The following approximate model is found to be adequate in circuit design:

sat sat (VG ) = IDSS (1 VG /VP )2 , where IDSS = ID (VG = 0 V ). ID
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .

sat sat (VG ) = IDSS (1 VG /VP )2 , where IDSS = ID (VG = 0 V ). ID ID , which is obtained as: In amplier design, we are interested in gm = VG V =constant D
( ID = G 0 VD
2 (Vbi VP ) 3
"
VD + Vbi VG Vbi VP
3/2
Vbi VG Vbi VP
3/2 #) .

sat sat (VG ) = IDSS (1 VG /VP )2 , where IDSS = ID (VG = 0 V ). ID ID , which is obtained as: In amplier design, we are interested in gm = VG V =constant D
gm = gm0 (1 VG /VP ), where gm0 = 2IDSS /VP = gm (VG = 0 V ).
JFET: source/drain resistances
p+
2a
S
n Si
D
S RS
S
G
D RD

Crosssectional view
JFET: source/drain resistances
p+
2a
S
n Si
D
S RS
S
G
D RD

Crosssectional view
In real JFETs, there is a separation between the source/drain contacts and the active channel. The n-type semiconductor regions between the active channel and the source/drain contacts can be modelled by resistances RS and RD .
JFET: small-signal model

VDD
D
R Vo RG
Cgd Cgs gm vg gd V1
G S
vg
V2 RG
VSS
Amplifier example
* A small-signal model of a JFET is required in analysis of an amplier.

VDD
D
R Vo RG
Cgd Cgs gm vg gd V1
G S
vg
V2 RG
VSS
Amplifier example
* A small-signal model of a JFET is required in analysis of an amplier. * The DC gate current, which is the reverse current of a p -n junction, is generally insignicant and is therefore ignored.

VDD
D
R Vo RG
Cgd Cgs gm vg gd V1
G S
vg
V2 RG
VSS
Amplifier example
* A small-signal model of a JFET is required in analysis of an amplier. * The DC gate current, which is the reverse current of a p -n junction, is generally insignicant and is therefore ignored. ID * gm = with VD = constant. VG

VDD
D
R Vo RG
Cgd Cgs gm vg gd V1
G S
vg
V2 RG
VSS
Amplifier example
* A small-signal model of a JFET is required in analysis of an amplier. * The DC gate current, which is the reverse current of a p -n junction, is generally insignicant and is therefore ignored. ID * gm = with VD = constant. VG ID with VG = constant. * gd = VD

VDD
D
R Vo RG
Cgd Cgs gm vg gd V1
G S
vg
V2 RG
VSS
Amplifier example
* A small-signal model of a JFET is required in analysis of an amplier. * The DC gate current, which is the reverse current of a p -n junction, is generally insignicant and is therefore ignored. ID * gm = with VD = constant. VG ID with VG = constant. * gd = VD * gm and gd can be obtained by dierentiating ID (VG , VD ). Note that, in our simple model, short-channel eects have not been included; we would therefore obtain gd = 0 in saturation. However, a real device would show a small increase in ID with an increase in VD in saturation, giving rise to a non-zero gd .

VDD
D
R Vo RG
Cgd Cgs gm vg gd V1
G S
vg
V2 RG
VSS
Amplifier example
* A small-signal model of a JFET is required in analysis of an amplier. * The DC gate current, which is the reverse current of a p -n junction, is generally insignicant and is therefore ignored. ID * gm = with VD = constant. VG ID with VG = constant. * gd = VD * gm and gd can be obtained by dierentiating ID (VG , VD ). Note that, in our simple model, short-channel eects have not been included; we would therefore obtain gd = 0 in saturation. However, a real device would show a small increase in ID with an increase in VD in saturation, giving rise to a non-zero gd . * The capacitances Cgs and Cgd are depletion capacitances of the p -n junction.

Ee101 Jfet 1

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Ee101 Jfet 1

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EE101: JFET operation and characteristics

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

Junction Field-eect transistors (JFET)

L G (Not drawn to scale. Typically, L 2a.)

M. B. Patil, IIT Bombay

Junction Field-eect transistors (JFET)

L G (Not drawn to scale. Typically, L 2a.)

M. B. Patil, IIT Bombay

Junction Field-eect transistors (JFET)

L G (Not drawn to scale. Typically, L 2a.)

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* The bias across the p -n junction is (VG VS ), i.e., VG , since VS = VD = 0 V .

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

* VP = VG for which h = 0, i.e., W = a.

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

* Example: Nd = 2 1015 cm3 , a = 1.5 m, Vbi = 0.8 V .

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

= 0.8 3.48 2.7 V .

M. B. Patil, IIT Bombay

JFET: pinch-o voltage

M. B. Patil, IIT Bombay

JFET with VG = constant, VD = 0 V

M. B. Patil, IIT Bombay

JFET with VG = constant, VD = 0 V

* Consider an n-JFET with VG constant (and not in pinch-o mode).

M. B. Patil, IIT Bombay

JFET with VG = constant, VD = 0 V

M. B. Patil, IIT Bombay

JFET with VG = constant, VD = 0 V

M. B. Patil, IIT Bombay

JFET with VG = constant, VD = 0 V

M. B. Patil, IIT Bombay

JFET with VG = constant, VD = 0 V

M. B. Patil, IIT Bombay

JFET: derivation of ID equation

M. B. Patil, IIT Bombay

JFET: derivation of ID equation

M. B. Patil, IIT Bombay

JFET: derivation of ID equation

M. B. Patil, IIT Bombay

JFET: derivation of ID equation

M. B. Patil, IIT Bombay