EL 114 Digital Logic Design

Instructor: Dr. Mazad S. Zaveri Faculty Block 4, Room 4206 Email: mazad_zaveri@daiict.ac.in http://intranet.daiict.ac.in/~mazad_zaveri/

Digital Logic Design

ALU Next weeks Lab

The ALU consists of several logic/arithmetic blocks
The output of each block is connected (via MUX or similar method) to the final output via a MUX
MUX based approach is much simpler (select the appropriate path/switch in the MUX) Other approach, where the MUX (tri-state buffers) are assumed to inside the blocks
Instead of a physical MUX, we simulate the behavior using floating or driven states

Required coding style

Release or take-control of the output bus
Release (make it float, assign 4bzzzz)
So that other blocks can drive the output if required

Take-control (drive the bus, assign some value)

Any other block should not (can not) drive at the same time

Example:
assign Y = (condition1)? (Y_block1) : (4bzzzz); assign Y = (condition2)? (Y_block2) : (4bzzzz); assign Y = (condition3)? (Y_block3) : (4bzzzz); Now depending on the above conditions (two valid cases are possible):
Only one condition can satisfy at any given time
That particular blocks value will be assigned to the output

None of the conditions satisfy at any given time

The output will float (none of the blocks will drive the output)

More than one conditions satisfy at any given time (Not a Valid Case)
This should never happen in your code

Digital Logic Design

Example: Mealy FSM

Sequence detector
Detect a sequence of two consecutive 1s in in the input (w)

Clock cycle: w: z:

t0 0 0

t1 1 0

t2 0 0

t3 1 0

t4 1 1

t5 0 0

t6 1 0

t7 1 1

t8 1 1

t9 0 0

t10 1 0

Digital Logic Design

Mealy FSM State Diagram

Reset w = 1z= 0 w = 0z= 0 A w = 0z= 0 B w = 1z= 1

Digital Logic Design

Mealy FSM State Table

Present state A B

Next state w= 0 A A w= 1 B B

Output z w= 0 0 0 w= 1 0 1

Digital Logic Design

Mealy FSM State Assigned Table

Next state w= 0 Y 0 0 w= 1 Y 1 1 Output w= 0 z 0 0 w= 1 z 0 1

Present state y A B 0 1

Digital Logic Design

Mealy FSM Circuit Diagram

z w Clock D Q Q

Resetn (a) Circuit t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

Clock w y z

1 0 1 0 1 0 1 0

(b) Timing diagram Digital Logic Design

Practice Example Implement a Moore FSM

Switch = 2b00
Green LEDs go ON-OFF, and continues RED LEDs go ON-OFF, and continues Green LEDs go ON-OFF,followed by Red LEDs go ON-OFF, and continues All LEDs go ON-OFF, and continues

Switch = 2b01 Switch = 2b10 Switch = 2b11 The switch can be changed at anytime
When a switch changes, turn the center LED ON-OFF for three times, and then start the new sequence

How many inputs do we have? (two binary inputs, corresponding to the switch) How many outputs do we have? (13 LEDs)

Digital Logic Design

Hazards
Static Hazards
The value of a signal should ideally remain at 0, but it temporarily (glitches) goes to 1 and comes back to 0 The value of a signal should ideally remain at 1, but it temporarily (glitches) goes to 0 and comes back to 1 The signal should ideally transition from 10

Dynamic Hazards
But the signal will transition from 1010 (or more transitions than necessary) But the signal will transition from 0101 (or more transitions than necessary)

The signal should ideally transition from 01

Hazards are important for sequential circuits, because we do not want glitching behavior to happen at the inputs of the Flip-Flops (especially during the setup and hold time windows around the active clock edge)
Generally, the outputs of a combinational block (that implements the next-state logic) will act as the inputs to a FF
If the combinational blocks output glitches, the FF may capture a wrong value

1 0 11 (a) Static hazard 1 0 10 01 (b) Dynamic hazard Digital Logic Design

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