Introduction to SPICE simulator

EE618 TAs
Department Of Electrical Engineering Indian Institute Of Technology, Bombay

August 13, 2012

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What is this SPICE all about?

Stands for Simulation Program with Integrated Circuit Emphasis Used for simulating circuits for verifying performance and optimization Powerful simulator with industry standards Supports different types of analysis like AC, DC, TRAN, PZ, OP etc.

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Why SPICE

Circuits get complex with inreasing number of transistors Analytically solving is impractical Even for small circuits in scaled technologies the number of parameters are far too many Example
The BSIM4 MOS model has about 39 technology dependent parameters!!

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Circuit elements and models

circuit elements and sources are identied by the rst alphabet of their name E* followed by node connections model_parameters, E* element name example R1 a b 100k; inserts a 100k resistor named R1 from net a to net b (net == wire) Elementary components in native spice are
R* => resistor C* => capacitor L* => inductor SW* => switch K* => coupled mutual inductor

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Sources

Elementary sources available are V* => Independent Volatge source

eg V1 1 2 DC/AC/Pulse/Sin/exp/pwl this is a voltage source named V1 between nets 1 and 2 the source may be set to be one of the many types specied example V1 1 2 DC 1V example Vinp in ground sin(voffset, amp, freq, tdelay, damp_factor)

All parameters need not be initialized. Most have default values

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Linear Dependent Sources

Dependent Sources G* => linear voltage controlled current source E* => linear voltage controlled voltage source F* => linear current controlled current source H* => linear current controlled voltage source Nonlinear dependent sources are also available (look at references if interested)

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MOS and BJT device instantiation

M* Drain Gate source substrate model_name W=* L=* Q* Collector Base Emmiter Substrate model_name area=*

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Subciruits

Regular circuits can be described using repeated instantiations of elemental cells Subcircuits description
.subckt ...netlist .ends

Subcircuits are identied by X* port list instance name

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Analysis and output control

DC analysis for DC transfer characteristics

.DC source_name vstart vstop stepsize

AC analysis for frequency response

.AC DEC/OCT/Lin NP fstart fstop .AC DEC 10 10 100M

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Analysis and output control

TRAN analysis for transient time domain simulation

.TRAN TSTEP TSTOP .tran 1u 100u

Operating point analysis .op

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Circuit Description
First line is title line and is ignored by the simulator. This line is printed verbatim on the output screen Comment lines should be preceeded with an * The program le should end with a .end directive multiple les can be included using .include directive. These other les may be subcircuits or model les for custom devices. After describing the circuit and the analysis the program has to be described using .control directive The control block begins with .control and terminates with .endc commands should be issued in this block for saving/printing/plotting outputs Commands not written in the .control block should be preceeded with a .
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Where to start?

create a text le using any text editor and save it with .spice extension in your simulation folder If you are using the tsmc spice model download the model le from the course webpage and include it in your netlist from a terminal CD to your simulation folder and type ngspice le_name.spice to run the simulation

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References

newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/index.html Other references uploaded on your course webpage

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