Beruflich Dokumente
Kultur Dokumente
. However, the all pass lter would also carry distortions from
the input. Others such as [33] and [34] generate the orthogonal component based on a
second order generalised integrator (SOGI). This structure eectively lters out the high
Chapter 1. Introduction 11
frequency distortion on the input and the orthogonal component before they are fed into
the - dq transform. The synchronous frame PLLs, although not explicitly specied,
has the potential to provide sucient phase information to the controller for the reactive
current reference generation. This eectively allows the inverter to have the ability of
controlling reactive power ow. Although this type of PLLs has the aforementioned
merits, its implementation process can be complicated due to the need for an orthogonal
component generator and sin and cos operations in the - dq transform.
This thesis proposes a low complexity grid synchronization method which extracts
both the parallel component and the orthogonal component from the grid voltage while
suciently ltering out grid distortions. The grid synchronizer is easy to implement and
provides the inverter the capability of controlling the reactive power generation without
the need for dq frame transformation.
1.3 Objectives
The objectives of this works are as follows:
Ensure that the voltage on the DC side of the VSI and the output current are well
regulated by choosing appropriate inverter topology, the output lter conguration
and proper control methods.
The output current should meet the standard associated with larger 3-phase PV
inverters as laid out in IEEE-1547. This will enable grid code compliance if a large
number of inverters are clustered together and grid interfaced at the same PCC.
Use high reliable energy storage components (i.e. lm capacitors) to increase the
life-span of the inverter in a low cost manner.
Introduce a new method of grid synchronization which gives the inverter the capa-
bility of controlling the reactive power generation at minimal computational burden.
Chapter 1. Introduction 12
Exploit new generation MOSFETs and low cost MCUs to maximize switching fre-
quency and drive down output lter size and cost.
Chapter 2
Single Phase Grid Connected
Inverter Design
In this chapter, the design of the single phase PV inverter power stage is described,
Figure 2.1. Firstly, the inverter design specications are given. Secondly, based on the
specications, the choice of the switching scheme is briey described. Thirdly, the selec-
tion of the DC-link capacitor is discussed based on its lifetime and size. Following this,
the design equations on DC-link capacitance are developed based on the power balance
and double-line frequency ripple voltage. Finally, the design guide for the output lter
is discussed based on the IEEE-1547 standard and the lter conguration is described.
2.1 Inverter Specications
The basic specications for the inverter design are listed in Table 2.1. Since the design
primarily focuses on the control and the grid synchronization method of the inverter,
the eciency target of the inverter is not specied because it is outside of the scope.
Although maximizing eciency is not the focus of this work, loss considerations still
drive selection of a viable converter topology.
In addition, Figure 2.2 illustrates a general waveform of the DC-link voltage to show
13
Chapter 2. Single Phase Grid Connected Inverter Design 14
v
g
(t)
+
-
i
g
(t)
Lg
Li
Cf
Rd
+
-
sa sb
sa
low
sb
low
i
dc
(t)
Cdc
i
gn
(t)
v
dc
(t)
v
t
(t)
Figure 2.1: Power stage conguration of the single phase PV inverter
the denition of the nominal DC-link voltage and the ripple component.
Rated grid voltage, V
rated
g
250V (RMS)
Rated grid current, I
rated
g
10A (RMS)
Switching frequency range, f
sw
>20kHz,<45kHz
Nominal DC-link voltage, V
n
dc
400V
Percentage DC-link voltage ripple (peak to nominal) 10%
Table 2.1: Inverter specications
2.2 Switching Circuit Conguration
A full bridge conguration with SPWM unipolar voltage switching scheme is used (Fig-
ure 2.3) as the switching circuit of the inverter. By selecting the full bridge conguration,
the minimal allowed DC-link voltage can be set to be the peak value of the AC grid volt-
age (plus margins). Thus, power MOSFETs, instead of higher voltage IGBTs, can be
used as the switching devices which enables use of a high switching frequency (> 20kHz)
without indroduction of excessive switching loss.
Furthermore, showing in Figure 2.3(d), using unipolar voltage switching scheme eec-
Chapter 2. Single Phase Grid Connected Inverter Design 15
v
dc
(t)
v
dc,ripple
(t)
V
dc
n
t
Figure 2.2: Generic DC-link voltage waveform
tively moves the rst major harmonic of the bridge output voltage from order m
f
1 to
the order of 2m
f
1, where m
f
is the frequency modulation ratio - the ratio between the
switching frequency and the fundamental frequency. The output lter thus reduces its
size for free. Since this full bridge conguration with SPWM unipolar voltage switch-
ing scheme is commonly used in voltage sourced inverters, further investigations will not
be presented in this thesis. A full detail analysis can be found in [35].
2.3 DC-link Capacitor
This section discusses the two types of capacitors that can be used as the DC-link buer-
ing capacitor. A brief comparison is made based on their life time and power decoupling
ability. Methods of ensuring the inverters power quality while using a capacitor that has
a small capacitance are also discussed. Finally, the calculation of the DC-link capacitance
is shown in this section.
2.3.1 Electrolytic Capacitors vs. Film Capacitors
The DC-link capacitor is important for the power decoupling between the input power to
the inverter and their output power to the utility grid. Normally, electrolytic capacitors
are used for their large capacitance and low cost. However, in PV applications where the
Chapter 2. Single Phase Grid Connected Inverter Design 16
+
-
vdc(t)
+
-
vt(t)
sa sb
sa
low
sb
low
A
B
(a) Full bridge conguration
t
v
r
e
f
(
-
v
r
e
f )
v
s
a
w
0
(b) Unipolar SPWM switching scheme
t
vdc
-vdc
0
vt
vt,fund(t)
(c) Waveform of the bridge output voltage
dc
h t
v
V)
(
h
0
0.2
0.4
0.6
0.8
1.0
1
mf 2mf 3mf 4mf
(2mf-1) (2mf+1)
(d) Harmonics on the nominlized frequency spectrum
Figure 2.3: Full bridge conguration with PWM unipolar voltage switching scheme
Chapter 2. Single Phase Grid Connected Inverter Design 17
inverters are usually exposed to outdoor temperatures, the lifetime of such electrolytic
capacitors is shorten drastically according to the equation below [8] [36]:
L
op
= L
op
(0) 2
T
0
T
h
T
(2.1)
where L
op
is the operational lifetime, L
op
(0) is the specied operational lifetime at the
hot-spot temperature T
0
(can be found in the product datasheets), T
h
is the operating
temperature and T is the degree Celsius increase that would results in half the oper-
ational life (also can be found in the product datasheet). Typically, L
op
(0) is between
3000 hours to 6000 hours (8 months to 16 months) at 85
= Scos + Scos(2
g
t ) (2.6)
The i
dc
(t) can be separated as a DC component, I
dc
and an AC component, i
dc,ripple
(t).
Then the double-line frequency component can be extracted such that:
V
n
dc
i
dc,ripple
(t) = Scos(2
g
t ) (2.7)
Rearranging the above equation yields:
i
dc,ripple
(t) =
S
V
n
dc
cos(2
g
t ) =
I
dc,ripple
cos(2
g
t ) (2.8)
Chapter 2. Single Phase Grid Connected Inverter Design 20
Then the capacitance of the DC-link capacitor can be easily obtained given the mag-
nitude of the maximum allowed ripple voltage, V
max
dc,ripple
:
C
dc
=
I
dc,ripple
2
g
V
max
dc,ripple
=
S
2
g
V
n
dc
V
max
dc,ripple
(2.9)
Finally, substituting, these parameters from the inverter specications.
C
dc
=
2.5kV A
2 377rad/s 400V 40V
= 207.2F (2.10)
Based on this, a 230F Cornell Dubilier lm type capacitor which as a life expectancy
of 200,000 hours (44 years) at 60
Vg=0
=
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(2.11)
I
g
(s)
V
g
(s)
Vt=0
=
s
2
L
i
C
f
+ sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(2.12)
From the above Equation (2.11) and (2.12), one can observe that the grid current i
g
(t)
1
IEEE-1547 directly references the grid current harmonic distortion limits for general distribution
systems stated in IEEE-519 [38]
2
TDD: the total root-sum-square harmonic current distortion, in percent of the maximum demand
load current or the rated DR current capacity [1]
Chapter 2. Single Phase Grid Connected Inverter Design 22
depends on both the terminal voltage v
t
(t) and the grid voltage v
g
(t). As discussed before,
the output lter design will not take harmonic grid voltage distortion into consideration
because IEEE-1547 allows the presence of harmonic current distortion caused by grid
voltage distortion. Therefore, Equation (2.12) will not be taken into consideration in
output lter design.
The terminal voltage v
t
(t) contains a fundamental component and higher frequency
components which could result in higher frequency distortions on the grid current i
g
(t).
Therefore, Equation (2.11) is used as the output lter transfer function as:
H
f
(s) =
I
g
(s)
V
t
(s)
Vg=0
=
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(2.13)
The RMS value of the higher order frequency components of v
t
(t) can be calculated
using the look up table from [35] (refer to Appendix C), given the nominal DC-link
voltage V
n
dc
:
|V
t
(jh
g
)| =
1
2
2
(
V
Ao
)
h
1/2V
n
dc
V
n
dc
2
=
1
2
k(h)V
n
dc
(2.14)
The (
V
Ao
)
h
is the peak value of each harmonic voltage between one leg of the bridge
and the centre point of the DC-link, v
Ao
(t). In full bridge conguration, v
t
(t) = 2v
Ao
(t).
k(h) =
(
V
Ao
)
h
1/2V
n
dc
is tabulated as a function of m
a
and the orders of harmonics (refer to
Appendix C for details about the harmonics table). Therefore, combining (2.13) and
(2.14), the RMS value of the harmonic current can be expressed as:
|I
g
(jh
g
)| =
1
2
|H
f
(jh
g
)| k(h) V
n
dc
(2.15)
Remember that |I
g
(jh
g
)| can not exceed 0.3% of the rated current of the inverter.
Therefore, given the RMS value of the rated grid current I
rated
g
the following relationship
can be derived:
Chapter 2. Single Phase Grid Connected Inverter Design 23
0dB
g i
L L
1
g i f
g i
L L C
L L
-70dB
376614
-20dB/dec
-60dB/dec
PeakdependsonR
d
|Hf(jw)|
Figure 2.5: Magnitude plot of the output lter transfer function H
f
(s)
|H
f
(jh
g
)| k(h) V
n
dc
2 I
rated
g
< 0.3% (2.16)
Rewrite for |H
f
(jh
g
)|, then
|H
f
(jh
g
)| <
0.3%
2 I
rated
g
V
n
dc
k(h)
(2.17)
Given from Appendix C, the worst case k(h) at 2m
f
1 is 0.37. Then, substituting
the parameters from the inverter specication and using a switching frequency of 30kHz,
we get the magnitude of the lter transfer function |H
f
(jh
g
)| at (2m
f
1):
H
f
_
j
_
(2m
f
1)377
_
_
H
f
_
j(376614)
_
=
0.3%
2 10A
400V 0.37
= 2.86 10
4
= 70dB
(2.18)
With the transfer function of the lter derived in Equation (2.13), the generic magni-
tude plot of H
f
(s) can be drawn as shown in Figure 2.5. At = 376614, the magnitude
of H
f
(j376614) from the magnitude plot of H
f
(j) should at most be -70dB. This is the
guideline of choosing the values for L
i
, L
g
, C
f
and R
d
. Finally, the LCL lter compo-
nents are chosen following this guideline and the values of each component are shown in
Table 2.2. The MATLAB magnitude plot of the lter is shown in Figure 2.6, and it can
Chapter 2. Single Phase Grid Connected Inverter Design 24
L
i
L
g
C
f
R
d
300H 100H 30F 1.5
Table 2.2: Output lter parameters and their chosen values
10
0
10
1
10
2
10
3
10
4
10
5
10
6
100
80
60
40
20
0
20
40
60
80
M
a
g
n
i
t
u
d
e
(
d
B
)
Bode Diagram
Frequency (rad/sec)
Figure 2.6: Magnitude plot of H
f
(j) using selected lter components values
be seen that with the components chosen in Table 2.2, the magnitude of H
f
(j) is under
-70dB at =376614.
Chapter 3
Controller Design
The discussion of the controller for the inverter can be divided into three parts: 1) current
controller, 2) grid synchronization and 3) DC voltage controller. A block diagram of the
controller is shown in Figure 3.1. Similarly to the control of a three phase VSI, the
current controller is used to regulate the current injected into the grid and the voltage
controller is used to regulate the DC voltage at a desirable level. Unlike the three phase
VSI, the active and the reactive power of the single phase VSI cannot be controlled by
varying i
d
and i
q
in the d-q frame. Instead, a grid synchronizer block is proposed to
create a grid current reference which has the control of the active and the reactive power
ow.
3.1 Current Controller
A single phase feedback current loop is used to regulate the grid current. A proportional
resonant (PR) compensator is used to track a sinusoidal current reference signal. The
plant modelling, PR compensator design and the closed loop stability is discussed in this
section. The current controller block diagram is shown in Figure 3.2.
25
Chapter 3. Controller Design 26
vg(t)
+
-
ig(t)
Lg
Li
Cf
Rd
+
-
sa sb
sa
low
sb
low
idc(t)
Vdc
ref
G
v
(s)
NotchFilter
vdc
fil
+
-
ev
ref
g
i
||
Grid
Synchronization
ref
g
i
ref
g
i
G
i
(s)
vdc
vg(t)
ig
+
-
ei
VoltageController
Current Controller
Grid
Synchronization
Cdc
SPWM
vref
a
vref
b
sa sa
low
sb sb
low
) (
1
t v
dc
*-1
ign(t)
vdc(t)
vt(t)
DC
voltage
feedward
Figure 3.1: The inverter controller overall block diagram
3.1.1 Plant Modelling
Before designing the loop compensator, the plant model of the inverter can be derived
from Section 2.4.1 by combining equation (2.11) and (2.12), which yields:
I
g
(s) = G
f
(s)
_
s
2
L
i
C
f
+ sC
f
R
d
+ 1
sC
f
R
d
+ 1
V
g
V
t
_
(3.1)
where,
G
f
(s) =
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(3.2)
Since the magnitude and phase response of
s
2
L
i
C
f
+sC
f
R
d
+1
sC
f
R
d
+1
are 0dB and 0
at the
fundamental frequency of V
g
(j). Therefore, equation (3.1) can be simplied to equa-
tion (3.3).
I
g
(s)
.
= G
f
(s)(V
g
V
t
) (3.3)
Chapter 3. Controller Design 27
G
i
(s) G
f
(s)
Vg(s)
+
-
Ig(s)
Ig
ref
(s)
+
-
Vt(s)
Plant
Current Controller
Figure 3.2: Current controller block diagram
Given the plant model, a PR compensator, G
i
(s) is then added to the closed loop
and the equivalent closed loop diagram can be seen in Figure 3.2.
3.1.2 Proportional Resonant Controller
Normally in a three phase VSI SPWM based current controller, the 60Hz three phase grid
signals can be transformed into DC quantities by performing the ABC to d-q transform
(Parks transform) so that the current reference can be set to be a DC quantity and a
PI compensator is sucient to track the DC reference signal. However, in a single phase
inverter, the grid signals cannot be transformed into DC quantities so that the reference
signal to the feedback loop has to be sinusoidal.
In high switching frequency converters, such as power factor corrected (PFC) power
supplies, non-DC quantities can still be regulated using a simple PI compensator because
of their fast switching frequency, i.e. 200kHz. However, in this PV inverter, switching at
such high frequency is not an option considering the switching loss associated with the
MOSFETs and their reverse conducting diodes that are connected to a DC-link with a
relatively high voltage level. Therefore, for this PV inverter that is switching at 30kHz, a
PI compensator is no longer sucient to track the reference. A higher order compensator
is needed to used as a substitute.
According to Figure 3.2, the relationship between the input and the output of the
current loop can be derived as:
Chapter 3. Controller Design 28
I
g
(s) = H
i
(s)I
ref
g
(s) + H
v
(s)V
g
(s) (3.4)
where,
H
i
(s) =
G
i
(s)G
f
(s)
G
i
(s)G
f
(s) 1
(3.5)
H
v
(s) =
G
f
(s)
1 G
i
(s)G
f
(s)
(3.6)
To successfully track the i
ref
g
(t) signal without steady state errors, the magnitude of
H
i
(j) in Equation (3.5) has to equal to 1 at the fundamental frequency of the i
ref
g
(t).
Thus, it is clear that if G
i
(j) has a innite gain at the fundamental frequency, H
i
(j)
would have a unity gain. On the other hand, if G
i
(j) has a innite gain at the fundamen-
tal frequency, H
i
(j) in Equation (3.6) would results in 0 at the fundamental frequency
so that the H
v
(j) term can be neglected. Therefore, it is not necessary to have the grid
voltage feed-forward in the current control loop. To conclude, the compensator, G
i
(j)
has to have a innite gain at the fundamental frequency in order to track the current
reference, i
ref
g
(t).
A proportional-resonant (PR) compensator meets the aforementioned controller re-
quirement. An ideal PR compensator which has an innite gain at
o
has a transfer
function shown in Equation (3.7) and a generic bode plot is shown in Figure 3.3(a).
However, the innite gain of the controller leads an innite quality factor of the system,
which cannot be achieved in either analog or digital controller implementation. Further-
more, since the gain of an ideal PR compensator at other frequencies is low, it is no
adequate either to eliminate the higher order harmonics inuenced by the grid voltage or
to react to slight grid frequency variation. This is undesirable because the harmonic grid
voltage distortion would results in a signicant amount of harmonic grid current distor-
tion. Therefore, a damping term is introduced to form a non-ideal PR compensator
transfer function shown in Equation (3.8). This damping term reduces the innite gain
Chapter 3. Controller Design 29
0
50
100
150
200
250
300
M
a
g
n
i
t
u
d
e
(
d
B
)
10
1
10
2
10
3
10
4
450
405
360
315
270
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
(a) Ideal PR compensator
0
5
10
15
20
25
30
M
a
g
n
i
t
u
d
e
(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
90
45
0
45
90
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
(b) Non-deal PR compensator
Figure 3.3: Bode plot of (a) ideal PR compensator, (b) non-ideal PR compensator, K
c
p
=1,
K
c
i
=2000, =0.1
Chapter 3. Controller Design 30
at the fundamental frequency to a nite large gain but increases the bandwidth of the
compensator. A generic bode plot of the non-ideal PR compensator is shown in Fig-
ure 3.3(b). In order to understand the non-ideal PR controllers behaviour, three groups
of bode plots are drawn in Appendix B to demonstrate how the PR controllers response
varies by changing the each parameter in the transfer function.
G
i
(s) = K
c
p
+
K
c
i
s
s
2
+
2
o
(3.7)
G
i
(s) = K
c
p
+
K
c
i
s
s
2
+ 2
o
s +
2
o
(3.8)
3.1.3 Closed-Loop Stability
The closed loop gain of the current control loop with the PR compensator can be simply
obtained by Equation (3.9). The PR compensators parameters and systems parameters
are chosen in Table 3.1.
T
c
(s) = G
i
(s)G
f
(s) =
_
K
c
p
+
K
c
i
s
s
2
+
o
s +
2
o
_
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(3.9)
K
c
p
K
c
i
L
i
L
g
C
f
R
d
3 20000 0.01 300H 100H 30F 1.5
Table 3.1: PR compensators parameters and systems parameters
The bode plot of the uncompensated loop gain and the compensated loop gain is
shown in Figure 3.4. It can be seen from the compensated current loop gain, the large
system bandwidth would give the current controller a fast response. Meanwhile, having
a phase margin of 50.9
leading the grid voltage (orthogonal component). This estimator has a state space
form of:
Gridvoltage
estimator
v
g
|| g
v
g
v
ref
g
i
||
Amplitude
identifier
g
V
ref
g
i
i
g
ref
x
1
=[1 0] y
Figure 3.6: Feedback loop of the grid voltage estimator
_
_
x
1
x
2
_
_
=
A
..
_
_
0
o
o
0
_
_
_
_
x
1
x
2
_
_
+
B
..
_
_
k
sync
0
_
_
(v
g
x
1
) (3.10)
_
_
v
g
v
g
_
_
=
_
_
y
1
y
2
_
_
=
C
..
_
_
1 0
0 1
_
_
_
_
x
1
x
2
_
_
The above state space form the estimator takes v
g
x
1
as its input and outputs x
1
as
the parallel component of v
g
. Thus, this essentially resembles a feedback loop illustrated
in Figure 3.6, where the output x
1
tracks v
g
.
The reference signal of this feedback loop is v
g
, a sinusoidal signal oscillating at the
grid frequency
g
. The state matrix
A provides the grid voltage estimator a internal
oscillator oscillating at the
o
. This provides the estimator an innite gain at
o
in the
frequency domain.
The k
sync
term introduces damping to the oscillator which widens the estimators
bandwidth and reduces the gain at
o
. As a result, x
1
tracks the input v
g
, at its funda-
mental frequency while also rejecting other harmonics that appeared on the grid voltage.
Following this, the output y
1
is denoted as v
g
to illustrate the its alignment with the
grid voltage and the output y
2
is denoted as v
g
to illustrate it is orthogonal to the
grid voltage. The state trajectory and the peak voltage phasor diagram are shown in
Chapter 3. Controller Design 34
Im
Re
||
g
V
g
V
x1
x2
wo
(a) (b)
Figure 3.7: (a) State trajectory of the estimator, (b)Peak voltage phasor diagram of the
estimators input and outputs
Figure 3.7.
The state space form of the compensator (Equation (3.10)) can be further rewritten
to the standard state space form shown in Equation (3.11) so that v
g
is expressed as the
input to the estimator and the outputs are the parallel component and the orthogonal
component of v
g
.
_
_
x
1
x
2
_
_
=
A
..
_
_
k
sync
o
o
0
_
_
_
_
x
1
x
2
_
_
+
B
..
_
_
k
sync
0
_
_
(v
g
) (3.11)
_
_
v
g
v
g
_
_
=
_
_
y
1
y
2
_
_
=
C
..
_
_
1 0
0 1
_
_
_
_
x
1
x
2
_
_
3.2.1.1 Simulations of the Grid Voltage Estimator
The behaviour of this grid synchronizer was further analyzed by means of studying its
responses in both frequency and time domain.
First, the bode plot of each output of the compensators responses are shown in Fig-
Chapter 3. Controller Design 35
ure 3.8. In Figure 3.8(a), the
V
g
(j)
Vg(j)
response has a magnitude of 0dB and a phase of
0
at the grid fundamental frequency and lters out distortions at any other frequen-
cies. In Figure 3.8(b), the
V
g
(j)
Vg(j)
response also keeps the magnitude at 0dB at the grid
fundamental frequency but only lters out distortions at higher frequencies. Meanwhile,
the phase of the
V
g
(j)
Vg(j)
response is at 90
phase dierence.
Second, the radius of the circle equals to the magnitude of the grid voltage indicating
that both sinusoidal functions have an amplitude that equals to the magnitude of the
grid voltage. This eectively proves that the grid estimator resembles the fundamental
component of the grid voltage and emulates an orthogonal component with the same
magnitude. Third, with the initial conditions of states x
1
and x
2
equal to zero, the plot
with the larger k
sync
has a faster speed to reach the nal trajectory.
Furthermore, we investigate how well the grid estimator responses to inputs that
contain both harmonics and a frequency variation. Figure 3.10 shows the time domain
simulation based on the worst case conditions on the frequency variations of the grid
provided by IEEE-1547 standard [1] and the percentage voltage harmonics on the grid
provided by IEEE-519 standard [38]. According to IEEE-519, the worst case harmonics
that would appear on the grid voltage is 3% of the fundamental voltage at each harmonic,
with a total harmonic distortion (THD) of 5%. The worst grid frequency is 59.3Hz
according to IEEE-1547.
Chapter 3. Controller Design 36
80
70
60
50
40
30
20
10
0
M
a
g
n
i
t
u
d
e
(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
90
45
0
45
90
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Ksync=100
Ksync=300
Ksync=500
Ksync=1000
(a) bode plot of
V
g
(j)
Vg(j)
100
80
60
40
20
0
20
M
a
g
n
i
t
u
d
e
(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
0
45
90
135
180
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Ksync=100
Ksync=300
Ksync=500
Ksync=1000
(b) bode plot of
V
g
(j)
Vg(j)
Figure 3.8: Bode plot of
V
g
(j)
Vg(j)
and
V
g
(j)
Vg(j)
Chapter 3. Controller Design 37
x2
x1
g
V
V
g
=
_
v
2
g
+ v
2
g
(3.12)
Equivalently, we may also write
V
g
=
_
x
2
1
+ x
2
2
which is graphically displayed in the
transient state plane plot of Figure 3.9.
Other options of implementing the amplitude identier may include peak detection
for the grid voltage or peak detection for either output of the grid voltage estimator. Both
methods avoid using the square root operand, the latter one is more preferred because
the grid voltage estimator lters out the harmonic distortions that appeared on the grid
voltage so that the peak detection for the output of the estimator is more accurate than
for the grid voltage itself.
Chapter 3. Controller Design 41
3.2.3 Synchronized Current Reference Creation
Once the v
g
and v
g
are obtained from the grid voltage estimator, and
V
g
is obtained
from the amplitude identier, the control of the phase of the synchronized current refer-
ence becomes possible. Therefore, given the grid reference currents parallel and orthog-
onal components, i
ref
g
and i
ref
g
, a synchronized current reference signal can be obtained
by the following equation:
i
ref
g
=
i
ref
g
v
g
+ i
ref
g
v
g
V
g
(3.13)
Since the parallel component of the current reference i
ref
g
is aligned with the grid
voltage, this part of the current then controls the active power ow to the grid. On the
other hand, since the orthogonal component of the current reference i
ref
g
is 90
leading
the grid voltage, this part of the current controls the reactive power ow to the grid.
Therefore, the input i
ref
g
and i
ref
g
are the input control commands for the active and
reactive power.
3.2.4 Discussion of the Proposed Grid Synchronization Method
The proposed grid synchronization method is advantageous in two major ways. Firstly,
comparing with the conventional method of single phase grid synchronization method
as discussed in [30] where v
g
(t) is simply duplicated for parallel synchronization, the
proposed grid synchronizer not only reproduces a ltered signal that is in phase with
grid voltage, but also emulates an orthogonal component of the grid voltage, which can
be used to generate reactive power reference to the inverter. Therefore, the inverter
gains the ability of controlling the reactive power ow comparing to the conventional
PV inverters that only transfer active power due to their inability of reproducing an
orthogonal component of the current reference.
Secondly, other systems [32] [33] [34] which uses a synchronous frame PLL to lock
Chapter 3. Controller Design 42
on the phase of the grid voltage would need zero voltage crossing detection to reset the
integrator and the d-q transformations used which would need sin and cos calculations.
Both actions increase the complexity of the implementing the synchronizer in a digital
processor. On the other hand, the proposed grid synchronizer only uses a two by two
state matrix and a two by two output matrix to generate the parallel component and the
orthogonal component. This method therefore lowers the computational burden of the
digital processor signicantly.
The down side of the synchronization method is that since the grid estimator has
a xed oscillator frequency
o
, exposure to large frequency variation would result in
undesirable power factor downgrade (refer to Figure 3.12). Although increasing k
sync
would minimize the eect, the noise suppression ability of the estimator would be hurt.
Another down side of the grid synchronization method is its need of a square root
calculation in the amplitude identier, which could increase the processing time of the
digital processor. Fortunately, the fast xed point square root algorithm can be used
in this case which signicantly increase the processing speed of square root calculation.
Other viable options such as peak detection on the output of the estimator would avoid
the square root calculation, therefore can be used as a substitute.
Finally, a k
sync
= 200 is used in the PSCAD/EMTDC simulation and the prototype
designed in the lab. This selection of k
sync
is more focused on noise suppression than
immunity to frequency variation because the grid frequency can be set exactly in 60Hz
in PSCAD/EMTDC simulation, and the grid frequency in the lab is well regulated at
60Hz with a maximum variation less than 0.5Hz.
3.3 Voltage Controller
The DC-link voltage can be regulated by a closed loop voltage controller. Figure 3.13 is
a simplied power stage diagram which is used to analyze the DC voltage behaviour.
Chapter 3. Controller Design 43
+
-
vdc(t)
ig(t)
Lg
Li
Cf
Rd
H
vt(t)
vg(t)
Cdc
idc(t)
Figure 3.13: Inverter power stage diagram
3.3.1 Voltage Loop Modelling
The dierential equation on the DC side is:
C
dc
dv
dc
(t)
dt
= i
dc
(t) (3.14)
Again, i
dc
(t) consists of two components, a DC component, I
dc
and a double-line
frequency AC component, i
dc,ripple
(t). Both of them can be obtained from the power
balance equation:
v
dc
(t)i
dc
(t) =
V
g
cos(
g
t)
I
g
cos(
g
t ) (3.15)
v
dc
(t)I
dc
+ v
dc
(t)i
dc,ripple
(t) =
V
g
I
g
2
cos +
V
g
I
g
2
cos(2
g
t ) (3.16)
From equation (3.16), the two components of the DC current can be expressed as:
I
dc
=
V
g
2v
dc
(t)
I
g
cos =
V
rms
g
2v
dc
(t)
I
g
cos (3.17)
i
dc,ripple
(t) =
V
g
I
g
cos(2
g
t )
2v
dc
(t)
(3.18)
Since we align the parallel component of the current reference signal with the grid
voltage using a grid synchronization function block, the grid current i
g
(t) has its parallel
component aligned with the grid voltage as shown in the phasor digram in Figure 3.14.
Chapter 3. Controller Design 44
Im
||
g
I
g
I
Re
g
I
g
V
2v
dc
(t)
I
g
(3.19)
Then, we linearize these parameters to about the nominal grid voltage V
n
g
and nominal
DC voltage V
n
dc
:
I
dc
=
V
n
g
2V
n
dc
I
g
(3.20)
Then, the complete model of the voltage loop can be drawn and is shown in Fig-
ure 3.15.
A notch lter, H
n
(s), has a form of Equation (3.21) is applied to the voltage loop
to lter out the double-line frequency current ripple component i
dc,ripple
(t) because the
double-line frequency ripple current produces a double-line frequency ripple voltage on
the DC-link. This is undesirable because this ripple signal would couple through the
voltage controller and cause undesirable high frequency component would appear on the
current reference signal of the current control loop, Figure 3.16. (Note: A, B, C, D, E,
F in the gure are constant numbers)
H
notch
=
s
2
+ 2
1
n
s +
2
n
s
2
+ 2
2
n
s +
2
n
(3.21)
Chapter 3. Controller Design 45
G
v
(s)
ig||
ref
G
c
(s)
ig
ref
ig
n
dc
n
g
V
V
2
H
n
(s)
dc
sC
1
idc vdc
vdc
fil
Vdc
ref +
-
Current Loop
NotchFilter
Grid
Synchronization
Voltage
Compensator
||
||
g g
I i
Gridde-
synchronization
g
g
V
v
||
||
g
g
v
V
Figure 3.15: Voltage loop of the inverter
Vdc
n
+vdc,ripple(t)
Vdc
ref
+
-
DC voltage
compensator
C+Dcos(2wgt)
Grid
sychronization
vg(t)
ref
g
i
||
ig
ref
A+Bcos(2wgt)
Ecos(wgt)+Fcos(wgt)cos(2wgt)
Gridcurrent
control loop
Undesired!
ig
Figure 3.16: Eect of the double-line frequency ripple on the current reference signal
where
n
is twice the fundamental frequency,
1
is chosen to be 0.008 and
2
is chosen
to be 1.
The current synchronization block in the diagram is the part that the parallel
current reference, which is generated from the voltage controller, is converted to a grid
synchronized sinusoidal signal which is discussed in Section 3.2.
The current loop, G
c
(s) has a form of:
G
c
(s) =
G
i
(s)G
f
(s)
G
i
(s)G
f
(s) 1
(3.22)
where G
i
(s) is the PR controller from the current loop and G
f
(s) is the plant model
Chapter 3. Controller Design 46
derived in Equation (3.2).
The gird de-synchronization block
|Vg|
V
g
is used to extract the current that is equivalent
to the parallel current reference i
ref
g
generated from the voltage controller. The output
of this block is denoted as i
g
, and it equals to the peak value of the parallel component
of the grid current
I
g
. This block works like an inverse d-q transform, except it is in
a single phase system instead of a three phase system.
3.3.2 DC Voltage Compensator
A simple PI controller is used as the DC voltage loop compensator, which has the form
of:
G
v
(s) = K
v
p
+
K
v
i
s
(3.23)
The uncompensated loop gain and the compensated loop gain of this voltage feedback
loop is shown in Figure 3.17. A selection of K
v
p
= 0.1 and K
v
i
= 1 yields a phase margin
of 60
*-1
DC
voltage
feedward
ig(t)
ign(t)
vt(t)
sb
low
Figure 4.1: Inverter current loop simulation setup
Chapter 4. PSCAD/EMTDC Simulation Results 51
|| g
v
g
v
vg
g
v
desired
(a) Start-up transisient
|| g
v
g
v
vg
g
v
desired
(b) Zoomed in result
Figure 4.2: PSCAD/EMTDC simulation result of the grid voltage estimators outputs
and their desired values
4.1.1 Steady State Response
The steady state response of the current loop simulation results are shown in Figure 4.3.
Simulation is done for the inverter output grid current i
gn
(t) being regulated at 10A
(RMS). Three dierent sub-gures are used to show that the inverters output grid current
i
gn
(t) and the grid voltage are in phase (Figure 4.3(a)), o phase by 90
(Figure 4.3(b))
and 45
o phase (Figure 4.3(c)) . Table 4.2 shows the measured average active power
and reactive power in each case from the P,Q meter of PSCAD/EMTDC to prove that
the inverter is capable of transferring pure active power, pure reactive power and both.
Figure 4.3(a) Figure 4.3(b) Figure 4.3(c)
Measured active power (kW) 2.5 0 1.767
Measured reactive power (kVar) 0 2.5 1.767
Table 4.2: Active and reactive power measurement of the current loop simulation
Chapter 4. PSCAD/EMTDC Simulation Results 52
(a) Grid current and voltage are in phase (b) Grid current lags the voltage by 90
*-1
ign(t)
vdc(t)
vt(t)
DC
voltage
feedward
Iin
Figure 4.5: Inverter voltage loop simulation setup
Figure 4.6(a) Figure 4.6(b) Figure 4.6(c)
Measured active power (kW) 2.5 0 1.766
Measured reactive power (kVar) 0 2.5 1.767
Table 4.3: Active and reactive power measurement of the voltage loop simulation
measured average active power and reactive power in each case from the P,Q meter of
PSCAD/EMTDC to prove that the inverter is capable of transferring pure active power,
pure reactive power and both.
In addition, the TDDs are measured for the output grid current in the entire current
operating range when the when the inverter is running pure real power, Figure 4.7(a),
and pure reactive power, Figure 4.7(b). One can observe that the grid current TDD is
far below the 5% threshold stated in IEEE-1547/IEEE-519
1
.
1
IEEE-1547 directly references the grid current harmonic distortion limits for general distribution
systems stated in IEEE-519
Chapter 4. PSCAD/EMTDC Simulation Results 55
(a) Grid current and voltage are in phase (b) Grid current lags the voltage by 90
Figure 4.8: Voltage loop simulation based on the DC-link voltage step change
(a) DC input current step change (b) i
ref
g
step change
Figure 4.9: Step response of the voltage loop simulation based on the DC input current
step change and i
ref
g
step change
Chapter 5
Inverter Experimental Results
This chapter shows the inverters experimental results. A prototype was built based on
the inverter specication. The inverters controller is implemented fully on a 32bits xed
point PIC32MX340F256H microcontroller. Voltage and current signals are sampled using
the internal 10-bit analog-to-digital converter inside the microcontroller. The output
compare module of the microcontroller allows the modulation signal to be compared
with an internal timer signal to resemble a SPWM function block.
In the experimental setup, a DC voltage source which has a greater magnitude than
the regulated DC-link voltage is connected at the DC-link capacitor through a variable
resistor so that the DC-link gets roughly a constant current from the DC source. This is
used to emulate the front end DC/DC converter in the PV system. A transformer and a
variac are connected at the AC grid end to provide isolation and AC voltage adjustability.
The experimental setup is shown in Figure 5.1.
5.1 Steady State Operation
Figure 5.2 shows the steady state operating DC-link voltage v
dc
(t), grid voltage v
g
(t), and
the grid output current i
gn
(t). Due to the limiting voltage level and current limit of the
DC power supply available in the lab, the inverters grid voltage is downgraded to 60V
58
Chapter 5. Inverter Experimental Results 59
vg(t)
+
-
Lg
Li
Cf
Rd
+
-
Vt
sa sb
sa
low
sb
low
Cdc Vin
Rin
1:1
. .
vdc(t)
ig(t)
ign(t)
Sin
Figure 5.1: Inverter experimental setup
(RMS). Therefore, in this section, the inverter is running 600VA with V
n
dc
=140V, v
g
=60V
(RMS), i
gn
=10A (RMS) and the grid frequency of 60Hz. The three sub-gures illustrate
when the inverter is outputting pure real power, pure reactive power with 90
lagging
power factor, and the mix with real and reactive power with 0.8 lagging power factor.
Table 5.1 is a summary of the measured power factor, output current TDD in each case.
It can be seen that the power factor in each case is very close to expected values and
the TDD is under 5% which is under the limit of IEEE-1547/IEEE-519 standard
1
. This
set of experimental results demonstrate the inverters ability of controlling the reactive
power ow. Furthermore, it can also be seen that with a fairly large double line frequency
voltage ripple presented on the DC-link, the output gird current is hardly distorted. This
proves the eectiveness of the notch lter in the voltage control loop.
Theoretical power factor measured power factor TDD (%)
1.0 (Figure 5.2(a)) 0.99 2.73
0 lagging (Figure 5.2(b)) 0.01 lagging 2.26
0.8 lagging (Figure 5.2(c)) 0.79 lagging 2.36
Table 5.1: Summary of measured power factor and TDD
Furthermore, Figure 5.3 shows the amount of output grid current TDD in the entire
1
IEEE-1547 directly references the grid current harmonic distortion limits for general distribution
systems stated in IEEE-519
Chapter 5. Inverter Experimental Results 60
vdc(t)
vg(t)
ign(t)
(a) Grid current is in phase with the voltage
vdc(t)
vg(t)
ign(t)
(b) Grid current lags the voltage by 90
vdc(t)
vg(t)
ign(t)
(c) Grid current lags the voltage by 36.8
(PF=0.8, lag-
ging)
Figure 5.2: Steady state operation of the inverter. From top to bottom: DC-link voltage
V
n
dc
=140V on CH1 at 50V/Div, grid voltage v
g
=60V(RMS) on CH4 at 100V/Div and
output current i
g
=10A (RMS) on CH3 at 20A/Div. Time scale 5ms/Div
Chapter 5. Inverter Experimental Results 61
0 1 2 3 4 5 6 7 8 9 10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
i
gn
(A),in phase
T
D
D
(
%
)
(a) TDD(%) vs. i
gn
where i
gn
is in phase with V
g
0 1 2 3 4 5 6 7 8 9 10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
i
gn
(A), 90degree lagging
T
D
D
(
%
)
(b) TDD(%) vs. i
gn
where i
gn
is 90
lags V
g
Figure 5.3: TDD vs. i
gn
when running pure real power and reactive power
current operating range when the inverter is running pure real power, Figure 5.3(a), and
pure reactive power, Figure 5.3(b). In the PSCAD/EMTDC simulation, the TDD in the
entire current operating range is much smaller as compared to the experimental results.
This is because the harmonic distortions that appeared in the experimental results are
mainly caused by the grid voltage low frequency distortions. IEEE-1547 states that the
harmonics current injection shall be exclusive to the grid voltage harmonic distortions, so
the extra percent of harmonic distortions shown in the experimental results is acceptable.
Besides, the amount of TDD in the entire current operating range of this inverter is still
less than 5% threshold stated in IEEE-1547/IEEE-519
1
.
5.2 Transient Response
The transient response of the inverter is tested through the step change of the DC-link
voltage, input current and the reactive power controlling command i
ref
g
.
Figure 5.4 shows the transient response of the inverter when the DC-link voltage
steps up from 120V to 140V. Figure 5.4(a) is when the grid current is 0A. Figure 5.4(b)
is when the grid current is at 7A, 90
Figure 5.4: DC-link voltage step response of the inverter. (a) From top to bottom:
DC-link voltage v
dc
(t) on CH1 at 10V/Div, grid voltage v
g
(t) on CH4 at 100V/Div and
output current i
gn
on CH3 at 2A/Div. Time scale 20ms/Div. (b) From top to bottom:
DC-link voltage v
dc
(t) on CH1 at 50V/Div, grid voltage v
g
(t) on CH4 at 100V/Div and
output current i
gn
(t) on CH3 at 10A/Div. Time scale 20ms/Div
Chapter 5. Inverter Experimental Results 64
vdc(t)
vg(t)
ign(t)
(a) input power step response of the inverter
vdc(t)
vg(t)
ign(t)
(b) i
ref
g
step response of the inverter
Figure 5.5: Input power step change and i
ref
g
step change response of the inverter. (a)
from top to bottom: DC-link voltage v
dc
(t) on CH1 at 50V/Div, grid voltage v
g
(t) on
CH4 at 100V/Div and output current i
gn
(t) on CH3 at 10A/Div, time scale 10ms/Div.
(b) from top to bottom: DC-link voltage v
dc
(t) on CH1 at 50V/Div, grid voltage v
g
(t) on
CH4 at 100V/Div and output current i
gn
(t) on CH3 at 5A/Div, time scale 100ms/Div
Chapter 6
Conclusion and Future Work
6.1 Conclusion
This research presented a single phase grid connected DC/AC inverter with reactive
power (VAR) control for residential PV application. It was shown that residential PV
power generation has garnered much attention in todays demand for renewable energy.
Grid interconnection standards such as IEEE-1547 are used to regulate the power quality
of the local DR power injection. As a consequence, single phase, low power VSIs are
commonly used for the interconnection between PV modules and the utility grid to ensure
that the power quality meets grid standard. Furthermore, as more distributed resources
such as local PV generation is integrated into the grid at the distribution level, the trend
that the DR units actively supply reactive power to the grid has appeared. Therefore,
this work proposed a solution for the VSI to actively control the reactive power injecting
to the grid. This leads to the main contribution of this work, which is the design of a low
complexity grid synchronization method that does not rely on use of high performance
control platforms for creating parallel and orthogonal component of the grid voltage in
order to control the real and reactive power ow. The synchronization method inherently
attenuates grid distortion and is immune to slight grid frequency variations. Meanwhile,
65
Chapter 6. Conclusion and Future Work 66
due to the manufactures guarantee on the life time of PV inverters, the VSI was designed
to use a small, more reliable, lm type capacitor on the DC-link in a cost eective way
while maintaining a good output power quality.
Simulations were performed on PSCAD/EMTDC platform and a prototype was also
developed in the lab to prove the eectiveness of the controller and the grid synchroniza-
tion method. A PR compensator and a PI compensator were used in the current control
loop and the voltage control loop respectively. It was shown that the resulting phase
dierence between the gird current and the voltage are very close to the expected values,
which proves the inverters ability of controlling reactive power ow. Furthermore, with a
small value lm type capacitor being place on the DC-link, the notch lter in the voltage
control loop was be able to average out the large double-line frequency voltage ripple
that appeared on the DC-link, so that the output grid current stayed unaected by the
DC-link double-line frequency voltage ripple. As a result, the total demand distortion of
the grid current stayed under 5 % which is acceptable by the IEEE-1547 grid intercon-
nection standard
1
. The system outputs, i
gn
(t) and v
dc
(t) also show acceptable behaviours
during transient responses in terms of percentage overshoot and settling time.
6.2 Future Work
The future work of this research can extend to design the front end DC/DC converter
so that a two stage PV inverter system can be built for the analysis of the inverters
response when it is connected to a power source that is generated from the PV modules
instead of a constant DC current source that is used in the lab.
This research furthermore opens up the topic of actively exchanging reactive power
with the utility grid at the distribution level. The control and communication methods
between these type of local DRs and the central dispatch would be a useful area of study.
1
IEEE-1547 directly references the grid current harmonic distortion limits for general distribution
systems stated in IEEE-519
Appendix A
IEEE-1547 Standard on Harmonic
Current Injection
1
When the DR is serving balanced linear loads, harmonic current injection into the
Area Electrical Power System (EPS) at the PCC shall not exceed the limits stated below
in Table A.1. The harmonic current injections shall be exclusive of any harmonic currents
due to harmonic voltage distortion present in the Area EPS without the DR connected.
Table A.1: Maximum harmonic current distortion in percent of current(I)
a
Individual Total
harmonic h < 11 11 h < 17 17 h < 23 23 h < 35 35 h demand
order h distortion
(odd harmonics)
b
(TDD)
Percent (%) 4.0 2.0 1.5 0.6 0.3 5.0
a
I=the DR unit rated current capacity
b
Even harmonics are limited to 25% of the odd harmonic limits above
1
IEEE-1547 directly references the grid current harmonic distortion limits for general distribution
systems stated in IEEE-519
67
Appendix B
PR Controller Behaviour
The PR controllers behaviour were studied by looking at the bode plots when changing
each parameter. Again, the transfer function of an non-ideal PR controller is:
G
i
(s) = K
c
p
+
K
c
i
s
s
2
+ 2
o
s +
2
o
(B.1)
Figure B.1(a) shows the frequency response of the PR controller when K
c
i
changes
from 1 to 1000, with one decade interval. K
c
p
is set to be 0, is set to be 0.001. As shown
in the plot, with K
c
i
increases, the gain of the controller increases whereas the bandwidth
stays constant.
Figure B.1(b) shows the frequency response of the PR controller when changes from
0.001 to 1, with one decade interval. K
c
p
is set to be 0, K
i
is set to be 1. As shown in the
plot, with increases, the peaking of the magnitude at the resonant frequency decreases.
Figure B.1(c) shows the frequency response of the PR controller when K
c
p
changes
from 1 to 1000, with one decade interval. K
c
i
is set to be 1000, is set to be 0.001. As
shown in the plot, with K
c
p
increases, the magnitude at all frequencies increases but the
bandwidth of the controller got reduced and the phase amplitude decreases.
68
Appendix B. PR Controller Behaviour 69
100
50
0
50
100
M
a
g
n
i
t
u
d
e
(
d
B
)
10
1
10
2
10
3
10
4
90
45
0
45
90
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Ki=1
Ki=10
Ki=100
Ki=1000
(a) Frequency response when K
c
i
changes
100
80
60
40
20
0
20
M
a
g
n
i
t
u
d
e
(
d
B
)
10
1
10
2
10
3
10
4
90
45
0
45
90
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
=0.001
=0.01
=0.1
=1
(b) Frequency response when changes
0
10
20
30
40
50
60
70
80
M
a
g
n
i
t
u
d
e
(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
90
45
0
45
90
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Kp=1
Kp=10
Kp=100
Kp=1000
(c) Frequency response when K
c
p
changes
Figure B.1: Frequency response of the PR controller with each parameter changes
Appendix C
Harmonics Table for Switch Mode
Inverters
H
H
H
H
H
H
H
H
H
H
h
m
a
0.2 0.4 0.6 0.8 1.0
Fundamental 0.2 0.4 0.6 0.8 1.0
m
f
1.242 1.15 1.006 0.818 0.601
m
f
2 0.016 0.0061 0.131 0.220 0.318
m
f
4 0.018
2m
f
1 0.190 0.326 0.370 0.341 0.181
2m
f
3 0.024 0.071 0.139 0.212
2m
f
5 0.013 0.033
3m
f
0.335 0.123 0.083 0.171 0.113
3m
f
1 0.044 0.139 0.203 0.176 0.062
3m
f
3 0.012 0.047 0.104 0.157
3m
f
5 0.016 0.044
4m
f
1 0.163 0.157 0.008 0.105 0.068
4m
f
3 0.012 0.070 0.132 0.115 0.009
4m
f
5 0.034 0.084 0.119
4m
f
7 0.017 0.050
Table C.1: Generalized harmonics of V
Ao
for a large m
f
70
Bibliography
[1] Ieee standard for interconnecting distributed resources with electric power sys-
tems, IEEE Std 1547-2003, pp. 1 16, 2003.
[2] K. Turitsyn, P. Sulc, S. Backhaus, and M. Chertkov, Local control of reactive power
by distributed photovoltaic generators, in Smart Grid Communications (Smart-
GridComm), 2010 First IEEE International Conference on, oct. 2010, pp. 79 84.
[3] E. Paal and Z. Tatai, Grid connected inverters inuence on power quality of smart
grid, in Power Electronics and Motion Control Conference (EPE/PEMC), 2010
14th International, sept. 2010, pp. T635 T639.
[4] M. Ettehadi, H. Ghasemi, and S. Vaez-Zadeh, Reactive power ranking for dg units
in distribution networks, in Environment and Electrical Engineering (EEEIC), 2011
10th International Conference on, may 2011, pp. 1 4.
[5] M. Kandil, M. El-Saadawi, A. Hassan, and K. Abo-Al-Ez, A proposed reactive
power controller for dg grid connected systems, in Energy Conference and Exhibi-
tion (EnergyCon), 2010 IEEE International, dec. 2010, pp. 446 451.
[6] S. Dasgupta, S. Sahoo, and S. Panda, Single-phase inverter control techniques
for interfacing renewable energy sources with microgrid, part i: Parallel-connected
inverter topology with active and reactive power ow control along with grid current
shaping, Power Electronics, IEEE Transactions on, vol. 26, no. 3, pp. 717 731,
march 2011.
71
Bibliography 72
[7] L. Liu, Y. Zhou, and H. Li, Coordinated active and reactive power management
implementation based on dual-stage pll method for grid-connected pv system with
battery, in Energy Conversion Congress and Exposition (ECCE), 2010 IEEE, sept.
2010, pp. 328 335.
[8] S. Kjaer, J. Pedersen, and F. Blaabjerg, A review of single-phase grid-connected
inverters for photovoltaic modules, Industry Applications, IEEE Transactions on,
vol. 41, no. 5, pp. 1292 1306, sept.-oct. 2005.
[9] G. Simeonov, Novel resonant boost converter for distributed mppt grid-connected
photovoltaic systems, Masters thesis, University of Toronto, Toronto, 2010.
[10] R. Erickson and A. Rogers, A microinverter for building-integrated photovoltaics,
in Applied Power Electronics Conference and Exposition, 2009. APEC 2009.
Twenty-Fourth Annual IEEE, feb. 2009, pp. 911 917.
[11] M. Kazmierkowski and L. Malesani, Current control techniques for three-phase
voltage-source pwm converters: a survey, Industrial Electronics, IEEE Transactions
on, vol. 45, no. 5, pp. 691 703, oct 1998.
[12] D. M. Brod and D. W. Novotny, Current control of vsi-pwm inverters, Industry
Applications, IEEE Transactions on, vol. IA-21, no. 3, pp. 562 570, may 1985.
[13] T. Kato and K. Miyao, Modied hysteresis control with minor loops for single-
phase full-bridge inverters, in Industry Applications Society Annual Meeting, 1988.,
Conference Record of the 1988 IEEE, oct 1988, pp. 689 693 vol.1.
[14] G. Vazquez, P. Rodriguez, R. Ordonez, T. Kerekes, and R. Teodorescu, Adaptive
hysteresis band current control for transformerless single-phase pv inverters, in
Industrial Electronics, 2009. IECON 09. 35th Annual Conference of IEEE, nov.
2009, pp. 173 177.
Bibliography 73
[15] B. Yu and L. Chang, Improved predictive current controlled pwm for single-phase
grid-connected voltage source inverters, in Power Electronics Specialists Confer-
ence, 2005. PESC 05. IEEE 36th, june 2005, pp. 231 236.
[16] T.-F. Wu, K.-H. Sun, C.-L. Kuo, and C.-H. Chang, Predictive current controlled
5-kw single-phase bidirectional inverter with wide inductance variation for dc-
microgrid applications, Power Electronics, IEEE Transactions on, vol. 25, no. 12,
pp. 3076 3084, dec. 2010.
[17] Y. Xue, Y. Wu, and H. Zhang, An adaptive predictive current-controlled pwm
strategy for single-phase grid-connected inverters, in Industrial Electronics Society,
2007. IECON 2007. 33rd Annual Conference of the IEEE, nov. 2007, pp. 1548 1552.
[18] S. Premrudeepreechacharn and T. Poapornsawan, Fuzzy logic control of predictive
current control for grid-connected single phase inverter, in Photovoltaic Specialists
Conference, 2000. Conference Record of the Twenty-Eighth IEEE, 2000, pp. 1715
1718.
[19] A. Kahrobaeian and S. Farhangi, Stationary frame current control of single phase
grid connected pv inverters, in Power Electronic Drive Systems Technologies Con-
ference (PEDSTC), 2010 1st, feb. 2010, pp. 435 438.
[20] D. Zmood and D. Holmes, Stationary frame current regulation of pwm inverters
with zero steady state error, in Power Electronics Specialists Conference, 1999.
PESC 99. 30th Annual IEEE, vol. 2, 1999, pp. 1185 1190 vol.2.
[21] X. Yuan, J. Allmeling, W. Merk, and H. Stemmler, Stationary frame generalized
integrators for current control of active power lters with zero steady state error for
current harmonics of concern under unbalanced and distorted operation conditions,
in Industry Applications Conference, 2000. Conference Record of the 2000 IEEE,
vol. 4, oct 2000, pp. 2143 2150 vol.4.
Bibliography 74
[22] B. Francis and W. Wonham, The internal model principle for linear multivariable
regulators, J. Appl. Maths. Optim., vol. 2, no. 2, pp. 170 194, 1975.
[23] H. Cha, T.-K. Vu, and J.-E. Kim, Design and control of proportional-resonant
controller based photovoltaic power conditioning system, in Energy Conversion
Congress and Exposition, 2009. ECCE 2009. IEEE, sept. 2009, pp. 2198 2205.
[24] A. Timbus, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, Adaptive resonant
controller for grid-connected converters in distributed power generation systems,
in Applied Power Electronics Conference and Exposition, 2006. APEC 06. Twenty-
First Annual IEEE, march 2006, p. 6 pp.
[25] F. Schimpf and L. Norum, Eective use of lm capacitors in single-phase pv-
inverters by active power decoupling, in IECON 2010 - 36th Annual Conference on
IEEE Industrial Electronics Society, nov. 2010, pp. 2784 2789.
[26] T. Shimizu, K. Wada, and N. Nakamura, Flyback-type single-phase utility interac-
tive inverter with power pulsation decoupling on the dc input for an ac photovoltaic
module system, Power Electronics, IEEE Transactions on, vol. 21, no. 5, pp. 1264
1272, sept. 2006.
[27] A. Kotsopoulos, J. Duarte, and M. Hendrix, Predictive dc voltage control of single-
phase pv inverters with small dc link capacitance, in Industrial Electronics, 2003.
ISIE 03. 2003 IEEE International Symposium on, vol. 2, june 2003, pp. 793 797
vol. 2.
[28] Y.-M. Chen, H.-C. Wu, and Y.-C. Chen, Dc bus regulation strategy for grid-
connected pv power generation system, in Sustainable Energy Technologies, 2008.
ICSET 2008. IEEE International Conference on, nov. 2008, pp. 437 442.
Bibliography 75
[29] Y.-M. Chen, C.-H. Chang, and H.-C. Wu, Dc-link capacitor selections for the single-
phase grid-connected pv system, in Power Electronics and Drive Systems, 2009.
PEDS 2009. International Conference on, nov. 2009, pp. 72 77.
[30] K. de Souza, M. de Castro, and F. Antunes, A dc/ac converter for single-phase
grid-connected photovoltaic systems, in IECON 02 [Industrial Electronics Society,
IEEE 2002 28th Annual Conference of the], vol. 4, nov. 2002, pp. 3268 3273 vol.4.
[31] T. Thacker, R. Wang, D. Dong, R. Burgos, F. Wang, and D. Boroyevich, Phase-
locked loops using state variable feedback for single-phase converter systems, in
Applied Power Electronics Conference and Exposition, 2009. APEC 2009. Twenty-
Fourth Annual IEEE, feb. 2009, pp. 864 870.
[32] H. Cha, T.-K. Vu, and J.-E. Kim, Design and control of proportional-resonant
controller based photovoltaic power conditioning system, in Energy Conversion
Congress and Exposition, 2009. ECCE 2009. IEEE, sept. 2009, pp. 2198 2205.
[33] M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, A new single-phase pll structure
based on second order generalized integrator, in Power Electronics Specialists Con-
ference, 2006. PESC 06. 37th IEEE, june 2006, pp. 1 6.
[34] E. Jung and S.-K. Sul, Implementation of grid-connected single-phase inverter
based on fpga, in Applied Power Electronics Conference and Exposition, 2009.
APEC 2009. Twenty-Fourth Annual IEEE, feb. 2009, pp. 889 893.
[35] N. Mohan, T. D. Underland, and W. P. Robbins, Power Electronics - Converters,
Applications, and Design. John Wiley & Sons, Inc, 2003.
[36] E. Leif, Aluminium electrolytic capacitors performance in very high ripple current
and temperature applications, in Proceedings CARTS Europe 2007 Symposium,
October-November 2007, p. 4 of 4.
Bibliography 76
[37] Electrolytic Capacitors Application Guide-Operational life time section, KEMET
Electronics Corporation, June 2009, avaliable at www.kemet.com.
[38] Ieee recommended practices and requirements for harmonic control in electrical
power systems, IEEE Std 519-1992, p. 85, 1993.