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SLIDES FOR

CHAPTER 16
SEQUENTIAL CIRCUIT DESIGN
This chapter in the book includes: Objectives Study Guide 16.1 Summary of Design Procedure for Sequential Circuits 16.2 Design Example--Code Converter 16.3 Design of Iterative Circuits 16.4 Design of Sequential Circuits Using ROMs and PLAs 16.5 Sequential Circuit Design Using CPLDs 16.6 Sequential Circuit Design Using FPGAs 16.7 Simulation and Testing of Sequential Circuits 16.8 Overview of Computer-Aided Design Design Problems Additional Problems
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Summary of Design Procedure for Sequential Circuits

1. Given the problem statement, determine the required relationship between the input and output sequences and derive a state table. For many problems it is easiest to first construct a state graph. 2. Reduce the table to a minimum number of states. First, eliminate duplicate rows by row matching and, then, form an implication table and follow the procedure in Section 15.3. 3. If the reduced table has m states (2n 1 < m 2n), n flip-flops are required. Assign a unique combination of flip-flop states to correspond to each state in the reduced table. The guidelines given in Section 15.8 may prove helpful in finding an assignment which leads to an economical circuit.

Section 16.1 (p. 514)

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Summary of Design Procedure for Sequential Circuits (continued)

4. Form the transition table by substituting the assigned flip-flop states for each state in the reduced state table. The resulting transition table specifies the next states of the flip-flops and the output in terms of the present states of the flip-flops and the input. 5. Plot next-state maps and input maps for each flip-flop and derive the flip-flop input equations. (Depending on the type of gates to be used, either determine the sum-of-products form from the 1s on the map or the product-of-sums form from the 0s on the map.) Derive the output functions. 6. Realize the flip-flop input equations and the output equations using the available logic gates. 7. Check your design by signal tracing, computer simulation, or laboratory testing.
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Table 16-1.

Design Example: BCD to Excess-3 Converter

Input and output are serial with least significant bit first.

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Table 16-2. State Table for Code Converter

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Table 16-3. Reduced State Table for Code Converter

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Figure 16-1:

State Graph for Code Converter

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A B C D E H M (b) Transition table

Figure 16-2:

Assignment Map and Transition Table for Flip-Flops

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Figure 16-3: Karnaugh Maps for Code Converter Design

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Figure 16-4:

Code Converter Circuit

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Design of Iterative Circuits

Many of the design procedures used for sequential circuits can be applied to the design of iterative circuits. An iterative circuit consists of a number of identical cells interconnected in a regular manner.

Figure 16-5: Unilateral Iterative Circuit

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Some operations, such as binary addition, naturally lend themselves to realization with an iterative circuit because the same operation is performed on each pair of input bits.

Comparator Example
Design a circuit which compares two n-bit binary numbers and determines if they are equal or which one is larger if they are not equal. X = x1x2 xn and Y = y1y2 yn
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Comparison proceeds from left to right. The first cell compares x1 and y1 and passes on the result of the comparison to the next cell, the second cell compares x2 and y2, etc. Finally xn and yn are compared by the last cell and the output circuit produces signals to indicate if X = Y, X > Y, or X < Y.

Figure 16-6:

Form of Iterative Circuit for Comparing Binary Numbers

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We will now design a typical cell for the comparator. To the left of cell i, three conditions are possible: 1. X = Y so far 2. X > Y so far 3. X < Y so far Table 16-4 State Table for Comparator

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Using the guidelines from Section 15.8 leads to the state assignment aibi = 00 for S0, 01 for S1, and 10 for S2. Table 16-5 Transition Table for Comparator

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Typical Cell for Comparator

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Figure 16-7:

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Figure 16-8:

Output Circuit for Comparator

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In a unilateral iterative circuit, the inputs are received in parallel as a sequence in space, while for the sequential circuit, the inputs are received serially as a sequence in time.

Figure 16-9:

Sequential Comparator for Binary Numbers

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BCD to Excess-3 Code Converter.

Table 16-6a

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BCD to Excess-3 Code Converter.

Table 16-6b

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BCD to Excess-3 Code Converter.

Table 16-6

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BCD to Excess-3 Code Converter.

Realization of Table 16.6(a) Using a ROM

Figure 16-10:

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As an example, we will consider realizing the state table using a PLA and three D flip-flops. The circuit configuration is the same as Figure 16-10, except that the ROM is replaced with a PLA of appropriate size. If the state assignment of Figure 16-2 is used, the resulting output equation and D flip-flop input equations, derived from the maps in Figure 16-3, are D1 = Q1+ = Q2 D2 = Q2+ = Q1 D3 = Q3+ = Q1Q2Q3 + X Q1Q3 + XQ1Q2 Z = X Q3 + XQ3
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(16-1)

BCD to Excess-3 Code Converter.

Here is the corresponding PLA Table: Table 16-7: PLA Table for Code Converter

X 0 1 0 1

Q1 1 1 1 0

Q2 0 1 0

Q3 1 0 0 1

Z 0 0 0 0 0 1 1

D1 1 0 0 0 0 0 0

D2 0 1 0 0 0 0 0

D3 0 0 1 1 1 0 0
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Q+ = D = ABQ + ABQ

Figure 16-11:

Segment of Sequential PAL

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Sequential Circuit Design Using CPLDs

A typical CPLD contains a number of macrocells that are grouped into function blocks. Connections between the function blocks are made through an interconnection array. Some CPLDs are based on PALs, in which case each OR gate has a fixed set of AND gates associated with it. Other CPLDs are based on PLAs, in which case any AND gate output within a function block can be connected to any OR gate input in that block. Section 16.5 (p. 525)
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Figure 16-12:

(Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, Inc. 1999-2003. All rights reserved.)

CoolRunner-II Architecture

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Figure 16-13:

(Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, 2010 Cengage Learning Inc. 1999-2003. All rights reserved.)

CoolRunner-II Macrocell

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Figure 16-14:

CPLD Implementation of a Mealy Machine

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Figure 16-15:

CPLD Implementation of a Shift Register

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Figure 16-16:

CPLD Implementation of a Parallel Adder with Accumulator

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Sequential Circuit Design Using FPGAs

An FPGA usually consists of an array of configurable logic blocks (CLBs) surrounded by a ring of I/O blocks. The FPGA may also contain other components such as memory blocks, clock generators, tri-state buffers, etc. A typical CLB contains two or more function generators, often referred to as look-up tables or LUTs, programmable multiplexers, and D-CE flip-flops. The I/O blocks usually contain additional flip-flops for storing inputs or outputs and tri-state buffers for driving I/O pins. Section 16.6 (p. 529)
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Figure 16-17:

(Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, Inc. 1999-2003. All rights reserved.)
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Xilinx Virtex/Spartan II CLB

FPGA Implementation of a Mealy Machine

Figure 16-18:

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Figure 16-19:

FPGA Implementation of a Shift Register

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Figure 16-20:

FPGA Implementation of a Parallel Adder with Accumulator

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Simulation and Testing of Sequential Circuits

The state table of a sequential circuit can be checked out with a simulator or in lab as follows: 1. Using the direct set and clear inputs, set the flip-flop states to correspond to one of the present states in the table. 2. For a Moore machine, check to see that the output is correct. For a Mealy machine, check to see that the output is correct for each input combination. 3. For each input combination, clock the circuit and check to see if the next state of the flip-flops is correct. (Reset the circuit to the proper state before each input combination is applied.) 4. Repeat steps 1, 2, and 3 for each of the present states in the table. Section 16.7 (p. 532)
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Inverter with nominal delay of 10 ns, minimum delay of 5 ns, and maximum delay of 15 ns.

Figure 16-21:

Simulator Output for an Inverter

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Figure 16-22:

Simulation Screen for Figure 13-7

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Figure 16-23

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Figure 16-24:

Using a Shift Register to Generate Synchronized Inputs

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If the input changes are not synchronized with the clock, edge-triggered D flip-flops can be used to synchronize them.

Figure 16-25
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Figure 16-26:

Synchronizer with Two D Flip-Flops

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Overview of Computer-Aided Design

1. Draw a block diagram of the digital system. Define the required control signals and construct a state graph that describes the required sequence of operations. 2. Work out a detailed logic design of the system using gates, flip-flops, registers, counters, adders, etc. 3. Construct a logic diagram of the system using a schematic capture program. 4. Simulate and debug the logic diagram and make any necessary corrections to the design.

Section 16.8 (p. 537-538)

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5. Run an implementation program that fits the design into the target FPGA. This program carries out the following steps: (a) Partition the logic diagram into pieces that will fit into CLBs of the target FPGA. (b) Place the CLBs within the logic cell array of the FPGA and route the connections between logic cells. (c) Generate the bit pattern necessary to program the FPGA. 6. Run a timing simulation of the completed design to verify that it meets specifications. Make any necessary corrections and repeat the process as necessary. 7. Download the bit pattern into the internal configuration memory cells in the FPGA and test the operation of the FPGA.
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Circuit

Figure 16-27. Sequential Circuit for Design Problems

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