Haps-54 March2009 Manual

HAPS
Motherboard HAPS-54
High-performance ASIC Prototyping System
Revision History
Date Sep 04, 2007 Sep 05, 2007 Sep 17, 2007 Sep 27, 2007 Oct 04, 2007 Nov 13, 2007 Nov 14, 2007 Nov 23, 2007 Dec 03, 2007 Dec 10, 2007 Jan 09, 2008 Feb 04, 2008 Feb 07, 2008 Mar 18, 2008 Apr 02, 2008 May 15, 2008 Jun 26, 2008 Nov 17, 2008 Dec 03, 2008 Feb 26, 2009 Mar 11, 2009 Mar 20, 2009 Name Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Bo Nilsson Comment Initial version Corrected GCLK numbering in table 9 and 11 Cooling fans are not mounted on delivery (p. 3, 44) Cut the VCCO wires before connecting together GPIO headers (p. 24, 56) Minor corrections Minor corrections p43: ALERT LED lights green indicating no overheating p69: Added pin numbers for the connectors p59, 60: Corrected bank numbers in HapsTrak connectors 4 and 7 p10: Updated fig 3 p37: Create lower frequencies with internal PLLs p41: Updated text about SPI Flash PROMs Updated fig 45, 60, 61 and 62 Updated table Global Clocks on page 66 p24: Updated fig 26 STB2_1x1 replaces STB1_1x1 Updated the Self-Test p66: Renamed A_RESET, etc to A_RESET_n, etc Updated section Board Setup p49: OSC2 default is 52 MHz HAPS SupportNet is moved to http://hapssupportnet.synplicity.com p3: Support is now on SolvNet. Documentation is still on SupportNet. p34: Output frequency from single-ended PLL defined up to 266 MHz p43: Updated table 13 (Power Good LED) p17: Updated figure 12; p69: Added delay for global signals between FPGAs p63, 64: Corrected the indexes for the tables A-B and D-C
S/N
HAPS-54 2009, Synopsys, Inc.

2 HAPS-54
March 20, 2009

Synopsys, Inc.
General Information
Contents of the box
A basic HAPS-54 delivery contains the following: This manual The manual HAPS Interconnect Boards & Cables The manual Custom Daughter Boards The STB2_1x1 User Guide 1 CD with manuals, application notes and design files 1 HAPS-54 board with 4 Xilinx Virtex-5 LX330 devices in FF1760 packages 2 interconnect boards CON_1x2 4 interconnect boards CON_2x1B 1 interconnect board CON_2x2 1 interconnect cable CON_CABLE40 2 TERM-TOP_1x1 1 STB2_1x1 (Self-Test Board) for testing the HAPS-54 board 1 LAB_1x1 experiment board 2 ribbon cables for GPIO, 320 mm [order code: HX-GPIO_CABLE] 7 MMCX coax cables, 300 mm [order code: HX-MMCX_CABLE] 1 RS232/SERIAL cable, [order code: HX-RS232_DATAPORT] 1 RS232/USB cable, [order code: HX-RS232_USB] 4 fans to be mounted on the FPGAs, [order code: HX-EBF42.5] 1 power cable (ATX MiniFit to Phoenix FMC plug), [order code: HX-ATX_ADAPTER] A sample of 5 HapsTrak II socket connectors (ASP-125516-03) 1 wrist strap Power Requirement A complete system with HAPS-54 and daughter boards may require as much as 40A on 5V. Use a power supply such as TP-II 550PEC from Antec (http://www.antec.com).
Technical Support
This manual contains all information you need to use the HAPS-54 motherboard. For each standard daughter board you are using, you should refer to the documentation provided with that board. If you want to design your own daughter boards, please see the manual Custom Daughter Boards. Technical support is available on SolvNet at https://solvnet.synopsys.com. SupportNet For registered customers we offer complete documentation of all HAPS products. Please register at http://hapssupportnet.synplicity.com. On SupportNet you will find the latest releases of all HAPS manuals, application notes, board files, HapsMap and other useful information.
HAPS-54
Synopsys, Inc.
Contents
Revision History.............................................................2 General Information..............................................................3 Contents of the box. ........................................................3 Power Requirement...................................................3 Technical Support...........................................................3 SupportNet.................................................................3 Overview.................................................................................6 Features. ..........................................................................6 Concept...........................................................................8 Daughter Boards........................................................8 Inter-FPGA Connections. ...........................................9 Height Dimension Rules..........................................10 Example of a HAPS System....................................10 HapsTrak. .................................................................11 Board Layout Top Side.................................................12 Board Layout Bottom Side...........................................13 I/O Signals & Interconnects.........................................15 VCCO Regions..........................................................15 I/O Signals...............................................................15 Inter-FPGA Connections. .........................................16 General Purpose I/Os...............................................16 Clocks...........................................................................16 Getting Started.....................................................................18 Applying Power the First Time....................................18 Test the Board...............................................................19 Adding Daughter Boards..............................................19 Connecting Clocks.......................................................20 Board Setup (SETUP switch).......................................20 Power-Up. .....................................................................20 Board Setup (Advanced Options). ................................20 Configuring the Devices...............................................21 Reset & Reconfigure....................................................22 Expansion and I/Os..............................................................23 HapsTrak II Connectors. ...............................................23 Signal Levels and I/O Standards. .............................24 GPIOs...........................................................................24 Power. ....................................................................................25 VCCO Regions...............................................................25 VCCO in the HapsTrak II Connectors...........................27 Battery..........................................................................27 Clocks....................................................................................28 Clock Generators..........................................................28 Global Single-Ended 1-to-1 Clocks. .............................29 Global Differential PLL Clocks. ...................................31 Global Single-Ended PLL Clocks................................33
HAPS-54
Synopsys, Inc.
Direct Clocks................................................................35 Synchronizing Clocks. ..................................................36 Direct coax inputs....................................................37 Using a PLL to synchronize clocks.........................37 Distributing clock hierarchies..................................37 Local Clocks.................................................................38 Configuration.......................................................................39 JTAG Cable..................................................................40 SPI Flash PROMs....................................................41 CompactFlash...............................................................42 Board Status.........................................................................43 Voltage Monitoring. ......................................................43 Temperature Monitoring. ..............................................43 Self-Test. .......................................................................44 Board Setup..........................................................................46 Board Supervisor Registers..........................................47 Setup via the Data Port.................................................54 Advanced Options................................................................56 VCCO in the Bottom Side Connectors. ..........................56 GCLK_IN parallel termination. .................................57 Design Considerations.........................................................58 Part Reference......................................................................59 Pin Tables..............................................................................60 HapsTrak II Connectors 1-3....................................60 HapsTrak II Connectors 4-6....................................61 HapsTrak II Connector 7.........................................62 Inter-FPGA Connections A-B (fast)........................63 Inter-FPGA Connections A-B (slow). ......................63 Inter-FPGA Connections D-C (fast)........................64 Inter-FPGA Connections D-C (slow)......................64 Inter-FPGA Connections A-D (fast)........................65 Inter-FPGA Connections B-C (fast)........................66 HapsTrak CDE In....................................................67 HapsTrak CDE Out. .................................................67 Global Clocks..........................................................68 Direct Differential Clocks. .......................................68 RESET.....................................................................68 GPIO........................................................................68 Signal Delays........................................................................69 Connectors to FPGAs..............................................69 FPGA to FPGA........................................................69 Layout...................................................................................70 Board Dimensions................................................................71 The Experiment Board LAB_1x1.......................................72
HAPS-54
Synopsys, Inc.
Overview
HAPS-54 is a versatile multi-FPGA board intended for ASIC prototyping and HW/SW co-verification. It is designed for all ASIC prototyping needs, including HW/SW co-development, proof-of-concept studies, IP development and end user evaluations. The flexibility allows the same board to be reused in several projects or configurations by replacing daughter boards containing I/O and custom subsystems. The 26-layer board is carefully designed for maximum performance, with respect to signal integrity, speed and other critical issues. Signals to connectors and between FPGAs are length matched, thus minimizing skew and allowing very high speed signaling. The modular system with daughter board connectors placed in an equidistant matrix (70x50 mm), as on all HAPS boards, allows any daughter board to be placed anywhere in the matrix. Several standard daughter boards are available: See http://www.synplicity.com for an up-to-date listing.
Features
4 Xilinx Virtex-5 LX330 devices in FF1760 packages 13 VCCO regions 9 regions can individually be adjusted to: 3.3, 2.5, 1.8, 1.5, or 1.2 V All 13 regions can be sourced externally for other voltages 3632 signals for I/O and inter-FPGA connection 2856 I/Os (LVDS as an option) in 24 HapsTrak II connectors 736 predefined inter-FPGA connections 466 fixed 32 available for SelectMap configuration 238 available in four HapsTrak II connectors for expansion to other motherboards 40 GPIOs 16 global clocks, sourced externally or generated on-board All clocks can be sourced from the FPGAs 2 PLLs, one single ended and one differential 2 external differential clocks to each FPGA 208 local clocks differential or single-ended 3 on-board programmable clock generators Configuration via JTAG, on-board SPI Flash PROMs, SelectMAP or optionally from a CompactFlash card High speed routing High speed I/O or TDM (Time Domain Multiplexing) of inter-FPGA signals for high-connectivity designs Configurable routing The existing buses between pairs of FPGAs are easily expanded by standard interconnect boards or cables On-board temperature and voltage watchdog Temperature controlled fan drivers Built-in self-test Battery backed-up encryption key Single +5 V power supply HapsTrak I & II compatible
6 HAPS-54
Synopsys, Inc.
The HAPS-54 motherboard is equipped with 4 Virtex-5 devices, 24 HapsTrak II terminal connectors on the top side of the board, and 24 socket connectors on the bottom side. The connectors are divided into 13 different VCCO regions. The voltages are set with DIP switches and are available in terminals for external use. Four additional HapsTrak II terminal connectors on the top side form two global buses with 2.5V VCCO. HAPS-54 requires a single +5 V power supply to operate. All other voltages are generated on-board. The FPGA devices can be configured either via a JTAG cable or from a CompactFlash memory. For CompactFlash configuration the board CONF30 can be used (not included in the delivery).
PWR on LED Select LEDs Global bus Test points Battery 5V IN Global bus V3a in/out V3ax in
GND
Global clock in DC/DC converters VCCO LEDs V3a adjust Global clock out Board Supervisor Reconfigure Reset JTAG in Mode select HapsTrak CDE in CONF Configuration LEDs Power-good LED OSC 1,2,3 out Frequency select JTAG out (factory testing) HapsTrak CDE out JTAG CFG RESET LED ALERT LED Select LEDs Differential PLL in V2a adjust Differential PLL out Optional oscillators Select LEDs Single ended PLL in V1a adjust Single ended PLL out Holes to secure daughter boards Data port V1ax in V1a in/out V1b adjust V1b in/out V2b adjust V1cx in V1c in/out V1c adjust Global bus V2c adjust Global bus
HapsTrak II connectors
Fan connectors
V3c adjust Virtex-5 LX330 V3b adjust V3c in/out V3cx in V3b in/out V2a in/out V2b in/out V2c in/out GPIO LEDs GPIO
Holes to secure daughter boards
Direct clocks
Fig 1. The HAPS-54 motherboard
HAPS-54
Synopsys, Inc.
Concept
A HAPS system consists of at least one motherboard. The motherboard is merely a logic container with the biggest FPGAs in the biggest packages. High quality connectors for I/Os and inter-FPGA buses are placed in a regular 70x50 mm matrix. Each FPGA is connected to a group of these connectors. Each connector has dedicated pins for power and for clocks. Dedicated clock inputs on the FPGA devices are connected to global clocks. The low skew, high-speed clocks are distributed by clock buffers. The clocks can be driven either externally, from the FPGAs or from on-board oscillators. Fixed buses connects the FPGAs together. Wider buses are easily created by low cost interconnect boards. Parts of the buses are connected to two pairs of HapsTrak connectors, which can be used to expand the buses to other motherboards. Each FPGA also has a number of GPIO. Ordinary daughter boards, like memory boards and interface boards can be placed on any connector. The size of a daughter board is strictly specified. There are no wasted connectors on the motherboard. The dimensions of motherboards follow the same rules as for daughter boards. This means that motherboards can be placed side by side and connected together with standard interconnect boards. Since all HAPS motherboards have mating connectors on the bottom side they can also be stacked together like LEGO bricks. All connectors conform to the HapsTrak standard.
Daughter Boards
Each daughter board mates with one or several connectors on the motherboard. The connectors are spaced evenly, so even a multi-connector daughter board can be moved around freely. This allows you to reconfigure the prototype system as parts of the design moves from one FPGA to another. Most daughter boards also have a connector on the top side, opposite to the connectors that mate the HAPS motherboard. All signals are connected straight through the board. This allows several daughter boards to be stacked on top of each other, and have access to the same FPGA signals. In some boards, certain signals (typically enable signals) are staggered through the board stack, so that the motherboard can identify each board even though they share a common bus. Consult each daughter board manual for details. Stacking of daughter boards also allows you to monitor signals in the connector with a logic analyzer while the system is running and the daughter board is still attached to the HAPS motherboard. The board LAB_1x1, supplied with HAPS-54, has a prototype area where the signals in the connector are available for use on the board, see page 70. The LAB_1x1 board alone is probably not sufficient to implement all your I/Os and subsystems. Look at http://www.synplicity.com to find our current list of standard daughter boards and try to find one that suits your needs. For special needs, we can develop custom daughter boards according to your specifications, or provide you with PCB layout templates that enable you to create your own daughter boards. See details about custom daughter boards in the manual Custom Daughter Boards.
LEGO is a trademark of the LEGO Group of companies which does not sponsor, authorize or endorse the HAPS product.
HAPS-54
Synopsys, Inc.
HapsTrak
HapsTrak
HapsTrak
HapsTrak
HapsTrak
HapsTrak
G
HapsTrak
FPGA
FPGA
HapsTrak
HapsTrak
HapsTrak
HapsTrak
HapsTrak
HapsTrak
C
Internal
HapsTrak
HapsTrak
HapsTrak
HapsTrak
HapsTrak
HapsTrak
FPGA
G
HapsTrak HapsTrak HapsTrak HapsTrak
FPGA
G
HapsTrak HapsTrak
Fixed inter-FPGA connections Global bus I/Os or inter-FPGA connections Local clocks C G Global clocks GPIO
50 mm
Fig 2. A HAPS motherboard
Inter-FPGA Connections
All daughter board connectors can be used either for I/O or for creating wider buses between the FPGAs. In fact they can even be used for a combination of both. A number of standard interconnect boards and cables are available from Synplicity. CON_2x1B CON_1x2 CON_2x2 CON_CABLE connects 119 signals between two FPGAs perpendicular to the connectors as CON_2x1B but along the connectors creates diagonal buses or a 4-way bus between four FPGAs connects any daughter board connector to any other
Look at http://www.synplicity.com to find a current list of interconnect boards.
HAPS-54
70 mm
FPGA
HapsTrak
HapsTrak
70 mm
External
70 mm
FPGA
HapsTrak
Synopsys, Inc.
Height Dimension Rules

* HX-QTH-YYY-XX for stackable daughter boards there is a height limit
daughter board 2 daughter board 1 HX-QTH-YYY-05 motherboard HX-QSH-YYY-01
* 5 mm 19 mm
~ 2.4 mm
max 3 mm
70 mm
* Connector HX-QTH-YYY-01 HX-QTH-YYY-03 HX-QTH-YYY-05 Mating height 5 mm 11 mm 19 mm
YYY = 060 or 064 YYY = 060 or 064 YYY = 060 or 064
Fig 3. Height dimensions
Example of a HAPS System

HAPS boards can be connected together in many ways. Below is an example just to point out some important features with the HAPS concept. Notice the similarity to building with LEGO bricks.
A Mictor board with logic analyzer headers can be placed on top of everything. Daughter boards can be stacked on top of each other.
The physical dimensions for daughter boards are strictly specified. All connectors can be used. Connectors at different heights can be aligned with extenders. Motherboards can be connected with interconnect boards.
Daughter boards are placed on the same connectors used for creating buses. Most boards have connectors on both sides.
FPGA FPGA
HAPS-52
FPGA FPGA
HAPS-51 HAPS-34 FPGA
Buses betwe FPGAs are e with intercon
FPGA
HAPS-54
FPGA
Boards can be stacked in a variety of ways.
Motherboards can be stacked on top of each other.
Daughter boards can be placed on the bottom side of a motherboard.
Fig 4. Example of a HAPS system
10
HAPS-54
Synopsys, Inc.
HapsTrak
Previous generations of HAPS boards used the 120-pin HapsTrak I connector. Boards in the HAPS-50 family use 128-pin HapsTrak II connectors. The physical dimensions for the two kinds of connectors are identical, thus a HapsTrak I terminal connector fits together with a HapsTrak II socket connector and vice versa. The 8 extra pins in HapsTrak II connectors are used for additional power and remote identification of boards.

Fig 5. Top side connector - HapsTrak I Fig 6. Top side connector - HapsTrak II
Pin B1-B59 and A1-A60 are connected straight through from the top side connectors to the bottom side, whereas pin B60 and H1-H8 are left open in the bottom side connectors. However, by mounting 0-Ohm resistors its possible to connect VCCO to the bottom side as well.
Top Top
Bottom
Bottom B60
VCCO
VCCO
B60 H7 B60 H7
H8
Fig 7. VCCO - HapsTrak I
HapsTrak I a set of rules for pinout and mechanical characteristics, which guarantees compatibility with previous and future generation of HAPS motherboards and daughter boards
HAPS-54
0
B60
H8
Fig 8. VCCO - HapsTrak II
HapsTrak II as HapsTrak I, but with extended power to daughter boards, and including remote identification, setup, and monitoring of the complete HAPS system fully compatible with HapsTrak I
11
Synopsys, Inc.
Board Layout Top Side

XA BCD
GND V3a V3ax
GCLK_IN
C5
5 6 7 8 9 1 2 3 4 5 6 7 8 9
RECONFIGURE
GND GND GND OVERRIDE GND GND GND GND
1 2 3
DC/DC V3a
3.3V 2.5V 1.8V 1.5V PWR
Fan B
DRIVE 5V TACH
GC_B2 N P
B7
2.5V
DC/DC V3b
V3b
3.3V 2.5V 1.8V 1.5V PWR
DC/DC V3c
3.3V 2.5V 1.8V 1.5V PWR
Fan C
DRIVE 5V TACH
GC_C2 N P
C7
2.5V
a b
ON
V3a
GCLK_OUT
V3a
V3b GND
XC5VLX330
RESET
V3cx V3c GND
BOARD SUPERVISOR
B
N P GC_B1
V3b
ON
ON
V3b
V3c
Battery
XC5VLX330 N P
C
GC_C1
C3
JTAG IN
off on
CDE In
TDI TDO TCK TMS +2.5 V
SETUP
ON 4 5 6 7 8 9 10
V2a
V2b
V2b
C1
INIT_B PROG_B
3.3 V
3.3 V
PWR_GR DONE A DONE B DONE C GND DONE D
6 7 8 9 10
V3cX
V3ax
6 7 8 9 10
GND
off on
Frequency select
1 2 3
GND OVERRIDE
Power Good
ON
GND
1 2 3
1 6
10
GB
off on
OVERRIDE
ON
GND V2a
V2b
GND
GC
1 6
10
OVERRIDE
off on
ON
V2a
6 7 8 9 10
6 7 8 9 10
CHAINED_n
CDE Out
D5
RESET ALERT
GND
TDO PU
J.A. PU GND
factory test only
B3_N B3_P GND
ALL_DONE
DC/DC VCCINT A GC_A2 N P
DC/DC VCCINT D GC_D2 N P
JTAG CFG XA BCD

REFp
DC/DC V2a
3.3V 2.5V 1.8V 1.5V PWR
Fan A
DRIVE 5V TACH
DC/DC V2b
V1b
3.3V 2.5V 1.8V 1.5V PWR
DC/DC V2c
3.3V 2.5V 1.8V 1.5V PWR
FanD
DRIVE 5V TACH
OSC1
REFB+
IN
REFn FBp FBn 1p
OSC
V1a
REFB-
ON
DIFFERENTIAL
FBA+
D3
FBA-
8A
OUT
1n 2p 2n
8B
OSC3
OSC
OSC
9A
9B
DC/DC V1a
3.3V 2.5V 1.8V 1.5V PWR
V1ax
XC5VLX330 N P GC_A1
DC/DC V1b
3.3V 2.5V 1.8V 1.5V PWR
DC/DC V1c
3.3V 2.5V 1.8V 1.5V PWR
XC5VLX330 N P GC_D1
XA BCD
REF FB 1 2
V1b
2.5V
V1b
IN
REFB+
ON
FBA+
V1a
A7
ON
ON
V1b
V1c
D7
2.5V
SINGLE ENDED
D1
6A
6B
OUT
3 4 5 6
7A
V1ax V1a GND
V1b GND
7B
8A
VCCAUX A
V1cx V1c GND
DATA PORT
CTS RXD GND GND TXD RTS
VCCAUX D
9A
Voltage regulator
Voltage regulator
Fig 9. HAPS-54 - top side
12
HAPS-54
D2
A1
A2
D4
V1cx
A3
A4
OSC2
V2a
V1b
ON
ON
V2b
V2c
D6
V1c
A5
A6
TDI TDO TCK TMS VCC
GND GND GND GND GND GND
JTAG OUT
1 2 3 4 5 6 7 8 9 10
GND V1ax
10
V1cx
GND
1 2 3 4 5
1 2 3 4 5
2.5V
2.5V B2_N B2_P
GPIO A
GPIO D
V1c
GND
1 6
V1a
GA
V2b GND
V2b
V2c GND GD
GND
V3a
V3c
1 2 3 4 5
1 2 3 4 5
GPIO B
GPIO C
GND
1 6
C2
V2c
B1
B2
CONF
1 2 3 4 5 6 7 8 9 10 B C DONE A D
DC/DC VCCINT B
DC/DC 3.3V
DC/DC 2.5V
DC/DC VCCINT C
C4
V2c
B3
B4
C6
V3c
B5
B6
PWR ON
Voltage regulator
V3ax
VCCAUX B
V3b
GND
5V
Voltage regulator
V3b
VCCAUX C
V3cx
Synopsys, Inc.
Board Layout Bottom Side

U61
V3cx
V3b
U62
V3b
V3ax
U120
U83
SIPO
U59
U60
U87
U90 U103 U114
Voltage monitor
Voltage regulator
EEPROM
C6
C5
B6
B5
U99
U102
Voltage regulator
U37
U38
Voltage regulator
V3c
U27
U77
XC5VLX330
UC14
C
Buffer
V3b
V3b
U41
XC5VLX330
UB14 U117
U76
U65
U64
U26
U36
U58
U97
U94
U78
U116
SU Flash
U79
U66
V2c
V2b
V2b
Buffer
V2a
U86
U128
U48
U28
UC8
UB8
UC10
UC11
UB10
UB11
C2
C1
UC13
PISO
B2
B1
U105
PISO
UC12
U111
SIPO
UB13
U67
UB12
U23
U29
UC4
UB4
Voltage regulator
X2
U24
V2c
U50
V2b
U135
U134
U133
U13
U11
U9
UD4
V2b
SIPO
U21
U122
U30
UA4
V2a
UD12
D6
D5
A6
A5
Buffer
UD13
UD11 UD10
U145
U95
U98
X3
SPI Flash
SIPO
SPI Flash
UA12
U121
UA13 UA8
UA11 UA10
U31
U70
SM-bus
UD8
SM-bus buffers
U109 U108 U110 U107

U72 U71
U52
Clock generator
UC5
UA5
UB5
U93
U127
U69
PISO
Clock generator
U68
U141 U139
U140
U14
U12
U10
U119 U25
U55
U115
U51
U49
Level shifters
U123
U22
X1
U106
SPI Flash
U91
SPI Flash
Clock generator
U146
UD5
Termination regulator
U113
SIPO
Temp monitor
V1c
UD9
Temp monitor
V1b V1b
UA9
U104
SIPO
U100
Voltage regulator
U89
U126
XC5VLX330
UD14
D4
D3
A4
U96
A3
SIPO
XC5VLX330
UA14
V1a
MUX
U44
PLL U42
SIPO
U92
U43
Voltage regulator
PLL
V1cx
V1b
V1b
V1ax
MUX
U47
D2
D1
A2
A1
U46
U45
RS-232
U118
Fig 10. HAPS-54 - bottom side
HAPS-54
U101
SIPO
13
U129 U82
SIPO
SIPO
V3a
U39
U53
U33
14.7456MHz
Voltage regulator
U34
U85
U88
U56
Temp monitor
UC9
Temp monitor
UB9
U32
C4
C3
B4
B3
U40
U84
U57
Clock select
U35
U54
Clock buffers
Synopsys, Inc.
The main components of a HAPS-54 board are: 4 Virtex-5 FPGAs (LX330) 24 HapsTrak II terminal connectors (128 pins, mating height 19 mm) 24 HapsTrak II socket connectors on the bottom side (128 pins) 4 HapsTrak II connectors (128 pins, mating height 11 mm)1 1 HapsTrak CDE In socket connector (60 pins) 1 HapsTrak CDE Out terminal connector (60 pins) 4 headers (2x7) for 4x10 GPIOs 2 headers (2x7) for JTAG, in and out 1 header (2x3) for JTAG configuration 1 header (2x7) for the CONF30 board 1 RJ11 connector for board setup and monitoring (Data Port) 4 headers (1x3) for fan driving 9 MMCX global clock inputs 2x9 MMCX global clock outputs 4 MMCX differential PLL clock inputs 4 MMCX differential PLL clock outputs 2 MMCX single ended PLL clock inputs 6 MMCX single ended PLL clock outputs 4x2 MMCX differential direct clock inputs for each FPGA 3 on-board programmable clock generators 3 sockets for alternative reference oscillators 9 DIP switches (5-pole) to set VCCO 1 DIP switch (10-pole) to set the clock source 3 DIP switches (10-pole) to set oscillator frequencies 1 terminal for +5 V: 5 pins for GND and 5 pins for +5 V 9 terminals for VCCO: 5 of them 2-pole, 4 of them 3-pole 4x11 yellow mini LEDs indicating clock sources 9x4 yellow mini LEDs indicating VCCO voltage levels 17 yellow mini LEDs indicating if DIP switch values are overridden 12 LEDs: 1 +5V, 1 Power Good, 4 DONE, 1 RESET, 1 ALERT, 4 GPIO 1 header (2x7) for factory testing 1 reset button 1 reconfigure button 1 socket for an optional battery
1 Boards with serial number 070647 and above. Previous versions had HapsTrak I connectors! 14 HAPS-54
Synopsys, Inc.
I/O Signals & Interconnects

24 32 6
B7
3.3V 2.5V 1.8V 1.5V PWR
2.5V
7 8 23 31
5 24 32 6
2.5V
ON
C7
7 8 23 31
B6
B5
3.3V 2.5V 1.8V 1.5V PWR
ON
GND
V3b
20 20 18
28
19
27
20
28
19
27
1 2
V3a
GND V3ax V3a
10
14 16
B_GPIO
119
12 16 14 18 22 26 30 34
18
12
B
2 4 6 8
13
15
14
16
15 11 17 13 21 25 33 29
119
17
119
12 16 14 18 22 26 30 34
11
18
12
C
2 4 6 8
13
15
15 11 17 13 21 25 33 29
B3
B4
C3
119
17
30
22
29
21
30
22
29
B1
B2
C1
3.3V 2.5V 1.8V 1.5V PWR
3.3V 2.5V 1.8V 1.5V PWR
ON
34
4 5
26
33
25
1 2
ON
34
4 5
26
33
25
1 2
V2a
GND V2a
24 32
167
119
23 31
V2b
GND V2b
32
2.5V
24 32
119
167
23 31
GND
A6
A5
111
33 V2b 45 2.5V 28 V1ax V3a

20
119
119
19
D5
119
119
19
D6
33 V2a
33 V2c 111 33 V2b 45 2.5V 28 V1cx V3c 56 28 V1c V3cx
28
27
20
28
27
56
28 V1a V3ax
14 16
167 inter-FPGA connects
28 32 24 20 12 16 14 18 22 26 30 34
D_GPIO
A_GPIO
3.3V 2.5V 1.8V 1.5V PWR
ON
18
12
V1a
GND V1ax V1a
18 34
10
30 22
2 4 6 8
21 25 33 29
17
11
V1b
18
12
66
29
3.3V 2.5V 1.8V 1.5V PWR
22 26 30 34
2 4 6 8
21 25 33 29
17
11
10
29 21
17 33
GND
V1c
3.3V 2.5V 1.8V 1.5V PWR
119
7 5 3 1
31 27 23 19 15 11 17 13
13
15
14
16
28 32 24 20 12 16 14 18
119
119
7 5 3 1
31 27 23 19 15 11 17 13
13
15
167 inter-FPGA connects
A3
A4
D3
119
D4
ON
V1c
V1cx
21
ON
30
22
A1
D1
119
5 6
119
A7
2.5V
7 8 33
A2
34
26
25
V1b
GND V1b
119
5 6
119
D7
2.5V
7 8 33
34
26
Fig 11. I/Os, interconnects, I/O banks and VCCO regions
VCCO Regions
All necessary voltages are generated on-board from a single +5 V power source. DC/DC converters generate the I/O voltages for the HapsTrak II connectors. These are divided into 13 independent VCCO regions, 9 of them individually configurable with DIP switches to 3.3V, 2.5V, 1.8V, 1.5V or 1.2V. The regions, V1ax, V3ax, V1cx and V3cx can easily be connected to regions V1a, V3a, V1c, and V3c respectively. Connectors A7, B7, C7 and D7 are fixed at 2.5V. If a voltage other than the predefined ones is required, the corresponding DC/DC converter can be switched off and the desired I/O voltage supplied from an external source.
I/O Signals
Each HapsTrak II connector is connected to an FPGA via 119 signals and three pins sourcing VCCO to daughter boards. Adjacent pins can be used as differential pairs.
HAPS-54
D2
25
V2c
5
3.3V 2.5V 1.8V 1.5V PWR
119
119
119
119
C2
C4
11
21
C_GPIO
28 32 24 20
7 5 3 1
31 27 23 19
66
V3b
28 32 24 20
7 5 3 1
31 27 23 19
10
19 17
GND
V3c
ON 3 4 5
3.3V 2.5V 1.8V 1.5V PWR

ON 3 4 5
119
119
C5
V3b
119
119
C6
V3c
V3cx
V2c
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Synopsys, Inc.
16 of the pins are routed to clock capable inputs to the Virtex-5 devices, while 8 signals are routed to VREF inputs. A daughter board that requires an I/O standard that needs VREF will create the necessary VREF voltage and feed it to HAPS-54 on dedicated pins in the connector. Daughter boards that dont need VREF can use these pins as ordinaryI/O.
Inter-FPGA Connections
The four FPGAs are connected together with totally 736 signals, with slightly different characteristics. Buried Interconnects 167 buried signals between the FPGAs A and B, and C and D respectively, can be divided into two groups: direct and via level shifters. 66 buried direct signals between the FPGAs A and D, and B and C respectively. Global Bus The HapsTrak II connectors A7 and B7 are connected together with FPGAs A and B, and connectors C7 and D7 are connected together with FPGAs C and D. These connectors are ideal for creating a global bus, even expanded to several motherboards. Use either cables (CON_CABLE40) or interconnect boards (CON_2x1B) to make the interconnect. Termination boards (TERM-TOP_1x1) are recommended on the first and last connector in the chain. Termination boards TERM-TOP_1x1 are included in the delivery. SelectMap The 32 data signals in the SelectMap In bus can also be used as ordinary inter-FPGA bus. These signals are terminated on-board.
General Purpose I/Os

Each FPGA has 10 I/O signals available in headers. Two of the signals also drive a twocolored LED. These are used by the self-test to indicate if the hardware is faultless or not.
Clocks
On HAPS-54, 20 global clock pins (GC inputs, see Xilinx documentation) on each Virtex-5 device are dedicated for clock signals. 16 of these signals drive all FPGAs and are also available externally in MMCX connectors. Each of these 16 clocks can be sourced from either FPGA or externally, selectable with a DIP switch. 9 clocks are driven directly via high-speed clock buffers. 3 clocks are sourced by a PLL in single ended mode, and 2 differential clocks are driven by another PLL. The 4 remaining clock pins can also be used in differential mode, and are directly connected from MMCX connectors to the FPGAs. Three on-board programmable clock generators are directly connected to MMCX connectors. The frequencies are set with DIP switches, but can also be altered by using reference oscillators with other frequencies. To use the clock signals in your design, just connect coax cables to any of the clock inputs, and do the pin assignment accordingly.
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HAPS-54
Synopsys, Inc.
Outputs from each FPGA
X_GCLK0(1) X_GCLK0(2) X_GCLK0(3) X_GCLK0(4) X_GCLK0(5) X_GCLK0(6) X_GCLK0(7) X_GCLK0(8) X_GCLK0(9)
Inputs to each FPGA 1 .. 9

X A B C D
mux ctrl Other FPGAs
GCLK(1) GCLK(2) GCLK(3) GCLK(4) GCLK(5) GCLK(6) GCLK(7) GCLK(8) GCLK(9)
mux
clk buf
Other FPGAs
X FB
X_PLL_D
A B C D
mux ctrl
mux
DIFF PLL
GCLK(10) GCLK(11) GCLK(12) GCLK(13)
PLL ctrl
Other FPGAs
X FB
X_PLL_SE
A B C D
mux ctrl
mux
SE PLL
GCLK(14) GCLK(15) GCLK(16)
PLL ctrl
GCLK(17) GCLK(18) GCLK(19) GCLK(20)
Same pinning for all FPGAs

frequency select frequency select frequency select
Same pinning for all FPGAs
Clock Generator 1
Clock Generator 2
Clock Generator 3
Fig 12. Clocks
Each FPGA also has 112 local clock pins (CC inputs, see Xilinx documentation) sourced from the HapsTrak II connectors.
HAPS-54
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Synopsys, Inc.
Getting Started
Remember that the HAPS-54 board, as all other electronic equipment, is sensitive to static discharge. Make sure that youre properly grounded whenever handling the board directly. All positional references to the motherboard are made assuming that the board is placed in front of you as in the figure in the Board Layout section on page 12. See SupportNet at http://hapssupportnet.synplicity.com for the latest version of this manual.
Applying Power the First Time

The connector for power supply is the terminal block at the top of the board. The board requires only 5V. All other voltages are generated on-board. The PWR ON LED indicates when 5V is available, and the PowerGood LED indicates if the on-board generated voltages are within tolerance. Both LEDs should light green. The power connector is separated in two parts: the header which is permanently soldered to the HAPS-54 board the plug in which power (5V) and ground (GND) cables are inserted To disconnect the plug, pull firmly. Dont use any of the HapsTrak connectors as support, as the soldering may break. Use a small screwdriver to press the orange lever next to one of the holes. Insert a suitable (~ 1.5 mm2) cable in the hole and release the lever. This will secure the cable. Notice that the hole in the middle is unused. This is to clearly separate the 5V from GND. Five holes may be used as GND and 5V, respectively. To connect the plug, press firmly while supporting the board at the opposite end. As before, dont use any of the HapsTrak connectors as support.
Fig 14. Power plug
GND 5V
Fig 13. Power supply connector
HAPS-54 requires about 4A at start-up and when the FPGA devices are unconfigured. Total power consumption of a configured HAPS board depends on mounted daughter boards, the design and the clock frequency. Consult the Xilinx manuals and web site for details of the FPGA current consumption. The other components on the board require negligible amounts of power in comparison to the FPGA devices.
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HAPS-54
Synopsys, Inc.
Adjust the VCCO voltages for the I/O voltage regions V1a, V2a, V3a, V1b, V2b, V3b, V1c, V2c and V3c by setting the nine DIP switches according to the table below. The regions V1ax, V3ax, V1cx and V3cx, are normally connected together with regions V1a, V3a, V1c and V3c, respectively. Only one of the switches 1, 2, 3 and 4 should be in the on-position.
3.3V 2.5V 1.8V 1.5V PWR

ON
ON
4 5
Fig 15. VCCO setting
OFF
GND V3a V3ax
The voltages are measured by a voltage monitoring curcuit and the corresponding LEDs are turned on. If other voltages are needed, set the switch PWR to off and supply external power via the VCCO connectors.
Default on delivery
1
3.3V
DIP switch 2 3 4
2.5V 1.8V 1.5V
5
PWR
VCCO
3.3 V 2.5 V * 1.8 V 1.5 V 1.2 V disabled
GND V2a
V2b GND
V2c GND
V1b GND
* default
Table 1. VCCO values
For more information, see section Power.
Test the Board

Before using a complex electronic device like HAPS-54 its wise to do a sanity check. A design with a self-test suite is included on the CD. The test suite first checks for short circuits on the board and if the enclosed self-test board (STB2_1x1) is used, also for open circuits in the connectors. For details, see Self-Test in section Board Status. The ALERT LED is blinking red if any of the FPGA devices is overheated.
Adding Daughter Boards

A good idea is to power up the board and check all VCCO voltages before plugging in daughter boards. Remember to turn off the power before mounting the daughter boards. Most daughter boards have connectors placed along one of its edges. The connectors have a small chamfer that prevents the board from being mounted the wrong way. Press the daughter board gently into the selected connectors. If it doesnt slide in easily, check the orientation of the board again. You have to use very little force, but be firm and make sure
HAPS-54
V1ax V1a GND
Fig 16. VCCO connectors
V1cx V1c GND
on off off off off
off on off off off
off off on off off
off off off on off
on on on on on off
Default on delivery
Default on delivery
V3cx V3c GND
V1a, V2a, V3a V1b, V2b, V3b V1c, V2c, V3c
V3b GND
Default on delivery
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Synopsys, Inc.
that you insert the board straight by pushing on both sides of the connector. A board inserted slightly ajar will not have a proper connection in all pins. Most daughter boards are powered through the daughter board connector, but some may need external power, perhaps by supplying power from the corresponding VCCO connector. Refer to the documentation of each board. Small boards can be attached on a single connector and will stay put without any additional support. Larger boards are mounted on several connectors for mechanical stability, or have additional support stands. If needed, the daughter boards can be secured in the mounting holes on the motherboard.
Connecting Clocks
Connect external clocks to the MMCX connectors. If you want to use the on-board oscillators you must connect a cable (included in the delivery) from one of the OSC outputs to one of the GCLK_IN inputs. If you run the self-test, you must connect a cable from OSC1a or OSC1b to GCLK_IN1. The coax cables can be a bit tricky to detach from the MMCX connectors. Use a pair of pliers and pull straight upwards without using excessive force.
Board Setup (SETUP switch)

Set the SETUP DIP switch to the correct value, see section Board Setup. Default is all switches in the off position. 1 If you run the self-test, the SETUP switch can be set 0 1 2 3 4 5 6 7 8 9 10 to any value.
ON 1 2 3 4 5 6 7 8 9 10
OVERRIDE
SETUP
Fig 17. SETUP switch
Power-Up
WARNING: Before power-up, double check that the HapsTrak II connectors are configured for the correct VCCO voltage. When power is applied to the board, all indicator LEDs are briefly lit up in sequence for a few seconds. Following this, the Power Good, PWR ON and ALERT LEDs should be green, and the DONE LEDs for each FPGA should be yellow.
PWR ON
DONE C D Power Good

Fig 18. Power On LED
B A
ALERT

Fig 20. ALERT LED
Fig 19. Done & Power Good LEDs
Board Setup (Advanced Options)

The settings of the SETUP and Frequency Select switches can be overridden from the Data Port. For more information, see section Board Setup.
20 HAPS-54
off on
Synopsys, Inc.
Configuring the Devices

The FPGA devices can be configured in several ways: 1 from the on-board SPI Flash PROMs 2 from Xilinx iMPACT via a JTAG cable 3 from a CompactFlash memory using the CONF30 board (option) 4 via the SelectMAP bus (requires external configuration circuitry) The four LEDs, marked DONE A, DONE B, DONE C, and DONE D, indicate if the corresponding FPGA is configured or not. After a successful configuration, the DONE LEDs will change color from orange to green.
Fig 21. JTAG configuration using a Xilinx Platform Cable USB
Fig 22. Configuration from a CompactFlash card using CONF30
HAPS-54
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Synopsys, Inc.
Reset & Reconfigure

Pressing the RESET button will send an asynchronous reset to all FPGAs on pin L14. Pressing the RECONFIGURE button will empty the configuration memory of the FPGAs. When the button is released, they will read a configuration data stream from the on-board SPI Flash PROMs or the JTAG programming cable.
Fig 23. Reconfigure button Fig 24. Reset button
For a more detailed explanation of reset, configuration schemes and how to daisy-chain several boards, see section Configuration.
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HAPS-54
Synopsys, Inc.
Expansion and I/Os

The connectors on HAPS-54 are used for expansion of a HAPS system with daughter boards, either supplied by Synplicity or custom-made. See http://www.synplicity.com for a list of standard daughter boards and interconnect boards.
HapsTrak II Connectors
The FPGAs on the HAPS-54 board are each connected to seven 128-pin terminal connectors, located on the top side of the board. All connectors, except A7 and B7, have mating 128-pin socket connectors mounted on the bottom side. The HapsTrak II connectors A1-A6, B1-B6, C1-C6 and D1-D6 can be used either as pure I/O or for creating wider buses between the FPGAs. Its even possible to use the connectors as a combination of both. The mating connectors on the bottom side of the board make it possible to stack several motherboards. In fact, boards can be connected together in many different ways since the connectors are symmetrically placed in a matrix. The HapsTrak II connectors A7 and B7 are connected together, and also wired to FPGA A and B to form a global bus, easily expandable to other motherboards. In the same way, connectors C7 and D7 are connected to FPGA C and D.
ASP-125521-03 ASP-132424-01 ASP-125516-03 Manufacturer Web Terminal connector, 128 pin; mating height 19 mm Mates with ASP-125516-03 (or HapsTrak I connector QSH-060-XX-L-D-A) Terminal connector, 128 pin; mating height 11 mm Mates with ASP-125516-03 (or HapsTrak I connector QSH-060-XX-L-D-A) Socket connector, 128 pin Mates with ASP-125521-03 and ASP-132424-01 (or HapsTrak I connector QTH-060-XX-L-D-A) Samtec Inc. http://www.samtec.com
70.00 mm
Samtec
01 02 03 04
HAPS
50.00 mm
A1 B1 A2 B2
117 118 119 120
A59 B59 A60 B60

Fig 25. Physical placement
Table 2. Pin mapping Samtec HAPS
HAPS-54
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Synopsys, Inc.
Signal Levels and I/O Standards

Any Virtex-5 I/O standard compatible with the chosen voltage can be used. We strongly recommend the use of the different DCI (Digitally Controlled Impedance) variants. They minimize signal reflections and will enable you to run your designs at higher speed. Signal traces on the board are designed as 50 Ohm transmission lines, and DCI resistors that match this impedance are mounted on the board. All VRN-pins are connected to the proper VCCO via 47 Ohm resistors and the VRP-pins to GND via 47 Ohm resistors. With DCI I/Os, and a carefully designed daughter board, it is possible to run singleended signaling at over 200 MHz across the connectors. At these speeds, great care must be taken to clock phases. You will almost certainly need to synchronize the daughter board clock with a DCM (Digital Clock Manager).
GPIOs
Each FPGA has ten I/O signals connected to 2 mm headers. Two of the ten signals are connected to a red/green LED. The LEDs are used by the self-test suite to report if the board is flawless or not, but can of course be used for other purposes as well.
V3ax 6 7 8 9 10 GND V3cx 6 7 8 9 10 GND
GPIO B
V3a 1 2 3 4 5 GND
1 6
GPIO C GB
V3c 1 2 3 4 5 GND
GC
1 6
1 6
V1a 6 7 8 9 10 GND
V1ax 1 2 3 4 5 GND
Fig 26. General purpose I/Os
The number of interconnects between the FPGAs can be expanded by connecting 14-pin ribbon cables (included in the delivery) between the headers. Cut the two VCCO wires in the ribbon cable and make sure the VCCO regions for each group of signals are set to the same voltage before power-up. Internal pull-up resistors dont work for the GPIO signals that also drive the red/green LEDs, since these signals are externally pulled down.
24
V1cx 1 2 3 4 5 GND
GPIO A
V1c 6 7 8 9 10 GND
GA
GD
1 6
GPIO D
HAPS-54
Synopsys, Inc.
Power
The HAPS-54 board is powered by connecting a single +5 V source to the power terminal. All required voltages are generated on-board from this source. A complete system with HAPS-54 and daughter boards may require as much as 40A on 5V. Use a power supply such as TP-II 550PEC from Antec (http://www.antec.com).
GND
5V

Fig 27. Power supply connector

Fig 28. PWR ON Fig 29. Power Good
The PWR ON LED and the PowerGood LED should both light green, indicating that +5 V is supplied and the on-board generated voltages (except the VCCO voltages) are within tolerance.
VCCO Regions
HAPS-54 has 14 different VCCO regions: V1ax, V1a, V2a, V3a, V3ax, V1b, V2b, V3b, V1cx, V1c, V2c, V3c, V3cx and a fixed 2.5V.
2.5V V3ax 28 32
24 20 7 5 3 1 31 27 23 19 15 11 17 13 21 25 33 29 28 32 24 20 12 16 14 18 22 0 26 30 34
2.5V
7 5 3 1 31 27 V3cx 23 19 15 11 17 13 21 25 33 29
V3a
12 16 14 18 22 0 26 30 34
B
2 4 6 8
V3b
C
2 4 6 8
V3c
V2a
2.5V 2.5V
28 32 24 20 7 5 3 1 31 27 23 19 15 11 17 13 21 25 33 29
V2b
2.5V 2.5V
28 32 24 20 12 16 14 18 22 0 26 30 34 7 5 3 1 31 27 23 19 15 11 17 13
V2c
V1a
12 16 14 18
22 0 26 V1ax 30 34
A
2 4 6 8
V1b
D
2 4 6 8
V1c
21 25 33 29 V1cx
2.5V 2.5V
2.5V 2.5V
Fig 30. Banks and VCCO regions in the Virtex-5 devices
HAPS-54
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Synopsys, Inc.
Voltage regions in the FPGAs Bank

0 18 11, 13, 15, 17 12, 14, 16, 18 19, 23, 27, 31 20, 24, 28, 32 21, 25, 29, 33 22, 26, 30, 34
A
2.5V 2.5V V1b V1a V2b V2a V1b V1ax
B
2.5V 2.5V V3b V3a V3b V3ax V2b V2a
C
2.5V 2.5V V3c V3b V3cx V3b V2c V2b
D
2.5V 2.5V V1c V1b V2c V2b V1cx V1b
Table 3. Banks and voltage regions
The VCCO voltage for the a, b and c regions are set by DIP switches. The regions V1ax, V3ax, V1cx and V3cx can be set to the same VCCO voltages as regions V1a, V3a, V1c and V3c, respectively, by connecting them together in the terminal blocks. Four terminal plugs for this purpose are included in the delivery. Only one of the switches 1, 2, 3 and 4 should be in the on-position.
3.3V 2.5V 1.8V 1.5V PWR

ON
ON
4 5
Fig 31. VCCO setting
OFF
The voltages are measured by a voltage monitoring curcuit and the corresponding LEDs are turned on. If other voltages are needed, set the switch PWR to off and supply external power via the VCCO connectors. See page 15 for a description of which VCCO region a particular connector belongs to. Always check the I/O voltages, and make sure they are correct, before attaching daughter boards. The voltages can also be measured in the corresponding terminals.
GND V3a V3ax
Default on delivery
1
3.3V
DIP switch 2 3 4
2.5V 1.8V 1.5V
5
PWR
VCCO
3.3 V 2.5 V * 1.8 V 1.5 V 1.2 V disabled
GND V2a
V2b GND
V2c GND
V1b GND
* default
Table 4. VCCO values
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HAPS-54
V1ax V1a GND
Fig 32. VCCO connectors
V1cx V1c GND
on off off off off
off on off off off
off off on off off
off off off on off
on on on on on off
Default on delivery
Default on delivery
V3cx V3c GND
V1a, V2a, V3a V1b, V2b, V3b V1c, V2c, V3c
V3b GND
Default on delivery
Synopsys, Inc.
VCCO in the HapsTrak II Connectors

VCCO is connected to the terminal connectors placed on the top side of the board. The bottom side socket connectors are disconnected from VCCO, which makes it possible to stack motherboards on top of each other. If power is required in the bottom side connectors, the board has to be modified. Follow the instructions in the section Advanced Options.
Battery
A feature in the Virtex-5 devices makes it possible to encrypt bitstreams in order to protect a design. The on-board battery powers the part of the Virtex-5 devices that holds the encryption key. Use a lithium coin cell, diameter 12 mm, e.g. BR1216, CR1216, BR1220, CR1220 or BR1225.
HAPS-54
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Synopsys, Inc.
Clocks
Each FPGA on HAPS-54 has 76 clocks connected to dedicated Virtex-5 clock inputs. 9 global single-ended clocks sourced externally or from any FPGA 2 global differential clocks sourced from a PLL 3 global single-ended clocks sourced from a PLL 2 differential direct clock inputs 8 differential (or single-ended) clocks from each connector 9 GC inputs 4 GC inputs 3 GC inputs 4 GC inputs 56 CC inputs
The global clocks can be sourced either externally or from any FPGA. The clock sources are controlled by the Board Setup Controller. Some predefined settings can be selected with the SETUP switch. For other settings see section Board Setup.
Clock Generators
HAPS-54 has three programmable clock generators (frequency synthesizer). They can be used to source any of the global clock inputs. Simply connect a coax cable from one of the outputs to one of the global clock inputs.
ICS8402 Manufacturer: Web:
Frequency Setup select
350MHz, Crystal-to-LVCMOS / LVTTL Frequency Synthesizer IDT http://www.idt.com

Frequency Setup select Frequency select Setup
16 MHz
Programmable Clock Generator
16.67 MHz
16 MHz
Alt. Clock
Alt. Clock
Alt. Clock
OSC1
1a 1b
OSC2
2a
OSC3
3a
2b
3b
Fig 33. Clock generator 1
The output frequency for the clock generators is set with DIP switches. If other reference frequencies are required, place an oscillator, e.g. Epson SG8002CE, in the corresponding socket, and set position 1 in the DIP switch to on.
Frequency select
1 2 3
1 2 3
off on
OVERRIDE
ON
10
DIP switch OSC1 3

1 *1 2 6 3 5 4 4 5 M 3 2 1 0 1 6 7 8 9 10 N 0
10
OVERRIDE
off on
ON
off on
OVERRIDE
ON
1 2 3 4 5 6 7 8 9 10
10
*1 off = on-board crystal on = socketed oscillator

Table 5. DIP switch positions
Fig 36. Frequency select 28 HAPS-54
Synopsys, Inc.
The frequency is calculated as below. A comprehensive Excel sheet is available on SupportNet: http://hapssupportnet.synplicity.com Frequency calculation
OSC
VCO = Ref_Freq*M Output frequency = VCO/2N+1 250 MHz < VCO < 700 MHz Ref_Freq M N VCO 16.00 16.66667 25 30 3 1 400.00 500.00
Output freq 25.00 125.00
1, 3 2
DIP switch = 0 001 1001 11
DIP switch = 0 001 1110 01
Table 6. Frequency calculation
The clock generators can also be configured by the Board Supervisor device, see Board Setup. If this option is used, the override LED next to the corresponding switch will be lit, indicating that the switch setting is not used.
Global Single-Ended 1-to-1 Clocks

HAPS-54 has 9 global single-ended clocks with a 1-to-1 relation from source to destination.
Global Clock In From FPGAs B C
9 9
A
9
D SuC
9 1 6 6 6 6 6 6 6 6
GCLK 1 2 3 4 5 6 7 8 9
1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 9
Global Clock Out GCLK_OUT 1a, 1b 2a, 2b 3a, 3b 4a, 4b 5a, 5b 6a, 6b 7a, 7b 8a, 8b 9a, 9b
C_GCLKO(1-9)
D_GCLKO(1-9)
A_GCLKO(1-9)
B_GCLKO(1-9)
GCLK_IN4
GCLK_IN3
GCLK_IN9
GCLK_IN2
GCLK_IN8
GCLK_IN7
GCLK_IN6
GCLK_IN5
GCLK_IN1
Select one source for each row
A B C D To FPGAs
Fig 37. Global single-ended clocks
The clocks can be sourced either externally or from any FPGA. Some predefined settings are controlled with the SETUP switch. For other settings see section Board Setup. Clock Source Select
SETUP switch
OVERRIDE
Clock Source 1 X X X X 2 X X X A 3 X X X A 4 X X A A 5 X A A A 6 X A A A 7 X X A A 8 X X X A 9 X X X A
1 2 3 4 5 6 7 8 9 10
10
off on
SETUP
ON
1 0 0 1 1
2 0 1 0 1
Table 7. Clock sources. X = External, A = FPGA A HAPS-54 29
Synopsys, Inc.
In order to minimize clock skew and reflections, the global clocks are distributed through high-speed clock buffers that drive each FPGA on individual board traces. All clock lines are individually length matched to all FPGAs to reduce skew. The clock traces on the board are 50 Ohm transmission lines, and all global clock outputs are series terminated at the driving end to avoid reflections. They should drive a single destination, and not be terminated in the receiving end. If parallel termination at the destination is preferred, the series terminating resistor can be removed and replaced by 0Ohm resistors. See Advanced Options. The global clock inputs are not terminated. However, the inputs from the MMCX connectors are protected against overvoltage with series resistors. If termination is needed for these clock inputs, parallel termination resistors have to be mounted. See Advanced Options.
2.5V
7
CLKVCC
Clock Buffer
43
50
A_GCLK(X)
GCLK_INX
50 trace impedance
33
100
Rp Rn
51k
43
50
B_GCLK(X)
Rprot
100
43
50
C_GCLK(X)
off
43
50
D_GCLK(X)
2.5V
on
43
50
Rsa
7 43 50
GCLK_OUTXa
A_GCLKO(X) B_GCLKO(X) C_GCLKO(X) D_GCLKO(X)
100
51k
Rsb
7
GCLK_OUTXb
100
output impedance
SetupBus SetupBus
Fig 39. Clock buffers
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Global Differential PLL Clocks

One frequency synthesizer PLL is available on the motherboard to create and distribute a synchronous hierarchy of differential clocks. The PLL will create several output frequencies based on a reference input and settings stored in the device. Four different frequency settings, profiles, are preconfigured according to table 9, and are selected with SETUP switches 5 and 6. The reference source can be an external coax input or FPGA A, controlled by SETUP switch 3. The external reference input is differential, while the FPGA clock sources are single ended signals.
Global Clock In
DIFF
From FPGAs B C
D
DIFF
FB
GCLK 10, 12 11, 13
Global Clock Out

2 1 2 1 4 2 1 2 1 4 2 1 2 1 4 2 1 2 1 4
D1P, D1N D2P, D2N
PLL
Differential PLL
10 10
DIFF
DIFF
C_PLL_D
D_PLL_D
A_PLL_D
B_PLL_D
PLL_DN
PLL_DP
MMCX connectors
Select one source
Fig 40. Differential PLL ispClock 5620A Manufacturer: Web:
A B C D To FPGAs
Enhanced Zero-Delay Clock Generator with Universal Fan-Out Buffer Lattice Semiconductor Corp. http://www.latticesemi.com
Clock Source Select

OVERRIDE
off on
1 0
1 2 3
SETUP
ON 4 5 6 7 8 9 10
SETUP switch 3 0 1
Clock Source PLL External FPGA A
1 2 3 4 5 6 7 8 9 10
Table 8. Clock source
SETUP switch 4 controls the PLL function of the synthesizer. If PLL_Enable is set to 0, the reference input will be divided down to create lower output frequencies. The phase of the global clocks will be unrelated to the phase of the incoming clock, but all output clocks will be synchronous. If PLL_Enable is set to 1, one of the PLL coax outputs carrying the same frequency as the reference input must be fed back from a global clock output coax to the FB input through an HX-MMCX_CABLE. In this case, the output frequencies will become multiples of the input reference, and the clocks will arrive at the FPGAs in phase with the incoming reference clock. For application examples using the PLL to synchronize motherboards, see page 36.
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Differential PLL
SETUP switch PLL_enable Output frequencies
Profile
4 0 0 0 0 1 1 1 1
5 0 0 1 1 0 0 1 1
6 0 1 0 1 0 1 0 1
10 F F F F/2 16F 4F 2F F/2
GCLK GCLK_OUT 11 12 13 D1P D1N D2P F F/16 F/16 F/16 F/16 F/16 F F/4 F/4 F/4 F/4 F/4 F F/2 F/2 F/2 F/2 F/2 F/2 F F F F F 16F F F F F F 4F F F F F F 2F F F F F F F/2 F F F F F
Fin range MHz D2N F/16 F/4 F/2 F F F F F 0 400 0 400 0 400 0 400 10 25 40 100 80 200 160 400
Table 9. Differential PLL settings
The source of the reference clock and profile selection can also be done under software control. See Board Setup. If this option is used, the override LED next to the SETUP switch will be lit, indicating that the switch setting is not used. The PLL devices can be reprogrammed to create frequencies other than those in table 9. PLL configuration profiles are created using the PAC Designer software, which can be downloaded from http://www.latticesemi.com. The profiles are stored in an internal EEPROM programmed via the JTAG interface. A separate application note describes how to reprogram the PLL if other frequency settings are required. Refer to the schematic in figure 42 when creating the PLL output profiles.
REF_PLL_DP REF_PLL_DN
REFB+ REFB 0A 0B 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B 9A 9B
FB_PLL_DP FB_PLL_DN
FBKA+ FBKA+
PLL differential
(VCCO = 2.5V)
2.5V
A_PLL_D B_PLL_D C_PLL_D
100
ispClock 5620A
REFA+ REFA-
GND 100
P N P N P N P N P N P N P N P N P N P N
A_GCLK(10) A_GCLK(11) A_GCLK(12) A_GCLK(13) B_GCLK(10) B_GCLK(11) B_GCLK(12) B_GCLK(13) C_GCLK(10) C_GCLK(11) C_GCLK(12) C_GCLK(13) D_GCLK(10) D_GCLK(11) D_GCLK(12) D_GCLK(13) GCLK_OUT_D1P GCLK_OUT_D1N GCLK_OUT_D2P GCLK_OUT_D2N
D_PLL_D
SetupBus
SetupBus
Fig 42. Differential PLL
Even if the FPGAs arent used as a source for the reference frequency, you should make sure that the FPGAs are configured to drive a constant 0 or 1 on the X_PLL_D outputs, to avoid leaving the REFA+ input at an undefined logic level.
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Global Single-Ended PLL Clocks

One frequency synthesizer PLL is available on the motherboard to create and distribute a synchronous hierarchy of single-ended clocks. The PLL will create several output frequencies based on a reference input and settings stored in the device. Four different frequency settings, profiles, are preconfigured according to table 11, and are selected with SETUP switches 8 and 9. The reference source can be an external coax input or FPGA A, controlled by SETUP switch 3.
Global Clock In From FPGAs B C
D
FB
PLL
C_PLL_SE D_PLL_SE A_PLL_SE B_PLL_SE PLL_SE
18
GCLK 14, 15, 16
Global Clock Out

SE1 SE2 SE3 SE4 SE5 SE6
3 3
3 1 3
3 3
3 1 3
MMCX connectors
Single-ended PLL
Select one source
A B C D To FPGAs
Fig 43. Single-ended PLL ispClock 5620A Manufacturer: Web: Enhanced Zero-Delay Clock Generator with Universal Fan-Out Buffer Lattice Semiconductor Corp. http://www.latticesemi.com
Clock Source Select

OVERRIDE
1 2 3 4 5 6 7 8 9 10
10
off on
SETUP
ON
SETUP switch 3 0 1
Clock Source PLL External FPGA A
Table 10. Clock source
SETUP switch 7 controls the PLL function of the synthesizer. If PLL_Enable is set to 0, the reference input will be divided down to create lower output frequencies. The phase of the global clocks will be unrelated to the phase of the incoming clock, but all output clocks will be synchronous. If PLL_Enable is set to 1, one of the PLL coax outputs carrying the same frequency as the reference input must be fed back from a global clock output coax to the FB input through an HX-MMCX_CABLE. In this case, the output frequencies will become multiples of the input reference, and the clocks will arrive at the FPGAs in phase with the incoming reference clock. For application examples using the PLL to synchronize motherboards, see page 36.
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Single-ended PLL
SETUP switch PLL_enable Output frequencies
Profile
7 0 0 0 0 1 1 1 1
8 0 0 1 1 0 0 1 1
9 0 1 0 1 0 1 0 1
14 F* F/2 F* F/2 8F* 8F 12F* F
GCLK 15 F/2 F/4 F/2 F/3 4F 4F 6F 2/3F
16 F/4 F/8 F/3 F/4 2F 2F 4F F/2
GCLK_OUT_SE 1 2 3 4 5 6 F/8 F/8 F/8 F/8 F/8 F/8 F/16 F/16 F/16 F/16 F/16 F/16 F/4 F/4 F/4 F/4 F/12 F/12 F/6 F/6 F/6 F/6 F/2 F/2 F F F F F F F F F F F F 3F 3F 3F 3F F F F/3 F/3 F/3 F/3 F F
Fin range MHz 0 0 0 0 20 10 13 80 400 400 400 400 50 25 33.3 200
Table 11. Single-ended PLL settings (* output defined for frequencies up to 266 MHz)
The source of the reference clock and profile selection can also be done under software control. See Board Setup. If this option is used, the override LED next to the SETUP switch will be lit, indicating that the switch setting is not used. The PLL device can be reprogrammed to create frequencies other than those in table 11. PLL configuration profiles are created using the PAC Designer software, which can be downloaded from http://www.latticesemi.com. The profiles are stored in an internal EEPROM programmed via the JTAG interface. A separate application note describes how to reprogram the PLL if other frequency settings are required. Refer to the schematic in figure 45 when creating the PLL output profiles.
REF_PLL_SE
REFB+ REFB0A 0B 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B 9A 9B
GND
FB_PLL_SE
FBKA+
PLL single-ended
(VCCO = 2.5V)
2.5V
A_PLL_SE B_PLL_SE C_PLL_SE D_PLL_SE
100 GND
ispClock 5620A
REFA+ REFA-
A_GCLK(14) D_GCLK(14) B_GCLK(14) C_GCLK(14) A_GCLK(15) D_GCLK(15) B_GCLK(15) C_GCLK(15) A_GCLK(16) D_GCLK(16) B_GCLK(16) C_GCLK(16) GCLK_OUT_SE1 GCLK_OUT_SE2 GCLK_OUT_SE3 GCLK_OUT_SE4 GCLK_OUT_SE5 GCLK_OUT_SE6
100
SetupBus
SetupBus
Fig 45. Single-ended PLL
Even if the FPGAs arent used as a source for the reference frequency, you should make sure that the FPGAs are configured to drive a constant 0 or 1 on the X_PLL_SE outputs, to avoid leaving the REFA+ input at an undefined logic level.
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Direct Clocks
Each FPGA has two differential pair of clocks directly connected from MMCX connectors.
DIFF
DIFF
GC_A1p GC_A1n GC_A2p GC_A2n
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 20 20 20 20
MMCX connectors
Direct Clock In
DIFF
DIFF
GC_B1p GC_B1n GC_B2p GC_B2n
DIFF
DIFF
GC_C1p GC_C1n GC_C2p GC_C2n
DIFF
DIFF
GC_D1p GC_D1n GC_D2p GC_D2n
Fig 46. Direct clocks
A B C D To FPGAs
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Synopsys, Inc.
Synchronizing Clocks
The global clock traces on the motherboard are delay matched to the delays in the coax cables (HX-MMCX_CABLE) delivered with the board. This allows synchronization of clocks on several motherboards using several different methods. The figures below show three examples.
X 2X+Y 2X+Y IN F X X X F F 2X+Y 2X+Y F X F
X F
F X
D
Board 1
Y X X
D
Board 2
Delays: X = 0.44 ns, Y = 1.45 ns
Fig 47. Direct coax inputs

X 2X+Y 2X+Y IN F X X X F 2X+Y 2X+Y F X F X F
IN
F X
F/8 F, F/2, F4 F, F/2, F4 F/8 F/8
Y 2X+Y 2X+Y Y 2X+Y 2X+Y Y
PLL
A
F X
F, F/2, F4 Y F, F/2, F4 F/8 F/8
D
FB
Board 1
X X X
D
Board 1
Y IN X F X F F Y Y X X F Y X X
Y IN X F/8 X F/8 F, F/2, F4 F, F/2, F4 X F/8 F/8 Y 2X+Y 2X+Y Y X Y 2X+Y 2X+Y X X
PLL
PLL
A
X
F, F/2, F4 Y F, F/2, F4 F/8 F/8
X FB F X Y X
F F
D
F/8 FB X
Board 2
X X Y
D
Board 2
Fig 48. Using a PLL to synchronize clocks Board 1: SETUP switch(7-9) = xxx Board 2: SETUP switch(7-9) = 100
Fig 49. Distributing clock hierarchies Board 1: SETUP switch(7-9) = 000 Board 2: SETUP switch(7-9) = 100
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HAPS-54
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Direct coax inputs The direct coax inputs can be used to input a global clock from another motherboard to one or more FPGAs as shown in figure 47. The global clock buffer distributes clocks on PCB traces to all FPGAs on the first board. The buffers coax outpus are connected to direct coax inputs of the FPGA(s) on the second motherboard. Since the delays are matched, the clock will arrive simultaneously at all FPGAs in the figure. The same method can be used to synchronize a global clock on a HAPS-5x board to older generation motherboards. If the clock signal is needed by more FPGAs on the second board, the FPGA with the direct coax input can redistribute the clock on a global net on the second board, through a DCM loop that removes board delays. Using a PLL to synchronize clocks In order to get global clock nets on two or more boards synchronized without using DCMs in the FPGAs, the PLLs can be used as in figure 48. The PLL reference input will be in phase with the global clock on the first board. If PLL_enable is set to 1 and one PLL output is connected back to the FB input, the PLL will output its clocks so the FB input is in phase with the input. Thus, all FPGAs on both boards will receive the clock simultaneously. The second coax output from the buffer on the first board can be used to synchronize a third board. Further boards can be cascaded by using the remaining PLL outputs as their reference inputs. Make sure that the coax output you feed back to the FB input and pass forward to other motherboards have the same frequency as the original reference signal input. Distributing clock hierarchies In order to synchronizee clock hierarchies across several boards, PLLs can be utilized as in figure 49. Here, the PLL on the first board is run with PLL_enable set to 0, because the phase of the incoming clock is irrelevant. This PLL creates a synchronous hierarchy of frequencies as global clocks on the first board. The lowest output frequency is passed on from a coax output to the reference input on the second board. Because the HX-MMCX_CABLE is delay matched to the on board traces, the reference input will be in phase with the global clocks on the first board. PLL_enable is set to 1 on the second board, with feedback taken from one of the coax outputs. The same PLL profile as on the first board is used, to create the same frequency hierarchy on the second board. All FPGAs on both boards will see all clock appear simultaneously. It is important that the lowest frequency clock is used as a reference passed between boards. If the highest frequency clock is used as reference, lower frequency clocks may run out of phase. The PLLs have a lowest reference frequency limit of around 10 MHz, depending on profile settings. If lower reference frequencies are necessary, you may be required to create them internally in the FPGAs with internal PLLs.
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Synopsys, Inc.
Local Clocks
In addition to the global clock nets, each HapsTrak II connector has 8 pairs of differential signals connected to CC (clock capable) inputs on the FPGA. These clocks can also be used in singleended mode (use the P-side of the pin pair). See section Pin Tables to find the corresponding FPGA pin for each connector. The local clock inputs have two significant usages: Clocks created by external subsystems can be fed onto the FPGA (and perhaps redistributed to a global net if necessary). As a clock feedback path if a clock sent from the FPGA to the daughter board has to be synchronized with internal FPGA clocks. Feeding a clock from a daughter board is straightforward: Just use one of the clock pins (*1) in the HapsTrak II connector. Clock feedback is a little trickier. The daughter board should be designed with two pins for the clock signal. One of them should be pin A60 (*1). Send the signal to the daughter board on the other pin, and use the signal on pin A60 as the feedback Fig 50. Clock regions in the HapsTrak connectors clock in a DCM loop that synchronizes it with the original clock on the device. Consult the Xilinx manuals for more information on how to do this. When the daughter board is designed, care should be taken to avoid reflections on the clock line, especially if high-speed OBUFs are used to drive the clock. Since the local clocks are connected to CC inputs on the Virtex-5 devices, input buffers of type BUFG should not be used. Instead, use a BUFIO buffer, possibly followed by a BUFR. Regional clock signals (BUFR) in one clock region can drive logic in the existing and adjacent clock regions. Figure 50 shows which clock regions are adjacent in the HapsTrak II connectors. (*1) HAPS motherboards in the HAPS-10 and -20 families had one clock signal only from each connector. This clock signal was placed on pin A60. If you intend to design your own daughter boards, this pin should be the primary choice for a clock.
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Synopsys, Inc.
Configuration
The FPGA devices can be configured in several ways: 1 from the on-board SPI Flash PROMs 2 from Xilinx iMPACT via a JTAG cable 3 from a CompactFlash memory using the CONF30 board (option) 4 via the SelectMAP bus (requires external configuration circuitry) Four headers, four LEDs and two buttons are dedicated for configuration of HAPS-54. Two of these headers, JTAG IN and CONF, connect CONF30 together with HAPS-54.
INIT_B PROG_B PWR_GR DONE A DONE B DONE C DONE D 3.3 V 3.3 V GND GND GND GND GND GND GND CHAINED_n GND GND GND GND GND GND
GND GND
TDI TDO TCK TMS +2.5 V
TDO Pullup ALL_DONE
JTAG_ALL Pullup GND
TDI TDO TCK TMS VCC
Fig 51. CONF
Fig 52. JTAG IN
Fig 53. JTAG CFG
Fig 54. JTAG OUT
The four LEDs, marked DONE A, DONE B, DONE C and DONE D indicate if the corresponding FPGA is configured or not. After a successful configuration, the DONE LED for the corresponding device will change color from orange to green. The ALERT LED is on when any of the FPGAs is overheated. See section Board Status.
DONE C D ALERT RESET
B A

Fig 56. ALERT LED Fig 57. RESET LED
Fig 55. Done LEDs
Reconfigure Pressing the RECONFIGURE button will empty the configuration memory. When the button is released, the FPGAs will either be automatically configured from the on-board SPI Flash PROMs, or await configuration data from the JTAG IN port. Reset and ALL_DONE The ALL_DONE signal in figure 53 is an active high open-collector output indicating that all on-board FPGAs are configured. It is also used as an input to create four active-low asynchronous reset signals, one for each FPGA. The reset signal is available on pin L14 on each FPGA. The ALL_DONE signals on several boards can be tied together to create an ALL_DONE signal that spans several boards. It can be used to keep the design in the FPGAs waiting until all devices on all boards are configured. ALL_DONE is released (= pulled high) asynchronously when:
- All PLLs with PLL_Enable set to one have locked - The DONE signals of all FPGAs on this motherboard are active - The ALL_DONE signal is high
Reset to the FPGAs is released (= driven high) asynchronously when:
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Synopsys, Inc.
The RESET LED shows the status of the reset signal. RESET LED
Steady Green Steady Red Steady Yellow Reset is released for all FPGAs Reset is active because an enabled PLL hasn't locked Enabled PLLs are locked, but Reset is still active, probably because of an unconfigured FPGA or that the reset button is pressed
Table 12. RESET LED
The RESET button shorts the ALL_DONE signal to GND. Pressing it has the same effect as activating the ALL_DONE signal from an external board.
Fig 58. Reconfigure button Fig 59. Reset button
Under some circumstances, the reset behavior above is not desirable. For instance, if an FPGA on the board is unused, you may want its DONE signal to be ignored when the FPGA reset and ALL_DONE signals are generated. You may want one FPGA to start without waiting for the PLLs to lock, or you may need a synchronous instead of an asynchronous reset. How to accomplish these and other reset behaviors is described in the section Board setup, Setup registers. Note that the reset signals are ordinary inputs to the FPGAs, so your design, or parts of it, may ignore it.
JTAG Cable
Connect the Xilinx pod to the JTAGIN connector on HAPS-54. Identify the JTAG chain with Xilinx iMPACT software, which should find and recognize the devices. Download the bitfiles to the corresponding FPGAs. After a successful configuration, the DONE LEDs for the programmed devices will change color from orange to green. For normal operation do not strap JTAG_ALL. If there is problem with the configuration, try to add a pullup resistor on TDO by strapping the JTAG CFG header. This can improve signal timing.
2.5 V
FPGA A
FPGA B
TDI TDO
FPGA C
TDI TDO
FPGA D
TDI TDO
TDI
JTAG IN
1K
TDI
TDO
TDI
JTAG OUT
TDO
TDO Pullup
TDO
Fig 60. JTAG chain (no strap on JTAG_ALL)
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HAPS-54
Synopsys, Inc.
Several boards can be daisy chained. Connect a 14-pin ribbon cable from JTAG OUT on the first board to JTAG IN on the next board. The TDO return path will automatically be disconnected if its not the last board in the chain (the signal CHAINED_n will be 0). By strapping JTAG_ALL, the supervisor CPLD and the PLLs appear in the JTAG chain, allowing you to reconfigure the PLLs. It will also enable you to upgrade the supervisor firmware to the latest version, available on the SupportNet web site.
2.5 V
Setup PROM
Setup Controller
TDI TDO
PLL Differential
TDI TDO
PLL Single-ended
TDI TDO
FPGA A
TDI TDO
FPGA B
TDI TDO
FPGA C
TDI TDO
FPGA D
TDI TDO
TDI
JTAG IN
1K
TDI
TDO
TDI
JTAG OUT
TDO
TDO Pullup
TDO
Fig 61. JTAG chain when JTAG_ALL is strapped
SPI Flash PROMs

Each FPGA is connected to a 128 Mbit SPI Flash PROM where configuration data for the FPGA can be stored. If a configuration is stored in an SPI PROM, it will load immediately when the board is powered up. An image for the PROM is generated by the Xilinx ISE tools. Program the SPI PROMs using Boundary Scan Mode in iMPACT. When associating a bit file with an FPGA, mark the check box Enable Programming of SPI FLASH Device.... You will be prompted for a PROM configuration file. The resulting JTAG chain will look similar to figure 62. Proceed to select the PROM and choose the program operation. Programming takes several minutes.
SPI Flash PROM FPGA
TDI TDO
TDI
JTAG IN
FPGA
TDI TDO
FPGA
TDI TDO
FPGA
TDI TDO
1K
SPI Flash PROM
SPI Flash PROM
SPI Flash PROM
2.5 V
TDI
JTAG OUT
D
TDO Pullup
TDO
TDO
Fig 62. SPI Flash PROMs (M25P128 from STMicroelectronics)
Note:
Use ISE 9.2i sp2 or later to handle the 128 MBit SPI Flash PROMs.
HAPS-54
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Synopsys, Inc.
CompactFlash
Using CONF30, a member of the HAPS family, you can configure HAPS-54 from a CompactFlash memory. Connect CONF30 to HAPS-54 with the ribbon cable that comes with CONF30.
JTAG OUT JTAG IN
HAPS-54
CONF30
9 0 1
2 3
4 5 6
Fig 63. Connect CONF30 to HAPS-54
CONF
CONF
A 512 MB CompactFlash card can contain up to eight different designs. Create the configuration image with Xilinx iMPACT software and program the CompactFlash card. Select which configuration to be used by setting the Address select switch (on CONF30) to the correct position. When a CompactFlash card is inserted, the ERR LED (on CONF30) will turn off. The STAT LED will blink yellow during configuration. After a successful configuration the DONE LEDs for the programmed devices will change color from yellow to green.
42
HAPS-54
7 8
(positions 8 and 9 are not used) Fig 64. Address select switch on CONF30
Synopsys, Inc.
Board Status
Before using a complex electronic device like HAPS-54 its wise to verify that the board is flawless. The first things to check are voltages and temperature. The PWR ON LED and the Power Good LED should both light green, indicating that +5 V is supplied and the on-board generated voltages are within tolerance. The ALERT LED should light green, indicating that the FPGAs are not overheated. Other failures, like shorts or open circuits, can be detected by downloading some appropriate design into the FPGAs. A design intended exactly for this purpose is included in the delivery. See section Self-Test below.
Voltage Monitoring
A special circuitry monitors the non-adjustable voltages and reports out-of-tolerance values, about 4%, by changing color from green to red on the Power Good LED. The adjustable VCCO voltages are measured with the same tolerance and indicated with the yellow LEDs placed close to the voltage DIP switches. The 5V input voltage is also monitored. If the input voltage is too high, the Power Good LED will flash RED. If power is subsequently lowered to 5V, the Power Good LED will flash yellow until the board is power-cycled, to indicate the previous power glitch. Power Good LED
Steady Green Steady Red Flashing Red Flashing Yellow Flashing Green All voltages are OK. Some voltage is incorrect. Overvoltage! Turn off power immediately! Overvoltage has been detected, but at the moment all voltages are within tolerance. Some voltage has been incorrect, but everything is currently OK.
Table 13. Power Good LED
Note : See also the command RBS on page 53.
Temperature Monitoring
The Board Supervisor circuit continuously monitors FPGA die temperatures. If an FPGA temperature exceeds 45 degrees C, power is applied to the fan on this FPGA. When die temperature exceeds 85 degrees C, the ALERT LED flashes red and all FPGAs are stopped and held in an unconfigured state. If the FPGAs subsequently cool down, the FPGAs are allowed to reconfigure. The ALERT LED continues to flash yellow until the board is power-cycled, to indicate the previous overheat condition. ALERT LED
Steady Green Flashing Red Flashing Yellow Temperature is OK. One or more FPGA is overheated. Overheating has been detected, but at the moment the temperatures are OK.
Table 14. ALERT LED
Note : See also the command RBS on page 53.

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Synopsys, Inc.
In order to protect against overheating, mount the speed regulated cooling fans on the FPGA devices.
Fig 65. Cooling fans to protect against excessive heat
Self-Test
The self-test suite on the CD will check HAPS-54 for hardware errors. The first test (Test0) checks for short circuits on the board and verifies that all pins in the connectors are connected. If errors are found, an additional test (Test 1) may be used to exactly locate the cause of the error. Checking for short circuits can be done without any additional hardware. Checking for open circuits, i.e. non-connected pins in the connectors, requires that the enclosed selftest board STB2_1x1 is used. The STB2_1x1 board has circuitry to verify that voltages and grounds are available in the tested connector. The other pins are simply connected together.
Top
H1 G1
Bottom
H2
B60, H1, H2, H4, H6, H7, H8, G1, G2 H4 H6 B60, H1, H2, H7, H8
Power and Ground Detection

B60 H7 G2 H8
Power Detection
D4
D3
D2
D1
HapsTrak II
D5
Fig 66. Schematic view of the STB2_1x1 board
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HAPS-54
Synopsys, Inc.
Test setup 1. Connect a coax cable from clock generator 1 (1a or 1b) to GCLK_IN1. 2. Configure the FPGAs with the designs selftest_a.bit, selftest_b.bit, selftest_c.bit and selftest_d.bit respectively. Short circuits The red/green LEDs GA, GB, GC and GD on HAPS-54 should all blink green to indicate that no short circuits were found. If errors are found, the corresponding LED will blink red. Open circuits To check for open circuits in the HapsTrak II connectors, the STB2_1x1 board must be used. When the STB2_1x1 board is attached to HAPS-54, the LED for the corresponding FPGA will light steady green to indicate a healthy connector. If errors are found, the LED will light steady red. Note that the LED may momentarily light red before the STB2_1x1 is properly mounted on the connector. Summary Green blinking Red blinking Green steady Red steady No short circuits in any HapsTrak II connector Short circuit in at least one HapsTrak II connector No unconnected pins in the connector where STB2_1x1 is attached Unconnected pins in the connector where STB2_1x1 is attached
Locating errors If errors are found during the test procedure above, an additional test may be used to track down the cause of the error. Repeat the procedure described in Test Setup using the designs toggletest_a.bit, toggletest_b.bit, toggletest_c.bit and toggletest_d.bit, respectively.This test toggles all pins in all HapsTrak II connectors between 0 and 1. Adjacent pins are in reversed phase. Measure with an oscilloscope on suspicious pins. If the pin is not connected the signal will be missing. If two or more pins are short-circuited, the signal levels on these pins are reduced or zero, depending on how many pins are short-circuited together. For detailed instructions, see the STB2_1x1 User Guide. The self-test suite is continually enhanced. The latest version can be downloaded from SupportNet: http://hapssupportnet.synplicity.com
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Board Setup
Board Setup is controlled by several DIP Switches on the board: the SETUP switch, the Frequency Select switches, and the VCCO Select switches. The switches provide a basic mechanism to setup the board in variety of different configurations, as described in other sections of this manual. For most uses, the capabilities of the DIP switches are sufficient, but some applications may require more detailed control of for instance clock distribution or reset behavior. For these cases, HAPS-5x motherboards have a USB interface that allows finer-grain control of many aspects of the board that you cant accomplish with the simple switches. The interface also allows you to control the board remotely, without ever having to rely on physical access to the board to make sure that switches are set correctly for your application. A detailed setting, created with the command interface, can be stored in non-volatile memory, and will be retrieved by the board at the next power-up. This allows the board to power-up with a complex setting even if no controlling terminal is available. This is useful if the board is shipped to end-users or used in demo or real-life environments. Note: Early production boards dont have non-volatile store. Contact support if this feature is needed and your board doesnt support it.
Each setup switch that can be overridden by the command interface has a yellow override LED placed next to it. When lit, it indicates that the switch settings are ignored. Switches that can be overridden by the command interface are the following: SETUP Switches 1-9 control clock distribution as described in section Clocks. Switch 10 is used in conjunction with the non-volatile store. When the board is powered-up with switch 10 in the on position, the remaining switches will be ignored, and setup is retrieved from the non-volatile store. Frequency Select The M and N values of each clock generator can be overridden. The reference oscillator select bit (switch 1) cannot be overridden and must be set manually on the DIP switches. VCCO Select The VCCO switches cannot be overridden by the command interface. They must be set manually.
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Board Supervisor Registers

The supervisor device has an internal array of addressable byte-wide registers controlling different aspects of the board. The registers are as follows: Board Supervisor Registers
Address Control
00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex 09hex 0Ahex 0Fhex 10hex 11hex 12hex 13hex 1Fhex 20hex 21hex 22hex 23hex 24hex 25hex 26hex 2Chex 2Dhex 2Ehex 2Fhex 30hex 31hex 32hex 33hex 34hex 35hex 36hex 37hex 38hex 3Fhex
Default Comment
Master control 00hex GCLK 1 control 00hex GCLK 2 control 00hex GCLK 3 control 00hex GCLK 4 control 00hex GCLK 5 control 00hex GCLK 6 control 00hex GCLK 7 control 00hex GCLK 8 control 00hex GCLK 9 control 00hex 00hex Reserved 00hex Reserved PLL1 control 00hex PLL2 control 00hex 00hex Reserved Osc1 M value 19hex Osc1 control and N value 83hex Osc2 M value 19hex Osc2 control and N value 82hex Osc3 M value 19hex Osc3 control and N value 81hex 00hex Reserved Fan off temperature 23hex Fan on temperature 2Dhex Communication control 00hex Master reset control 00hex FPGA A reset mask 7Fhex FPGA B reset mask 7Fhex FPGA C reset mask 7Fhex FPGA D reset mask 7Fhex ALL_DONE mask 7Fhex Board status 1 (read only) N/A Board status 2 (read only) N/A Reserved. Do not write to these registers!
Table 15. Board Supervisor Registers
The Supervisor Registers are accessed from the Data Port. The STORE command will store an image of the registers in a non-volatile memory. Memory contents are copied back to the Supervisor Registers when switch 10 in the SETUP switch is flipped to the on position, or if its on at power-up. This allows a board to power-up in a non-default state without external intervention.
OVERRIDE
off on
1 0
1 2 3
SETUP
ON 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
Note: The non-volatile memory is not available on early production boards.

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00 : Master control
Master Control Register
addr (hex) 00 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU 1 OSC Override 0 GCLK Override
Table 16. Master Control Register (default value: 00hex)
Bit 1 : OSC Override When 1, the clock generators are controlled from their respective control bytes, 20hex 25hex. When 0, the clock generators are controlled from their respective DIP switch. The override LEDs for the Frequency Select switches reflect the logical AND between this bit and the individual override controls in the corresponding OSC Control Register. Bit 0 : GCLK Override When 1, The SETUP switch settings are overridden for the global clocks. All GCLKs and PLLs are controlled from configuration control bytes 01hex 09hex and 11hex 12hex. When 0, global clocks and PLLs are controlled from the SETUP switch. The SETUP switch override LED reflects the value of this control bit.
01 09 : GCLK control
These bytes control the distribution of the global clocks. Each byte controls a specific clock.
GCLK Control Registers
addr (hex) 01 02 03 04 05 06 07 08 09 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7 GCLK8 GCLK9 7 6 5 4 3 2 1 0
GCLK Source Select
Table 17. GCLK Control Registers (default value: 00hex)
00hex 07hex 0Ahex 0Bhex 0Chex 0Dhex
=> => => => =>
External Coax FPGA A FPGA B FPGA C FPGA D
Example: To set the source of GCLK2 to FPGA B => Address 02hex = 0Bhex Bit 0 in the Master Control Register (address 00hex) must also be set to override the SETUP switch settings. If this bit is not set, the GCLK Control Registers will be ignored, and the GLCKs will be controlled from the SETUP switch.
11 12 : PLL control
These bytes control the PLLs. Address 11 selects PLL1 (the differential PLL), while address 12 selects PLL2 (the single-ended PLL).
PLL Control Registers
addr (hex) 11 PLL1 12 PLL2 7 PLL Enable 6 RFU 5 4 3 2 1 0 PLL Profile Select PLL Clock Source Select
Table 18. Master PLL Registers (default value: 00hex)
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Synopsys, Inc. Bit 7 : PLL Enable When 1, the PLL feedback loop is enabled. When 0, the PLL is bypassed. Bit 5 4 : PLL Profile Select These bits are just passed on to the PLLs. Bit 3 0 : PLL Clock Source Select 0hex 7hex => External Coax Ahex => FPGA A Bhex => FPGA B Chex => FPGA C Dhex => FPGA D A write that changes the value of these registers will cause the corresponding PLL to be reset. Example: To set the source of the single-ended PLL (PLL2) to FPGA C and use PLL profile 1 while disabling the PLL loop => Address 12hex = 1Chex Bit 0 in the Master Control Register (address 00hex) must also be set to override the SETUP switch settings. If this bit is not set, the PLL Control Registers will be ignored, and the PLLs will be controlled from the SETUP switch.
20 25 : OSC1 OSC3
Each clock generator is controlled by two bytes. The first byte controls the M value (Synthesis Multiplier) programmed into the part. The second byte controls the N value, and also has a separate bit indicating the individual override value for each clock generator.
OSC Control Registers
addr (hex) 20 OSC1 22 OSC2 24 OSC3 21 OSC1 23 OSC2 25 OSC3 Override RFU RFU 7 6 5 4 M Value 3 2 1 0
RFU
RFU
RFU
N Value
Table 19. OSC Control Registers (default value: 20hex => 19hex; 21hex => 83hex ; 22hex => 19hex; 23hex => 82hex; 24hex => 19hex; 25hex => 81hex; the default values set the clock generators to run at 25, 52 and 100 MHz respectively)
Bit 7 : Override When 1, the clock generator is controlled by its control bytes. When 0, the clock generator is controlled by its Frequency Select DIP switch. The value of the Override bit directly controls the override LED placed next to the DIP switch. Note that switch 1 (socketed oscillator / on-board crystal) cant be overridden and must be set manually on the board. Example: The following bytes will set OSC1 to 32 MHz. 32 MHz = (Reference Frequency * M) / 2N+1 = (16 * 32) / 23+1 Address 20hex = 20hex (M = 32dec) Address 21hex = 83hex Bit 1 in the Master Control Register (address 00hex) must also be set to override the Frequency Select switch settings. If this bit is not set, the OSC Control Registers will be ignored, and the clock generators will be controlled from their respective switch.
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2D 2E : Fan control
The FPGA is cooled by a fan that is turned on when the temperature of the FPGA is above the Fan on temperature. The fan stays on until the FPGA has cooled down to the Fanoff temperature.
Fan Control
addr (hex) 2D Fan off 2E Fan on 7 6 5 4 3 2 1 0 Temperature in degrees Centigrade
Example: Turn on the fan at 64C and off at 32C. Address 2Dhex = 20hex (32dec) Address 2Ehex = 40hex (64dec)
Table 11. Fan Control Registers (default values: 23hex, 2Dhex; the default values turn on the fan at 45C and off at 35C)
To turn on the fan unconditionally, set both registers to 0.
2F : Communication control
This byte controls the Data Port communication mode.
Communication Control
addr (hex) 2F CC 7 No CR 6 No LF 5 Silent 4 RFU 3 RFU 2 RFU 1 RFU 0 RFU
Table 12. Communication Control Registers (default value: 00hex)
Bit 7, 6 : No CR, No LF When 11, no <CR><LF>. When 10, the output lines end with <LF> only. When 01, the output lines end with <CR> only. When 00, the output lines end with <CR><LF>. Bit 5 : Silent When 1, command input is not echoed, and output is reduced. When 0, command input is echoed back, and output is verbose.
30 : Master reset control

This byte controls the reset signal of all FPGAs unconditionally.
Master Reset Register
addr (hex) 30 7 RFU 6 RFU 5 RFU 4 3 2 1 0 Force Reset Force Reset Force Reset Force Reset Force Reset ALL_DONE A B C D
Table 20. Master Reset Register (default value: 00hex)
Bit 4 0 : Force Reset x When 1, the corresponding reset signal is forced active regardless of other reset conditions. When 0, the corresponding reset signal is released and controlled by normal reset conditions according to each Reset Mask Register described below. Note that forcing ALL_DONE may reset individual FPGAs depending on their Reset Mask settings.
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31 35 : Reset mask
Each FPGA has an individual active low reset input signal that can be triggered from several sources, depending on the setting of a mask register. The supervisor device also outputs the ALL_DONE open-collector signal which is created similarly as the FPGA reset signals. Each reset/ALL_DONE signal is individually masked by its corresponding register. E.g., Reset Mask C is used to create the reset signal for FPGA C. Note that the ALL_DONE pin is used both as an output generated by reset sources through register 35hex, and also as an input to generate resets for the on-board FPGAs.
Reset Mask Registers
addr (hex) 31 32 33 34 RMSK A RMSK B RMSK C RMSK D 7 Sync PLL1 Lock PLL2 Lock 6 5 4 ALL_DONE DONE A DONE B DONE C DONE D 3 2 1 0
35 RMSK ALL_DONE
Table 21. Reset Mask Registers (default value: 7Fhex)
Bit 7 : Sync When 1, the reset signal is always released synchronous with a positive edge on GCLK1. When 0, the reset signal is asserted and released asynchronously. The ALL_DONE signal is always asserted asynchronously, regardless of the setting of this bit. Bit 6 5 : PLLx Lock When 1, if PLLx is enabled, the reset signal will be held low until PLLx has locked. When 0, the lock status of PLLx wont affect the reset signal. Only PLLs that are enabled will affect the reset signal. Disabled PLLs are always considered locked for the purpose of generating reset signals. Bit 4 : ALL_DONE When 1, the reset signal will be held low until the ALL_DONE signal is asserted. When 0, the ALL_DONE signal will be ignored. Note that masking off ALL_DONE will also ignore the reset push-button on the board, since the reset button mimics an ALL_DONE signal. Also note that if a reset source is masked off for a specific FPGA, that reset source can still affect that FPGA through the ALL_DONE signal. E.g., if Reset Mask B (address 32hex) is set to to 5Fhex to ignore PLL2 Lock, while the ALL_DONE Reset Mask (address 35hex ) is 7Fhex, the lock status of PLL2 may keep ALL_DONE asserted, which will reset FPGA B. Bit 3 0 : DONE X When 1, the reset signal will be held low until FPGA x is configured (= DONE). When 0, the reset signal will ignore the DONE signal of FPGA X. These bits are normally set to 1 to keep all FPGAs in reset until all FPGAs are configured. Set the bits to 0 for FPGAs that arent used in your project and therefore wont be configured.
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36 37 : Board status
These bytes are read-only and returns different status aspects of the board.
Board Status Registers
addr (hex) 36 BST1 37 BST2 7 RFU 6 RFU 5 RFU 4 OT 3 DONE A OT_q 2 DONE B Power Fail 1 DONE C OV 0 DONE D OV_q PLL1 Lock PLL2 Lock ALL_DN_int ALL_DONE
Table 22. Board Status Registers (default value: 00hex)
36 : Bit 7 6 : PLLx Lock 1 when the corresponding PLL has locked. 0 when the corresponding PLL has not locked. 36 : Bit 5 : ALL_DN_int 1 when this board has released the ALL_DONE pin. 0 when this board is pulling the ALL_DONE pin low, signifying that this board is not ready. 36 : Bit 4 : ALL_DONE Returns the value of the ALL_DONE pin, as generated by external or internal sources. 1 indicates that all boards are ready to go and that no one is pressing the reset button. 36 : Bit 3 0 : DONE X 1 when the corresponding FPGA is configured. 0 when the corresponding FPGA is not configured. 37 : Bit 4 : OT 1 when one or more FPGAs are above the temperature limit. 0 when temperatures are OK. 37 : Bit 3 : OT_q 1 if overtemperature has been detected since the last power cycle. 0 if no overtemperature event has been detected. 37 : Bit 2 : Power Fail 1 when a power regulator has failed or input voltage is too low. 0 when all power rails are OK. 37 : Bit 1 : OV 1 when the input power supply voltage is too high. 0 when the input power supply voltage is within limits. 37 : Bit 0 : OV_q 1 when the input power supply has had an overvoltage event since the last power cycle. 0 when no overvoltage event has been detected.
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Setup via the Data Port

The Data Port connector is a 6-pin modular jack. An adapter cable that converts this jack to a normal RS-232 port is included in the delivery. For computers without an RS-232 port, a USB serial adapter is also included. If you want to use the USB adapter and your computer doesnt have a suitable driver, download and install the VCP driver from http://www.ftdichip.com. Connect a terminal to the Data Port. Set your terminal emulator to 38400 baud, 8 bits, no parity. Use the following commands at the HAPS-54> prompt: HELP Prints a command summary RSV Report Supervisor Version Prints a version string. WSR <addr> <data> <data> <data> ... <data> Write Supervisor Register <addr> is a two-digit hex setup register address. <data> are two-digit hex data values that will be written to the supervisor register bank on consecutive addresses starting at address <addr>. Example: The following command will enable GCLK Override and set the GLCK Control Registers for GCLK1 GCLK5.
HAPS-54> wsr 00 01 00 0a 0b 0b 0b
RSR <addr> <count> Read Supervisor Register <addr> is a two-digit hex setup register address. <count> is an optional two-digit hex data value describing the number of consecutive registers to read. Example: The following command will print the values of the six OSC Control Registers.
HAPS-54> rsr 20 06
STORE Store supervisor registers in non-volatile memory The current register values will be stored. This command doesnt work for early board versions. Contact support if this feature is needed and is unavailable on your board. RESTORE Restore supervisor registers from non-volatile memory This command has the same effect as flipping SETUP switch 10 to the on position. This command doesnt work for early board versions. Contact support if this feature is needed and is unavailable on your board. RESET Reset supervisor registers to their default values The supervisor registers are set to the default values according to table 15.
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RBS Report Board Status Measured voltages and temperatures are reported. RBI Report Board Identity The board Vendor ID, Product Code, Product Name and Serial Number are reported. This command doesnt work for early board versions. Contact support if this feature is needed and is unavailable on your board. RDB <con> Report Daughter Boards <con> is a two-character connector name. The Supervisor will report the board Vendor ID, Product Code, Product Name and Serial Number of one or more HapsTrak II daughter board placed on the selected connector. The connectors are named according to the normal HapsTrak naming rules. BOARD <nn> Board Select <nn> is a two-digit hex board number. Control boards chained with a CDE_CABLE from a single Data Port connection. BOARD 01 will select the first board in a chain. BOARD 02 the second board, etc. After issuing this command, the selected board will print the prompt and will respond to future Data Port commands. If a non-existing board is chosen, no prompt will be printed. If this happens, enter <CR>BOARD 01<CR> (characters wont be echoed) to return to the first board and get the prompt back.
Fig 68. Terminal window HAPS-54

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Advanced Options
The HAPS-54 board can be modified from the default configuration to suit most needs. The modifications require resistors (mostly 0-Ohm resistors) to be mounted/dismounted. The location of the resistors can be found in the layout diagram on page 68. WARNING: Be careful when replacing the resistors. If you are unsure, please contact us and let us do the modification. Resistors drawn with a dashed line in the following figures are not mounted by default.
VCCO in the Bottom Side Connectors

VCCO is connected to pin B60, H7 and H8 in the HapsTrak II connectors placed on the top side. The bottom side connectors are disconnected from VCCO, which makes it possible to stack boards on top of each other. By mounting 0-Ohm resistors, VCCO can be supplied to the bottom connectors too.
Top
Bottom
VCCO
B60 H7 B60 H7
H8
Fig 67. VCCO in HapsTrak II connectors
H8
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GCLK_IN parallel termination

The clock inputs from the 5 MMCX connectors are normally not terminated. If needed, these inputs can be parallel terminated. Replace the protection resistor Rprot with a 0-Ohm resistor and add the resistors Rp and Rn.
Clock Buffer
CLKVCC
2.5V
7 43 50 A_GCLK(X)
GCLK_INX
50 trace impedance
33
100
Rp Rn
51k
43
50
B_GCLK(X)
Rprot
100
43
50
C_GCLK(X)
off
43
50
D_GCLK(X)
2.5V
on
43
50
Rsa
7 43 50
GCLK_OUTXa
A_GCLKO(X) B_GCLKO(X) C_GCLKO(X) D_GCLKO(X)
100
51k
Rsb
7
GCLK_OUTXb
100
output impedance
SetupBus SetupBus
Fig 68. Clock buffers
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Design Considerations
The inter-FPGA signals with level shifters, AB(112167) and DC(112167), all have strong pull-up resistors. Internal pull-down dont work for these signals. The signals connected to the FPGA in the HapsTrak CDE In bus, D[031], RDWR, CS, BUSY and CCLK, all have 100 Ohm pull-up resistors. Internal pull-up/pull-down resistors dont work for these signals. The signals driving the internal source to the global clocks, X_GCLKO(19), X_PLL_D and X_PLL_SE, where X is A, B, C or D, are parallel terminated and should not be left undriven. Use LVCMOS drivers for these signals. Do not use DCI. Internal pull-up resistors dont work for GPIOX1 and GPIOX6, the signals that also drive the red/green LEDs. Before connecting two GPIO headers together, cut the two VCCO wires in the ribbon cable and make sure the VCCO regions for each group of signals are set to the same voltage.
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Part Reference
FPGA, Virtex-5 Board Supervisor Configuration PROM SPI Flash PROM EEPROM Clock generator PLL Clock oscillator XTAL Clock buffer Temperature watchdog Voltage monitor DC/DC converter 10A Linear regulator HapsTrak II terminal connector HapsTrak II terminal connector HapsTrak II socket connector HapsTrak CDE In HapsTrak CDE Out Coax connector Voltage connector Pin header (2 mm) Data Port Battery Analog Devices Epson Hosonic Integrated Device Technology ISSI Lattice Semiconductor Linear Technology Phoenix Samtec STMicroelectronics Texas Instruments Xilinx XC5VLX330 XC3S200 XCF01S M25P128 IS24C02 ICS8402 isp5620A SG-8002CE PC HCX-6FA, 16.00MHz HCX-6FA, 16.67MHz ICS8308I ADM1033 AD7908 PTH08T240WAZ LT1963A ASP-125521-03 (mating height 19 mm) ASP-132424-01 (mating height 11 mm) ASP-125516-03 QSH-030-01-L-D-A QTH-030-01-L-D-A MMCX 50 Ohm receptacle, straight MC1.5/X-G3.5 FMC 1,5/XX-ST-3,5 TMM series MODS-D-6P6C-L-SM BR1225 http://www.analog.com http://www.epson.com http://www.hosonic.com http://www.idt.com http://www.issi.com http://www.latticesemi.com http://www.linear.com http://www.phoenixcontact.com http://www.samtec.com http://www.st.com http://www.ti.com http://www.xilinx.com Xilinx Xilinx Xilinx STMicroelectronics ISSI Integrated Circuit Systems Lattice Semiconductor Epson Hosonic Hosonic IDT Analog Devices Analog Devices Texas Instruments Linear Technology Samtec (Synplicity ASP) Samtec (Synplicity ASP) Samtec (Synplicity ASP) Samtec Samtec Samtec Phoenix Phoenix Samtec Samtec Any brand (optional)
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Pin Tables
HapsTrak II Connectors 1-3
bank bank bank bank bank bank 3.3V E4 E3 J3 H4 G3 H3 L4 L5 K4 K3 P5 N5 M4 N4 T5 T6 AA10 AA11 W10 W11 Y9 Y10 AA9 Y8 W6 Y7 AA6 AA7 V6 W5 A0 A1 V5 U6 F1 G2 J1 J2 H1 G1 L1 K2 M2 L2 N1 M1 N3 M3 R3 P3 AA5 Y5 Y4 AA4 W3 W2 V1 W1 V4 V3 T1 VR CN 16 CP VR RFU RFU CN 16 CP VR CN CP 12 VR CN CP VCCO
B
CN CP 3.3V BA7 BB7 BB4 BA5 BA4 AY4 AW5 AY5 BB3 BB2 AW3 AY3 BA2 BA1 AY2 AW2 AW8 AY7 AW10 AY10 AY9 AY8 BA10 BB9 AW12 AW11 BB12 BA12 BA11 BB11 SCK SDA AY12 AY13 BA22 BA21 AY18 AY17 BA19 AY19 BB19 BB18 BA17 BB17 BB14 BA15 BA16 BB16 AY15 AY14 AY23 AY22 BA24 BB23 BA25 BB24 BA26 BB26 BB27 BA27 AY28 V1ax V2a V2b V1b V1ax V2a V2b V1b H1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H3 H5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
1
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P
A
H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H4 H6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 3.3V AE8 AE9 AF9 AF10 AF7 AG7 AG8 AH8 AK7 AJ7 AJ8 AH9 AG9 AH10 AF12 AG12 AU3 AV3 AT6 AT5 AT4 AU4 AV4 AV5 AP5 AR5 AP6 AP7 AM8 AN8 A0 A1 AK9 AL9 AV8 AU8 AU6 AT7 AR8 AR7 AV9 AV10 AT9 AU9 AU12 AU13 AU11 AV11 AT11 AT10 AL10 AK10 AL12 AL11 AP10 AN11 AM11 AM12 AN10 AM9 AP12
B
CN CP 3.3V BA37 BB37 AY39 AW38 AW37 AY38 BA39 BB38 BB39 BA40 BB41 BA42 BA41 AY40 AW40 AW41 AW35 AY35 BA34 BB33 AW32 AW33 AY34 AY33 BA32 AY32 BB31 BB32 BA31 BA30 SCK SDA AW31 AY30 AW25 AW26 AV23 AV24 AV28 AW27 AU27 AU28 AW22 AW23 AU24 AV25 AW30 AV30 AU26 AV26 AW20 AW21 AV19 AW18 AV18 AW17 AU16 AU17 AW13 AV13 AV16 V1b V2b V2c V1c V1b V2b V2c V1c H1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H3 H5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
2
A
H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H4 H6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 3.3V AD32 AC33 AE32 AD33 AE34 AE33 AV38 AV39 AU37 AU38 AR38 AT37 AT36 AR37 AF34 AE35 AK34 AL34 AL35 AL36 AK35 AJ35 AJ36 AH36 AN35 AM36 AM34 AN34 AN36 AP35 A0 A1 AG36 AH35 AG33 AF32 AG32 AH33 AJ31 AH31 AT35 AU36 AV36 AV35 AT34 AU34 AR34 AR35 AU33 AU32 AK32 AJ32 AJ33 AK33 AP33 AR33 AM33 AN33 AP32 AR32 AT31
B
CN CP 3.3V AG2 AF2 AF1 AE2 AD1 AC1 AB1 AB2 AE3 AD2 AB4 AB3 AD3 AC3 AC5 AC4 AG1 AH1 AJ1 AK2 AL1 AM1 AM2 AM3 AP2 AR2 AN1 AP1 AT2 AT1 SCK SDA AU1 AU2 AF4 AE4 AD8 AD7 AE7 AD6 AB7 AC8 AE5 AD5 AB9 AB8 AC9 AC10 AD10 AD11 AG4 AH4 AH5 AJ6 AL4 AK5 AL5 AL6 AN3 AP3 AM4 V1a V3a V3b V1b V1a V3a V3b V1b H1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H3 H5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
3
A
H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H4 H6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
VR VR
VR VR
VR
30 CN CP
CN 22 CP
29 CN CP
CN 21 CP
14 CN CP
VR
VR VR
VR VR
RFU RFU 30 CN CP
VR
34 CN CP
VR
VCCO
VCCO
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N A B 60 AP11 60 C D V1ax A V2a B H7 H8 V2b C V1b D
RFU RFU CN 22 CP
RFU RFU 29 CN CP
VR VR
CN CP 26
33 CN CP
VR VR
CN CP VCCO
VCCO
VCCO
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N A B 60 AT32 60 C D V1b A V2b B H7 H8 V2c C V1c D
RFU RFU CN 21 CP
RFU RFU 14 CN CP
VR VR
CN CP 25
18 CN CP
VR VR
CN CP VCCO
VCCO
VCCO
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N A B 60 U1 60 C D V1a A V3a B H7 H8 V3b C V1b D
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Synopsys, Inc.
HapsTrak II Connectors 4-6

bank bank bank bank bank bank 3.3V F14 E15 D17 D16 F15 F16 E17 F17 F20 E20 E18 D18 F19 E19 D23 D22 E30 D30 F29 F30 D28 D27 E28 E29 E27 F27 F25 F26 E25 E24 A0 A1 F24 E23 C30 B31 A31 A30 B32 A32 D33 D32 C33 B33 B34 C34 A35 A34 D36 D35 C41 B42 B41 A41 B38 B39 A40 A39 C40 C39 B36 VR CN 31 CP VR RFU RFU CN 31 CP VR CN CP 27 VR CN CP VCCO
B
CN CP 3.3V AB38 AB37 AJ40 AH40 AJ41 AJ42 AH41 AG42 AG41 AF40 AF42 AF41 AD41 AE42 AD42 AC41 AC39 AC40 AK42 AL41 AN41 AM41 AM42 AL42 AP41 AP42 AT42 AR42 AU41 AT41 SCK SDA AV41 AU42 AP40 AN40 AF37 AG37 AG38 AF39 AD38 AE37 AE38 AE39 AD37 AD36 AD35 AC36 AB36 AC35 AR39 AT39 AK39 AJ38 AH38 AJ37 AK37 AK38 AM39 AL39 AP38 V1b V3b V3c V1c V1b V3b V3c V1c H1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H3 H5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
4
A
H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H4 H6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 3.3V G39 G38 F40 F39 E40 E39 R38 R39 P37 R37 N38 P38 M39 N39 L39 M38 W37 W36 W35 Y35 Y34 AA34 AA36 AA35 U39 T39 W38 V39 U38 T37 A0 A1 K39 K40 G41 F41 J41 H41 K42 J42 M41 L42 L41 L40 N41 M42 P40 N40 Y40 W40 W41 V40 V41 U42 T41 T40 U41 T42 R40 P41 AA37
B
CN CP 3.3V G13 H13 J11 J10 J12 K12 L10 L11 K10 L9 M11 N11 L12 M12 N10 P10 G11 F12 H10 H9 G9 F9 E9 E10 J8 H8 K9 K8 E8 E7 SCK SDA G8 F7 N9 P8 L6 L7 M6 M7 K7 J7 J6 K5 H5 J5 H6 G7 E5 F5 P6 N6 T9 R9 T7 U7 R8 R7 U9 U8 T11 V2a V3ax V3b V2b V2a V3ax V3b V2b H1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H3 H5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
5
A
H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H4 H6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 3.3V A26 B27 C28 C29 A27 B28 A25 B24 C25 C24 A24 B23 B26 C26 B22 C23 B14 B13 C15 C14 C16 B16 A15 A14 A17 A16 B18 B17 C19 C18 A0 A1 A22 A21 C11 B11 A12 B12 D12 D11 A10 A11 D8 C9 D10 C10 B9 A9 B8 C8 B1 C1 C3 B3 D5 C5 C4 D3 A4 B4 B7
B
CN CP 3.3V E35 F35 J31 H31 G31 G32 H33 G33 G34 H34 P31 N31 M31 M32 M33 M34 E33 E32 J33 K33 L31 L32 J32 K32 P32 P33 R32 R33 U32 T32 SCK SDA T31 U31 T35 U34 J37 K37 J36 H35 L35 L36 J35 K35 P36 N36 M37 L37 M36 N35 V36 U36 G36 F36 D37 E38 E37 F37 V34 V35 W33 V2b V3b V3cx V2c V2b V3b V3cx V2c H1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H3 H5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
6
A
H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H4 H6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
VR VR
VR VR
VR
13 CN CP
CN 15 CP
24 CN CP
CN 32 CP
23 CN CP
VR
VR VR
VR VR
RFU RFU 13 CN CP
VR
17 CN CP
VR
VCCO
VCCO
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N A B 60 Y37 60 C D V1b A V3b B H7 H8 V3c C V1c D
RFU RFU CN 15 CP
RFU RFU 24 CN CP
VR VR
CN CP 11
20 CN CP
VR VR
CN CP VCCO
VCCO
VCCO
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N A B 60 A7 60 C D V2a A V3ax B H7 H8 V3b C V2b D
RFU RFU CN 32 CP
RFU RFU 23 CN CP
VR VR
CN CP 28
19 CN CP
VR VR
CN CP VCCO
VCCO
VCCO
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N A B 60 B37 60 C D V2b A V3b B H7 H8 V3cx C V2c D
RFU = Reserved for future use HAPS-54

61
Synopsys, Inc.
HapsTrak II Connector 7
bank bank 3.3V H14 G14 G16 H16 J15 H15 J16 J17 L17 M17 H18 J18 N19 N18 J23 J22 J20 K20 N20 P20 L21 L20 N21 P21 M21 N22 H21 J21 P22 P23 A0 A1 F22 G22 M22 L22 K23 K22 G24 H24 G23 H23 J25 H25 L24 L25 K24 K25 N25 P25 H28 G27 L26 M26 H26 G26 K27 J28 G29 G28 J27 5 7 5 CN CP 7 RFU RFU CN CP 7 CN CP 5 7
B
CN CP 3.3V AR29 AR28 AT15 AT14 AM17 AM18 AM19 AL19 AL17 AK18 AJ18 AK19 AL20 AK20 AP17 AN18 AR30 AT30 AN20 AP20 AT21 AT20 AP18 AN19 AJ20 AJ21 AT19 AR20 AL21 AM21 SCK SDA AK22 AK23 AT24 AT25 AK24 AJ25 AN24 AP23 AN23 AM23 AM24 AL25 AK25 AL24 AR25 AP25 AN25 AN26 AR24 AR23 AR27 AP26 AT26 AT27 AP27 AP28 AT29 AU29 AM22 H1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H3 H5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
7
A
H2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H4 H6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
8 6
CN CP
8 6
RFU RFU 8 6 8 CN CP
6 8 6 CN 8 CP 6 8 6 8 VCCO
VCCO
N P N P N P N P N P N P N P N P N P N P N P N P N P N P N A B 2.5V 60 60 J26 C D A B 2.5V H7 H8 2.5V C D
CN CP
Note
Connectors A7, B7, C7 and D7 are HapsTrak II connectors for boards with serial number 070647 and above. Previous versions had HapsTrak I connectors!
VCCO
Note The VREF pins in connector 7 are not connected to the same pins as other HapsTrak connectors!
RFU = Reserved for future use
62
HAPS-54
Synopsys, Inc.
Inter-FPGA Connections A-B (fast)

AB
bank bank bank
bank
bank
A
R28 R27 M13 N13 AH16 AJ15 AH30 AH29 AJ16 AJ17 AK30 AJ30 M23 N23 G21 H20 H19 G19 M24 N24 K19 L19 M18 M19 R18 P18 H29 H30 AL26 AM26 AR15 AP15 AR13 AR14 AJ23 AJ22 AN21 AP21 AR18 AR19 AL22 AU21 AT22 AR22 AP22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 R28 R27 M13 N13 AH16 AJ15 AH30 AH29 AJ16 AJ17 AK30 AJ30 M23 N23 G21 H20 H19 G19 M24 N24 K19 L19 M18 M19 R18 P18 H29 H30 AL26 AM26 AR15 AP15 AR13 AR14 AJ23 AJ22 AN21 AP21 AR18 AR19 AL22 AU21 AT22 AR22 AP22
A
CP CN CP CN A29 B29 C21 C20 A20 B21 C13 D13 B6 C6 D7 D6 A2 B2 D1 D2 P12 P11 H11 G12 E12 E13 G6 F6 M8 M9 P7 N8 U11 V9 V8 V11 V10 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
B
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 BA29 AY29 BA20 AY20 BB21 BB22 AJ12 AK12 AV6 AU7 AW7 AW6 AK8 AL7 AV1 AW1 BB29 BB28 AR12 AT12 BB13 BA14 BB6 BA6 AJ10 AJ11 AR9 AR10 AY27 AF11 AE10 AH11 AG11
A
CP CN CP CN E14 D15 D21 D20 F21 E22 D31 C31 C36 C35 A37 A36 D40 D41 E42 D42 N33 N34 E34 F34 F31 F32 R34 P35 T34 U33 R35 T36 V33 Y33 W32 Y32 AA32 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
B
79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 AU14 AV14 AW15 AV15 AV21 AV20 AU23 AU22 AL32 AM32 AB33 AB32 AY37 AW36 AY42 AW42 AV33 AV34 AH34 AG34 AV31 AU31 AF35 AF36 AL31 AM31 BB36 BA36 AW16 AV29 AW28 AG31 AF31
1 CP CN CP CN
1 CP CN CP CN
32
CP 34 CN CP CN 26 CP 30 CN CP 22 CN 30 34 CP 26 CN 34 CP 30 CN CP CN 26 34 22
31
CP CN CP 28 CN
CP CN CP 27 CN
CP CN CP CN
CP CN CP CN CP CN CP CN CP CN
CP CN CP CN
CP CN CP CN
CP 24 CN CP CN 5 CP CN CP 20 CN
CP 23 CN CP CN CP CN CP 19 CN
CP 29 CN 33 25
6 CP CN
6 CP CN CP CN CP CN
CP CN
CP CN CP CN
Inter-FPGA Connections A-B (slow)

8
AB
bank bank bank
AB
G4 F4 R5 R4 U4 T4 E2 F2 P2 P1 R2 T2 AA1 AA2 Y2 Y3 AB6 AC6 AG3 AH3 AJ2 AJ3 AB11 AC11 AF6 AF5 AG6 AH6
22
26
Note The inter-FPGA signals with level shifters all have strong pull-up resistors. Internal pull-down dont work for these signals.
30
34
AF11 AE10 AH11 AG11 AK8 AL7 AV6 AU7 AR9 AR10 AR12 AT12 AJ10 AJ11 AJ12 AK12 AV1 AW1 AW7 AW6 BB6 BA6 BB13 BA14 BB21 BB22 BA20 AY20
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
16
16
12
12
14
14
18
18
G4 F4 R5 R4 U4 T4 E2 F2 P2 P1 R2 T2 AA1 AA2 Y2 Y3 AB6 AC6 AG3 AH3 AJ2 AJ3 AB11 AC11 AF6 AF5 AG6 AH6
140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167
A29 B29 C21 C20 A20 B21 C13 D13 B6 C6 D7 D6 A2 B2 D1 D2 P12 P11 H11 G12 E12 E13 G6 F6 M8 M9 P7 N8
HAPS-54
bank 32 28 24 20
V1ax
V3a
V1a
V3ax
bank 33 25 21 29 25 21 25 21 25
2.5V
AB
V2a
AB
V2b
63
Synopsys, Inc.
Inter-FPGA Connections D-C (fast)

DC
bank bank bank
bank
bank
D
R28 R27 M13 N13 AH16 AJ15 AH30 AH29 AJ16 AJ17 AK30 AJ30 M23 N23 G21 H20 H19 G19 M24 N24 K19 L19 M18 M19 R18 P18 H29 H30 AL26 AM26 AR15 AP15 AR13 AR14 AJ23 AJ22 AN21 AP21 AR18 AR19 AL22 AU21 AT22 AR22 AP22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 R28 R27 M13 N13 AH16 AJ15 AH30 AH29 AJ16 AJ17 AK30 AJ30 M23 N23 G21 H20 H19 G19 M24 N24 K19 L19 M18 M19 R18 P18 H29 H30 AL26 AM26 AR15 AP15 AR13 AR14 AJ23 AJ22 AN21 AP21 AR18 AR19 AL22 AU21 AT22 AR22 AP22
D
CP CN CP CN A29 B29 C21 C20 A20 B21 C13 D13 B6 C6 D7 D6 A2 B2 D1 D2 P12 P11 H11 G12 E12 E13 G6 F6 M8 M9 P7 N8 U11 V9 V8 V11 V10 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
C
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 BA29 AY29 BA20 AY20 BB21 BB22 AJ12 AK12 AV6 AU7 AW7 AW6 AK8 AL7 AV1 AW1 BB29 BB28 AR12 AT12 BB13 BA14 BB6 BA6 AJ10 AJ11 AR9 AR10 AY27 AF11 AE10 AH11 AG11
D
C
79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 AU14 AV14 AW15 AV15 AV21 AV20 AU23 AU22 AL32 AM32 AB33 AB32 AY37 AW36 AY42 AW42 AV33 AV34 AH34 AG34 AV31 AU31 AF35 AF36 AL31 AM31 BB36 BA36 AW16 AV29 AW28 AG31 AF31
1 CP CN CP CN
1 CP CN CP CN
32
CP 34 CN CP CN 26 CP 30 CN CP 22 CN 30 34 CP 26 CN 34 CP 30 CN CP CN 26 34 22
31
CP CN CP 28 CN
CP CN CP 27 CN
CP CN CP CN
CP CN CP CN CP CN CP CN CP CN
CP CN CP CN
CP CN CP CN
CP 24 CN CP CN 5 CP CN CP 20 CN
CP 29 CN 33 25
6 CP CN
6 CP CN CP CN CP CN
CP CN
CP CN CP CN
Inter-FPGA Connections D-C (slow)

8
DC
bank bank bank
DC
H38 H39 K38 J38 H40 J40 F42 G42 AA40 AA39 Y39 Y38 W42 Y42 AA42 AA41 AB41 AB42 AB39 AC38 AE40 AD40 AB34 AC34 AR40 AT40 AV40 AU39
21
25
Note The inter-FPGA signals with level shifters all have strong pull-up resistors. Internal pull-down dont work for these signals.
64
29
33
AB33 AB32 AF35 AF36 AH34 AG34 AG31 AF31 AV33 AV34 AV31 AU31 AL32 AM32 AL31 AM31 AY42 AW42 AY37 AW36 BB36 BA36 AV29 AW28 AU23 AU22 AV21 AV20
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
15
15
11
11
13
13
17
17
H38 H39 K38 J38 H40 J40 F42 G42 AA40 AA39 Y39 Y38 W42 Y42 AA42 AA41 AB41 AB42 AB39 AC38 AE40 AD40 AB34 AC34 AR40 AT40 AV40 AU39
140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167
E14 D15 D21 D20 F21 E22 D31 C31 C36 C35 A37 A36 D40 D41 E42 D42 N33 N34 E34 F34 F31 F32 R34 P35 T34 U33 R35 T36
HAPS-54
bank 31 27 23 19
V1cx
V3c
V1c
V3cx
bank 33 25 21 29 25 21 25 21 25
2.5V
DC
V2b
DC
V2c
Synopsys, Inc.
Inter-FPGA Connections A-D (fast)

AD
bank bank bank
A
CP CN CP CN H38 H39 K38 J38 H40 J40 F42 G42 AA40 AA39 Y39 Y38 W42 Y42 AA42 AA41 AB41 AB42 AB39 AC38 AE40 AD40 AB34 AC34 AR40 AT40 AV40 AU39 AN39 AN38 AM38 AM37 AL37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 G4 F4 R5 R4 U4 T4 E2 F2 P2 P1 R2 T2 AA1 AA2 Y2 Y3 AB6 AC6 AG3 AH3 AJ2 AJ3 AB11 AC11 AF6 AF5 AG6 AH6 AN4 AR3 AR4 AM6 AN5
A
CP CN CP CN AB33 AB32 AF35 AF36 AH34 AG34 AG31 AF31 AV33 AV34 AV31 AU31 AL32 AM32 AL31 AM31 AY42 AW42 AY37 AW36 BB36 BA36 AV29 AW28 AU23 AU22 AV21 AV20 AW16 AU14 AV14 AW15 AV15 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
D
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 AF11 AE10 AH11 AG11 AK8 AL7 AV6 AU7 AR9 AR10 AR12 AT12 AJ10 AJ11 AJ12 AK12 AV1 AW1 AW7 AW6 BB6 BA6 BB13 BA14 BB21 BB22 BA20 AY20 AY27 BB29 BB28 BA29 AY29
15
21
CP CN CP 11 CN
CP CN CP 25 CN
13
CP CN CP CN
CP 14 CN CP CN CP CN CP CN 18
29
CP CN CP CN
CP CN CP 17 CN
CP CN CP 33 CN
HAPS-54
bank
V1b
AD
V1b
65
Synopsys, Inc.
Inter-FPGA Connections B-C (fast)

BC
bank bank bank
B
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A29 B29 C21 C20 A20 B21 C13 D13 B6 C6 D7 D6 A2 B2 D1 D2 P12 P11 H11 G12 E12 E13 G6 F6 M8 M9 P7 N8 U11 V9 V8 V11 V10
B
CP CN CP CN H38 H39 K38 J38 H40 J40 F42 G42 AA40 AA39 Y39 Y38 W42 Y42 AA42 AA41 AB41 AB42 AB39 AC38 AE40 AD40 AB34 AC34 AR40 AT40 AV40 AU39 AN39 AN38 AM38 AM37 AL37 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N
C
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 G4 F4 R5 R4 U4 T4 E2 F2 P2 P1 R2 T2 AA1 AA2 Y2 Y3 AB6 AC6 AG3 AH3 AJ2 AJ3 AB11 AC11 AF6 AF5 AG6 AH6 AN4 AR3 AR4 AM6 AN5
31
15
CP CN CP 27 CN
CP CN CP 11 CN
23
CP CN CP CN
13
CP CN CP CN
CP CN CP 19 CN
CP CN CP 17 CN
66
HAPS-54
bank
V3b
BC
V3b
Synopsys, Inc.
HapsTrak CDE In
CDE In
2.5V
bank pin R15 P16 N30 P30 P13 N14 M29 N29 P15 N15 P28 N28 R17 P17 P26 P27 R30 T30 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 RDWR CS TMS TCK TDI TDO 2.5V GND ALL_DONE BOARD_INIT_B BOARD_PROG_B Reserved_8 Reserved_9 2.5V
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 BUSY CCLK CDE_IN_1 CDE_IN_2 CDE_IN_3 CDE_IN_4 Reserved_1 Reserved_2 Reserved_3 Reserved_4 Reserved_5 Reserved_6 Reserved_7 (No Connect)
pin AJ27 AJ26 AL14 AL15 AK29 AJ28 AK13 AJ13 AM16 AN16 AN30 AM29 AK17 AL16 AK27 AK28 AH15 AF15
bank
Note The signals connected to the FPGAs are all terminated to 1.25V with 100 Ohm resistors. Internal pull-up/pull-down resistors dont work for these signals.
HapsTrak CDE Out

CDE Out
2.5V
B
B_D16 B_D17 B_D18 B_D19 B_D20 B_D21 B_D22 B_D23 B_D24 B_D25 B_D26 B_D27 B_D28 B_D29 B_D30 B_D31 B_RDWR B_CS TMS_O TCK_O TDI_O TDO_O VCONF CHAINED_n ALL_DONE BOARD_INIT_B BOARD_PROG_B Reserved_8 Reserved_9 (No Connect) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 B_D0 B_D1 B_D2 B_D3 B_D4 B_D5 B_D6 B_D7 B_D8 B_D9 B_D10 B_D11 B_D12 B_D13 B_D14 B_D15 B_BUSY B_CCLK CDE_OUT_1 CDE_OUT_2 CDE_OUT_3 CDE_OUT_4 Reserved_1 Reserved_2 Reserved_3 Reserved_4 Reserved_5 Reserved_6 Reserved_7 2.5V
HAPS-54
67
Synopsys, Inc.
Global Clocks
Global Clocks Source
From MMCX External GCLK_IN1 Outputs from FPGAs To MMCX
Destination
Inputs to FPGAs
2.5V
Internal A_GCLKO(1) B_GCLKO(1) C_GCLKO(1) D_GCLKO(1) A_GCLKO(2) B_GCLKO(2) C_GCLKO(2) D_GCLKO(2) A_GCLKO(3) B_GCLKO(3) C_GCLKO(3) D_GCLKO(3) A_GCLKO(4) B_GCLKO(4) C_GCLKO(4) D_GCLKO(4) A_GCLKO(5) B_GCLKO(5) C_GCLKO(5) D_GCLKO(5) A_GCLKO(6) B_GCLKO(6) C_GCLKO(6) D_GCLKO(6) A_GCLKO(7) B_GCLKO(7) C_GCLKO(7) D_GCLKO(7) A_GCLKO(8) B_GCLKO(8) C_GCLKO(8) D_GCLKO(8) A_GCLKO(9) B_GCLKO(9) C_GCLKO(9) D_GCLKO(9) A_PLL_D B_PLL_D C_PLL_D D_PLL_D A_PLL_SE B_PLL_SE C_PLL_SE D_PLL_SE pin / bank External AN29 GCLK_OUT1a GCLK_OUT1b GCLK_OUT2a GCLK_OUT2b GCLK_OUT3a GCLK_OUT3b GCLK_OUT4a GCLK_OUT4b GCLK_OUT5a GCLK_OUT5b GCLK_OUT6a GCLK_OUT6b 3 K29 GCLK_OUT7a GCLK_OUT7b GCLK_OUT8a GCLK_OUT8b 2 AL30 GCLK_OUT9a GCLK_OUT9b GCLK_OUT_D1P GCLK_OUT_D1N GCLK_OUT_D2P GCLK_OUT_D2N GCLK_OUT_SE1 GCLK_OUT_SE2 GCLK_OUT_SE3 3 GCLK_OUT_SE4 GCLK_OUT_SE5 GCLK_OUT_SE6 3 GCLK(9) GCLK(10) GCLK(11) GCLK(12) GCLK(13) GCLK(14) GCLK(15) GCLK(16) P P N P N P P P GCLK(7) P Internal GCLK(1)
2.5V
P/N pin / bank P AP30
GCLK_IN2
AM14
GCLK(2)
AM13
GCLK_IN3
AN28
GCLK(3)
AM28
GCLK_IN4
AM27
GCLK(4)
AL27
GCLK_IN5
AN13
GCLK(5)
AP13
GCLK_IN6
L16
GCLK(6)
K28
GCLK_IN7
M14 3
GCLK_IN8
AL29
GCLK(8)
N16
GCLK_IN9
L29 K15 K14 M27 N26 K13 L27 L15 3
PLL_DP PLL_DN
J13
PLL_SE
M28
Note The signals driving the internal source are parallel terminated and should not be left undriven. Use LVCMOS drivers for these signals. Do not use DCI. Direct Differential Clocks
Direct Clocks
GC_A1 GC_A2 GC_B1 GC_B2 GC_C1 GC_C2 GC_D1 GC_D2 N AN14 K30 pin P AN15 J30 2.5V bank 4 3
RESET
RESET
pin A_RESET_n B_RESET_n D_RESET_n 2.5V bank 3
C_RESET_n
L14
GPIO
GPIO A
1 2 3 4 5 6 7 8 9 10 pin AY27 BB29 BB28 BA29 AY29 AN4 AR3 AR4 AM6 AN5 bank 34 V V1ax pin AN4 AR3 AR4 AM6 AN5 U11 V9 V8 V11 V10
B
bank 18 pin AN39 AN38 V3a AM38 AM37 AL37 V33 Y33 V3ax W32 Y32 AA32 V
C
bank 17 pin AW16 AU14 V3c AV14 AW15 AV15 AN39 AN38 V3cx AM38 AM37 AL37 V
D
bank 33 V V1cx LEDs A, B, C, D : Red 17 V1c LEDs A, B, C, D : Green
18
V1a
20
19
68
HAPS-54
Synopsys, Inc.
Signal Delays
Connectors to FPGAs
Average delay in pico-seconds from connectors to FPGAs FPGA A Delay +/724 2 721 4 356 4 293 1 694 3 710 2 490 3 FPGA B Delay +/724 2 721 4 356 4 293 1 694 3 710 2 507 4 FPGA C Delay +/724 2 721 4 356 4 293 1 694 3 710 2 507 4 FPGA D Delay +/724 2 721 4 356 4 293 1 694 3 710 2 490 3
1 2 3 4 5 6 7
FPGA to FPGA
Average delay in pico-seconds from FPGA to FPGA Pin 1 66 1 111 * 112 167 Global signals 1 119 AB Delay +/ 1 197 1 2 787 2 1 197 1 DC Delay +/ 1 197 1 2 787 2 1 197 1 AD Delay +/1 199 3 BC Delay +/1 199 3
* The delay of the transmission gate must be added. This delay depends on the voltage translation. The performance is optimal when the voltage is the same on both sides.
HAPS-54
69
Synopsys, Inc.
Layout
V3cx
V3b
V3b
V3ax
GCLK_IN
Rprot
Rprot
Rprot
Rprot
Rprot
Rprot
Rprot
RC915
RC916
R740
R741
VCCO
Rvcco
Rvcco
R135
Rvcco
Rvcco
R134
VCCO
VCCO
GCLK_IN
Rsa
Rprot
VCCO
V3c
C170 C175
CC950
C463
R864 R865 Rn Rp C105
Rprot
XC5VLX330
V3b
V3b
XC5VLX330
V3a
2 3 4 5 6 7 8 9
Rvcco
C169
C164
Rsb
1 2 3 4 5 6 7 8 9
C6
C5
B6
B5
C102 Rsa
R867 R866
Rn Rp
C100 C1999 C1995 C1991 C1984 C115 C110 C95
C165 C160 C179 C174 C185 C180 C1892 C1899 C1900 C1907 C1908 C1915 C1916 C1922
C4
C3
B4
B3
Rvcco
Rvcco
Rvcco
V2c
V2b
V2b
V2a
C2
C1
B2
B1
Rsb
Rsb
Rsb
VCCO
VCCO
VCCO
VCCO
Rsb
Rsb
Rsb
Rsb
Rsb Rn Rp Rn Rp Rn Rp Rn Rp Rn Rp Rn Rp Rn Rp
C96
Rsa
R862 R863
C92
Rsa
R871 R870
C106
Rsa
R873 R872
C112
Rsa
R925 R926
C1981
Rsa
R927 R928
C1985
Rsa
R929 R930
C1989
Rsa
R923 R924
C1993
R1126 Rvcco Rvcco R1122

RC209
Rvcco
Rvcco
8 9
C1908 C1915 C1916 C1922
R929 R930
Rn Rp
C1995 C1999
VCCO
V2c V2b
VCCO
V2b
VCCO
V2a
VCCO
D6
D5
A6
Rvcco
Rvcco
R130
VCCO
V1c
VCCO
VCCO
V1b
VCCO
XC5VLX330
V1b
Rvcco
Rvcco
Rvcco
R138
VCCO
V1cx
VCCO
V1b V1b
VCCO
V1ax
VCCO
D2
D1
A2
VCCO
VCCO
VCCO
A1
Rvcco
R139
XC5VLX330
V1a
D4
D3
A4
A3
Rvcco
Rvcco
R132
A5
VCCO
Rvcco
Rvcco
Placement of 0-Ohm resistors. See Advanced Options.
70
HAPS-54
Rvcco
Rvcco
Rsb
Rsb
C1989
Rsa
R923 R924
Rn Rp
C1993
Synopsys, Inc.
Board Dimensions
V3ax H1 H2 B1 V3b A1
V3b
V3cx
43.5 mm 2.75 mm
H1 B1
B60 H7
B7
2.5V B60 H7 A60 H8
C7
2.5V
V3a
XC5VLX330
V3b
V3b
XC5VLX330
V3c
43.5 mm
V2a
A1 B1
V2b
V2b
V2c
43.5 mm
A30
B30
V2a
V2b
V2b
V2c
43.5 mm
B30
A30
V1a
XC5VLX330
A
A7
V1b
V1b
XC5VLX330
D
D7
V1c
43.5 mm
V1ax
V1b
2.5V
V1b
2.5V
V1cx
299.0 mm 52.75 mm 49.5 mm 46.25 mm 43.5 mm 2.75 mm
All mounting holes are 3.2 mm in diameter 2.75 mm 61.0 mm 131.0 mm 201.0 mm 279.0 mm 70.0 mm 70.0 mm 70.0 mm
HAPS-54
0.5 mm 50.0 mm
D1
D2
A1
A2
71
50.0 mm
D3
D4
A3
A4
50.0 mm
B1
CDE Out
A1
D5
D6
A5
A6
50.0 mm
CDE In
C1
C2
B1
B2
50.0 mm
C3
C4
B3
B4
0.5 mm 50.0 mm
H2 A1
A60 H8
C5
C6
B5
B6
Synopsys, Inc.
The Experiment Board LAB_1x1

In order to get signals onto and out from your HAPS design, you need some kind of I/O subsystem. The LAB_1x1 board is a simple prototyping board that you can use to break out signals from a HapsTrak connector to a more convenient 0.1 grid, and/or build a simple I/O device or adapter.
Description
The signals in the connector are connected to an area with 4x30 holes with 0.05 mm spacing, and also fed through to the top side connector. VCC and GND are available in separate soldering points. VCC is connected to B60 and to a VCC plane on the bottom side of the board. GND is connected to the GND rail in the connector and to a GND plane on the top side. Be careful so that no device pin is shorted to the GND plane or the VCC plane as you mount it. Dont forget to mount decoupling capacitors!
Strap to power LAB_1x1 from the HAPS connector
Connector
VCC
1 2 21
GND
A13 A10 B14 B9
A B
VCC
AB
To the VCC plane on the bottom side
GND

LAB_1x1
59 59 60 Pinout
Note 1: The numbering, 1 to 60, may be marked wrong. The correct numbering is as in the figure above. Note 2: The LAB_1x1 board was designed to fit all members of the HAPS family, and thus use HapsTrak I connectors.
72
HAPS-54
Synopsys, Inc.
Current Members of the HAPS family

see http://www.synplicity.com for an up-to-date listing Motherboards
HAPS-54 HAPS-52 HAPS-51 HAPS-34 HAPS-32 HAPS-31 4 Virtex-5 LX330 2 Virtex-5 LX330 1 Virtex-5 LX330 4 Virtex-4 LX100/160/200 2 Virtex-4 LX100/160/200 1 Virtex-4 LX40/60/80/100/160 or SX55
Daughter Boards
SRAM_1x1 SDRAM_1x1 DDR_1x1 DDR2_1x2 GDDR_1x1 FLASH_1x1 ETH_USB_1x1 GEPHY_1x1 PCIX PCIE-1-KIT PCIE-1-KIT_LAP PCIE-4-BP ADC_1x1 DVB-OUT_1x1 LCD1_1x1 GBx1_1x2 DVI_1x1A CON_2x1 CON_1x2 CON_2x2 CON_1x1 CON_CABLE40 CON_CABLEX40 CONF30 CTI_2x2 HAPS_CMI PD_1x2 BIO1 LAB_1x1 MICT_1x1 STB1_1x1 STB2_1x1 TERM-TOP_1x1 Memory: SRAM Memory: SDRAM Memory: DDR SDRAM Memory: DDR2 SDRAM Memory: GDDR SDRAM Memory: Flash PROM Ethernet + USB + RS232 Gigabit Ethernet PHY PCI/PCIX interface PCI Express interface (1-lane) PCI Express interface (1-lane) for laptops PCI Express backplane (4-lane) Combined A/D and D/A SPI and ASI-C interface Flat panel display interface LSI SerDes evaluation board Digital video with HDMI support 2-way bus 2-way bus 4-way bus Vertical bus 2-way bus Extension cable CompactFlash conguration board ARM Core Tile Interface ARM Core Module Interface Cadence Palladium Interface Basic I/O Experiment board Mictor interface Self-test board for HapsTrak I Self-test board for HapsTrak II Termination board
Miscellaneous
HAPS Case Metal chassis
HAPS-54
73
HAPS High-performance ASIC Prototyping System HAPS is a high capacity FPGA based system for ASIC prototyping and emulation. The modular system is built with multi-FPGA motherboards and standard or custom-made daughter boards which can be stacked together in a variety of ways. Amongst the functions available on standard daughter boards are video processing, various memory types, and interfaces to Ethernet, USB, PCI Express and ARM core modules.
Synopsys, Inc. Synplicity Business Group 600 West California Avenue Sunnyvale, CA 94086 USA haps@synplicity.com www.synplicity.com
Copyright 2009 Synopsys, Inc. All rights reserved. Synopsys, Synplicity, the Synplicity logo, and Simply Better Results, are registered trademarks of Synopsys, Inc. Conrma, HAPS, HapsTrak, and High-performance ASIC Prototyping System are trademarks of Synopsys, Inc. All other names mentioned herein are trademarks or registered trademarks of their respective companies.

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HAPS

High-performance ASIC Prototyping System

HAPS-54 2009, Synopsys, Inc.

March 20, 2009

Holes to secure daughter boards

Fig 1. The HAPS-54 motherboard

Fig 2. A HAPS motherboard

Look at http://www.synplicity.com to find a current list of interconnect boards.

Height Dimension Rules

YYY = 060 or 064 YYY = 060 or 064 YYY = 060 or 064

Fig 3. Height dimensions

Example of a HAPS System

HAPS-51 HAPS-34 FPGA

Buses betwe FPGAs are e with intercon

Boards can be stacked in a variety of ways.

Motherboards can be stacked on top of each other.

Daughter boards can be placed on the bottom side of a motherboard.

Fig 4. Example of a HAPS system

Fig 7. VCCO - HapsTrak I

Fig 8. VCCO - HapsTrak II

Board Layout Top Side

GND V3a V3ax

V3cx V3c GND

TDI TDO TCK TMS +2.5 V

PWR_GR DONE A DONE B DONE C GND DONE D

factory test only

B3_N B3_P GND

DC/DC VCCINT A GC_A2 N P

DC/DC VCCINT D GC_D2 N P

JTAG CFG XA BCD

REFn FBp FBn 1p

V1ax V1a GND

V1cx V1c GND

Fig 9. HAPS-54 - top side

TDI TDO TCK TMS VCC

GND GND GND GND GND GND

2.5V B2_N B2_P

Board Layout Bottom Side

U109 U108 U110 U107

Fig 10. HAPS-54 - bottom side

I/O Signals & Interconnects

3.3V 2.5V 1.8V 1.5V PWR

3.3V 2.5V 1.8V 1.5V PWR

3.3V 2.5V 1.8V 1.5V PWR

3.3V 2.5V 1.8V 1.5V PWR

33 V2b 45 2.5V 28 V1ax V3a

33 V2c 111 33 V2b 45 2.5V 28 V1cx V3c 56 28 V1c V3cx

167 inter-FPGA connects

3.3V 2.5V 1.8V 1.5V PWR

3.3V 2.5V 1.8V 1.5V PWR

167 inter-FPGA connects

Fig 11. I/Os, interconnects, I/O banks and VCCO regions

3.3V 2.5V 1.8V 1.5V PWR

3.3V 2.5V 1.8V 1.5V PWR

General Purpose I/Os

Inputs to each FPGA 1 .. 9

GCLK(1) GCLK(2) GCLK(3) GCLK(4) GCLK(5) GCLK(6) GCLK(7) GCLK(8) GCLK(9)

GCLK(10) GCLK(11) GCLK(12) GCLK(13)

GCLK(14) GCLK(15) GCLK(16)

GCLK(17) GCLK(18) GCLK(19) GCLK(20)

Same pinning for all FPGAs

Same pinning for all FPGAs

Fig 12. Clocks

Applying Power the First Time